1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2011 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

/* Linux PRO/1000 Ethernet Driver main header file */

    30

    31

#ifndef _E1000_H_

    32

#define _E1000_H_

    33

    34

#include <linux/bitops.h>

    35

#include <linux/types.h>

    36

#include <linux/timer.h>

    37

#include <linux/workqueue.h>

    38

#include <linux/io.h>

    39

#include <linux/netdevice.h>

    40

#include <linux/pci.h>

    41

#include <linux/pci-aspm.h>

    42

#include <linux/crc32.h>

    43

#include <linux/if_vlan.h>

    44

    45

#include "hw.h"

    46

    47

struct e1000_info;

    48

    49

#define e_dbg(format, arg...) \

    50

	netdev_dbg(hw->adapter->netdev, format, ## arg)

    51

#define e_err(format, arg...) \

    52

	netdev_err(adapter->netdev, format, ## arg)

    53

#define e_info(format, arg...) \

    54

	netdev_info(adapter->netdev, format, ## arg)

    55

#define e_warn(format, arg...) \

    56

	netdev_warn(adapter->netdev, format, ## arg)

    57

#define e_notice(format, arg...) \

    58

	netdev_notice(adapter->netdev, format, ## arg)

    59

    60

    61

/* Interrupt modes, as used by the IntMode parameter */

    62

#define E1000E_INT_MODE_LEGACY		0

    63

#define E1000E_INT_MODE_MSI		1

    64

#define E1000E_INT_MODE_MSIX		2

    65

    66

/* Tx/Rx descriptor defines */

    67

#define E1000_DEFAULT_TXD		256

    68

#define E1000_MAX_TXD			4096

    69

#define E1000_MIN_TXD			64

    70

    71

#define E1000_DEFAULT_RXD		256

    72

#define E1000_MAX_RXD			4096

    73

#define E1000_MIN_RXD			64

    74

    75

#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */

    76

#define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */

    77

    78

/* Early Receive defines */

    79

#define E1000_ERT_2048			0x100

    80

    81

#define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */

    82

    83

/* How many Tx Descriptors do we need to call netif_wake_queue ? */

    84

/* How many Rx Buffers do we bundle into one write to the hardware ? */

    85

#define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */

    86

    87

#define AUTO_ALL_MODES			0

    88

#define E1000_EEPROM_APME		0x0400

    89

    90

#define E1000_MNG_VLAN_NONE		(-1)

    91

    92

/* Number of packet split data buffers (not including the header buffer) */

    93

#define PS_PAGE_BUFFERS			(MAX_PS_BUFFERS - 1)

    94

    95

#define DEFAULT_JUMBO			9234

    96

    97

/* BM/HV Specific Registers */

    98

#define BM_PORT_CTRL_PAGE                 769

    99

   100

#define PHY_UPPER_SHIFT                   21

   101

#define BM_PHY_REG(page, reg) \

   102

	(((reg) & MAX_PHY_REG_ADDRESS) |\

   103

	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\

   104

	 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))

   105

   106

/* PHY Wakeup Registers and defines */

   107

#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)

   108

#define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)

   109

#define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)

   110

#define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)

   111

#define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)

   112

#define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))

   113

#define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))

   114

#define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))

   115

#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))

   116

#define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))

   117

   118

#define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */

   119

#define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */

   120

#define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */

   121

#define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */

   122

#define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */

   123

#define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */

   124

#define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */

   125

   126

#define HV_STATS_PAGE	778

   127

#define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */

   128

#define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)

   129

#define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */

   130

#define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)

   131

#define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */

   132

#define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)

   133

#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */

   134

#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)

   135

#define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */

   136

#define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)

   137

#define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */

   138

#define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)

   139

#define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */

   140

#define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)

   141

   142

#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */

   143

   144

/* BM PHY Copper Specific Status */

   145

#define BM_CS_STATUS                      17

   146

#define BM_CS_STATUS_LINK_UP              0x0400

   147

#define BM_CS_STATUS_RESOLVED             0x0800

   148

#define BM_CS_STATUS_SPEED_MASK           0xC000

   149

#define BM_CS_STATUS_SPEED_1000           0x8000

   150

   151

/* 82577 Mobile Phy Status Register */

   152

#define HV_M_STATUS                       26

   153

#define HV_M_STATUS_AUTONEG_COMPLETE      0x1000

   154

#define HV_M_STATUS_SPEED_MASK            0x0300

   155

#define HV_M_STATUS_SPEED_1000            0x0200

   156

#define HV_M_STATUS_LINK_UP               0x0040

   157

   158

#define E1000_ICH_FWSM_PCIM2PCI		0x01000000 /* ME PCIm-to-PCI active */

   159

#define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000

   160

   161

/* Time to wait before putting the device into D3 if there's no link (in ms). */

   162

#define LINK_TIMEOUT		100

   163

   164

#define DEFAULT_RDTR			0

   165

#define DEFAULT_RADV			8

   166

#define BURST_RDTR			0x20

   167

#define BURST_RADV			0x20

   168

   169

/*

   170

 * in the case of WTHRESH, it appears at least the 82571/2 hardware

   171

 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when

   172

 * WTHRESH=4, and since we want 64 bytes at a time written back, set

   173

 * it to 5

   174

 */

   175

#define E1000_TXDCTL_DMA_BURST_ENABLE                          \

   176

	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \

   177

	 E1000_TXDCTL_COUNT_DESC |                             \

   178

	 (5 << 16) | /* wthresh must be +1 more than desired */\

   179

	 (1 << 8)  | /* hthresh */                             \

   180

	 0x1f)       /* pthresh */

   181

   182

#define E1000_RXDCTL_DMA_BURST_ENABLE                          \

   183

	(0x01000000 | /* set descriptor granularity */         \

   184

	 (4 << 16)  | /* set writeback threshold    */         \

   185

	 (4 << 8)   | /* set prefetch threshold     */         \

   186

	 0x20)        /* set hthresh                */

   187

   188

#define E1000_TIDV_FPD (1 << 31)

   189

#define E1000_RDTR_FPD (1 << 31)

   190

   191

enum e1000_boards {

   192

	board_82571,

   193

	board_82572,

   194

	board_82573,

   195

	board_82574,

   196

	board_82583,

   197

	board_80003es2lan,

   198

	board_ich8lan,

   199

	board_ich9lan,

   200

	board_ich10lan,

   201

	board_pchlan,

   202

	board_pch2lan,

   203

};

   204

   205

struct e1000_ps_page {

   206

	struct page *page;

   207

	u64 dma; /* must be u64 - written to hw */

   208

};

   209

   210

/*

   211

 * wrappers around a pointer to a socket buffer,

   212

 * so a DMA handle can be stored along with the buffer

   213

 */

   214

struct e1000_buffer {

   215

	dma_addr_t dma;

   216

	struct sk_buff *skb;

   217

	union {

   218

		/* Tx */

   219

		struct {

   220

			unsigned long time_stamp;

   221

			u16 length;

   222

			u16 next_to_watch;

   223

			unsigned int segs;

   224

			unsigned int bytecount;

   225

			u16 mapped_as_page;

   226

		};

   227

		/* Rx */

   228

		struct {

   229

			/* arrays of page information for packet split */

   230

			struct e1000_ps_page *ps_pages;

   231

			struct page *page;

   232

		};

   233

	};

   234

};

   235

   236

struct e1000_ring {

   237

	void *desc;			/* pointer to ring memory  */

   238

	dma_addr_t dma;			/* phys address of ring    */

   239

	unsigned int size;		/* length of ring in bytes */

   240

	unsigned int count;		/* number of desc. in ring */

   241

   242

	u16 next_to_use;

   243

	u16 next_to_clean;

   244

   245

	u16 head;

   246

	u16 tail;

   247

   248

	/* array of buffer information structs */

   249

	struct e1000_buffer *buffer_info;

   250

   251

	char name[IFNAMSIZ + 5];

   252

	u32 ims_val;

   253

	u32 itr_val;

   254

	u16 itr_register;

   255

	int set_itr;

   256

   257

	struct sk_buff *rx_skb_top;

   258

};

   259

   260

/* PHY register snapshot values */

   261

struct e1000_phy_regs {

   262

	u16 bmcr;		/* basic mode control register    */

   263

	u16 bmsr;		/* basic mode status register     */

   264

	u16 advertise;		/* auto-negotiation advertisement */

   265

	u16 lpa;		/* link partner ability register  */

   266

	u16 expansion;		/* auto-negotiation expansion reg */

   267

	u16 ctrl1000;		/* 1000BASE-T control register    */

   268

	u16 stat1000;		/* 1000BASE-T status register     */

   269

	u16 estatus;		/* extended status register       */

   270

};

   271

   272

/* board specific private data structure */

   273

struct e1000_adapter {

   274

	struct timer_list watchdog_timer;

   275

	struct timer_list phy_info_timer;

   276

	struct timer_list blink_timer;

   277

   278

	struct work_struct reset_task;

   279

	struct work_struct watchdog_task;

   280

   281

	const struct e1000_info *ei;

   282

   283

	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

   284

	u32 bd_number;

   285

	u32 rx_buffer_len;

   286

	u16 mng_vlan_id;

   287

	u16 link_speed;

   288

	u16 link_duplex;

   289

	u16 eeprom_vers;

   290

   291

	/* track device up/down/testing state */

   292

	unsigned long state;

   293

   294

	/* Interrupt Throttle Rate */

   295

	u32 itr;

   296

	u32 itr_setting;

   297

	u16 tx_itr;

   298

	u16 rx_itr;

   299

   300

	/*

   301

	 * Tx

   302

	 */

   303

	struct e1000_ring *tx_ring /* One per active queue */

   304

						____cacheline_aligned_in_smp;

   305

   306

	struct napi_struct napi;

   307

   308

	unsigned int restart_queue;

   309

	u32 txd_cmd;

   310

   311

	bool detect_tx_hung;

   312

	bool tx_hang_recheck;

   313

	u8 tx_timeout_factor;

   314

   315

	u32 tx_int_delay;

   316

	u32 tx_abs_int_delay;

   317

   318

	unsigned int total_tx_bytes;

   319

	unsigned int total_tx_packets;

   320

	unsigned int total_rx_bytes;

   321

	unsigned int total_rx_packets;

   322

   323

	/* Tx stats */

   324

	u64 tpt_old;

   325

	u64 colc_old;

   326

	u32 gotc;

   327

	u64 gotc_old;

   328

	u32 tx_timeout_count;

   329

	u32 tx_fifo_head;

   330

	u32 tx_head_addr;

   331

	u32 tx_fifo_size;

   332

	u32 tx_dma_failed;

   333

   334

	/*

   335

	 * Rx

   336

	 */

   337

	bool (*clean_rx) (struct e1000_adapter *adapter,

   338

			  int *work_done, int work_to_do)

   339

						____cacheline_aligned_in_smp;

   340

	void (*alloc_rx_buf) (struct e1000_adapter *adapter,

   341

			      int cleaned_count, gfp_t gfp);

   342

	struct e1000_ring *rx_ring;

   343

   344

	u32 rx_int_delay;

   345

	u32 rx_abs_int_delay;

   346

   347

	/* Rx stats */

   348

	u64 hw_csum_err;

   349

	u64 hw_csum_good;

   350

	u64 rx_hdr_split;

   351

	u32 gorc;

   352

	u64 gorc_old;

   353

	u32 alloc_rx_buff_failed;

   354

	u32 rx_dma_failed;

   355

   356

	unsigned int rx_ps_pages;

   357

	u16 rx_ps_bsize0;

   358

	u32 max_frame_size;

   359

	u32 min_frame_size;

   360

   361

	/* OS defined structs */

   362

	struct net_device *netdev;

   363

	struct pci_dev *pdev;

   364

   365

	/* structs defined in e1000_hw.h */

   366

	struct e1000_hw hw;

   367

   368

	spinlock_t stats64_lock;

   369

	struct e1000_hw_stats stats;

   370

	struct e1000_phy_info phy_info;

   371

	struct e1000_phy_stats phy_stats;

   372

   373

	/* Snapshot of PHY registers */

   374

	struct e1000_phy_regs phy_regs;

   375

   376

	struct e1000_ring test_tx_ring;

   377

	struct e1000_ring test_rx_ring;

   378

	u32 test_icr;

   379

   380

	u32 msg_enable;

   381

	unsigned int num_vectors;

   382

	struct msix_entry *msix_entries;

   383

	int int_mode;

   384

	u32 eiac_mask;

   385

   386

	u32 eeprom_wol;

   387

	u32 wol;

   388

	u32 pba;

   389

	u32 max_hw_frame_size;

   390

   391

	bool fc_autoneg;

   392

   393

	unsigned int flags;

   394

	unsigned int flags2;

   395

	struct work_struct downshift_task;

   396

	struct work_struct update_phy_task;

   397

	struct work_struct print_hang_task;

   398

   399

	bool idle_check;

   400

	int phy_hang_count;

   401

};

   402

   403

struct e1000_info {

   404

	enum e1000_mac_type	mac;

   405

	unsigned int		flags;

   406

	unsigned int		flags2;

   407

	u32			pba;

   408

	u32			max_hw_frame_size;

   409

	s32			(*get_variants)(struct e1000_adapter *);

   410

	const struct e1000_mac_operations *mac_ops;

   411

	const struct e1000_phy_operations *phy_ops;

   412

	const struct e1000_nvm_operations *nvm_ops;

   413

};

   414

   415

/* hardware capability, feature, and workaround flags */

   416

#define FLAG_HAS_AMT                      (1 << 0)

   417

#define FLAG_HAS_FLASH                    (1 << 1)

   418

#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)

   419

#define FLAG_HAS_WOL                      (1 << 3)

   420

#define FLAG_HAS_ERT                      (1 << 4)

   421

#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)

   422

#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)

   423

#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)

   424

#define FLAG_READ_ONLY_NVM                (1 << 8)

   425

#define FLAG_IS_ICH                       (1 << 9)

   426

#define FLAG_HAS_MSIX                     (1 << 10)

   427

#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)

   428

#define FLAG_IS_QUAD_PORT_A               (1 << 12)

   429

#define FLAG_IS_QUAD_PORT                 (1 << 13)

   430

#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN   (1 << 14)

   431

#define FLAG_APME_IN_WUC                  (1 << 15)

   432

#define FLAG_APME_IN_CTRL3                (1 << 16)

   433

#define FLAG_APME_CHECK_PORT_B            (1 << 17)

   434

#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)

   435

#define FLAG_NO_WAKE_UCAST                (1 << 19)

   436

#define FLAG_MNG_PT_ENABLED               (1 << 20)

   437

#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)

   438

#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)

   439

#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)

   440

#define FLAG_RX_NEEDS_RESTART             (1 << 24)

   441

#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)

   442

#define FLAG_SMART_POWER_DOWN             (1 << 26)

   443

#define FLAG_MSI_ENABLED                  (1 << 27)

   444

/* reserved (1 << 28) */

   445

#define FLAG_TSO_FORCE                    (1 << 29)

   446

#define FLAG_RX_RESTART_NOW               (1 << 30)

   447

#define FLAG_MSI_TEST_FAILED              (1 << 31)

   448

   449

#define FLAG2_CRC_STRIPPING               (1 << 0)

   450

#define FLAG2_HAS_PHY_WAKEUP              (1 << 1)

   451

#define FLAG2_IS_DISCARDING               (1 << 2)

   452

#define FLAG2_DISABLE_ASPM_L1             (1 << 3)

   453

#define FLAG2_HAS_PHY_STATS               (1 << 4)

   454

#define FLAG2_HAS_EEE                     (1 << 5)

   455

#define FLAG2_DMA_BURST                   (1 << 6)

   456

#define FLAG2_DISABLE_ASPM_L0S            (1 << 7)

   457

#define FLAG2_DISABLE_AIM                 (1 << 8)

   458

#define FLAG2_CHECK_PHY_HANG              (1 << 9)

   459

#define FLAG2_NO_DISABLE_RX               (1 << 10)

   460

#define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)

   461

   462

#define E1000_RX_DESC_PS(R, i)	    \

   463

	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))

   464

#define E1000_RX_DESC_EXT(R, i)	    \

   465

	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))

   466

#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))

   467

#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)

   468

#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)

   469

   470

enum e1000_state_t {

   471

	__E1000_TESTING,

   472

	__E1000_RESETTING,

   473

	__E1000_ACCESS_SHARED_RESOURCE,

   474

	__E1000_DOWN

   475

};

   476

   477

enum latency_range {

   478

	lowest_latency = 0,

   479

	low_latency = 1,

   480

	bulk_latency = 2,

   481

	latency_invalid = 255

   482

};

   483

   484

extern char e1000e_driver_name[];

   485

extern const char e1000e_driver_version[];

   486

   487

extern void e1000e_check_options(struct e1000_adapter *adapter);

   488

extern void e1000e_set_ethtool_ops(struct net_device *netdev);

   489

   490

extern int e1000e_up(struct e1000_adapter *adapter);

   491

extern void e1000e_down(struct e1000_adapter *adapter);

   492

extern void e1000e_reinit_locked(struct e1000_adapter *adapter);

   493

extern void e1000e_reset(struct e1000_adapter *adapter);

   494

extern void e1000e_power_up_phy(struct e1000_adapter *adapter);

   495

extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);

   496

extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);

   497

extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);

   498

extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);

   499

extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,

   500

                                                    struct rtnl_link_stats64

   501

                                                    *stats);

   502

extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);

   503

extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);

   504

extern void e1000e_get_hw_control(struct e1000_adapter *adapter);

   505

extern void e1000e_release_hw_control(struct e1000_adapter *adapter);

   506

   507

extern unsigned int copybreak;

   508

   509

extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);

   510

   511

extern const struct e1000_info e1000_82571_info;

   512

extern const struct e1000_info e1000_82572_info;

   513

extern const struct e1000_info e1000_82573_info;

   514

extern const struct e1000_info e1000_82574_info;

   515

extern const struct e1000_info e1000_82583_info;

   516

extern const struct e1000_info e1000_ich8_info;

   517

extern const struct e1000_info e1000_ich9_info;

   518

extern const struct e1000_info e1000_ich10_info;

   519

extern const struct e1000_info e1000_pch_info;

   520

extern const struct e1000_info e1000_pch2_info;

   521

extern const struct e1000_info e1000_es2_info;

   522

   523

extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,

   524

					 u32 pba_num_size);

   525

   526

extern s32  e1000e_commit_phy(struct e1000_hw *hw);

   527

   528

extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);

   529

   530

extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);