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/* Intel(R) Gigabit Ethernet Linux driver

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 * Copyright(c) 2007-2014 Intel Corporation.

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

     6

 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

     8

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

     9

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    10

 * more details.

    11

 *

    12

 * You should have received a copy of the GNU General Public License along with

    13

 * this program; if not, see <http://www.gnu.org/licenses/>.

    14

 *

    15

 * The full GNU General Public License is included in this distribution in

    16

 * the file called "COPYING".

    17

 *

    18

 * Contact Information:

    19

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    20

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    21

 */

    22

    23

#ifndef _E1000_HW_H_

    24

#define _E1000_HW_H_

    25

    26

#include <linux/types.h>

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#include <linux/delay.h>

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#include <linux/io.h>

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#include <linux/netdevice.h>

    30

    31

#include "e1000_regs-3.18-ethercat.h"

    32

#include "e1000_defines-3.18-ethercat.h"

    33

    34

struct e1000_hw;

    35

    36

#define E1000_DEV_ID_82576			0x10C9

    37

#define E1000_DEV_ID_82576_FIBER		0x10E6

    38

#define E1000_DEV_ID_82576_SERDES		0x10E7

    39

#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8

    40

#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526

    41

#define E1000_DEV_ID_82576_NS			0x150A

    42

#define E1000_DEV_ID_82576_NS_SERDES		0x1518

    43

#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D

    44

#define E1000_DEV_ID_82575EB_COPPER		0x10A7

    45

#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9

    46

#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6

    47

#define E1000_DEV_ID_82580_COPPER		0x150E

    48

#define E1000_DEV_ID_82580_FIBER		0x150F

    49

#define E1000_DEV_ID_82580_SERDES		0x1510

    50

#define E1000_DEV_ID_82580_SGMII		0x1511

    51

#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516

    52

#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527

    53

#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438

    54

#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A

    55

#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C

    56

#define E1000_DEV_ID_DH89XXCC_SFP		0x0440

    57

#define E1000_DEV_ID_I350_COPPER		0x1521

    58

#define E1000_DEV_ID_I350_FIBER			0x1522

    59

#define E1000_DEV_ID_I350_SERDES		0x1523

    60

#define E1000_DEV_ID_I350_SGMII			0x1524

    61

#define E1000_DEV_ID_I210_COPPER		0x1533

    62

#define E1000_DEV_ID_I210_FIBER			0x1536

    63

#define E1000_DEV_ID_I210_SERDES		0x1537

    64

#define E1000_DEV_ID_I210_SGMII			0x1538

    65

#define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B

    66

#define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C

    67

#define E1000_DEV_ID_I211_COPPER		0x1539

    68

#define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40

    69

#define E1000_DEV_ID_I354_SGMII			0x1F41

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#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45

    71

    72

#define E1000_REVISION_2 2

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#define E1000_REVISION_4 4

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    75

#define E1000_FUNC_0     0

    76

#define E1000_FUNC_1     1

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#define E1000_FUNC_2     2

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#define E1000_FUNC_3     3

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    80

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0

    81

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3

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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6

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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9

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    85

enum e1000_mac_type {

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	e1000_undefined = 0,

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	e1000_82575,

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	e1000_82576,

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	e1000_82580,

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	e1000_i350,

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	e1000_i354,

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	e1000_i210,

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	e1000_i211,

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	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */

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};

    96

    97

enum e1000_media_type {

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	e1000_media_type_unknown = 0,

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	e1000_media_type_copper = 1,

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	e1000_media_type_fiber = 2,

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	e1000_media_type_internal_serdes = 3,

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	e1000_num_media_types

   103

};

   104

   105

enum e1000_nvm_type {

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	e1000_nvm_unknown = 0,

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	e1000_nvm_none,

   108

	e1000_nvm_eeprom_spi,

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	e1000_nvm_flash_hw,

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	e1000_nvm_invm,

   111

	e1000_nvm_flash_sw

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};

   113

   114

enum e1000_nvm_override {

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	e1000_nvm_override_none = 0,

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	e1000_nvm_override_spi_small,

   117

	e1000_nvm_override_spi_large,

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};

   119

   120

enum e1000_phy_type {

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	e1000_phy_unknown = 0,

   122

	e1000_phy_none,

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	e1000_phy_m88,

   124

	e1000_phy_igp,

   125

	e1000_phy_igp_2,

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	e1000_phy_gg82563,

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	e1000_phy_igp_3,

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	e1000_phy_ife,

   129

	e1000_phy_82580,

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	e1000_phy_i210,

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};

   132

   133

enum e1000_bus_type {

   134

	e1000_bus_type_unknown = 0,

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	e1000_bus_type_pci,

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	e1000_bus_type_pcix,

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	e1000_bus_type_pci_express,

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	e1000_bus_type_reserved

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};

   140

   141

enum e1000_bus_speed {

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	e1000_bus_speed_unknown = 0,

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	e1000_bus_speed_33,

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	e1000_bus_speed_66,

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	e1000_bus_speed_100,

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	e1000_bus_speed_120,

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	e1000_bus_speed_133,

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	e1000_bus_speed_2500,

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	e1000_bus_speed_5000,

   150

	e1000_bus_speed_reserved

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};

   152

   153

enum e1000_bus_width {

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	e1000_bus_width_unknown = 0,

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	e1000_bus_width_pcie_x1,

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	e1000_bus_width_pcie_x2,

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	e1000_bus_width_pcie_x4 = 4,

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	e1000_bus_width_pcie_x8 = 8,

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	e1000_bus_width_32,

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	e1000_bus_width_64,

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	e1000_bus_width_reserved

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};

   163

   164

enum e1000_1000t_rx_status {

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	e1000_1000t_rx_status_not_ok = 0,

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	e1000_1000t_rx_status_ok,

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	e1000_1000t_rx_status_undefined = 0xFF

   168

};

   169

   170

enum e1000_rev_polarity {

   171

	e1000_rev_polarity_normal = 0,

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	e1000_rev_polarity_reversed,

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	e1000_rev_polarity_undefined = 0xFF

   174

};

   175

   176

enum e1000_fc_mode {

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	e1000_fc_none = 0,

   178

	e1000_fc_rx_pause,

   179

	e1000_fc_tx_pause,

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	e1000_fc_full,

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	e1000_fc_default = 0xFF

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};

   183

   184

/* Statistics counters collected by the MAC */

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struct e1000_hw_stats {

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	u64 crcerrs;

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	u64 algnerrc;

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	u64 symerrs;

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	u64 rxerrc;

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	u64 mpc;

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	u64 scc;

   192

	u64 ecol;

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	u64 mcc;

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	u64 latecol;

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	u64 colc;

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	u64 dc;

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	u64 tncrs;

   198

	u64 sec;

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	u64 cexterr;

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	u64 rlec;

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	u64 xonrxc;

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	u64 xontxc;

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	u64 xoffrxc;

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	u64 xofftxc;

   205

	u64 fcruc;

   206

	u64 prc64;

   207

	u64 prc127;

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	u64 prc255;

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	u64 prc511;

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	u64 prc1023;

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	u64 prc1522;

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	u64 gprc;

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	u64 bprc;

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	u64 mprc;

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	u64 gptc;

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	u64 gorc;

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	u64 gotc;

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	u64 rnbc;

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	u64 ruc;

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	u64 rfc;

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	u64 roc;

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	u64 rjc;

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	u64 mgprc;

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	u64 mgpdc;

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	u64 mgptc;

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	u64 tor;

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	u64 tot;

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	u64 tpr;

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	u64 tpt;

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	u64 ptc64;

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	u64 ptc127;

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	u64 ptc255;

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	u64 ptc511;

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	u64 ptc1023;

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	u64 ptc1522;

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	u64 mptc;

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	u64 bptc;

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	u64 tsctc;

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	u64 tsctfc;

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	u64 iac;

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	u64 icrxptc;

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	u64 icrxatc;

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	u64 ictxptc;

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	u64 ictxatc;

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	u64 ictxqec;

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	u64 ictxqmtc;

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	u64 icrxdmtc;

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	u64 icrxoc;

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	u64 cbtmpc;

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	u64 htdpmc;

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	u64 cbrdpc;

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	u64 cbrmpc;

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	u64 rpthc;

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	u64 hgptc;

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	u64 htcbdpc;

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	u64 hgorc;

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	u64 hgotc;

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	u64 lenerrs;

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	u64 scvpc;

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	u64 hrmpc;

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	u64 doosync;

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	u64 o2bgptc;

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	u64 o2bspc;

   264

	u64 b2ospc;

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	u64 b2ogprc;

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};

   267

   268

struct e1000_host_mng_dhcp_cookie {

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	u32 signature;

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	u8  status;

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	u8  reserved0;

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	u16 vlan_id;

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	u32 reserved1;

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	u16 reserved2;

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	u8  reserved3;

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	u8  checksum;

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};

   278

   279

/* Host Interface "Rev 1" */

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struct e1000_host_command_header {

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	u8 command_id;

   282

	u8 command_length;

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	u8 command_options;

   284

	u8 checksum;

   285

};

   286

   287

#define E1000_HI_MAX_DATA_LENGTH     252

   288

struct e1000_host_command_info {

   289

	struct e1000_host_command_header command_header;

   290

	u8 command_data[E1000_HI_MAX_DATA_LENGTH];

   291

};

   292

   293

/* Host Interface "Rev 2" */

   294

struct e1000_host_mng_command_header {

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	u8  command_id;

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	u8  checksum;

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	u16 reserved1;

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	u16 reserved2;

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	u16 command_length;

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};

   301

   302

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8

   303

struct e1000_host_mng_command_info {

   304

	struct e1000_host_mng_command_header command_header;

   305

	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];

   306

};

   307

   308

#include "e1000_mac-3.18-ethercat.h"

   309

#include "e1000_phy-3.18-ethercat.h"

   310

#include "e1000_nvm-3.18-ethercat.h"

   311

#include "e1000_mbx-3.18-ethercat.h"

   312

   313

struct e1000_mac_operations {

   314

	s32 (*check_for_link)(struct e1000_hw *);

   315

	s32 (*reset_hw)(struct e1000_hw *);

   316

	s32 (*init_hw)(struct e1000_hw *);

   317

	bool (*check_mng_mode)(struct e1000_hw *);

   318

	s32 (*setup_physical_interface)(struct e1000_hw *);

   319

	void (*rar_set)(struct e1000_hw *, u8 *, u32);

   320

	s32 (*read_mac_addr)(struct e1000_hw *);

   321

	s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);

   322

	s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);

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	void (*release_swfw_sync)(struct e1000_hw *, u16);

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#ifdef CONFIG_IGB_HWMON

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	s32 (*get_thermal_sensor_data)(struct e1000_hw *);

   326

	s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);

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#endif

   328

   329

};

   330

   331

struct e1000_phy_operations {

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	s32 (*acquire)(struct e1000_hw *);

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	s32 (*check_polarity)(struct e1000_hw *);

   334

	s32 (*check_reset_block)(struct e1000_hw *);

   335

	s32 (*force_speed_duplex)(struct e1000_hw *);

   336

	s32 (*get_cfg_done)(struct e1000_hw *hw);

   337

	s32 (*get_cable_length)(struct e1000_hw *);

   338

	s32 (*get_phy_info)(struct e1000_hw *);

   339

	s32 (*read_reg)(struct e1000_hw *, u32, u16 *);

   340

	void (*release)(struct e1000_hw *);

   341

	s32 (*reset)(struct e1000_hw *);

   342

	s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);

   343

	s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);

   344

	s32 (*write_reg)(struct e1000_hw *, u32, u16);

   345

	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);

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	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);

   347

};

   348

   349

struct e1000_nvm_operations {

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	s32 (*acquire)(struct e1000_hw *);

   351

	s32 (*read)(struct e1000_hw *, u16, u16, u16 *);

   352

	void (*release)(struct e1000_hw *);

   353

	s32 (*write)(struct e1000_hw *, u16, u16, u16 *);

   354

	s32 (*update)(struct e1000_hw *);

   355

	s32 (*validate)(struct e1000_hw *);

   356

	s32 (*valid_led_default)(struct e1000_hw *, u16 *);

   357

};

   358

   359

#define E1000_MAX_SENSORS		3

   360

   361

struct e1000_thermal_diode_data {

   362

	u8 location;

   363

	u8 temp;

   364

	u8 caution_thresh;

   365

	u8 max_op_thresh;

   366

};

   367

   368

struct e1000_thermal_sensor_data {

   369

	struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];

   370

};

   371

   372

struct e1000_info {

   373

	s32 (*get_invariants)(struct e1000_hw *);

   374

	struct e1000_mac_operations *mac_ops;

   375

	struct e1000_phy_operations *phy_ops;

   376

	struct e1000_nvm_operations *nvm_ops;

   377

};

   378

   379

extern const struct e1000_info e1000_82575_info;

   380

   381

struct e1000_mac_info {

   382

	struct e1000_mac_operations ops;

   383

   384

	u8 addr[6];

   385

	u8 perm_addr[6];

   386

   387

	enum e1000_mac_type type;

   388

   389

	u32 ledctl_default;

   390

	u32 ledctl_mode1;

   391

	u32 ledctl_mode2;

   392

	u32 mc_filter_type;

   393

	u32 txcw;

   394

   395

	u16 mta_reg_count;

   396

	u16 uta_reg_count;

   397

   398

	/* Maximum size of the MTA register table in all supported adapters */

   399

	#define MAX_MTA_REG 128

   400

	u32 mta_shadow[MAX_MTA_REG];

   401

	u16 rar_entry_count;

   402

   403

	u8  forced_speed_duplex;

   404

   405

	bool adaptive_ifs;

   406

	bool arc_subsystem_valid;

   407

	bool asf_firmware_present;

   408

	bool autoneg;

   409

	bool autoneg_failed;

   410

	bool disable_hw_init_bits;

   411

	bool get_link_status;

   412

	bool ifs_params_forced;

   413

	bool in_ifs_mode;

   414

	bool report_tx_early;

   415

	bool serdes_has_link;

   416

	bool tx_pkt_filtering;

   417

	struct e1000_thermal_sensor_data thermal_sensor_data;

   418

};

   419

   420

struct e1000_phy_info {

   421

	struct e1000_phy_operations ops;

   422

   423

	enum e1000_phy_type type;

   424

   425

	enum e1000_1000t_rx_status local_rx;

   426

	enum e1000_1000t_rx_status remote_rx;

   427

	enum e1000_ms_type ms_type;

   428

	enum e1000_ms_type original_ms_type;

   429

	enum e1000_rev_polarity cable_polarity;

   430

	enum e1000_smart_speed smart_speed;

   431

   432

	u32 addr;

   433

	u32 id;

   434

	u32 reset_delay_us; /* in usec */

   435

	u32 revision;

   436

   437

	enum e1000_media_type media_type;

   438

   439

	u16 autoneg_advertised;

   440

	u16 autoneg_mask;

   441

	u16 cable_length;

   442

	u16 max_cable_length;

   443

	u16 min_cable_length;

   444

   445

	u8 mdix;

   446

   447

	bool disable_polarity_correction;

   448

	bool is_mdix;

   449

	bool polarity_correction;

   450

	bool reset_disable;

   451

	bool speed_downgraded;

   452

	bool autoneg_wait_to_complete;

   453

};

   454

   455

struct e1000_nvm_info {

   456

	struct e1000_nvm_operations ops;

   457

	enum e1000_nvm_type type;

   458

	enum e1000_nvm_override override;

   459

   460

	u32 flash_bank_size;

   461

	u32 flash_base_addr;

   462

   463

	u16 word_size;

   464

	u16 delay_usec;

   465

	u16 address_bits;

   466

	u16 opcode_bits;

   467

	u16 page_size;

   468

};

   469

   470

struct e1000_bus_info {

   471

	enum e1000_bus_type type;

   472

	enum e1000_bus_speed speed;

   473

	enum e1000_bus_width width;

   474

   475

	u32 snoop;

   476

   477

	u16 func;

   478

	u16 pci_cmd_word;

   479

};

   480

   481

struct e1000_fc_info {

   482

	u32 high_water;     /* Flow control high-water mark */

   483

	u32 low_water;      /* Flow control low-water mark */

   484

	u16 pause_time;     /* Flow control pause timer */

   485

	bool send_xon;      /* Flow control send XON */

   486

	bool strict_ieee;   /* Strict IEEE mode */

   487

	enum e1000_fc_mode current_mode; /* Type of flow control */

   488

	enum e1000_fc_mode requested_mode;

   489

};

   490

   491

struct e1000_mbx_operations {

   492

	s32 (*init_params)(struct e1000_hw *hw);

   493

	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);

   494

	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);

   495

	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);

   496

	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);

   497

	s32 (*check_for_msg)(struct e1000_hw *, u16);

   498

	s32 (*check_for_ack)(struct e1000_hw *, u16);

   499

	s32 (*check_for_rst)(struct e1000_hw *, u16);

   500

};

   501

   502

struct e1000_mbx_stats {

   503

	u32 msgs_tx;

   504

	u32 msgs_rx;

   505

   506

	u32 acks;

   507

	u32 reqs;

   508

	u32 rsts;

   509

};

   510

   511

struct e1000_mbx_info {

   512

	struct e1000_mbx_operations ops;

   513

	struct e1000_mbx_stats stats;

   514

	u32 timeout;

   515

	u32 usec_delay;

   516

	u16 size;

   517

};

   518

   519

struct e1000_dev_spec_82575 {

   520

	bool sgmii_active;

   521

	bool global_device_reset;

   522

	bool eee_disable;

   523

	bool clear_semaphore_once;

   524

	struct e1000_sfp_flags eth_flags;

   525

	bool module_plugged;

   526

	u8 media_port;

   527

	bool media_changed;

   528

	bool mas_capable;

   529

};

   530