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/* Intel(R) Gigabit Ethernet Linux driver

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 * Copyright(c) 2007-2014 Intel Corporation.

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

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 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

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 *

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 * You should have received a copy of the GNU General Public License along with

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 * this program; if not, see <http://www.gnu.org/licenses/>.

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 *

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 * The full GNU General Public License is included in this distribution in

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 * the file called "COPYING".

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 *

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 * Contact Information:

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 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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 */

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#ifndef _E1000_DEFINES_H_

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#define _E1000_DEFINES_H_

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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */

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#define REQ_TX_DESCRIPTOR_MULTIPLE  8

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#define REQ_RX_DESCRIPTOR_MULTIPLE  8

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    31

/* Definitions for power management and wakeup registers */

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/* Wake Up Control */

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#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */

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    35

/* Wake Up Filter Control */

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#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */

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#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */

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#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */

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#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */

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#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */

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    42

/* Extended Device Control */

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#define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */

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#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */

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#define E1000_CTRL_EXT_SDP2_DIR  0x00000400 /* SDP2 Data direction */

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#define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* SDP3 Data direction */

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    48

/* Physical Func Reset Done Indication */

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#define E1000_CTRL_EXT_PFRSTD	0x00004000

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#define E1000_CTRL_EXT_SDLPE	0X00040000  /* SerDes Low Power Enable */

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#define E1000_CTRL_EXT_LINK_MODE_MASK	0x00C00000

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#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00C00000

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#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX	0x00400000

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#define E1000_CTRL_EXT_LINK_MODE_SGMII	0x00800000

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#define E1000_CTRL_EXT_LINK_MODE_GMII	0x00000000

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#define E1000_CTRL_EXT_EIAME	0x01000000

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#define E1000_CTRL_EXT_IRCA		0x00000001

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/* Interrupt delay cancellation */

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/* Driver loaded bit for FW */

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#define E1000_CTRL_EXT_DRV_LOAD       0x10000000

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/* Interrupt acknowledge Auto-mask */

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/* Clear Interrupt timers after IMS clear */

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/* packet buffer parity error detection enabled */

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/* descriptor FIFO parity error detection enable */

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#define E1000_CTRL_EXT_PBA_CLR		0x80000000 /* PBA Clear */

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#define E1000_CTRL_EXT_PHYPDEN		0x00100000

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#define E1000_I2CCMD_REG_ADDR_SHIFT	16

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#define E1000_I2CCMD_PHY_ADDR_SHIFT	24

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#define E1000_I2CCMD_OPCODE_READ	0x08000000

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#define E1000_I2CCMD_OPCODE_WRITE	0x00000000

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#define E1000_I2CCMD_READY		0x20000000

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#define E1000_I2CCMD_ERROR		0x80000000

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#define E1000_I2CCMD_SFP_DATA_ADDR(a)	(0x0000 + (a))

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#define E1000_I2CCMD_SFP_DIAG_ADDR(a)	(0x0100 + (a))

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#define E1000_MAX_SGMII_PHY_REG_ADDR	255

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#define E1000_I2CCMD_PHY_TIMEOUT	200

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#define E1000_IVAR_VALID		0x80

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#define E1000_GPIE_NSICR		0x00000001

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#define E1000_GPIE_MSIX_MODE		0x00000010

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#define E1000_GPIE_EIAME		0x40000000

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#define E1000_GPIE_PBA			0x80000000

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    83

/* Receive Descriptor bit definitions */

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#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */

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#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */

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#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */

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#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */

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#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */

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#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */

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#define E1000_RXD_STAT_TS       0x10000 /* Pkt was time stamped */

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#define E1000_RXDEXT_STATERR_LB    0x00040000

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#define E1000_RXDEXT_STATERR_CE    0x01000000

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#define E1000_RXDEXT_STATERR_SE    0x02000000

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#define E1000_RXDEXT_STATERR_SEQ   0x04000000

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#define E1000_RXDEXT_STATERR_CXE   0x10000000

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#define E1000_RXDEXT_STATERR_TCPE  0x20000000

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#define E1000_RXDEXT_STATERR_IPE   0x40000000

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#define E1000_RXDEXT_STATERR_RXE   0x80000000

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   101

/* Same mask, but for extended and packet split descriptors */

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#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \

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	E1000_RXDEXT_STATERR_CE  |            \

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	E1000_RXDEXT_STATERR_SE  |            \

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	E1000_RXDEXT_STATERR_SEQ |            \

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	E1000_RXDEXT_STATERR_CXE |            \

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	E1000_RXDEXT_STATERR_RXE)

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#define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000

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#define E1000_MRQC_RSS_FIELD_IPV4              0x00020000

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#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000

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#define E1000_MRQC_RSS_FIELD_IPV6              0x00100000

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#define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000

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   115

   116

/* Management Control */

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#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */

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#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */

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#define E1000_MANC_EN_BMC2OS     0x10000000 /* OSBMC is Enabled or not */

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/* Enable Neighbor Discovery Filtering */

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#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */

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#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */

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/* Enable MAC address filtering */

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#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000

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   126

/* Receive Control */

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#define E1000_RCTL_EN             0x00000002    /* enable */

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#define E1000_RCTL_SBP            0x00000004    /* store bad packet */

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#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */

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#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */

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#define E1000_RCTL_LPE            0x00000020    /* long packet enable */

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#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */

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#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */

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#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */

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#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */

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#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */

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#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */

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#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */

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#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */

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#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */

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#define E1000_RCTL_DPF            0x00400000    /* Discard Pause Frames */

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#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */

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#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */

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/* Use byte values for the following shift parameters

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 * Usage:

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 *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &

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 *                  E1000_PSRCTL_BSIZE0_MASK) |

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 *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &

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 *                  E1000_PSRCTL_BSIZE1_MASK) |

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 *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &

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 *                  E1000_PSRCTL_BSIZE2_MASK) |

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 *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;

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 *                  E1000_PSRCTL_BSIZE3_MASK))

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 * where value0 = [128..16256],  default=256

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 *       value1 = [1024..64512], default=4096

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 *       value2 = [0..64512],    default=4096

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 *       value3 = [0..64512],    default=0

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 */

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#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F

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#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00

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#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000

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#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000

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#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */

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#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */

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#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */

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#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */

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   171

/* SWFW_SYNC Definitions */

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#define E1000_SWFW_EEP_SM   0x1

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#define E1000_SWFW_PHY0_SM  0x2

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#define E1000_SWFW_PHY1_SM  0x4

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#define E1000_SWFW_PHY2_SM  0x20

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#define E1000_SWFW_PHY3_SM  0x40

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   178

/* FACTPS Definitions */

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/* Device Control */

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#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */

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#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */

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#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */

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#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */

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#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */

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#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */

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#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */

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#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */

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#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */

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#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */

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#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */

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/* Defined polarity of Dock/Undock indication in SDP[0] */

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/* Reset both PHY ports, through PHYRST_N pin */

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/* enable link status from external LINK_0 and LINK_1 pins */

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#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */

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#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */

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#define E1000_CTRL_SDP0_DIR 0x00400000  /* SDP0 Data direction */

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#define E1000_CTRL_SDP1_DIR 0x00800000  /* SDP1 Data direction */

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#define E1000_CTRL_RST      0x04000000  /* Global reset */

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#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */

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#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */

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#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */

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#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */

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/* Initiate an interrupt to manageability engine */

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#define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */

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   206

/* Bit definitions for the Management Data IO (MDIO) and Management Data

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 * Clock (MDC) pins in the Device Control Register.

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 */

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#define E1000_CONNSW_ENRGSRC             0x4

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#define E1000_CONNSW_PHYSD		0x400

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#define E1000_CONNSW_PHY_PDN		0x800

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#define E1000_CONNSW_SERDESD		0x200

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#define E1000_CONNSW_AUTOSENSE_CONF	0x2

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#define E1000_CONNSW_AUTOSENSE_EN	0x1

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#define E1000_PCS_CFG_PCS_EN             8

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#define E1000_PCS_LCTL_FLV_LINK_UP       1

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#define E1000_PCS_LCTL_FSV_100           2

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#define E1000_PCS_LCTL_FSV_1000          4

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#define E1000_PCS_LCTL_FDV_FULL          8

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#define E1000_PCS_LCTL_FSD               0x10

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#define E1000_PCS_LCTL_FORCE_LINK        0x20

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#define E1000_PCS_LCTL_FORCE_FCTRL       0x80

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#define E1000_PCS_LCTL_AN_ENABLE         0x10000

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#define E1000_PCS_LCTL_AN_RESTART        0x20000

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#define E1000_PCS_LCTL_AN_TIMEOUT        0x40000

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#define E1000_ENABLE_SERDES_LOOPBACK     0x0410

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#define E1000_PCS_LSTS_LINK_OK           1

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#define E1000_PCS_LSTS_SPEED_100         2

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#define E1000_PCS_LSTS_SPEED_1000        4

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#define E1000_PCS_LSTS_DUPLEX_FULL       8

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#define E1000_PCS_LSTS_SYNK_OK           0x10

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   235

/* Device Status */

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#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */

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#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */

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#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */

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#define E1000_STATUS_FUNC_SHIFT 2

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#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */

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#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */

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#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */

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#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */

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/* Change in Dock/Undock state. Clear on write '0'. */

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/* Status of Master requests. */

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#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000

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/* BMC external code execution disabled */

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#define E1000_STATUS_2P5_SKU		0x00001000 /* Val of 2.5GBE SKU strap */

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#define E1000_STATUS_2P5_SKU_OVER	0x00002000 /* Val of 2.5GBE SKU Over */

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/* Constants used to intrepret the masked PCI-X bus speed. */

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#define SPEED_10    10

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#define SPEED_100   100

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#define SPEED_1000  1000

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#define SPEED_2500  2500

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#define HALF_DUPLEX 1

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#define FULL_DUPLEX 2

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#define ADVERTISE_10_HALF                 0x0001

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#define ADVERTISE_10_FULL                 0x0002

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#define ADVERTISE_100_HALF                0x0004

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#define ADVERTISE_100_FULL                0x0008

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#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */

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#define ADVERTISE_1000_FULL               0x0020

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/* 1000/H is not supported, nor spec-compliant. */

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#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \

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				ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \

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						      ADVERTISE_1000_FULL)

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#define E1000_ALL_NOT_GIG      (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \

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				ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

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#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

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#define E1000_ALL_10_SPEED     (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL)

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#define E1000_ALL_FULL_DUPLEX  (ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \

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						      ADVERTISE_1000_FULL)

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#define E1000_ALL_HALF_DUPLEX  (ADVERTISE_10_HALF  |  ADVERTISE_100_HALF)

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   280

#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX

   281

   282

/* LED Control */

   283

#define E1000_LEDCTL_LED0_MODE_SHIFT	0

   284

#define E1000_LEDCTL_LED0_BLINK		0x00000080

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#define E1000_LEDCTL_LED0_MODE_MASK	0x0000000F

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#define E1000_LEDCTL_LED0_IVRT		0x00000040

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   288

#define E1000_LEDCTL_MODE_LED_ON        0xE

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#define E1000_LEDCTL_MODE_LED_OFF       0xF

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   291

/* Transmit Descriptor bit definitions */

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#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */

   293

#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */

   294

#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */

   295

#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

   296

#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */

   297

#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

   298

#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */

   299

/* Extended desc bits for Linksec and timesync */

   300

   301

/* Transmit Control */

   302

#define E1000_TCTL_EN     0x00000002    /* enable tx */

   303

#define E1000_TCTL_PSP    0x00000008    /* pad short packets */

   304

#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */

   305

#define E1000_TCTL_COLD   0x003ff000    /* collision distance */

   306

#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */

   307

   308

/* DMA Coalescing register fields */

   309

#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coal Watchdog Timer */

   310

#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coal Rx Threshold */

   311

#define E1000_DMACR_DMACTHR_SHIFT       16

   312

#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe trans */

   313

#define E1000_DMACR_DMAC_LX_SHIFT       28

   314

#define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */

   315

/* DMA Coalescing BMC-to-OS Watchdog Enable */

   316

#define E1000_DMACR_DC_BMC2OSW_EN	0x00008000

   317

   318

#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coal Tx Threshold */

   319

   320

#define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */

   321

   322

#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Rx Traffic Rate Thresh */

   323

#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rx pkt rate curr window */

   324

   325

#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rx Current Cnt */

   326

   327

#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* FC Rx Thresh High val */

   328

#define E1000_FCRTC_RTH_COAL_SHIFT      4

   329

#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision */

   330

   331

/* Timestamp in Rx buffer */

   332

#define E1000_RXPBS_CFG_TS_EN           0x80000000

   333

   334

#define I210_RXPBSIZE_DEFAULT		0x000000A2 /* RXPBSIZE default */

   335

#define I210_TXPBSIZE_DEFAULT		0x04000014 /* TXPBSIZE default */

   336

   337

/* SerDes Control */

   338

#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400

   339

   340

/* Receive Checksum Control */

   341

#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */

   342

#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */

   343

#define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */

   344

#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */

   345

   346

/* Header split receive */

   347

#define E1000_RFCTL_LEF        0x00040000

   348

   349

/* Collision related configuration parameters */

   350

#define E1000_COLLISION_THRESHOLD       15

   351

#define E1000_CT_SHIFT                  4

   352

#define E1000_COLLISION_DISTANCE        63

   353

#define E1000_COLD_SHIFT                12

   354

   355

/* Ethertype field values */

   356

#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */

   357

   358

#define MAX_JUMBO_FRAME_SIZE    0x3F00

   359

   360

/* PBA constants */

   361

#define E1000_PBA_34K 0x0022

   362

#define E1000_PBA_64K 0x0040    /* 64KB */

   363

   364

/* SW Semaphore Register */

   365

#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */

   366

#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */

   367

   368

/* Interrupt Cause Read */

   369

#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */

   370

#define E1000_ICR_LSC           0x00000004 /* Link Status Change */

   371

#define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */

   372

#define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */

   373

#define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */

   374

#define E1000_ICR_VMMB          0x00000100 /* VM MB event */

   375

#define E1000_ICR_TS            0x00080000 /* Time Sync Interrupt */

   376

#define E1000_ICR_DRSTA         0x40000000 /* Device Reset Asserted */

   377

/* If this bit asserted, the driver should claim the interrupt */

   378

#define E1000_ICR_INT_ASSERTED  0x80000000

   379

/* LAN connected device generates an interrupt */

   380

#define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */

   381

   382

/* Extended Interrupt Cause Read */

   383

#define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */

   384

#define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */

   385

#define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */

   386

#define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */

   387

#define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */

   388

#define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */

   389

#define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */

   390

#define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */

   391

#define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */

   392

/* TCP Timer */

   393

   394

/* This defines the bits that are set in the Interrupt Mask

   395

 * Set/Read Register.  Each bit is documented below:

   396

 *   o RXT0   = Receiver Timer Interrupt (ring 0)

   397

 *   o TXDW   = Transmit Descriptor Written Back

   398

 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)

   399

 *   o RXSEQ  = Receive Sequence Error

   400

 *   o LSC    = Link Status Change

   401

 */

   402

#define IMS_ENABLE_MASK ( \

   403

	E1000_IMS_RXT0   |    \

   404

	E1000_IMS_TXDW   |    \

   405

	E1000_IMS_RXDMT0 |    \

   406

	E1000_IMS_RXSEQ  |    \

   407

	E1000_IMS_LSC    |    \

   408

	E1000_IMS_DOUTSYNC)

   409

   410

/* Interrupt Mask Set */

   411

#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */

   412

#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */

   413

#define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */

   414

#define E1000_IMS_TS        E1000_ICR_TS        /* Time Sync Interrupt */

   415

#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */

   416

#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */

   417

#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */

   418

#define E1000_IMS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Asserted */

   419

#define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */

   420

   421

/* Extended Interrupt Mask Set */

   422

#define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */

   423

   424

/* Interrupt Cause Set */

   425

#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */

   426

#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */

   427

#define E1000_ICS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Aserted */

   428

   429

/* Extended Interrupt Cause Set */

   430

/* E1000_EITR_CNT_IGNR is only for 82576 and newer */

   431

#define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */

   432

   433

   434

/* Transmit Descriptor Control */

   435

/* Enable the counting of descriptors still to be processed. */

   436

   437

/* Flow Control Constants */

   438

#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001

   439

#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100

   440

#define FLOW_CONTROL_TYPE         0x8808

   441

   442

/* Transmit Config Word */

   443

#define E1000_TXCW_ASM_DIR	0x00000100 /* TXCW astm pause direction */

   444

#define E1000_TXCW_PAUSE	0x00000080 /* TXCW sym pause request */

   445

   446

/* 802.1q VLAN Packet Size */

   447

#define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */

   448

#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */

   449

   450

/* Receive Address */

   451

/* Number of high/low register pairs in the RAR. The RAR (Receive Address

   452

 * Registers) holds the directed and multicast addresses that we monitor.

   453

 * Technically, we have 16 spots.  However, we reserve one of these spots

   454

 * (RAR[15]) for our directed address used by controllers with

   455

 * manageability enabled, allowing us room for 15 multicast addresses.

   456

 */

   457

#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */

   458

#define E1000_RAL_MAC_ADDR_LEN 4

   459

#define E1000_RAH_MAC_ADDR_LEN 2

   460

#define E1000_RAH_POOL_MASK 0x03FC0000

   461

#define E1000_RAH_POOL_1 0x00040000

   462

   463

/* Error Codes */

   464

#define E1000_ERR_NVM      1

   465

#define E1000_ERR_PHY      2

   466

#define E1000_ERR_CONFIG   3

   467

#define E1000_ERR_PARAM    4

   468

#define E1000_ERR_MAC_INIT 5

   469

#define E1000_ERR_RESET   9

   470

#define E1000_ERR_MASTER_REQUESTS_PENDING 10

   471

#define E1000_BLK_PHY_RESET   12

   472

#define E1000_ERR_SWFW_SYNC 13

   473

#define E1000_NOT_IMPLEMENTED 14

   474

#define E1000_ERR_MBX      15

   475

#define E1000_ERR_INVALID_ARGUMENT  16

   476

#define E1000_ERR_NO_SPACE          17

   477

#define E1000_ERR_NVM_PBA_SECTION   18

   478

#define E1000_ERR_INVM_VALUE_NOT_FOUND	19

   479

#define E1000_ERR_I2C               20

   480

   481

/* Loop limit on how long we wait for auto-negotiation to complete */

   482

#define COPPER_LINK_UP_LIMIT              10

   483

#define PHY_AUTO_NEG_LIMIT                45

   484

#define PHY_FORCE_LIMIT                   20

   485

/* Number of 100 microseconds we wait for PCI Express master disable */

   486

#define MASTER_DISABLE_TIMEOUT      800

   487

/* Number of milliseconds we wait for PHY configuration done after MAC reset */

   488

#define PHY_CFG_TIMEOUT             100

   489

/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */

   490

/* Number of milliseconds for NVM auto read done after MAC reset. */

   491

#define AUTO_READ_DONE_TIMEOUT      10

   492

   493

/* Flow Control */

   494

#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */

   495

   496

#define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */

   497

#define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */

   498

   499

#define E1000_TSYNCRXCTL_VALID      0x00000001 /* rx timestamp valid */

   500

#define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* rx type mask */

   501

#define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00

   502

#define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02

   503

#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04

   504

#define E1000_TSYNCRXCTL_TYPE_ALL         0x08

   505

#define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A

   506

#define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable rx timestampping */

   507

   508

#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF

   509

#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00

   510

#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01

   511

#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02

   512

#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03

   513

#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04

   514

   515

#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00

   516

#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000

   517

#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100

   518

#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200

   519

#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300

   520

#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800

   521

#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900

   522

#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00

   523

#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00

   524

#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00

   525

#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00

   526

   527

#define E1000_TIMINCA_16NS_SHIFT 24

   528

   529

/* Time Sync Interrupt Cause/Mask Register Bits */

   530