1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 */

    10

    11

#include <linux/module.h>

    12

#include <linux/moduleparam.h>

    13

#include <linux/pci.h>

    14

#include <linux/netdevice.h>

    15

#include <linux/etherdevice.h>

    16

#include <linux/delay.h>

    17

#include <linux/ethtool.h>

    18

#include <linux/mii.h>

    19

#include <linux/if_vlan.h>

    20

#include <linux/crc32.h>

    21

#include <linux/in.h>

    22

#include <linux/ip.h>

    23

#include <linux/tcp.h>

    24

#include <linux/init.h>

    25

#include <linux/dma-mapping.h>

    26

    27

#include <asm/system.h>

    28

#include <asm/io.h>

    29

#include <asm/irq.h>

    30

    31

#define RTL8169_VERSION "2.3LK-NAPI"

    32

#define MODULENAME "r8169"

    33

#define PFX MODULENAME ": "

    34

    35

#ifdef RTL8169_DEBUG

    36

#define assert(expr) \

    37

	if (!(expr)) {					\

    38

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    39

		#expr,__FILE__,__FUNCTION__,__LINE__);		\

    40

	}

    41

#define dprintk(fmt, args...) \

    42

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    43

#else

    44

#define assert(expr) do {} while (0)

    45

#define dprintk(fmt, args...)	do {} while (0)

    46

#endif /* RTL8169_DEBUG */

    47

    48

#define R8169_MSG_DEFAULT \

    49

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    50

    51

#define TX_BUFFS_AVAIL(tp) \

    52

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    53

    54

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

    55

static const int max_interrupt_work = 20;

    56

    57

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    58

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    59

static const int multicast_filter_limit = 32;

    60

    61

/* MAC address length */

    62

#define MAC_ADDR_LEN	6

    63

    64

#define MAX_READ_REQUEST_SHIFT	12

    65

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

    66

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    67

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    68

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

    69

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    70

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    71

    72

#define R8169_REGS_SIZE		256

    73

#define R8169_NAPI_WEIGHT	64

    74

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    75

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    76

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    77

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    78

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    79

    80

#define RTL8169_TX_TIMEOUT	(6*HZ)

    81

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    82

    83

/* write/read MMIO register */

    84

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

    85

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

    86

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

    87

#define RTL_R8(reg)		readb (ioaddr + (reg))

    88

#define RTL_R16(reg)		readw (ioaddr + (reg))

    89

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

    90

    91

enum mac_version {

    92

	RTL_GIGA_MAC_NONE   = 0x00,

    93

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

    94

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

    95

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

    96

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

    97

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

    98

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

    99

	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e

   100

	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e

   101

	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e

   102

	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e

   103

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   104

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be

   105

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb

   106

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?

   107

	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?

   108

	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec

   109

	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf

   110

	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP

   111

	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C

   112

	RTL_GIGA_MAC_VER_20 = 0x14  // 8168C

   113

};

   114

   115

#define _R(NAME,MAC,MASK) \

   116

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   117

   118

static const struct {

   119

	const char *name;

   120

	u8 mac_version;

   121

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   122

} rtl_chip_info[] = {

   123

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   124

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   125

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   126

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   127

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   128

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   129

	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E

   130

	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E

   131

	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E

   132

	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E

   133

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   134

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   135

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   136

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   137

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139

   138

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E

   139

	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E

   140

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E

   141

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E

   142

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E

   143

};

   144

#undef _R

   145

   146

enum cfg_version {

   147

	RTL_CFG_0 = 0x00,

   148

	RTL_CFG_1,

   149

	RTL_CFG_2

   150

};

   151

   152

static void rtl_hw_start_8169(struct net_device *);

   153

static void rtl_hw_start_8168(struct net_device *);

   154

static void rtl_hw_start_8101(struct net_device *);

   155

   156

static struct pci_device_id rtl8169_pci_tbl[] = {

   157

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   158

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   159

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   160

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   161

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   162

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   163

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   164

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   165

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   166

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   167

	{ 0x0001,				0x8168,

   168

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   169

	{0,},

   170

};

   171

   172

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   173

   174

static int rx_copybreak = 200;

   175

static int use_dac;

   176

static struct {

   177

	u32 msg_enable;

   178

} debug = { -1 };

   179

   180

enum rtl_registers {

   181

	MAC0		= 0,	/* Ethernet hardware address. */

   182

	MAC4		= 4,

   183

	MAR0		= 8,	/* Multicast filter. */

   184

	CounterAddrLow		= 0x10,

   185

	CounterAddrHigh		= 0x14,

   186

	TxDescStartAddrLow	= 0x20,

   187

	TxDescStartAddrHigh	= 0x24,

   188

	TxHDescStartAddrLow	= 0x28,

   189

	TxHDescStartAddrHigh	= 0x2c,

   190

	FLASH		= 0x30,

   191

	ERSR		= 0x36,

   192

	ChipCmd		= 0x37,

   193

	TxPoll		= 0x38,

   194

	IntrMask	= 0x3c,

   195

	IntrStatus	= 0x3e,

   196

	TxConfig	= 0x40,

   197

	RxConfig	= 0x44,

   198

	RxMissed	= 0x4c,

   199

	Cfg9346		= 0x50,

   200

	Config0		= 0x51,

   201

	Config1		= 0x52,

   202

	Config2		= 0x53,

   203

	Config3		= 0x54,

   204

	Config4		= 0x55,

   205

	Config5		= 0x56,

   206

	MultiIntr	= 0x5c,

   207

	PHYAR		= 0x60,

   208

	PHYstatus	= 0x6c,

   209

	RxMaxSize	= 0xda,

   210

	CPlusCmd	= 0xe0,

   211

	IntrMitigate	= 0xe2,

   212

	RxDescAddrLow	= 0xe4,

   213

	RxDescAddrHigh	= 0xe8,

   214

	EarlyTxThres	= 0xec,

   215

	FuncEvent	= 0xf0,

   216

	FuncEventMask	= 0xf4,

   217

	FuncPresetState	= 0xf8,

   218

	FuncForceEvent	= 0xfc,

   219

};

   220

   221

enum rtl8110_registers {

   222

	TBICSR			= 0x64,

   223

	TBI_ANAR		= 0x68,

   224

	TBI_LPAR		= 0x6a,

   225

};

   226

   227

enum rtl8168_8101_registers {

   228

	CSIDR			= 0x64,

   229

	CSIAR			= 0x68,

   230

#define	CSIAR_FLAG			0x80000000

   231

#define	CSIAR_WRITE_CMD			0x80000000

   232

#define	CSIAR_BYTE_ENABLE		0x0f

   233

#define	CSIAR_BYTE_ENABLE_SHIFT		12

   234

#define	CSIAR_ADDR_MASK			0x0fff

   235

   236

	EPHYAR			= 0x80,

   237

#define	EPHYAR_FLAG			0x80000000

   238

#define	EPHYAR_WRITE_CMD		0x80000000

   239

#define	EPHYAR_REG_MASK			0x1f

   240

#define	EPHYAR_REG_SHIFT		16

   241

#define	EPHYAR_DATA_MASK		0xffff

   242

	DBG_REG			= 0xd1,

   243

#define	FIX_NAK_1			(1 << 4)

   244

#define	FIX_NAK_2			(1 << 3)

   245

};

   246

   247

enum rtl_register_content {

   248

	/* InterruptStatusBits */

   249

	SYSErr		= 0x8000,

   250

	PCSTimeout	= 0x4000,

   251

	SWInt		= 0x0100,

   252

	TxDescUnavail	= 0x0080,

   253

	RxFIFOOver	= 0x0040,

   254

	LinkChg		= 0x0020,

   255

	RxOverflow	= 0x0010,

   256

	TxErr		= 0x0008,

   257

	TxOK		= 0x0004,

   258

	RxErr		= 0x0002,

   259

	RxOK		= 0x0001,

   260

   261

	/* RxStatusDesc */

   262

	RxFOVF	= (1 << 23),

   263

	RxRWT	= (1 << 22),

   264

	RxRES	= (1 << 21),

   265

	RxRUNT	= (1 << 20),

   266

	RxCRC	= (1 << 19),

   267

   268

	/* ChipCmdBits */

   269

	CmdReset	= 0x10,

   270

	CmdRxEnb	= 0x08,

   271

	CmdTxEnb	= 0x04,

   272

	RxBufEmpty	= 0x01,

   273

   274

	/* TXPoll register p.5 */

   275

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   276

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   277

	FSWInt		= 0x01,		/* Forced software interrupt */

   278

   279

	/* Cfg9346Bits */

   280

	Cfg9346_Lock	= 0x00,

   281

	Cfg9346_Unlock	= 0xc0,

   282

   283

	/* rx_mode_bits */

   284

	AcceptErr	= 0x20,

   285

	AcceptRunt	= 0x10,

   286

	AcceptBroadcast	= 0x08,

   287

	AcceptMulticast	= 0x04,

   288

	AcceptMyPhys	= 0x02,

   289

	AcceptAllPhys	= 0x01,

   290

   291

	/* RxConfigBits */

   292

	RxCfgFIFOShift	= 13,

   293

	RxCfgDMAShift	=  8,

   294

   295

	/* TxConfigBits */

   296

	TxInterFrameGapShift = 24,

   297

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   298

   299

	/* Config1 register p.24 */

   300

	LEDS1		= (1 << 7),

   301

	LEDS0		= (1 << 6),

   302

	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */

   303

	Speed_down	= (1 << 4),

   304

	MEMMAP		= (1 << 3),

   305

	IOMAP		= (1 << 2),

   306

	VPD		= (1 << 1),

   307

	PMEnable	= (1 << 0),	/* Power Management Enable */

   308

   309

	/* Config2 register p. 25 */

   310

	PCI_Clock_66MHz = 0x01,

   311

	PCI_Clock_33MHz = 0x00,

   312

   313

	/* Config3 register p.25 */

   314

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   315

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   316

	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */

   317

   318

	/* Config5 register p.27 */

   319

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   320

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   321

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   322

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   323

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   324

   325

	/* TBICSR p.28 */

   326

	TBIReset	= 0x80000000,

   327

	TBILoopback	= 0x40000000,

   328

	TBINwEnable	= 0x20000000,

   329

	TBINwRestart	= 0x10000000,

   330

	TBILinkOk	= 0x02000000,

   331

	TBINwComplete	= 0x01000000,

   332

   333

	/* CPlusCmd p.31 */

   334

	EnableBist	= (1 << 15),	// 8168 8101

   335

	Mac_dbgo_oe	= (1 << 14),	// 8168 8101

   336

	Normal_mode	= (1 << 13),	// unused

   337

	Force_half_dup	= (1 << 12),	// 8168 8101

   338

	Force_rxflow_en	= (1 << 11),	// 8168 8101

   339

	Force_txflow_en	= (1 << 10),	// 8168 8101

   340

	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101

   341

	ASF		= (1 << 8),	// 8168 8101

   342

	PktCntrDisable	= (1 << 7),	// 8168 8101

   343

	Mac_dbgo_sel	= 0x001c,	// 8168

   344

	RxVlan		= (1 << 6),

   345

	RxChkSum	= (1 << 5),

   346

	PCIDAC		= (1 << 4),

   347

	PCIMulRW	= (1 << 3),

   348

	INTT_0		= 0x0000,	// 8168

   349

	INTT_1		= 0x0001,	// 8168

   350

	INTT_2		= 0x0002,	// 8168

   351

	INTT_3		= 0x0003,	// 8168

   352

   353

	/* rtl8169_PHYstatus */

   354

	TBI_Enable	= 0x80,

   355

	TxFlowCtrl	= 0x40,

   356

	RxFlowCtrl	= 0x20,

   357

	_1000bpsF	= 0x10,

   358

	_100bps		= 0x08,

   359

	_10bps		= 0x04,

   360

	LinkStatus	= 0x02,

   361

	FullDup		= 0x01,

   362

   363

	/* _TBICSRBit */

   364

	TBILinkOK	= 0x02000000,

   365

   366

	/* DumpCounterCommand */

   367

	CounterDump	= 0x8,

   368

};

   369

   370

enum desc_status_bit {

   371

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   372

	RingEnd		= (1 << 30), /* End of descriptor ring */

   373

	FirstFrag	= (1 << 29), /* First segment of a packet */

   374

	LastFrag	= (1 << 28), /* Final segment of a packet */

   375

   376

	/* Tx private */

   377

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   378

	MSSShift	= 16,        /* MSS value position */

   379

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   380

	IPCS		= (1 << 18), /* Calculate IP checksum */

   381

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   382

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   383

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   384

   385

	/* Rx private */

   386

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   387

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   388

   389

#define RxProtoUDP	(PID1)

   390

#define RxProtoTCP	(PID0)

   391

#define RxProtoIP	(PID1 | PID0)

   392

#define RxProtoMask	RxProtoIP

   393

   394

	IPFail		= (1 << 16), /* IP checksum failed */

   395

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   396

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   397

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   398

};

   399

   400

#define RsvdMask	0x3fffc000

   401

   402

struct TxDesc {

   403

	__le32 opts1;

   404

	__le32 opts2;

   405

	__le64 addr;

   406

};

   407

   408

struct RxDesc {

   409

	__le32 opts1;

   410

	__le32 opts2;

   411

	__le64 addr;

   412

};

   413

   414

struct ring_info {

   415

	struct sk_buff	*skb;

   416

	u32		len;

   417

	u8		__pad[sizeof(void *) - sizeof(u32)];

   418

};

   419

   420

enum features {

   421

	RTL_FEATURE_WOL		= (1 << 0),

   422

	RTL_FEATURE_MSI		= (1 << 1),

   423

	RTL_FEATURE_GMII	= (1 << 2),

   424

};

   425

   426

struct rtl8169_counters {

   427

	__le64	tx_packets;

   428

	__le64	rx_packets;

   429

	__le64	tx_errors;

   430

	__le32	rx_errors;

   431

	__le16	rx_missed;

   432

	__le16	align_errors;

   433

	__le32	tx_one_collision;

   434

	__le32	tx_multi_collision;

   435

	__le64	rx_unicast;

   436

	__le64	rx_broadcast;

   437

	__le32	rx_multicast;

   438

	__le16	tx_aborted;

   439

	__le16	tx_underun;

   440

};

   441

   442

struct rtl8169_private {

   443

	void __iomem *mmio_addr;	/* memory map physical address */

   444

	struct pci_dev *pci_dev;	/* Index of PCI device */

   445

	struct net_device *dev;

   446

	struct napi_struct napi;

   447

	spinlock_t lock;		/* spin lock flag */

   448

	u32 msg_enable;

   449

	int chipset;

   450

	int mac_version;

   451

	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   452

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   453

	u32 dirty_rx;

   454

	u32 dirty_tx;

   455

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   456

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   457

	dma_addr_t TxPhyAddr;

   458

	dma_addr_t RxPhyAddr;

   459

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   460

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

   461

	unsigned align;

   462

	unsigned rx_buf_sz;

   463

	struct timer_list timer;

   464

	u16 cp_cmd;

   465

	u16 intr_event;

   466

	u16 napi_event;

   467

	u16 intr_mask;

   468

	int phy_auto_nego_reg;

   469

	int phy_1000_ctrl_reg;

   470

#ifdef CONFIG_R8169_VLAN

   471

	struct vlan_group *vlgrp;

   472

#endif

   473

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   474

	int (*get_settings)(struct net_device *, struct ethtool_cmd *);

   475

	void (*phy_reset_enable)(void __iomem *);

   476

	void (*hw_start)(struct net_device *);

   477

	unsigned int (*phy_reset_pending)(void __iomem *);

   478

	unsigned int (*link_ok)(void __iomem *);

   479

	int pcie_cap;

   480

	struct delayed_work task;

   481

	unsigned features;

   482

   483

	struct mii_if_info mii;

   484

	struct rtl8169_counters counters;

   485

};

   486

   487

MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");

   488

MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");

   489

module_param(rx_copybreak, int, 0);

   490

MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

   491

module_param(use_dac, int, 0);

   492

MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

   493

module_param_named(debug, debug.msg_enable, int, 0);

   494

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   495

MODULE_LICENSE("GPL");

   496

MODULE_VERSION(RTL8169_VERSION);

   497

   498

static int rtl8169_open(struct net_device *dev);

   499

static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);

   500

static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);

   501

static int rtl8169_init_ring(struct net_device *dev);

   502

static void rtl_hw_start(struct net_device *dev);

   503

static int rtl8169_close(struct net_device *dev);

   504

static void rtl_set_rx_mode(struct net_device *dev);

   505

static void rtl8169_tx_timeout(struct net_device *dev);

   506

static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);

   507

static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,

   508

				void __iomem *, u32 budget);

   509

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);

   510

static void rtl8169_down(struct net_device *dev);

   511

static void rtl8169_rx_clear(struct rtl8169_private *tp);

   512

static int rtl8169_poll(struct napi_struct *napi, int budget);

   513

   514

static const unsigned int rtl8169_rx_config =

   515

	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);

   516

   517

static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)

   518

{

   519

	int i;

   520

   521

	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));

   522

   523

	for (i = 20; i > 0; i--) {

   524

		/*

   525

		 * Check if the RTL8169 has completed writing to the specified

   526

		 * MII register.

   527

		 */

   528

		if (!(RTL_R32(PHYAR) & 0x80000000))

   529

			break;

   530

		udelay(25);