etherlabmaster: devices/e1000/e1000_hw-2.6.31-orig.c@8cbb68315d29 (annotated)

2313 7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1	/*******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3	Intel PRO/1000 Linux driver
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4	Copyright(c) 1999 - 2006 Intel Corporation.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6	This program is free software; you can redistribute it and/or modify it
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7	under the terms and conditions of the GNU General Public License,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8	version 2, as published by the Free Software Foundation.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	9
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	10	This program is distributed in the hope it will be useful, but WITHOUT
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	13	more details.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	14
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	15	You should have received a copy of the GNU General Public License along with
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	16	this program; if not, write to the Free Software Foundation, Inc.,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	18
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	19	The full GNU General Public License is included in this distribution in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	20	the file called "COPYING".
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	21
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	22	Contact Information:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	23	Linux NICS <linux.nics@intel.com>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	26
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	27	*******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	28
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	29	/* e1000_hw.c
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	30	* Shared functions for accessing and configuring the MAC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	31	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	32
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	33
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	34	#include "e1000_hw.h"
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	35
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	36	static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	37	static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	38	static s32 e1000_read_kmrn_reg(struct e1000_hw hw, u32 reg_addr, u16 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	39	static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	40	static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	41	static void e1000_release_software_semaphore(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	42
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	43	static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	44	static s32 e1000_check_downshift(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	45	static s32 e1000_check_polarity(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	46	e1000_rev_polarity *polarity);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	47	static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	48	static void e1000_clear_vfta(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	49	static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	50	static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	51	bool link_up);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	52	static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	53	static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	54	static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	55	static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	56	static s32 e1000_get_cable_length(struct e1000_hw hw, u16 min_length,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	57	u16 *max_length);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	58	static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	59	static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	60	static s32 e1000_get_software_flag(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	61	static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	62	static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	63	static s32 e1000_id_led_init(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	64	static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	65	u32 cnf_base_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	66	u32 cnf_size);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	67	static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	68	static void e1000_init_rx_addrs(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	69	static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	70	static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	71	static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	72	static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	73	static s32 e1000_mng_host_if_write(struct e1000_hw hw, u8 buffer, u16 length,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	74	u16 offset, u8 *sum);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	75	static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	76	struct e1000_host_mng_command_header
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	77	*hdr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	78	static s32 e1000_mng_write_commit(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	79	static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	80	struct e1000_phy_info *phy_info);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	81	static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	82	struct e1000_phy_info *phy_info);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	83	static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	84	u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	85	static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	86	u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	87	static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	88	static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	89	struct e1000_phy_info *phy_info);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	90	static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	91	static s32 e1000_read_ich8_byte(struct e1000_hw hw, u32 index, u8 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	92	static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	93	u8 byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	94	static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	95	static s32 e1000_read_ich8_word(struct e1000_hw hw, u32 index, u16 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	96	static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	97	u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	98	static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	99	u16 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	100	static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	101	u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	102	static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	103	u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	104	static void e1000_release_software_flag(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	105	static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	106	static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	107	static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	108	static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	109	static s32 e1000_wait_autoneg(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	110	static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	111	static s32 e1000_set_phy_type(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	112	static void e1000_phy_init_script(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	113	static s32 e1000_setup_copper_link(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	114	static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	115	static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	116	static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	117	static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	118	static void e1000_raise_mdi_clk(struct e1000_hw hw, u32 ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	119	static void e1000_lower_mdi_clk(struct e1000_hw hw, u32 ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	120	static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	121	u16 count);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	122	static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	123	static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	124	static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	125	u16 words, u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	126	static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	127	u16 words, u16 *data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	128	static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	129	static void e1000_raise_ee_clk(struct e1000_hw hw, u32 eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	130	static void e1000_lower_ee_clk(struct e1000_hw hw, u32 eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	131	static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	132	static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	133	u16 phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	134	static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	135	u16 *phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	136	static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	137	static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	138	static void e1000_release_eeprom(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	139	static void e1000_standby_eeprom(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	140	static s32 e1000_set_vco_speed(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	141	static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	142	static s32 e1000_set_phy_mode(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	143	static s32 e1000_host_if_read_cookie(struct e1000_hw hw, u8 buffer);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	144	static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	145	static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	146	static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	147	static s32 e1000_do_read_eeprom(struct e1000_hw hw, u16 offset, u16 words, u16 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	148	static s32 e1000_do_write_eeprom(struct e1000_hw hw, u16 offset, u16 words, u16 data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	149
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	150	/* IGP cable length table */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	151	static const
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	152	u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	153	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	154	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	155	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	156	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	157	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	158	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	159	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	160	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	161
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	162	static const
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	163	u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	164	{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	165	0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	166	6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	167	21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	168	40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	169	60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	170	83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	171	104, 109, 114, 118, 121, 124};
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	172
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	173	static DEFINE_SPINLOCK(e1000_eeprom_lock);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	174
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	175	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	176	* Set the phy type member in the hw struct.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	177	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	178	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	179	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	180	static s32 e1000_set_phy_type(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	181	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	182	DEBUGFUNC("e1000_set_phy_type");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	183
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	184	if (hw->mac_type == e1000_undefined)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	185	return -E1000_ERR_PHY_TYPE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	186
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	187	switch (hw->phy_id) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	188	case M88E1000_E_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	189	case M88E1000_I_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	190	case M88E1011_I_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	191	case M88E1111_I_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	192	hw->phy_type = e1000_phy_m88;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	193	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	194	case IGP01E1000_I_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	195	if (hw->mac_type == e1000_82541 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	196	hw->mac_type == e1000_82541_rev_2 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	197	hw->mac_type == e1000_82547 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	198	hw->mac_type == e1000_82547_rev_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	199	hw->phy_type = e1000_phy_igp;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	200	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	201	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	202	case IGP03E1000_E_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	203	hw->phy_type = e1000_phy_igp_3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	204	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	205	case IFE_E_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	206	case IFE_PLUS_E_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	207	case IFE_C_E_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	208	hw->phy_type = e1000_phy_ife;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	209	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	210	case GG82563_E_PHY_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	211	if (hw->mac_type == e1000_80003es2lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	212	hw->phy_type = e1000_phy_gg82563;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	213	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	214	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	215	/* Fall Through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	216	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	217	/* Should never have loaded on this device */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	218	hw->phy_type = e1000_phy_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	219	return -E1000_ERR_PHY_TYPE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	220	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	221
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	222	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	223	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	224
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	225	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	226	* IGP phy init script - initializes the GbE PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	227	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	228	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	229	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	230	static void e1000_phy_init_script(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	231	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	232	u32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	233	u16 phy_saved_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	234
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	235	DEBUGFUNC("e1000_phy_init_script");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	236
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	237	if (hw->phy_init_script) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	238	msleep(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	239
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	240	/* Save off the current value of register 0x2F5B to be restored at
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	241	* the end of this routine. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	242	ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	243
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	244	/* Disabled the PHY transmitter */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	245	e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	246
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	247	msleep(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	248
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	249	e1000_write_phy_reg(hw,0x0000,0x0140);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	250
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	251	msleep(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	252
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	253	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	254	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	255	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	256	e1000_write_phy_reg(hw, 0x1F95, 0x0001);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	257
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	258	e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	259
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	260	e1000_write_phy_reg(hw, 0x1F79, 0x0018);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	261
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	262	e1000_write_phy_reg(hw, 0x1F30, 0x1600);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	263
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	264	e1000_write_phy_reg(hw, 0x1F31, 0x0014);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	265
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	266	e1000_write_phy_reg(hw, 0x1F32, 0x161C);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	267
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	268	e1000_write_phy_reg(hw, 0x1F94, 0x0003);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	269
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	270	e1000_write_phy_reg(hw, 0x1F96, 0x003F);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	271
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	272	e1000_write_phy_reg(hw, 0x2010, 0x0008);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	273	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	274
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	275	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	276	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	277	e1000_write_phy_reg(hw, 0x1F73, 0x0099);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	278	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	279	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	280	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	281	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	282
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	283	e1000_write_phy_reg(hw, 0x0000, 0x3300);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	284
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	285	msleep(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	286
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	287	/* Now enable the transmitter */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	288	e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	289
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	290	if (hw->mac_type == e1000_82547) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	291	u16 fused, fine, coarse;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	292
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	293	/* Move to analog registers page */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	294	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	295
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	296	if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	297	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	298
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	299	fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	300	coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	301
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	302	if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	303	coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	304	fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	305	} else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	306	fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	307
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	308	fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	309	(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	310	(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	311
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	312	e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	313	e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	314	IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	315	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	316	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	317	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	318	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	319
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	320	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	321	* Set the mac type member in the hw struct.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	322	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	323	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	324	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	325	s32 e1000_set_mac_type(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	326	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	327	DEBUGFUNC("e1000_set_mac_type");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	328
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	329	switch (hw->device_id) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	330	case E1000_DEV_ID_82542:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	331	switch (hw->revision_id) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	332	case E1000_82542_2_0_REV_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	333	hw->mac_type = e1000_82542_rev2_0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	334	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	335	case E1000_82542_2_1_REV_ID:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	336	hw->mac_type = e1000_82542_rev2_1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	337	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	338	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	339	/* Invalid 82542 revision ID */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	340	return -E1000_ERR_MAC_TYPE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	341	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	342	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	343	case E1000_DEV_ID_82543GC_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	344	case E1000_DEV_ID_82543GC_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	345	hw->mac_type = e1000_82543;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	346	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	347	case E1000_DEV_ID_82544EI_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	348	case E1000_DEV_ID_82544EI_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	349	case E1000_DEV_ID_82544GC_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	350	case E1000_DEV_ID_82544GC_LOM:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	351	hw->mac_type = e1000_82544;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	352	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	353	case E1000_DEV_ID_82540EM:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	354	case E1000_DEV_ID_82540EM_LOM:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	355	case E1000_DEV_ID_82540EP:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	356	case E1000_DEV_ID_82540EP_LOM:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	357	case E1000_DEV_ID_82540EP_LP:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	358	hw->mac_type = e1000_82540;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	359	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	360	case E1000_DEV_ID_82545EM_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	361	case E1000_DEV_ID_82545EM_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	362	hw->mac_type = e1000_82545;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	363	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	364	case E1000_DEV_ID_82545GM_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	365	case E1000_DEV_ID_82545GM_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	366	case E1000_DEV_ID_82545GM_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	367	hw->mac_type = e1000_82545_rev_3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	368	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	369	case E1000_DEV_ID_82546EB_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	370	case E1000_DEV_ID_82546EB_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	371	case E1000_DEV_ID_82546EB_QUAD_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	372	hw->mac_type = e1000_82546;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	373	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	374	case E1000_DEV_ID_82546GB_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	375	case E1000_DEV_ID_82546GB_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	376	case E1000_DEV_ID_82546GB_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	377	case E1000_DEV_ID_82546GB_PCIE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	378	case E1000_DEV_ID_82546GB_QUAD_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	379	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	380	hw->mac_type = e1000_82546_rev_3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	381	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	382	case E1000_DEV_ID_82541EI:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	383	case E1000_DEV_ID_82541EI_MOBILE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	384	case E1000_DEV_ID_82541ER_LOM:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	385	hw->mac_type = e1000_82541;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	386	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	387	case E1000_DEV_ID_82541ER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	388	case E1000_DEV_ID_82541GI:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	389	case E1000_DEV_ID_82541GI_LF:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	390	case E1000_DEV_ID_82541GI_MOBILE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	391	hw->mac_type = e1000_82541_rev_2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	392	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	393	case E1000_DEV_ID_82547EI:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	394	case E1000_DEV_ID_82547EI_MOBILE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	395	hw->mac_type = e1000_82547;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	396	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	397	case E1000_DEV_ID_82547GI:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	398	hw->mac_type = e1000_82547_rev_2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	399	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	400	case E1000_DEV_ID_82571EB_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	401	case E1000_DEV_ID_82571EB_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	402	case E1000_DEV_ID_82571EB_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	403	case E1000_DEV_ID_82571EB_SERDES_DUAL:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	404	case E1000_DEV_ID_82571EB_SERDES_QUAD:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	405	case E1000_DEV_ID_82571EB_QUAD_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	406	case E1000_DEV_ID_82571PT_QUAD_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	407	case E1000_DEV_ID_82571EB_QUAD_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	408	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	409	hw->mac_type = e1000_82571;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	410	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	411	case E1000_DEV_ID_82572EI_COPPER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	412	case E1000_DEV_ID_82572EI_FIBER:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	413	case E1000_DEV_ID_82572EI_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	414	case E1000_DEV_ID_82572EI:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	415	hw->mac_type = e1000_82572;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	416	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	417	case E1000_DEV_ID_82573E:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	418	case E1000_DEV_ID_82573E_IAMT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	419	case E1000_DEV_ID_82573L:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	420	hw->mac_type = e1000_82573;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	421	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	422	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	423	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	424	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	425	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	426	hw->mac_type = e1000_80003es2lan;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	427	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	428	case E1000_DEV_ID_ICH8_IGP_M_AMT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	429	case E1000_DEV_ID_ICH8_IGP_AMT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	430	case E1000_DEV_ID_ICH8_IGP_C:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	431	case E1000_DEV_ID_ICH8_IFE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	432	case E1000_DEV_ID_ICH8_IFE_GT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	433	case E1000_DEV_ID_ICH8_IFE_G:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	434	case E1000_DEV_ID_ICH8_IGP_M:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	435	hw->mac_type = e1000_ich8lan;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	436	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	437	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	438	/* Should never have loaded on this device */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	439	return -E1000_ERR_MAC_TYPE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	440	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	441
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	442	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	443	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	444	hw->swfwhw_semaphore_present = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	445	hw->asf_firmware_present = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	446	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	447	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	448	hw->swfw_sync_present = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	449	/* fall through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	450	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	451	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	452	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	453	hw->eeprom_semaphore_present = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	454	/* fall through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	455	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	456	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	457	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	458	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	459	hw->asf_firmware_present = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	460	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	461	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	462	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	463	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	464
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	465	/* The 82543 chip does not count tx_carrier_errors properly in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	466	* FD mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	467	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	468	if (hw->mac_type == e1000_82543)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	469	hw->bad_tx_carr_stats_fd = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	470
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	471	/* capable of receiving management packets to the host */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	472	if (hw->mac_type >= e1000_82571)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	473	hw->has_manc2h = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	474
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	475	/* In rare occasions, ESB2 systems would end up started without
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	476	* the RX unit being turned on.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	477	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	478	if (hw->mac_type == e1000_80003es2lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	479	hw->rx_needs_kicking = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	480
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	481	if (hw->mac_type > e1000_82544)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	482	hw->has_smbus = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	483
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	484	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	485	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	486
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	487	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	488	* Set media type and TBI compatibility.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	489	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	490	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	491	* **************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	492	void e1000_set_media_type(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	493	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	494	u32 status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	495
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	496	DEBUGFUNC("e1000_set_media_type");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	497
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	498	if (hw->mac_type != e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	499	/* tbi_compatibility is only valid on 82543 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	500	hw->tbi_compatibility_en = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	501	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	502
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	503	switch (hw->device_id) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	504	case E1000_DEV_ID_82545GM_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	505	case E1000_DEV_ID_82546GB_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	506	case E1000_DEV_ID_82571EB_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	507	case E1000_DEV_ID_82571EB_SERDES_DUAL:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	508	case E1000_DEV_ID_82571EB_SERDES_QUAD:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	509	case E1000_DEV_ID_82572EI_SERDES:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	510	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	511	hw->media_type = e1000_media_type_internal_serdes;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	512	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	513	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	514	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	515	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	516	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	517	hw->media_type = e1000_media_type_fiber;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	518	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	519	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	520	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	521	/* The STATUS_TBIMODE bit is reserved or reused for the this
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	522	* device.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	523	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	524	hw->media_type = e1000_media_type_copper;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	525	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	526	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	527	status = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	528	if (status & E1000_STATUS_TBIMODE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	529	hw->media_type = e1000_media_type_fiber;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	530	/* tbi_compatibility not valid on fiber */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	531	hw->tbi_compatibility_en = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	532	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	533	hw->media_type = e1000_media_type_copper;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	534	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	535	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	536	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	537	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	538	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	539
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	540	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	541	* Reset the transmit and receive units; mask and clear all interrupts.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	542	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	543	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	544	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	545	s32 e1000_reset_hw(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	546	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	547	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	548	u32 ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	549	u32 icr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	550	u32 manc;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	551	u32 led_ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	552	u32 timeout;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	553	u32 extcnf_ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	554	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	555
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	556	DEBUGFUNC("e1000_reset_hw");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	557
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	558	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	559	if (hw->mac_type == e1000_82542_rev2_0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	560	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	561	e1000_pci_clear_mwi(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	562	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	563
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	564	if (hw->bus_type == e1000_bus_type_pci_express) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	565	/* Prevent the PCI-E bus from sticking if there is no TLP connection
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	566	* on the last TLP read/write transaction when MAC is reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	567	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	568	if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	569	DEBUGOUT("PCI-E Master disable polling has failed.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	570	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	571	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	572
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	573	/* Clear interrupt mask to stop board from generating interrupts */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	574	DEBUGOUT("Masking off all interrupts\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	575	ew32(IMC, 0xffffffff);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	576
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	577	/* Disable the Transmit and Receive units. Then delay to allow
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	578	* any pending transactions to complete before we hit the MAC with
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	579	* the global reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	580	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	581	ew32(RCTL, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	582	ew32(TCTL, E1000_TCTL_PSP);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	583	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	584
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	585	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	586	hw->tbi_compatibility_on = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	587
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	588	/* Delay to allow any outstanding PCI transactions to complete before
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	589	* resetting the device
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	590	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	591	msleep(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	592
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	593	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	594
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	595	/* Must reset the PHY before resetting the MAC */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	596	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	597	ew32(CTRL, (ctrl \| E1000_CTRL_PHY_RST));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	598	msleep(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	599	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	600
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	601	/* Must acquire the MDIO ownership before MAC reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	602	* Ownership defaults to firmware after a reset. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	603	if (hw->mac_type == e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	604	timeout = 10;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	605
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	606	extcnf_ctrl = er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	607	extcnf_ctrl \|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	608
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	609	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	610	ew32(EXTCNF_CTRL, extcnf_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	611	extcnf_ctrl = er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	612
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	613	if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	614	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	615	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	616	extcnf_ctrl \|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	617
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	618	msleep(2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	619	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	620	} while (timeout);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	621	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	622
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	623	/* Workaround for ICH8 bit corruption issue in FIFO memory */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	624	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	625	/* Set Tx and Rx buffer allocation to 8k apiece. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	626	ew32(PBA, E1000_PBA_8K);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	627	/* Set Packet Buffer Size to 16k. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	628	ew32(PBS, E1000_PBS_16K);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	629	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	630
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	631	/* Issue a global reset to the MAC. This will reset the chip's
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	632	* transmit, receive, DMA, and link units. It will not effect
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	633	* the current PCI configuration. The global reset bit is self-
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	634	* clearing, and should clear within a microsecond.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	635	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	636	DEBUGOUT("Issuing a global reset to MAC\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	637
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	638	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	639	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	640	case e1000_82540:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	641	case e1000_82545:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	642	case e1000_82546:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	643	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	644	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	645	/* These controllers can't ack the 64-bit write when issuing the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	646	* reset, so use IO-mapping as a workaround to issue the reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	647	E1000_WRITE_REG_IO(hw, CTRL, (ctrl \| E1000_CTRL_RST));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	648	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	649	case e1000_82545_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	650	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	651	/* Reset is performed on a shadow of the control register */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	652	ew32(CTRL_DUP, (ctrl \| E1000_CTRL_RST));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	653	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	654	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	655	if (!hw->phy_reset_disable &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	656	e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	657	/* e1000_ich8lan PHY HW reset requires MAC CORE reset
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	658	* at the same time to make sure the interface between
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	659	* MAC and the external PHY is reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	660	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	661	ctrl \|= E1000_CTRL_PHY_RST;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	662	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	663
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	664	e1000_get_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	665	ew32(CTRL, (ctrl \| E1000_CTRL_RST));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	666	msleep(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	667	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	668	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	669	ew32(CTRL, (ctrl \| E1000_CTRL_RST));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	670	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	671	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	672
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	673	/* After MAC reset, force reload of EEPROM to restore power-on settings to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	674	* device. Later controllers reload the EEPROM automatically, so just wait
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	675	* for reload to complete.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	676	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	677	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	678	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	679	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	680	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	681	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	682	/* Wait for reset to complete */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	683	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	684	ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	685	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	686	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	687	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	688	/* Wait for EEPROM reload */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	689	msleep(2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	690	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	691	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	692	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	693	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	694	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	695	/* Wait for EEPROM reload */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	696	msleep(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	697	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	698	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	699	if (!e1000_is_onboard_nvm_eeprom(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	700	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	701	ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	702	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	703	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	704	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	705	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	706	/* fall through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	707	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	708	/* Auto read done will delay 5ms or poll based on mac type */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	709	ret_val = e1000_get_auto_rd_done(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	710	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	711	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	712	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	713	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	714
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	715	/* Disable HW ARPs on ASF enabled adapters */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	716	if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	717	manc = er32(MANC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	718	manc &= ~(E1000_MANC_ARP_EN);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	719	ew32(MANC, manc);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	720	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	721
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	722	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	723	e1000_phy_init_script(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	724
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	725	/* Configure activity LED after PHY reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	726	led_ctrl = er32(LEDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	727	led_ctrl &= IGP_ACTIVITY_LED_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	728	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	729	ew32(LEDCTL, led_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	730	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	731
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	732	/* Clear interrupt mask to stop board from generating interrupts */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	733	DEBUGOUT("Masking off all interrupts\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	734	ew32(IMC, 0xffffffff);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	735
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	736	/* Clear any pending interrupt events. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	737	icr = er32(ICR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	738
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	739	/* If MWI was previously enabled, reenable it. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	740	if (hw->mac_type == e1000_82542_rev2_0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	741	if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	742	e1000_pci_set_mwi(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	743	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	744
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	745	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	746	u32 kab = er32(KABGTXD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	747	kab \|= E1000_KABGTXD_BGSQLBIAS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	748	ew32(KABGTXD, kab);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	749	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	750
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	751	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	752	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	753
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	754	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	755	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	756	* Initialize a number of hardware-dependent bits
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	757	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	758	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	759	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	760	* This function contains hardware limitation workarounds for PCI-E adapters
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	761	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	762	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	763	static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	764	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	765	if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	766	/* Settings common to all PCI-express silicon */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	767	u32 reg_ctrl, reg_ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	768	u32 reg_tarc0, reg_tarc1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	769	u32 reg_tctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	770	u32 reg_txdctl, reg_txdctl1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	771
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	772	/* link autonegotiation/sync workarounds */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	773	reg_tarc0 = er32(TARC0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	774	reg_tarc0 &= ~((1 << 30)\|(1 << 29)\|(1 << 28)\|(1 << 27));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	775
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	776	/* Enable not-done TX descriptor counting */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	777	reg_txdctl = er32(TXDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	778	reg_txdctl \|= E1000_TXDCTL_COUNT_DESC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	779	ew32(TXDCTL, reg_txdctl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	780	reg_txdctl1 = er32(TXDCTL1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	781	reg_txdctl1 \|= E1000_TXDCTL_COUNT_DESC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	782	ew32(TXDCTL1, reg_txdctl1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	783
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	784	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	785	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	786	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	787	/* Clear PHY TX compatible mode bits */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	788	reg_tarc1 = er32(TARC1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	789	reg_tarc1 &= ~((1 << 30)\|(1 << 29));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	790
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	791	/* link autonegotiation/sync workarounds */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	792	reg_tarc0 \|= ((1 << 26)\|(1 << 25)\|(1 << 24)\|(1 << 23));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	793
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	794	/* TX ring control fixes */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	795	reg_tarc1 \|= ((1 << 26)\|(1 << 25)\|(1 << 24));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	796
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	797	/* Multiple read bit is reversed polarity */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	798	reg_tctl = er32(TCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	799	if (reg_tctl & E1000_TCTL_MULR)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	800	reg_tarc1 &= ~(1 << 28);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	801	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	802	reg_tarc1 \|= (1 << 28);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	803
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	804	ew32(TARC1, reg_tarc1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	805	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	806	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	807	reg_ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	808	reg_ctrl_ext &= ~(1 << 23);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	809	reg_ctrl_ext \|= (1 << 22);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	810
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	811	/* TX byte count fix */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	812	reg_ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	813	reg_ctrl &= ~(1 << 29);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	814
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	815	ew32(CTRL_EXT, reg_ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	816	ew32(CTRL, reg_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	817	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	818	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	819	/* improve small packet performace for fiber/serdes */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	820	if ((hw->media_type == e1000_media_type_fiber) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	821	(hw->media_type == e1000_media_type_internal_serdes)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	822	reg_tarc0 &= ~(1 << 20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	823	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	824
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	825	/* Multiple read bit is reversed polarity */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	826	reg_tctl = er32(TCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	827	reg_tarc1 = er32(TARC1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	828	if (reg_tctl & E1000_TCTL_MULR)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	829	reg_tarc1 &= ~(1 << 28);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	830	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	831	reg_tarc1 \|= (1 << 28);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	832
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	833	ew32(TARC1, reg_tarc1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	834	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	835	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	836	/* Reduce concurrent DMA requests to 3 from 4 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	837	if ((hw->revision_id < 3) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	838	((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	839	(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	840	reg_tarc0 \|= ((1 << 29)\|(1 << 28));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	841
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	842	reg_ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	843	reg_ctrl_ext \|= (1 << 22);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	844	ew32(CTRL_EXT, reg_ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	845
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	846	/* workaround TX hang with TSO=on */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	847	reg_tarc0 \|= ((1 << 27)\|(1 << 26)\|(1 << 24)\|(1 << 23));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	848
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	849	/* Multiple read bit is reversed polarity */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	850	reg_tctl = er32(TCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	851	reg_tarc1 = er32(TARC1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	852	if (reg_tctl & E1000_TCTL_MULR)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	853	reg_tarc1 &= ~(1 << 28);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	854	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	855	reg_tarc1 \|= (1 << 28);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	856
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	857	/* workaround TX hang with TSO=on */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	858	reg_tarc1 \|= ((1 << 30)\|(1 << 26)\|(1 << 24));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	859
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	860	ew32(TARC1, reg_tarc1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	861	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	862	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	863	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	864	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	865
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	866	ew32(TARC0, reg_tarc0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	867	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	868	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	869
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	870	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	871	* Performs basic configuration of the adapter.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	872	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	873	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	874	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	875	* Assumes that the controller has previously been reset and is in a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	876	* post-reset uninitialized state. Initializes the receive address registers,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	877	* multicast table, and VLAN filter table. Calls routines to setup link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	878	* configuration and flow control settings. Clears all on-chip counters. Leaves
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	879	* the transmit and receive units disabled and uninitialized.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	880	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	881	s32 e1000_init_hw(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	882	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	883	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	884	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	885	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	886	u32 mta_size;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	887	u32 reg_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	888	u32 ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	889
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	890	DEBUGFUNC("e1000_init_hw");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	891
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	892	/* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	893	if ((hw->mac_type == e1000_ich8lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	894	((hw->revision_id < 3) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	895	((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	896	(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	897	reg_data = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	898	reg_data &= ~0x80000000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	899	ew32(STATUS, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	900	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	901
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	902	/* Initialize Identification LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	903	ret_val = e1000_id_led_init(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	904	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	905	DEBUGOUT("Error Initializing Identification LED\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	906	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	907	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	908
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	909	/* Set the media type and TBI compatibility */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	910	e1000_set_media_type(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	911
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	912	/* Must be called after e1000_set_media_type because media_type is used */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	913	e1000_initialize_hardware_bits(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	914
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	915	/* Disabling VLAN filtering. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	916	DEBUGOUT("Initializing the IEEE VLAN\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	917	/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	918	if (hw->mac_type != e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	919	if (hw->mac_type < e1000_82545_rev_3)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	920	ew32(VET, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	921	e1000_clear_vfta(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	922	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	923
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	924	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	925	if (hw->mac_type == e1000_82542_rev2_0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	926	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	927	e1000_pci_clear_mwi(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	928	ew32(RCTL, E1000_RCTL_RST);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	929	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	930	msleep(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	931	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	932
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	933	/* Setup the receive address. This involves initializing all of the Receive
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	934	* Address Registers (RARs 0 - 15).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	935	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	936	e1000_init_rx_addrs(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	937
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	938	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	939	if (hw->mac_type == e1000_82542_rev2_0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	940	ew32(RCTL, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	941	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	942	msleep(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	943	if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	944	e1000_pci_set_mwi(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	945	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	946
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	947	/* Zero out the Multicast HASH table */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	948	DEBUGOUT("Zeroing the MTA\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	949	mta_size = E1000_MC_TBL_SIZE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	950	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	951	mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	952	for (i = 0; i < mta_size; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	953	E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	954	/* use write flush to prevent Memory Write Block (MWB) from
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	955	* occuring when accessing our register space */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	956	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	957	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	958
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	959	/* Set the PCI priority bit correctly in the CTRL register. This
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	960	* determines if the adapter gives priority to receives, or if it
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	961	* gives equal priority to transmits and receives. Valid only on
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	962	* 82542 and 82543 silicon.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	963	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	964	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	965	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	966	ew32(CTRL, ctrl \| E1000_CTRL_PRIOR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	967	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	968
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	969	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	970	case e1000_82545_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	971	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	972	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	973	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	974	/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	975	if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	976	e1000_pcix_set_mmrbc(hw, 2048);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	977	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	978	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	979
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	980	/* More time needed for PHY to initialize */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	981	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	982	msleep(15);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	983
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	984	/* Call a subroutine to configure the link and setup flow control. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	985	ret_val = e1000_setup_link(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	986
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	987	/* Set the transmit descriptor write-back policy */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	988	if (hw->mac_type > e1000_82544) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	989	ctrl = er32(TXDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	990	ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	991	ew32(TXDCTL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	992	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	993
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	994	if (hw->mac_type == e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	995	e1000_enable_tx_pkt_filtering(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	996	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	997
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	998	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	999	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1000	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1001	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1002	/* Enable retransmit on late collisions */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1003	reg_data = er32(TCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1004	reg_data \|= E1000_TCTL_RTLC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1005	ew32(TCTL, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1006
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1007	/* Configure Gigabit Carry Extend Padding */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1008	reg_data = er32(TCTL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1009	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1010	reg_data \|= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1011	ew32(TCTL_EXT, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1012
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1013	/* Configure Transmit Inter-Packet Gap */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1014	reg_data = er32(TIPG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1015	reg_data &= ~E1000_TIPG_IPGT_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1016	reg_data \|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1017	ew32(TIPG, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1018
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1019	reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1020	reg_data &= ~0x00100000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1021	E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1022	/* Fall through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1023	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1024	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1025	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1026	ctrl = er32(TXDCTL1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1027	ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1028	ew32(TXDCTL1, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1029	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1030	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1031
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1032
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1033	if (hw->mac_type == e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1034	u32 gcr = er32(GCR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1035	gcr \|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1036	ew32(GCR, gcr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1037	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1038
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1039	/* Clear all of the statistics registers (clear on read). It is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1040	* important that we do this after we have tried to establish link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1041	* because the symbol error count will increment wildly if there
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1042	* is no link.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1043	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1044	e1000_clear_hw_cntrs(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1045
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1046	/* ICH8 No-snoop bits are opposite polarity.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1047	* Set to snoop by default after reset. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1048	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1049	e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1050
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1051	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1052	hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1053	ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1054	/* Relaxed ordering must be disabled to avoid a parity
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1055	* error crash in a PCI slot. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1056	ctrl_ext \|= E1000_CTRL_EXT_RO_DIS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1057	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1058	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1059
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1060	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1061	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1062
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1063	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1064	* Adjust SERDES output amplitude based on EEPROM setting.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1065	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1066	* hw - Struct containing variables accessed by shared code.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1067	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1068	static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1069	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1070	u16 eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1071	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1072
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1073	DEBUGFUNC("e1000_adjust_serdes_amplitude");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1074
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1075	if (hw->media_type != e1000_media_type_internal_serdes)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1076	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1077
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1078	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1079	case e1000_82545_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1080	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1081	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1082	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1083	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1084	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1085
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1086	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1087	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1088	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1089	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1090
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1091	if (eeprom_data != EEPROM_RESERVED_WORD) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1092	/* Adjust SERDES output amplitude only. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1093	eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1094	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1095	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1096	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1097	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1098
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1099	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1100	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1101
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1102	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1103	* Configures flow control and link settings.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1104	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1105	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1106	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1107	* Determines which flow control settings to use. Calls the apropriate media-
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1108	* specific link configuration function. Configures the flow control settings.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1109	* Assuming the adapter has a valid link partner, a valid link should be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1110	* established. Assumes the hardware has previously been reset and the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1111	* transmitter and receiver are not enabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1112	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1113	s32 e1000_setup_link(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1114	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1115	u32 ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1116	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1117	u16 eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1118
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1119	DEBUGFUNC("e1000_setup_link");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1120
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1121	/* In the case of the phy reset being blocked, we already have a link.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1122	* We do not have to set it up again. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1123	if (e1000_check_phy_reset_block(hw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1124	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1125
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1126	/* Read and store word 0x0F of the EEPROM. This word contains bits
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1127	* that determine the hardware's default PAUSE (flow control) mode,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1128	* a bit that determines whether the HW defaults to enabling or
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1129	* disabling auto-negotiation, and the direction of the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1130	* SW defined pins. If there is no SW over-ride of the flow
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1131	* control setting, then the variable hw->fc will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1132	* be initialized based on a value in the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1133	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1134	if (hw->fc == E1000_FC_DEFAULT) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1135	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1136	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1137	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1138	hw->fc = E1000_FC_FULL;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1139	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1140	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1141	ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1142	1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1143	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1144	DEBUGOUT("EEPROM Read Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1145	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1146	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1147	if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1148	hw->fc = E1000_FC_NONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1149	else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1150	EEPROM_WORD0F_ASM_DIR)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1151	hw->fc = E1000_FC_TX_PAUSE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1152	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1153	hw->fc = E1000_FC_FULL;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1154	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1155	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1156	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1157
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1158	/* We want to save off the original Flow Control configuration just
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1159	* in case we get disconnected and then reconnected into a different
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1160	* hub or switch with different Flow Control capabilities.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1161	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1162	if (hw->mac_type == e1000_82542_rev2_0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1163	hw->fc &= (~E1000_FC_TX_PAUSE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1164
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1165	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1166	hw->fc &= (~E1000_FC_RX_PAUSE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1167
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1168	hw->original_fc = hw->fc;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1169
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1170	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1171
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1172	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1173	* polarity value for the SW controlled pins, and setup the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1174	* Extended Device Control reg with that info.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1175	* This is needed because one of the SW controlled pins is used for
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1176	* signal detection. So this should be done before e1000_setup_pcs_link()
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1177	* or e1000_phy_setup() is called.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1178	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1179	if (hw->mac_type == e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1180	ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1181	1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1182	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1183	DEBUGOUT("EEPROM Read Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1184	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1185	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1186	ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1187	SWDPIO__EXT_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1188	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1189	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1190
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1191	/* Call the necessary subroutine to configure the link. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1192	ret_val = (hw->media_type == e1000_media_type_copper) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1193	e1000_setup_copper_link(hw) :
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1194	e1000_setup_fiber_serdes_link(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1195
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1196	/* Initialize the flow control address, type, and PAUSE timer
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1197	* registers to their default values. This is done even if flow
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1198	* control is disabled, because it does not hurt anything to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1199	* initialize these registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1200	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1201	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1202
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1203	/* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1204	if (hw->mac_type != e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1205	ew32(FCT, FLOW_CONTROL_TYPE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1206	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1207	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1208	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1209
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1210	ew32(FCTTV, hw->fc_pause_time);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1211
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1212	/* Set the flow control receive threshold registers. Normally,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1213	* these registers will be set to a default threshold that may be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1214	* adjusted later by the driver's runtime code. However, if the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1215	* ability to transmit pause frames in not enabled, then these
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1216	* registers will be set to 0.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1217	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1218	if (!(hw->fc & E1000_FC_TX_PAUSE)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1219	ew32(FCRTL, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1220	ew32(FCRTH, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1221	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1222	/* We need to set up the Receive Threshold high and low water marks
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1223	* as well as (optionally) enabling the transmission of XON frames.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1224	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1225	if (hw->fc_send_xon) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1226	ew32(FCRTL, (hw->fc_low_water \| E1000_FCRTL_XONE));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1227	ew32(FCRTH, hw->fc_high_water);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1228	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1229	ew32(FCRTL, hw->fc_low_water);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1230	ew32(FCRTH, hw->fc_high_water);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1231	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1232	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1233	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1234	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1235
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1236	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1237	* Sets up link for a fiber based or serdes based adapter
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1238	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1239	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1240	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1241	* Manipulates Physical Coding Sublayer functions in order to configure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1242	* link. Assumes the hardware has been previously reset and the transmitter
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1243	* and receiver are not enabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1244	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1245	static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1246	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1247	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1248	u32 status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1249	u32 txcw = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1250	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1251	u32 signal = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1252	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1253
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1254	DEBUGFUNC("e1000_setup_fiber_serdes_link");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1255
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1256	/* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1257	* until explicitly turned off or a power cycle is performed. A read to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1258	* the register does not indicate its status. Therefore, we ensure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1259	* loopback mode is disabled during initialization.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1260	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1261	if (hw->mac_type == e1000_82571 \|\| hw->mac_type == e1000_82572)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1262	ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1263
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1264	/* On adapters with a MAC newer than 82544, SWDP 1 will be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1265	* set when the optics detect a signal. On older adapters, it will be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1266	* cleared when there is a signal. This applies to fiber media only.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1267	* If we're on serdes media, adjust the output amplitude to value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1268	* set in the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1269	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1270	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1271	if (hw->media_type == e1000_media_type_fiber)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1272	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1273
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1274	ret_val = e1000_adjust_serdes_amplitude(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1275	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1276	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1277
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1278	/* Take the link out of reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1279	ctrl &= ~(E1000_CTRL_LRST);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1280
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1281	/* Adjust VCO speed to improve BER performance */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1282	ret_val = e1000_set_vco_speed(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1283	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1284	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1285
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1286	e1000_config_collision_dist(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1287
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1288	/* Check for a software override of the flow control settings, and setup
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1289	* the device accordingly. If auto-negotiation is enabled, then software
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1290	* will have to set the "PAUSE" bits to the correct value in the Tranmsit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1291	* Config Word Register (TXCW) and re-start auto-negotiation. However, if
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1292	* auto-negotiation is disabled, then software will have to manually
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1293	* configure the two flow control enable bits in the CTRL register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1294	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1295	* The possible values of the "fc" parameter are:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1296	* 0: Flow control is completely disabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1297	* 1: Rx flow control is enabled (we can receive pause frames, but
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1298	* not send pause frames).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1299	* 2: Tx flow control is enabled (we can send pause frames but we do
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1300	* not support receiving pause frames).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1301	* 3: Both Rx and TX flow control (symmetric) are enabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1302	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1303	switch (hw->fc) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1304	case E1000_FC_NONE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1305	/* Flow control is completely disabled by a software over-ride. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1306	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1307	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1308	case E1000_FC_RX_PAUSE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1309	/* RX Flow control is enabled and TX Flow control is disabled by a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1310	* software over-ride. Since there really isn't a way to advertise
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1311	* that we are capable of RX Pause ONLY, we will advertise that we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1312	* support both symmetric and asymmetric RX PAUSE. Later, we will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1313	* disable the adapter's ability to send PAUSE frames.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1314	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1315	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1316	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1317	case E1000_FC_TX_PAUSE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1318	/* TX Flow control is enabled, and RX Flow control is disabled, by a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1319	* software over-ride.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1320	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1321	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_ASM_DIR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1322	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1323	case E1000_FC_FULL:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1324	/* Flow control (both RX and TX) is enabled by a software over-ride. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1325	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1326	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1327	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1328	DEBUGOUT("Flow control param set incorrectly\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1329	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1330	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1331	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1332
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1333	/* Since auto-negotiation is enabled, take the link out of reset (the link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1334	* will be in reset, because we previously reset the chip). This will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1335	* restart auto-negotiation. If auto-neogtiation is successful then the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1336	* link-up status bit will be set and the flow control enable bits (RFCE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1337	* and TFCE) will be set according to their negotiated value.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1338	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1339	DEBUGOUT("Auto-negotiation enabled\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1340
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1341	ew32(TXCW, txcw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1342	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1343	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1344
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1345	hw->txcw = txcw;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1346	msleep(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1347
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1348	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1349	* indication in the Device Status Register. Time-out if a link isn't
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1350	* seen in 500 milliseconds seconds (Auto-negotiation should complete in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1351	* less than 500 milliseconds even if the other end is doing it in SW).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1352	* For internal serdes, we just assume a signal is present, then poll.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1353	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1354	if (hw->media_type == e1000_media_type_internal_serdes \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1355	(er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1356	DEBUGOUT("Looking for Link\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1357	for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1358	msleep(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1359	status = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1360	if (status & E1000_STATUS_LU) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1361	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1362	if (i == (LINK_UP_TIMEOUT / 10)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1363	DEBUGOUT("Never got a valid link from auto-neg!!!\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1364	hw->autoneg_failed = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1365	/* AutoNeg failed to achieve a link, so we'll call
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1366	* e1000_check_for_link. This routine will force the link up if
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1367	* we detect a signal. This will allow us to communicate with
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1368	* non-autonegotiating link partners.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1369	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1370	ret_val = e1000_check_for_link(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1371	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1372	DEBUGOUT("Error while checking for link\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1373	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1374	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1375	hw->autoneg_failed = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1376	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1377	hw->autoneg_failed = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1378	DEBUGOUT("Valid Link Found\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1379	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1380	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1381	DEBUGOUT("No Signal Detected\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1382	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1383	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1384	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1385
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1386	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1387	* Make sure we have a valid PHY and change PHY mode before link setup.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1388	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1389	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1390	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1391	static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1392	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1393	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1394	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1395	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1396
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1397	DEBUGFUNC("e1000_copper_link_preconfig");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1398
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1399	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1400	/* With 82543, we need to force speed and duplex on the MAC equal to what
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1401	* the PHY speed and duplex configuration is. In addition, we need to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1402	* perform a hardware reset on the PHY to take it out of reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1403	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1404	if (hw->mac_type > e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1405	ctrl \|= E1000_CTRL_SLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1406	ctrl &= ~(E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1407	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1408	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1409	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX \| E1000_CTRL_SLU);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1410	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1411	ret_val = e1000_phy_hw_reset(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1412	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1413	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1414	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1415
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1416	/* Make sure we have a valid PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1417	ret_val = e1000_detect_gig_phy(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1418	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1419	DEBUGOUT("Error, did not detect valid phy.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1420	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1421	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1422	DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1423
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1424	/* Set PHY to class A mode (if necessary) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1425	ret_val = e1000_set_phy_mode(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1426	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1427	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1428
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1429	if ((hw->mac_type == e1000_82545_rev_3) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1430	(hw->mac_type == e1000_82546_rev_3)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1431	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1432	phy_data \|= 0x00000008;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1433	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1434	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1435
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1436	if (hw->mac_type <= e1000_82543 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1437	hw->mac_type == e1000_82541 \|\| hw->mac_type == e1000_82547 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1438	hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1439	hw->phy_reset_disable = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1440
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1441	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1442	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1443
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1444
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1445	/********************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1446	* Copper link setup for e1000_phy_igp series.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1447	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1448	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1449	*********************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1450	static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1451	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1452	u32 led_ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1453	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1454	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1455
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1456	DEBUGFUNC("e1000_copper_link_igp_setup");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1457
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1458	if (hw->phy_reset_disable)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1459	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1460
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1461	ret_val = e1000_phy_reset(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1462	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1463	DEBUGOUT("Error Resetting the PHY\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1464	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1465	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1466
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1467	/* Wait 15ms for MAC to configure PHY from eeprom settings */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1468	msleep(15);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1469	if (hw->mac_type != e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1470	/* Configure activity LED after PHY reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1471	led_ctrl = er32(LEDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1472	led_ctrl &= IGP_ACTIVITY_LED_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1473	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1474	ew32(LEDCTL, led_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1475	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1476
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1477	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1478	if (hw->phy_type == e1000_phy_igp) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1479	/* disable lplu d3 during driver init */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1480	ret_val = e1000_set_d3_lplu_state(hw, false);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1481	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1482	DEBUGOUT("Error Disabling LPLU D3\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1483	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1484	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1485	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1486
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1487	/* disable lplu d0 during driver init */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1488	ret_val = e1000_set_d0_lplu_state(hw, false);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1489	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1490	DEBUGOUT("Error Disabling LPLU D0\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1491	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1492	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1493	/* Configure mdi-mdix settings */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1494	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1495	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1496	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1497
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1498	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1499	hw->dsp_config_state = e1000_dsp_config_disabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1500	/* Force MDI for earlier revs of the IGP PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1501	phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX \| IGP01E1000_PSCR_FORCE_MDI_MDIX);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1502	hw->mdix = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1503
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1504	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1505	hw->dsp_config_state = e1000_dsp_config_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1506	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1507
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1508	switch (hw->mdix) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1509	case 1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1510	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1511	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1512	case 2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1513	phy_data \|= IGP01E1000_PSCR_FORCE_MDI_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1514	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1515	case 0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1516	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1517	phy_data \|= IGP01E1000_PSCR_AUTO_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1518	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1519	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1520	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1521	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1522	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1523	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1524
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1525	/* set auto-master slave resolution settings */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1526	if (hw->autoneg) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1527	e1000_ms_type phy_ms_setting = hw->master_slave;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1528
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1529	if (hw->ffe_config_state == e1000_ffe_config_active)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1530	hw->ffe_config_state = e1000_ffe_config_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1531
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1532	if (hw->dsp_config_state == e1000_dsp_config_activated)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1533	hw->dsp_config_state = e1000_dsp_config_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1534
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1535	/* when autonegotiation advertisment is only 1000Mbps then we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1536	* should disable SmartSpeed and enable Auto MasterSlave
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1537	* resolution as hardware default. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1538	if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1539	/* Disable SmartSpeed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1540	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1541	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1542	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1543	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1544	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1545	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1546	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1547	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1548	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1549	/* Set auto Master/Slave resolution process */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1550	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1551	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1552	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1553	phy_data &= ~CR_1000T_MS_ENABLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1554	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1555	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1556	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1557	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1558
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1559	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1560	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1561	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1562
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1563	/* load defaults for future use */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1564	hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1565	((phy_data & CR_1000T_MS_VALUE) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1566	e1000_ms_force_master :
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1567	e1000_ms_force_slave) :
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1568	e1000_ms_auto;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1569
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1570	switch (phy_ms_setting) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1571	case e1000_ms_force_master:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1572	phy_data \|= (CR_1000T_MS_ENABLE \| CR_1000T_MS_VALUE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1573	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1574	case e1000_ms_force_slave:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1575	phy_data \|= CR_1000T_MS_ENABLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1576	phy_data &= ~(CR_1000T_MS_VALUE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1577	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1578	case e1000_ms_auto:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1579	phy_data &= ~CR_1000T_MS_ENABLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1580	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1581	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1582	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1583	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1584	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1585	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1586	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1587
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1588	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1589	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1590
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1591	/********************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1592	* Copper link setup for e1000_phy_gg82563 series.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1593	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1594	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1595	*********************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1596	static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1597	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1598	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1599	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1600	u32 reg_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1601
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1602	DEBUGFUNC("e1000_copper_link_ggp_setup");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1603
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1604	if (!hw->phy_reset_disable) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1605
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1606	/* Enable CRS on TX for half-duplex operation. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1607	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1608	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1609	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1610	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1611
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1612	phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1613	/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1614	phy_data \|= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1615
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1616	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1617	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1618	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1619	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1620
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1621	/* Options:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1622	* MDI/MDI-X = 0 (default)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1623	* 0 - Auto for all speeds
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1624	* 1 - MDI mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1625	* 2 - MDI-X mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1626	* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1627	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1628	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1629	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1630	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1631
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1632	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1633
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1634	switch (hw->mdix) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1635	case 1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1636	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_MDI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1637	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1638	case 2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1639	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1640	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1641	case 0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1642	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1643	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_AUTO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1644	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1645	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1646
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1647	/* Options:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1648	* disable_polarity_correction = 0 (default)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1649	* Automatic Correction for Reversed Cable Polarity
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1650	* 0 - Disabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1651	* 1 - Enabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1652	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1653	phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1654	if (hw->disable_polarity_correction == 1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1655	phy_data \|= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1656	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1657
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1658	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1659	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1660
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1661	/* SW Reset the PHY so all changes take effect */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1662	ret_val = e1000_phy_reset(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1663	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1664	DEBUGOUT("Error Resetting the PHY\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1665	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1666	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1667	} /* phy_reset_disable */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1668
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1669	if (hw->mac_type == e1000_80003es2lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1670	/* Bypass RX and TX FIFO's */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1671	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1672	E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1673	E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1674	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1675	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1676
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1677	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1678	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1679	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1680
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1681	phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1682	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1683
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1684	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1685	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1686
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1687	reg_data = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1688	reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1689	ew32(CTRL_EXT, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1690
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1691	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1692	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1693	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1694	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1695
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1696	/* Do not init these registers when the HW is in IAMT mode, since the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1697	* firmware will have already initialized them. We only initialize
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1698	* them if the HW is not in IAMT mode.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1699	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1700	if (!e1000_check_mng_mode(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1701	/* Enable Electrical Idle on the PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1702	phy_data \|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1703	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1704	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1705	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1706	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1707
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1708	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1709	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1710	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1711	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1712
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1713	phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1714	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1715	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1716
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1717	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1718	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1719	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1720
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1721	/* Workaround: Disable padding in Kumeran interface in the MAC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1722	* and in the PHY to avoid CRC errors.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1723	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1724	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1725	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1726	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1727	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1728	phy_data \|= GG82563_ICR_DIS_PADDING;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1729	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1730	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1731	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1732	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1733	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1734
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1735	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1736	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1737
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1738	/********************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1739	* Copper link setup for e1000_phy_m88 series.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1740	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1741	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1742	*********************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1743	static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1744	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1745	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1746	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1747
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1748	DEBUGFUNC("e1000_copper_link_mgp_setup");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1749
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1750	if (hw->phy_reset_disable)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1751	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1752
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1753	/* Enable CRS on TX. This must be set for half-duplex operation. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1754	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1755	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1756	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1757
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1758	phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1759
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1760	/* Options:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1761	* MDI/MDI-X = 0 (default)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1762	* 0 - Auto for all speeds
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1763	* 1 - MDI mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1764	* 2 - MDI-X mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1765	* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1766	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1767	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1768
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1769	switch (hw->mdix) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1770	case 1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1771	phy_data \|= M88E1000_PSCR_MDI_MANUAL_MODE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1772	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1773	case 2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1774	phy_data \|= M88E1000_PSCR_MDIX_MANUAL_MODE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1775	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1776	case 3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1777	phy_data \|= M88E1000_PSCR_AUTO_X_1000T;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1778	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1779	case 0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1780	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1781	phy_data \|= M88E1000_PSCR_AUTO_X_MODE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1782	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1783	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1784
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1785	/* Options:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1786	* disable_polarity_correction = 0 (default)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1787	* Automatic Correction for Reversed Cable Polarity
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1788	* 0 - Disabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1789	* 1 - Enabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1790	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1791	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1792	if (hw->disable_polarity_correction == 1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1793	phy_data \|= M88E1000_PSCR_POLARITY_REVERSAL;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1794	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1795	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1796	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1797
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1798	if (hw->phy_revision < M88E1011_I_REV_4) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1799	/* Force TX_CLK in the Extended PHY Specific Control Register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1800	* to 25MHz clock.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1801	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1802	ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1803	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1804	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1805
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1806	phy_data \|= M88E1000_EPSCR_TX_CLK_25;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1807
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1808	if ((hw->phy_revision == E1000_REVISION_2) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1809	(hw->phy_id == M88E1111_I_PHY_ID)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1810	/* Vidalia Phy, set the downshift counter to 5x */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1811	phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1812	phy_data \|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1813	ret_val = e1000_write_phy_reg(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1814	M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1815	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1816	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1817	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1818	/* Configure Master and Slave downshift values */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1819	phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1820	M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1821	phy_data \|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1822	M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1823	ret_val = e1000_write_phy_reg(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1824	M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1825	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1826	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1827	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1828	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1829
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1830	/* SW Reset the PHY so all changes take effect */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1831	ret_val = e1000_phy_reset(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1832	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1833	DEBUGOUT("Error Resetting the PHY\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1834	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1835	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1836
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1837	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1838	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1839
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1840	/********************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1841	* Setup auto-negotiation and flow control advertisements,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1842	* and then perform auto-negotiation.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1843	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1844	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1845	*********************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1846	static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1847	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1848	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1849	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1850
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1851	DEBUGFUNC("e1000_copper_link_autoneg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1852
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1853	/* Perform some bounds checking on the hw->autoneg_advertised
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1854	* parameter. If this variable is zero, then set it to the default.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1855	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1856	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1857
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1858	/* If autoneg_advertised is zero, we assume it was not defaulted
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1859	* by the calling code so we set to advertise full capability.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1860	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1861	if (hw->autoneg_advertised == 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1862	hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1863
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1864	/* IFE phy only supports 10/100 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1865	if (hw->phy_type == e1000_phy_ife)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1866	hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1867
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1868	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1869	ret_val = e1000_phy_setup_autoneg(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1870	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1871	DEBUGOUT("Error Setting up Auto-Negotiation\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1872	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1873	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1874	DEBUGOUT("Restarting Auto-Neg\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1875
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1876	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1877	* the Auto Neg Restart bit in the PHY control register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1878	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1879	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1880	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1881	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1882
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1883	phy_data \|= (MII_CR_AUTO_NEG_EN \| MII_CR_RESTART_AUTO_NEG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1884	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1885	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1886	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1887
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1888	/* Does the user want to wait for Auto-Neg to complete here, or
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1889	* check at a later time (for example, callback routine).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1890	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1891	if (hw->wait_autoneg_complete) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1892	ret_val = e1000_wait_autoneg(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1893	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1894	DEBUGOUT("Error while waiting for autoneg to complete\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1895	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1896	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1897	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1898
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1899	hw->get_link_status = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1900
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1901	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1902	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1903
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1904	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1905	* Config the MAC and the PHY after link is up.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1906	* 1) Set up the MAC to the current PHY speed/duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1907	* if we are on 82543. If we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1908	* are on newer silicon, we only need to configure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1909	* collision distance in the Transmit Control Register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1910	* 2) Set up flow control on the MAC to that established with
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1911	* the link partner.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1912	* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1913	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1914	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1915	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1916	static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1917	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1918	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1919	DEBUGFUNC("e1000_copper_link_postconfig");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1920
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1921	if (hw->mac_type >= e1000_82544) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1922	e1000_config_collision_dist(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1923	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1924	ret_val = e1000_config_mac_to_phy(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1925	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1926	DEBUGOUT("Error configuring MAC to PHY settings\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1927	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1928	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1929	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1930	ret_val = e1000_config_fc_after_link_up(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1931	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1932	DEBUGOUT("Error Configuring Flow Control\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1933	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1934	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1935
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1936	/* Config DSP to improve Giga link quality */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1937	if (hw->phy_type == e1000_phy_igp) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1938	ret_val = e1000_config_dsp_after_link_change(hw, true);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1939	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1940	DEBUGOUT("Error Configuring DSP after link up\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1941	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1942	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1943	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1944
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1945	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1946	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1947
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1948	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1949	* Detects which PHY is present and setup the speed and duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1950	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1951	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1952	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1953	static s32 e1000_setup_copper_link(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1954	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1955	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1956	u16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1957	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1958	u16 reg_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1959
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1960	DEBUGFUNC("e1000_setup_copper_link");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1961
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1962	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1963	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1964	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1965	/* Set the mac to wait the maximum time between each
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1966	* iteration and increase the max iterations when
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1967	* polling the phy; this fixes erroneous timeouts at 10Mbps. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1968	ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1969	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1970	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1971	ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1972	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1973	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1974	reg_data \|= 0x3F;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1975	ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1976	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1977	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1978	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1979	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1980	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1981
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1982	/* Check if it is a valid PHY and set PHY mode if necessary. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1983	ret_val = e1000_copper_link_preconfig(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1984	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1985	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1986
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1987	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1988	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1989	/* Kumeran registers are written-only */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1990	reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1991	reg_data \|= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1992	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1993	reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1994	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1995	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1996	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1997	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1998	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	1999	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2000
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2001	if (hw->phy_type == e1000_phy_igp \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2002	hw->phy_type == e1000_phy_igp_3 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2003	hw->phy_type == e1000_phy_igp_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2004	ret_val = e1000_copper_link_igp_setup(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2005	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2006	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2007	} else if (hw->phy_type == e1000_phy_m88) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2008	ret_val = e1000_copper_link_mgp_setup(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2009	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2010	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2011	} else if (hw->phy_type == e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2012	ret_val = e1000_copper_link_ggp_setup(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2013	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2014	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2015	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2016
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2017	if (hw->autoneg) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2018	/* Setup autoneg and flow control advertisement
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2019	* and perform autonegotiation */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2020	ret_val = e1000_copper_link_autoneg(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2021	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2022	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2023	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2024	/* PHY will be set to 10H, 10F, 100H,or 100F
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2025	* depending on value from forced_speed_duplex. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2026	DEBUGOUT("Forcing speed and duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2027	ret_val = e1000_phy_force_speed_duplex(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2028	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2029	DEBUGOUT("Error Forcing Speed and Duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2030	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2031	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2032	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2033
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2034	/* Check link status. Wait up to 100 microseconds for link to become
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2035	* valid.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2036	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2037	for (i = 0; i < 10; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2038	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2039	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2040	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2041	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2042	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2043	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2044
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2045	if (phy_data & MII_SR_LINK_STATUS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2046	/* Config the MAC and PHY after link is up */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2047	ret_val = e1000_copper_link_postconfig(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2048	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2049	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2050
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2051	DEBUGOUT("Valid link established!!!\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2052	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2053	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2054	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2055	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2056
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2057	DEBUGOUT("Unable to establish link!!!\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2058	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2059	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2060
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2061	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2062	* Configure the MAC-to-PHY interface for 10/100Mbps
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2063	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2064	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2065	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2066	static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2067	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2068	s32 ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2069	u32 tipg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2070	u16 reg_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2071
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2072	DEBUGFUNC("e1000_configure_kmrn_for_10_100");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2073
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2074	reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2075	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2076	reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2077	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2078	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2079
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2080	/* Configure Transmit Inter-Packet Gap */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2081	tipg = er32(TIPG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2082	tipg &= ~E1000_TIPG_IPGT_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2083	tipg \|= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2084	ew32(TIPG, tipg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2085
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2086	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2087
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2088	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2089	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2090
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2091	if (duplex == HALF_DUPLEX)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2092	reg_data \|= GG82563_KMCR_PASS_FALSE_CARRIER;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2093	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2094	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2095
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2096	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2097
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2098	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2099	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2100
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2101	static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2102	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2103	s32 ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2104	u16 reg_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2105	u32 tipg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2106
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2107	DEBUGFUNC("e1000_configure_kmrn_for_1000");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2108
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2109	reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2110	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2111	reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2112	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2113	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2114
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2115	/* Configure Transmit Inter-Packet Gap */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2116	tipg = er32(TIPG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2117	tipg &= ~E1000_TIPG_IPGT_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2118	tipg \|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2119	ew32(TIPG, tipg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2120
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2121	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2122
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2123	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2124	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2125
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2126	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2127	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2128
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2129	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2130	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2131
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2132	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2133	* Configures PHY autoneg and flow control advertisement settings
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2134	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2135	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2136	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2137	s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2138	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2139	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2140	u16 mii_autoneg_adv_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2141	u16 mii_1000t_ctrl_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2142
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2143	DEBUGFUNC("e1000_phy_setup_autoneg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2144
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2145	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2146	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2147	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2148	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2149
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2150	if (hw->phy_type != e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2151	/* Read the MII 1000Base-T Control Register (Address 9). */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2152	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2153	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2154	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2155	} else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2156	mii_1000t_ctrl_reg=0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2157
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2158	/* Need to parse both autoneg_advertised and fc and set up
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2159	* the appropriate PHY registers. First we will parse for
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2160	* autoneg_advertised software override. Since we can advertise
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2161	* a plethora of combinations, we need to check each bit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2162	* individually.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2163	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2164
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2165	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2166	* Advertisement Register (Address 4) and the 1000 mb speed bits in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2167	* the 1000Base-T Control Register (Address 9).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2168	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2169	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2170	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2171
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2172	DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2173
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2174	/* Do we want to advertise 10 Mb Half Duplex? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2175	if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2176	DEBUGOUT("Advertise 10mb Half duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2177	mii_autoneg_adv_reg \|= NWAY_AR_10T_HD_CAPS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2178	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2179
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2180	/* Do we want to advertise 10 Mb Full Duplex? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2181	if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2182	DEBUGOUT("Advertise 10mb Full duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2183	mii_autoneg_adv_reg \|= NWAY_AR_10T_FD_CAPS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2184	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2185
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2186	/* Do we want to advertise 100 Mb Half Duplex? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2187	if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2188	DEBUGOUT("Advertise 100mb Half duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2189	mii_autoneg_adv_reg \|= NWAY_AR_100TX_HD_CAPS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2190	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2191
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2192	/* Do we want to advertise 100 Mb Full Duplex? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2193	if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2194	DEBUGOUT("Advertise 100mb Full duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2195	mii_autoneg_adv_reg \|= NWAY_AR_100TX_FD_CAPS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2196	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2197
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2198	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2199	if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2200	DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2201	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2202
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2203	/* Do we want to advertise 1000 Mb Full Duplex? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2204	if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2205	DEBUGOUT("Advertise 1000mb Full duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2206	mii_1000t_ctrl_reg \|= CR_1000T_FD_CAPS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2207	if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2208	DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2209	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2210	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2211
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2212	/* Check for a software override of the flow control settings, and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2213	* setup the PHY advertisement registers accordingly. If
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2214	* auto-negotiation is enabled, then software will have to set the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2215	* "PAUSE" bits to the correct value in the Auto-Negotiation
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2216	* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2217	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2218	* The possible values of the "fc" parameter are:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2219	* 0: Flow control is completely disabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2220	* 1: Rx flow control is enabled (we can receive pause frames
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2221	* but not send pause frames).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2222	* 2: Tx flow control is enabled (we can send pause frames
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2223	* but we do not support receiving pause frames).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2224	* 3: Both Rx and TX flow control (symmetric) are enabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2225	* other: No software override. The flow control configuration
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2226	* in the EEPROM is used.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2227	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2228	switch (hw->fc) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2229	case E1000_FC_NONE: /* 0 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2230	/* Flow control (RX & TX) is completely disabled by a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2231	* software over-ride.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2232	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2233	mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2234	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2235	case E1000_FC_RX_PAUSE: /* 1 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2236	/* RX Flow control is enabled, and TX Flow control is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2237	* disabled, by a software over-ride.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2238	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2239	/* Since there really isn't a way to advertise that we are
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2240	* capable of RX Pause ONLY, we will advertise that we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2241	* support both symmetric and asymmetric RX PAUSE. Later
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2242	* (in e1000_config_fc_after_link_up) we will disable the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2243	*hw's ability to send PAUSE frames.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2244	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2245	mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2246	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2247	case E1000_FC_TX_PAUSE: /* 2 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2248	/* TX Flow control is enabled, and RX Flow control is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2249	* disabled, by a software over-ride.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2250	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2251	mii_autoneg_adv_reg \|= NWAY_AR_ASM_DIR;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2252	mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2253	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2254	case E1000_FC_FULL: /* 3 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2255	/* Flow control (both RX and TX) is enabled by a software
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2256	* over-ride.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2257	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2258	mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2259	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2260	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2261	DEBUGOUT("Flow control param set incorrectly\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2262	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2263	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2264
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2265	ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2266	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2267	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2268
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2269	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2270
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2271	if (hw->phy_type != e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2272	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2273	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2274	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2275	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2276
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2277	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2278	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2279
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2280	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2281	* Force PHY speed and duplex settings to hw->forced_speed_duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2282	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2283	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2284	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2285	static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2286	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2287	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2288	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2289	u16 mii_ctrl_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2290	u16 mii_status_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2291	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2292	u16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2293
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2294	DEBUGFUNC("e1000_phy_force_speed_duplex");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2295
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2296	/* Turn off Flow control if we are forcing speed and duplex. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2297	hw->fc = E1000_FC_NONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2298
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2299	DEBUGOUT1("hw->fc = %d\n", hw->fc);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2300
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2301	/* Read the Device Control Register. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2302	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2303
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2304	/* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2305	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2306	ctrl &= ~(DEVICE_SPEED_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2307
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2308	/* Clear the Auto Speed Detect Enable bit. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2309	ctrl &= ~E1000_CTRL_ASDE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2310
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2311	/* Read the MII Control Register. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2312	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2313	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2314	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2315
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2316	/* We need to disable autoneg in order to force link and duplex. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2317
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2318	mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2319
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2320	/* Are we forcing Full or Half Duplex? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2321	if (hw->forced_speed_duplex == e1000_100_full \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2322	hw->forced_speed_duplex == e1000_10_full) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2323	/* We want to force full duplex so we SET the full duplex bits in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2324	* Device and MII Control Registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2325	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2326	ctrl \|= E1000_CTRL_FD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2327	mii_ctrl_reg \|= MII_CR_FULL_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2328	DEBUGOUT("Full Duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2329	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2330	/* We want to force half duplex so we CLEAR the full duplex bits in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2331	* the Device and MII Control Registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2332	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2333	ctrl &= ~E1000_CTRL_FD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2334	mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2335	DEBUGOUT("Half Duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2336	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2337
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2338	/* Are we forcing 100Mbps??? */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2339	if (hw->forced_speed_duplex == e1000_100_full \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2340	hw->forced_speed_duplex == e1000_100_half) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2341	/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2342	ctrl \|= E1000_CTRL_SPD_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2343	mii_ctrl_reg \|= MII_CR_SPEED_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2344	mii_ctrl_reg &= ~(MII_CR_SPEED_1000 \| MII_CR_SPEED_10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2345	DEBUGOUT("Forcing 100mb ");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2346	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2347	/* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2348	ctrl &= ~(E1000_CTRL_SPD_1000 \| E1000_CTRL_SPD_100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2349	mii_ctrl_reg \|= MII_CR_SPEED_10;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2350	mii_ctrl_reg &= ~(MII_CR_SPEED_1000 \| MII_CR_SPEED_100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2351	DEBUGOUT("Forcing 10mb ");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2352	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2353
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2354	e1000_config_collision_dist(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2355
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2356	/* Write the configured values back to the Device Control Reg. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2357	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2358
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2359	if ((hw->phy_type == e1000_phy_m88) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2360	(hw->phy_type == e1000_phy_gg82563)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2361	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2362	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2363	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2364
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2365	/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2366	* forced whenever speed are duplex are forced.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2367	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2368	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2369	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2370	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2371	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2372
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2373	DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2374
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2375	/* Need to reset the PHY or these changes will be ignored */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2376	mii_ctrl_reg \|= MII_CR_RESET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2377
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2378	/* Disable MDI-X support for 10/100 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2379	} else if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2380	ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2381	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2382	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2383
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2384	phy_data &= ~IFE_PMC_AUTO_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2385	phy_data &= ~IFE_PMC_FORCE_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2386
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2387	ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2388	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2389	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2390
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2391	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2392	/* Clear Auto-Crossover to force MDI manually. IGP requires MDI
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2393	* forced whenever speed or duplex are forced.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2394	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2395	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2396	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2397	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2398
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2399	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2400	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2401
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2402	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2403	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2404	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2405	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2406
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2407	/* Write back the modified PHY MII control register. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2408	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2409	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2410	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2411
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2412	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2413
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2414	/* The wait_autoneg_complete flag may be a little misleading here.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2415	* Since we are forcing speed and duplex, Auto-Neg is not enabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2416	* But we do want to delay for a period while forcing only so we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2417	* don't generate false No Link messages. So we will wait here
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2418	* only if the user has set wait_autoneg_complete to 1, which is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2419	* the default.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2420	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2421	if (hw->wait_autoneg_complete) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2422	/* We will wait for autoneg to complete. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2423	DEBUGOUT("Waiting for forced speed/duplex link.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2424	mii_status_reg = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2425
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2426	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2427	for (i = PHY_FORCE_TIME; i > 0; i--) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2428	/* Read the MII Status Register and wait for Auto-Neg Complete bit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2429	* to be set.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2430	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2431	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2432	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2433	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2434
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2435	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2436	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2437	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2438
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2439	if (mii_status_reg & MII_SR_LINK_STATUS) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2440	msleep(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2441	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2442	if ((i == 0) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2443	((hw->phy_type == e1000_phy_m88) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2444	(hw->phy_type == e1000_phy_gg82563))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2445	/* We didn't get link. Reset the DSP and wait again for link. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2446	ret_val = e1000_phy_reset_dsp(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2447	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2448	DEBUGOUT("Error Resetting PHY DSP\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2449	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2450	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2451	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2452	/* This loop will early-out if the link condition has been met. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2453	for (i = PHY_FORCE_TIME; i > 0; i--) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2454	if (mii_status_reg & MII_SR_LINK_STATUS) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2455	msleep(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2456	/* Read the MII Status Register and wait for Auto-Neg Complete bit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2457	* to be set.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2458	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2459	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2460	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2461	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2462
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2463	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2464	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2465	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2466	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2467	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2468
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2469	if (hw->phy_type == e1000_phy_m88) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2470	/* Because we reset the PHY above, we need to re-force TX_CLK in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2471	* Extended PHY Specific Control Register to 25MHz clock. This value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2472	* defaults back to a 2.5MHz clock when the PHY is reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2473	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2474	ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2475	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2476	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2477
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2478	phy_data \|= M88E1000_EPSCR_TX_CLK_25;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2479	ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2480	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2481	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2482
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2483	/* In addition, because of the s/w reset above, we need to enable CRS on
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2484	* TX. This must be set for both full and half duplex operation.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2485	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2486	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2487	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2488	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2489
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2490	phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2491	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2492	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2493	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2494
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2495	if ((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2496	(!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2497	hw->forced_speed_duplex == e1000_10_half)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2498	ret_val = e1000_polarity_reversal_workaround(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2499	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2500	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2501	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2502	} else if (hw->phy_type == e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2503	/* The TX_CLK of the Extended PHY Specific Control Register defaults
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2504	* to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2505	* we're not in a forced 10/duplex configuration. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2506	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2507	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2508	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2509
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2510	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2511	if ((hw->forced_speed_duplex == e1000_10_full) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2512	(hw->forced_speed_duplex == e1000_10_half))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2513	phy_data \|= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2514	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2515	phy_data \|= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2516
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2517	/* Also due to the reset, we need to enable CRS on Tx. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2518	phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2519
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2520	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2521	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2522	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2523	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2524	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2525	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2526
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2527	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2528	* Sets the collision distance in the Transmit Control register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2529	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2530	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2531	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2532	* Link should have been established previously. Reads the speed and duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2533	* information from the Device Status register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2534	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2535	void e1000_config_collision_dist(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2536	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2537	u32 tctl, coll_dist;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2538
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2539	DEBUGFUNC("e1000_config_collision_dist");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2540
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2541	if (hw->mac_type < e1000_82543)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2542	coll_dist = E1000_COLLISION_DISTANCE_82542;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2543	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2544	coll_dist = E1000_COLLISION_DISTANCE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2545
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2546	tctl = er32(TCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2547
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2548	tctl &= ~E1000_TCTL_COLD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2549	tctl \|= coll_dist << E1000_COLD_SHIFT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2550
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2551	ew32(TCTL, tctl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2552	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2553	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2554
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2555	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2556	* Sets MAC speed and duplex settings to reflect the those in the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2557	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2558	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2559	* mii_reg - data to write to the MII control register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2560	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2561	* The contents of the PHY register containing the needed information need to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2562	* be passed in.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2563	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2564	static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2565	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2566	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2567	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2568	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2569
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2570	DEBUGFUNC("e1000_config_mac_to_phy");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2571
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2572	/* 82544 or newer MAC, Auto Speed Detection takes care of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2573	* MAC speed/duplex configuration.*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2574	if (hw->mac_type >= e1000_82544)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2575	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2576
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2577	/* Read the Device Control Register and set the bits to Force Speed
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2578	* and Duplex.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2579	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2580	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2581	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2582	ctrl &= ~(E1000_CTRL_SPD_SEL \| E1000_CTRL_ILOS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2583
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2584	/* Set up duplex in the Device Control and Transmit Control
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2585	* registers depending on negotiated values.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2586	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2587	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2588	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2589	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2590
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2591	if (phy_data & M88E1000_PSSR_DPLX)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2592	ctrl \|= E1000_CTRL_FD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2593	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2594	ctrl &= ~E1000_CTRL_FD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2595
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2596	e1000_config_collision_dist(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2597
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2598	/* Set up speed in the Device Control register depending on
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2599	* negotiated values.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2600	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2601	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2602	ctrl \|= E1000_CTRL_SPD_1000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2603	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2604	ctrl \|= E1000_CTRL_SPD_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2605
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2606	/* Write the configured values back to the Device Control Reg. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2607	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2608	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2609	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2610
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2611	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2612	* Forces the MAC's flow control settings.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2613	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2614	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2615	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2616	* Sets the TFCE and RFCE bits in the device control register to reflect
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2617	* the adapter settings. TFCE and RFCE need to be explicitly set by
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2618	* software when a Copper PHY is used because autonegotiation is managed
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2619	* by the PHY rather than the MAC. Software must also configure these
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2620	* bits when link is forced on a fiber connection.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2621	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2622	s32 e1000_force_mac_fc(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2623	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2624	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2625
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2626	DEBUGFUNC("e1000_force_mac_fc");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2627
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2628	/* Get the current configuration of the Device Control Register */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2629	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2630
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2631	/* Because we didn't get link via the internal auto-negotiation
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2632	* mechanism (we either forced link or we got link via PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2633	* auto-neg), we have to manually enable/disable transmit an
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2634	* receive flow control.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2635	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2636	* The "Case" statement below enables/disable flow control
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2637	* according to the "hw->fc" parameter.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2638	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2639	* The possible values of the "fc" parameter are:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2640	* 0: Flow control is completely disabled
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2641	* 1: Rx flow control is enabled (we can receive pause
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2642	* frames but not send pause frames).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2643	* 2: Tx flow control is enabled (we can send pause frames
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2644	* frames but we do not receive pause frames).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2645	* 3: Both Rx and TX flow control (symmetric) is enabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2646	* other: No other values should be possible at this point.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2647	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2648
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2649	switch (hw->fc) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2650	case E1000_FC_NONE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2651	ctrl &= (~(E1000_CTRL_TFCE \| E1000_CTRL_RFCE));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2652	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2653	case E1000_FC_RX_PAUSE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2654	ctrl &= (~E1000_CTRL_TFCE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2655	ctrl \|= E1000_CTRL_RFCE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2656	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2657	case E1000_FC_TX_PAUSE:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2658	ctrl &= (~E1000_CTRL_RFCE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2659	ctrl \|= E1000_CTRL_TFCE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2660	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2661	case E1000_FC_FULL:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2662	ctrl \|= (E1000_CTRL_TFCE \| E1000_CTRL_RFCE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2663	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2664	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2665	DEBUGOUT("Flow control param set incorrectly\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2666	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2667	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2668
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2669	/* Disable TX Flow Control for 82542 (rev 2.0) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2670	if (hw->mac_type == e1000_82542_rev2_0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2671	ctrl &= (~E1000_CTRL_TFCE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2672
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2673	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2674	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2675	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2676
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2677	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2678	* Configures flow control settings after link is established
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2679	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2680	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2681	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2682	* Should be called immediately after a valid link has been established.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2683	* Forces MAC flow control settings if link was forced. When in MII/GMII mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2684	* and autonegotiation is enabled, the MAC flow control settings will be set
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2685	* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2686	* and RFCE bits will be automaticaly set to the negotiated flow control mode.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2687	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2688	static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2689	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2690	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2691	u16 mii_status_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2692	u16 mii_nway_adv_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2693	u16 mii_nway_lp_ability_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2694	u16 speed;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2695	u16 duplex;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2696
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2697	DEBUGFUNC("e1000_config_fc_after_link_up");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2698
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2699	/* Check for the case where we have fiber media and auto-neg failed
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2700	* so we had to force link. In this case, we need to force the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2701	* configuration of the MAC to match the "fc" parameter.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2702	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2703	if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2704	((hw->media_type == e1000_media_type_internal_serdes) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2705	(hw->autoneg_failed)) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2706	((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2707	ret_val = e1000_force_mac_fc(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2708	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2709	DEBUGOUT("Error forcing flow control settings\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2710	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2711	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2712	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2713
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2714	/* Check for the case where we have copper media and auto-neg is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2715	* enabled. In this case, we need to check and see if Auto-Neg
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2716	* has completed, and if so, how the PHY and link partner has
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2717	* flow control configured.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2718	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2719	if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2720	/* Read the MII Status Register and check to see if AutoNeg
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2721	* has completed. We read this twice because this reg has
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2722	* some "sticky" (latched) bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2723	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2724	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2725	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2726	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2727	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2728	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2729	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2730
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2731	if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2732	/* The AutoNeg process has completed, so we now need to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2733	* read both the Auto Negotiation Advertisement Register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2734	* (Address 4) and the Auto_Negotiation Base Page Ability
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2735	* Register (Address 5) to determine how flow control was
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2736	* negotiated.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2737	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2738	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2739	&mii_nway_adv_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2740	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2741	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2742	ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2743	&mii_nway_lp_ability_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2744	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2745	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2746
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2747	/* Two bits in the Auto Negotiation Advertisement Register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2748	* (Address 4) and two bits in the Auto Negotiation Base
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2749	* Page Ability Register (Address 5) determine flow control
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2750	* for both the PHY and the link partner. The following
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2751	* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2752	* 1999, describes these PAUSE resolution bits and how flow
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2753	* control is determined based upon these settings.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2754	* NOTE: DC = Don't Care
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2755	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2756	* LOCAL DEVICE \| LINK PARTNER
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2757	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| NIC Resolution
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2758	*-------\|---------\|-------\|---------\|--------------------
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2759	* 0 \| 0 \| DC \| DC \| E1000_FC_NONE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2760	* 0 \| 1 \| 0 \| DC \| E1000_FC_NONE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2761	* 0 \| 1 \| 1 \| 0 \| E1000_FC_NONE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2762	* 0 \| 1 \| 1 \| 1 \| E1000_FC_TX_PAUSE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2763	* 1 \| 0 \| 0 \| DC \| E1000_FC_NONE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2764	* 1 \| DC \| 1 \| DC \| E1000_FC_FULL
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2765	* 1 \| 1 \| 0 \| 0 \| E1000_FC_NONE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2766	* 1 \| 1 \| 0 \| 1 \| E1000_FC_RX_PAUSE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2767	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2768	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2769	/* Are both PAUSE bits set to 1? If so, this implies
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2770	* Symmetric Flow Control is enabled at both ends. The
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2771	* ASM_DIR bits are irrelevant per the spec.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2772	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2773	* For Symmetric Flow Control:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2774	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2775	* LOCAL DEVICE \| LINK PARTNER
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2776	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2777	*-------\|---------\|-------\|---------\|--------------------
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2778	* 1 \| DC \| 1 \| DC \| E1000_FC_FULL
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2779	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2780	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2781	if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2782	(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2783	/* Now we need to check if the user selected RX ONLY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2784	* of pause frames. In this case, we had to advertise
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2785	* FULL flow control because we could not advertise RX
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2786	* ONLY. Hence, we must now check to see if we need to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2787	* turn OFF the TRANSMISSION of PAUSE frames.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2788	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2789	if (hw->original_fc == E1000_FC_FULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2790	hw->fc = E1000_FC_FULL;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2791	DEBUGOUT("Flow Control = FULL.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2792	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2793	hw->fc = E1000_FC_RX_PAUSE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2794	DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2795	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2796	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2797	/* For receiving PAUSE frames ONLY.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2798	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2799	* LOCAL DEVICE \| LINK PARTNER
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2800	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2801	*-------\|---------\|-------\|---------\|--------------------
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2802	* 0 \| 1 \| 1 \| 1 \| E1000_FC_TX_PAUSE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2803	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2804	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2805	else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2806	(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2807	(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2808	(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2809	hw->fc = E1000_FC_TX_PAUSE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2810	DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2811	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2812	/* For transmitting PAUSE frames ONLY.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2813	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2814	* LOCAL DEVICE \| LINK PARTNER
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2815	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2816	*-------\|---------\|-------\|---------\|--------------------
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2817	* 1 \| 1 \| 0 \| 1 \| E1000_FC_RX_PAUSE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2818	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2819	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2820	else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2821	(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2822	!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2823	(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2824	hw->fc = E1000_FC_RX_PAUSE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2825	DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2826	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2827	/* Per the IEEE spec, at this point flow control should be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2828	* disabled. However, we want to consider that we could
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2829	* be connected to a legacy switch that doesn't advertise
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2830	* desired flow control, but can be forced on the link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2831	* partner. So if we advertised no flow control, that is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2832	* what we will resolve to. If we advertised some kind of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2833	* receive capability (Rx Pause Only or Full Flow Control)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2834	* and the link partner advertised none, we will configure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2835	* ourselves to enable Rx Flow Control only. We can do
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2836	* this safely for two reasons: If the link partner really
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2837	* didn't want flow control enabled, and we enable Rx, no
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2838	* harm done since we won't be receiving any PAUSE frames
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2839	* anyway. If the intent on the link partner was to have
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2840	* flow control enabled, then by us enabling RX only, we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2841	* can at least receive pause frames and process them.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2842	* This is a good idea because in most cases, since we are
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2843	* predominantly a server NIC, more times than not we will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2844	* be asked to delay transmission of packets than asking
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2845	* our link partner to pause transmission of frames.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2846	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2847	else if ((hw->original_fc == E1000_FC_NONE \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2848	hw->original_fc == E1000_FC_TX_PAUSE) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2849	hw->fc_strict_ieee) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2850	hw->fc = E1000_FC_NONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2851	DEBUGOUT("Flow Control = NONE.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2852	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2853	hw->fc = E1000_FC_RX_PAUSE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2854	DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2855	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2856
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2857	/* Now we need to do one last check... If we auto-
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2858	* negotiated to HALF DUPLEX, flow control should not be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2859	* enabled per IEEE 802.3 spec.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2860	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2861	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2862	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2863	DEBUGOUT("Error getting link speed and duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2864	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2865	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2866
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2867	if (duplex == HALF_DUPLEX)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2868	hw->fc = E1000_FC_NONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2869
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2870	/* Now we call a subroutine to actually force the MAC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2871	* controller to use the correct flow control settings.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2872	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2873	ret_val = e1000_force_mac_fc(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2874	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2875	DEBUGOUT("Error forcing flow control settings\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2876	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2877	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2878	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2879	DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2880	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2881	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2882	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2883	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2884
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2885	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2886	* Checks to see if the link status of the hardware has changed.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2887	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2888	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2889	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2890	* Called by any function that needs to check the link status of the adapter.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2891	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2892	s32 e1000_check_for_link(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2893	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2894	u32 rxcw = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2895	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2896	u32 status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2897	u32 rctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2898	u32 icr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2899	u32 signal = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2900	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2901	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2902
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2903	DEBUGFUNC("e1000_check_for_link");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2904
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2905	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2906	status = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2907
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2908	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2909	* set when the optics detect a signal. On older adapters, it will be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2910	* cleared when there is a signal. This applies to fiber media only.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2911	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2912	if ((hw->media_type == e1000_media_type_fiber) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2913	(hw->media_type == e1000_media_type_internal_serdes)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2914	rxcw = er32(RXCW);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2915
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2916	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2917	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2918	if (status & E1000_STATUS_LU)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2919	hw->get_link_status = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2920	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2921	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2922
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2923	/* If we have a copper PHY then we only want to go out to the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2924	* registers to see if Auto-Neg has completed and/or if our link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2925	* status has changed. The get_link_status flag will be set if we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2926	* receive a Link Status Change interrupt or we have Rx Sequence
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2927	* Errors.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2928	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2929	if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2930	/* First we want to see if the MII Status Register reports
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2931	* link. If so, then we want to get the current speed/duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2932	* of the PHY.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2933	* Read the register twice since the link bit is sticky.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2934	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2935	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2936	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2937	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2938	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2939	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2940	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2941
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2942	if (phy_data & MII_SR_LINK_STATUS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2943	hw->get_link_status = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2944	/* Check if there was DownShift, must be checked immediately after
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2945	* link-up */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2946	e1000_check_downshift(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2947
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2948	/* If we are on 82544 or 82543 silicon and speed/duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2949	* are forced to 10H or 10F, then we will implement the polarity
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2950	* reversal workaround. We disable interrupts first, and upon
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2951	* returning, place the devices interrupt state to its previous
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2952	* value except for the link status change interrupt which will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2953	* happen due to the execution of this workaround.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2954	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2955
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2956	if ((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2957	(!hw->autoneg) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2958	(hw->forced_speed_duplex == e1000_10_full \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2959	hw->forced_speed_duplex == e1000_10_half)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2960	ew32(IMC, 0xffffffff);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2961	ret_val = e1000_polarity_reversal_workaround(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2962	icr = er32(ICR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2963	ew32(ICS, (icr & ~E1000_ICS_LSC));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2964	ew32(IMS, IMS_ENABLE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2965	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2966
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2967	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2968	/* No link detected */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2969	e1000_config_dsp_after_link_change(hw, false);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2970	return 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2971	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2972
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2973	/* If we are forcing speed/duplex, then we simply return since
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2974	* we have already determined whether we have link or not.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2975	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2976	if (!hw->autoneg) return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2977
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2978	/* optimize the dsp settings for the igp phy */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2979	e1000_config_dsp_after_link_change(hw, true);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2980
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2981	/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2982	* have Si on board that is 82544 or newer, Auto
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2983	* Speed Detection takes care of MAC speed/duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2984	* configuration. So we only need to configure Collision
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2985	* Distance in the MAC. Otherwise, we need to force
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2986	* speed/duplex on the MAC to the current PHY speed/duplex
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2987	* settings.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2988	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2989	if (hw->mac_type >= e1000_82544)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2990	e1000_config_collision_dist(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2991	else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2992	ret_val = e1000_config_mac_to_phy(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2993	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2994	DEBUGOUT("Error configuring MAC to PHY settings\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2995	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2996	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2997	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2998
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	2999	/* Configure Flow Control now that Auto-Neg has completed. First, we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3000	* need to restore the desired flow control settings because we may
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3001	* have had to re-autoneg with a different link partner.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3002	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3003	ret_val = e1000_config_fc_after_link_up(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3004	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3005	DEBUGOUT("Error configuring flow control\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3006	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3007	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3008
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3009	/* At this point we know that we are on copper and we have
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3010	* auto-negotiated link. These are conditions for checking the link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3011	* partner capability register. We use the link speed to determine if
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3012	* TBI compatibility needs to be turned on or off. If the link is not
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3013	* at gigabit speed, then TBI compatibility is not needed. If we are
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3014	* at gigabit speed, we turn on TBI compatibility.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3015	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3016	if (hw->tbi_compatibility_en) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3017	u16 speed, duplex;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3018	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3019	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3020	DEBUGOUT("Error getting link speed and duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3021	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3022	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3023	if (speed != SPEED_1000) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3024	/* If link speed is not set to gigabit speed, we do not need
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3025	* to enable TBI compatibility.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3026	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3027	if (hw->tbi_compatibility_on) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3028	/* If we previously were in the mode, turn it off. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3029	rctl = er32(RCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3030	rctl &= ~E1000_RCTL_SBP;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3031	ew32(RCTL, rctl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3032	hw->tbi_compatibility_on = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3033	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3034	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3035	/* If TBI compatibility is was previously off, turn it on. For
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3036	* compatibility with a TBI link partner, we will store bad
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3037	* packets. Some frames have an additional byte on the end and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3038	* will look like CRC errors to to the hardware.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3039	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3040	if (!hw->tbi_compatibility_on) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3041	hw->tbi_compatibility_on = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3042	rctl = er32(RCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3043	rctl \|= E1000_RCTL_SBP;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3044	ew32(RCTL, rctl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3045	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3046	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3047	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3048	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3049	/* If we don't have link (auto-negotiation failed or link partner cannot
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3050	* auto-negotiate), the cable is plugged in (we have signal), and our
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3051	* link partner is not trying to auto-negotiate with us (we are receiving
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3052	* idles or data), we need to force link up. We also need to give
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3053	* auto-negotiation time to complete, in case the cable was just plugged
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3054	* in. The autoneg_failed flag does this.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3055	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3056	else if ((((hw->media_type == e1000_media_type_fiber) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3057	((ctrl & E1000_CTRL_SWDPIN1) == signal)) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3058	(hw->media_type == e1000_media_type_internal_serdes)) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3059	(!(status & E1000_STATUS_LU)) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3060	(!(rxcw & E1000_RXCW_C))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3061	if (hw->autoneg_failed == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3062	hw->autoneg_failed = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3063	return 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3064	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3065	DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3066
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3067	/* Disable auto-negotiation in the TXCW register */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3068	ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3069
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3070	/* Force link-up and also force full-duplex. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3071	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3072	ctrl \|= (E1000_CTRL_SLU \| E1000_CTRL_FD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3073	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3074
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3075	/* Configure Flow Control after forcing link up. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3076	ret_val = e1000_config_fc_after_link_up(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3077	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3078	DEBUGOUT("Error configuring flow control\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3079	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3080	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3081	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3082	/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3083	* auto-negotiation in the TXCW register and disable forced link in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3084	* Device Control register in an attempt to auto-negotiate with our link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3085	* partner.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3086	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3087	else if (((hw->media_type == e1000_media_type_fiber) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3088	(hw->media_type == e1000_media_type_internal_serdes)) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3089	(ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3090	DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3091	ew32(TXCW, hw->txcw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3092	ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3093
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3094	hw->serdes_link_down = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3095	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3096	/* If we force link for non-auto-negotiation switch, check link status
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3097	* based on MAC synchronization for internal serdes media type.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3098	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3099	else if ((hw->media_type == e1000_media_type_internal_serdes) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3100	!(E1000_TXCW_ANE & er32(TXCW))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3101	/* SYNCH bit and IV bit are sticky. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3102	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3103	if (E1000_RXCW_SYNCH & er32(RXCW)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3104	if (!(rxcw & E1000_RXCW_IV)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3105	hw->serdes_link_down = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3106	DEBUGOUT("SERDES: Link is up.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3107	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3108	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3109	hw->serdes_link_down = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3110	DEBUGOUT("SERDES: Link is down.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3111	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3112	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3113	if ((hw->media_type == e1000_media_type_internal_serdes) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3114	(E1000_TXCW_ANE & er32(TXCW))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3115	hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3116	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3117	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3118	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3119
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3120	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3121	* Detects the current speed and duplex settings of the hardware.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3122	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3123	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3124	* speed - Speed of the connection
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3125	* duplex - Duplex setting of the connection
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3126	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3127	s32 e1000_get_speed_and_duplex(struct e1000_hw hw, u16 speed, u16 *duplex)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3128	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3129	u32 status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3130	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3131	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3132
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3133	DEBUGFUNC("e1000_get_speed_and_duplex");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3134
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3135	if (hw->mac_type >= e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3136	status = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3137	if (status & E1000_STATUS_SPEED_1000) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3138	*speed = SPEED_1000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3139	DEBUGOUT("1000 Mbs, ");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3140	} else if (status & E1000_STATUS_SPEED_100) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3141	*speed = SPEED_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3142	DEBUGOUT("100 Mbs, ");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3143	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3144	*speed = SPEED_10;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3145	DEBUGOUT("10 Mbs, ");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3146	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3147
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3148	if (status & E1000_STATUS_FD) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3149	*duplex = FULL_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3150	DEBUGOUT("Full Duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3151	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3152	*duplex = HALF_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3153	DEBUGOUT(" Half Duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3154	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3155	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3156	DEBUGOUT("1000 Mbs, Full Duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3157	*speed = SPEED_1000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3158	*duplex = FULL_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3159	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3160
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3161	/* IGP01 PHY may advertise full duplex operation after speed downgrade even
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3162	* if it is operating at half duplex. Here we set the duplex settings to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3163	* match the duplex in the link partner's capabilities.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3164	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3165	if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3166	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3167	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3168	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3169
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3170	if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3171	*duplex = HALF_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3172	else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3173	ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3174	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3175	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3176	if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3177	(*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3178	*duplex = HALF_DUPLEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3179	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3180	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3181
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3182	if ((hw->mac_type == e1000_80003es2lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3183	(hw->media_type == e1000_media_type_copper)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3184	if (*speed == SPEED_1000)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3185	ret_val = e1000_configure_kmrn_for_1000(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3186	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3187	ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3188	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3189	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3190	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3191
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3192	if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3193	ret_val = e1000_kumeran_lock_loss_workaround(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3194	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3195	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3196	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3197
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3198	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3199	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3200
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3201	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3202	* Blocks until autoneg completes or times out (~4.5 seconds)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3203	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3204	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3205	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3206	static s32 e1000_wait_autoneg(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3207	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3208	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3209	u16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3210	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3211
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3212	DEBUGFUNC("e1000_wait_autoneg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3213	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3214
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3215	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3216	for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3217	/* Read the MII Status Register and wait for Auto-Neg
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3218	* Complete bit to be set.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3219	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3220	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3221	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3222	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3223	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3224	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3225	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3226	if (phy_data & MII_SR_AUTONEG_COMPLETE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3227	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3228	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3229	msleep(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3230	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3231	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3232	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3233
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3234	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3235	* Raises the Management Data Clock
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3236	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3237	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3238	* ctrl - Device control register's current value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3239	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3240	static void e1000_raise_mdi_clk(struct e1000_hw hw, u32 ctrl)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3241	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3242	/* Raise the clock input to the Management Data Clock (by setting the MDC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3243	* bit), and then delay 10 microseconds.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3244	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3245	ew32(CTRL, (*ctrl \| E1000_CTRL_MDC));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3246	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3247	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3248	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3249
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3250	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3251	* Lowers the Management Data Clock
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3252	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3253	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3254	* ctrl - Device control register's current value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3255	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3256	static void e1000_lower_mdi_clk(struct e1000_hw hw, u32 ctrl)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3257	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3258	/* Lower the clock input to the Management Data Clock (by clearing the MDC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3259	* bit), and then delay 10 microseconds.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3260	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3261	ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3262	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3263	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3264	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3265
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3266	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3267	* Shifts data bits out to the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3268	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3269	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3270	* data - Data to send out to the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3271	* count - Number of bits to shift out
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3272	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3273	* Bits are shifted out in MSB to LSB order.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3274	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3275	static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3276	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3277	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3278	u32 mask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3279
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3280	/* We need to shift "count" number of bits out to the PHY. So, the value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3281	* in the "data" parameter will be shifted out to the PHY one bit at a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3282	* time. In order to do this, "data" must be broken down into bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3283	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3284	mask = 0x01;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3285	mask <<= (count - 1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3286
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3287	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3288
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3289	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3290	ctrl \|= (E1000_CTRL_MDIO_DIR \| E1000_CTRL_MDC_DIR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3291
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3292	while (mask) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3293	/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3294	* then raising and lowering the Management Data Clock. A "0" is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3295	* shifted out to the PHY by setting the MDIO bit to "0" and then
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3296	* raising and lowering the clock.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3297	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3298	if (data & mask)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3299	ctrl \|= E1000_CTRL_MDIO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3300	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3301	ctrl &= ~E1000_CTRL_MDIO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3302
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3303	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3304	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3305
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3306	udelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3307
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3308	e1000_raise_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3309	e1000_lower_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3310
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3311	mask = mask >> 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3312	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3313	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3314
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3315	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3316	* Shifts data bits in from the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3317	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3318	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3319	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3320	* Bits are shifted in in MSB to LSB order.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3321	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3322	static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3323	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3324	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3325	u16 data = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3326	u8 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3327
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3328	/* In order to read a register from the PHY, we need to shift in a total
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3329	* of 18 bits from the PHY. The first two bit (turnaround) times are used
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3330	* to avoid contention on the MDIO pin when a read operation is performed.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3331	* These two bits are ignored by us and thrown away. Bits are "shifted in"
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3332	* by raising the input to the Management Data Clock (setting the MDC bit),
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3333	* and then reading the value of the MDIO bit.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3334	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3335	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3336
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3337	/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3338	ctrl &= ~E1000_CTRL_MDIO_DIR;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3339	ctrl &= ~E1000_CTRL_MDIO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3340
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3341	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3342	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3343
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3344	/* Raise and Lower the clock before reading in the data. This accounts for
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3345	* the turnaround bits. The first clock occurred when we clocked out the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3346	* last bit of the Register Address.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3347	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3348	e1000_raise_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3349	e1000_lower_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3350
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3351	for (data = 0, i = 0; i < 16; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3352	data = data << 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3353	e1000_raise_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3354	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3355	/* Check to see if we shifted in a "1". */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3356	if (ctrl & E1000_CTRL_MDIO)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3357	data \|= 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3358	e1000_lower_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3359	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3360
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3361	e1000_raise_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3362	e1000_lower_mdi_clk(hw, &ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3363
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3364	return data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3365	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3366
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3367	static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3368	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3369	u32 swfw_sync = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3370	u32 swmask = mask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3371	u32 fwmask = mask << 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3372	s32 timeout = 200;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3373
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3374	DEBUGFUNC("e1000_swfw_sync_acquire");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3375
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3376	if (hw->swfwhw_semaphore_present)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3377	return e1000_get_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3378
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3379	if (!hw->swfw_sync_present)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3380	return e1000_get_hw_eeprom_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3381
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3382	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3383	if (e1000_get_hw_eeprom_semaphore(hw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3384	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3385
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3386	swfw_sync = er32(SW_FW_SYNC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3387	if (!(swfw_sync & (fwmask \| swmask))) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3388	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3389	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3390
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3391	/* firmware currently using resource (fwmask) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3392	/* or other software thread currently using resource (swmask) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3393	e1000_put_hw_eeprom_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3394	mdelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3395	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3396	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3397
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3398	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3399	DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3400	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3401	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3402
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3403	swfw_sync \|= swmask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3404	ew32(SW_FW_SYNC, swfw_sync);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3405
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3406	e1000_put_hw_eeprom_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3407	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3408	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3409
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3410	static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3411	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3412	u32 swfw_sync;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3413	u32 swmask = mask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3414
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3415	DEBUGFUNC("e1000_swfw_sync_release");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3416
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3417	if (hw->swfwhw_semaphore_present) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3418	e1000_release_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3419	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3420	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3421
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3422	if (!hw->swfw_sync_present) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3423	e1000_put_hw_eeprom_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3424	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3425	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3426
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3427	/* if (e1000_get_hw_eeprom_semaphore(hw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3428	* return -E1000_ERR_SWFW_SYNC; */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3429	while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3430	/* empty */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3431
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3432	swfw_sync = er32(SW_FW_SYNC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3433	swfw_sync &= ~swmask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3434	ew32(SW_FW_SYNC, swfw_sync);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3435
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3436	e1000_put_hw_eeprom_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3437	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3438
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3439	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3440	* Reads the value from a PHY register, if the value is on a specific non zero
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3441	* page, sets the page first.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3442	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3443	* reg_addr - address of the PHY register to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3444	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3445	s32 e1000_read_phy_reg(struct e1000_hw hw, u32 reg_addr, u16 phy_data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3446	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3447	u32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3448	u16 swfw;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3449
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3450	DEBUGFUNC("e1000_read_phy_reg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3451
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3452	if ((hw->mac_type == e1000_80003es2lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3453	(er32(STATUS) & E1000_STATUS_FUNC_1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3454	swfw = E1000_SWFW_PHY1_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3455	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3456	swfw = E1000_SWFW_PHY0_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3457	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3458	if (e1000_swfw_sync_acquire(hw, swfw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3459	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3460
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3461	if ((hw->phy_type == e1000_phy_igp \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3462	hw->phy_type == e1000_phy_igp_3 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3463	hw->phy_type == e1000_phy_igp_2) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3464	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3465	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3466	(u16)reg_addr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3467	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3468	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3469	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3470	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3471	} else if (hw->phy_type == e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3472	if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3473	(hw->mac_type == e1000_80003es2lan)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3474	/* Select Configuration Page */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3475	if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3476	ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3477	(u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3478	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3479	/* Use Alternative Page Select register to access
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3480	* registers 30 and 31
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3481	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3482	ret_val = e1000_write_phy_reg_ex(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3483	GG82563_PHY_PAGE_SELECT_ALT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3484	(u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3485	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3486
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3487	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3488	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3489	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3490	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3491	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3492	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3493
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3494	ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3495	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3496
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3497	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3498	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3499	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3500
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3501	static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3502	u16 *phy_data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3503	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3504	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3505	u32 mdic = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3506	const u32 phy_addr = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3507
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3508	DEBUGFUNC("e1000_read_phy_reg_ex");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3509
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3510	if (reg_addr > MAX_PHY_REG_ADDRESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3511	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3512	return -E1000_ERR_PARAM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3513	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3514
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3515	if (hw->mac_type > e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3516	/* Set up Op-code, Phy Address, and register address in the MDI
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3517	* Control register. The MAC will take care of interfacing with the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3518	* PHY to retrieve the desired data.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3519	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3520	mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3521	(phy_addr << E1000_MDIC_PHY_SHIFT) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3522	(E1000_MDIC_OP_READ));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3523
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3524	ew32(MDIC, mdic);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3525
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3526	/* Poll the ready bit to see if the MDI read completed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3527	for (i = 0; i < 64; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3528	udelay(50);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3529	mdic = er32(MDIC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3530	if (mdic & E1000_MDIC_READY) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3531	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3532	if (!(mdic & E1000_MDIC_READY)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3533	DEBUGOUT("MDI Read did not complete\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3534	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3535	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3536	if (mdic & E1000_MDIC_ERROR) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3537	DEBUGOUT("MDI Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3538	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3539	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3540	*phy_data = (u16)mdic;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3541	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3542	/* We must first send a preamble through the MDIO pin to signal the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3543	* beginning of an MII instruction. This is done by sending 32
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3544	* consecutive "1" bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3545	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3546	e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3547
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3548	/* Now combine the next few fields that are required for a read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3549	* operation. We use this method instead of calling the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3550	* e1000_shift_out_mdi_bits routine five different times. The format of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3551	* a MII read instruction consists of a shift out of 14 bits and is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3552	* defined as follows:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3553	* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3554	* followed by a shift in of 18 bits. This first two bits shifted in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3555	* are TurnAround bits used to avoid contention on the MDIO pin when a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3556	* READ operation is performed. These two bits are thrown away
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3557	* followed by a shift in of 16 bits which contains the desired data.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3558	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3559	mdic = ((reg_addr) \| (phy_addr << 5) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3560	(PHY_OP_READ << 10) \| (PHY_SOF << 12));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3561
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3562	e1000_shift_out_mdi_bits(hw, mdic, 14);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3563
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3564	/* Now that we've shifted out the read command to the MII, we need to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3565	* "shift in" the 16-bit value (18 total bits) of the requested PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3566	* register address.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3567	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3568	*phy_data = e1000_shift_in_mdi_bits(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3569	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3570	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3571	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3572
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3573	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3574	* Writes a value to a PHY register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3575	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3576	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3577	* reg_addr - address of the PHY register to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3578	* data - data to write to the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3579	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3580	s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3581	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3582	u32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3583	u16 swfw;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3584
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3585	DEBUGFUNC("e1000_write_phy_reg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3586
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3587	if ((hw->mac_type == e1000_80003es2lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3588	(er32(STATUS) & E1000_STATUS_FUNC_1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3589	swfw = E1000_SWFW_PHY1_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3590	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3591	swfw = E1000_SWFW_PHY0_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3592	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3593	if (e1000_swfw_sync_acquire(hw, swfw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3594	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3595
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3596	if ((hw->phy_type == e1000_phy_igp \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3597	hw->phy_type == e1000_phy_igp_3 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3598	hw->phy_type == e1000_phy_igp_2) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3599	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3600	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3601	(u16)reg_addr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3602	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3603	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3604	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3605	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3606	} else if (hw->phy_type == e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3607	if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3608	(hw->mac_type == e1000_80003es2lan)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3609	/* Select Configuration Page */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3610	if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3611	ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3612	(u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3613	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3614	/* Use Alternative Page Select register to access
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3615	* registers 30 and 31
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3616	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3617	ret_val = e1000_write_phy_reg_ex(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3618	GG82563_PHY_PAGE_SELECT_ALT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3619	(u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3620	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3621
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3622	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3623	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3624	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3625	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3626	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3627	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3628
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3629	ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3630	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3631
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3632	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3633	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3634	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3635
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3636	static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3637	u16 phy_data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3638	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3639	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3640	u32 mdic = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3641	const u32 phy_addr = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3642
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3643	DEBUGFUNC("e1000_write_phy_reg_ex");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3644
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3645	if (reg_addr > MAX_PHY_REG_ADDRESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3646	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3647	return -E1000_ERR_PARAM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3648	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3649
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3650	if (hw->mac_type > e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3651	/* Set up Op-code, Phy Address, register address, and data intended
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3652	* for the PHY register in the MDI Control register. The MAC will take
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3653	* care of interfacing with the PHY to send the desired data.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3654	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3655	mdic = (((u32)phy_data) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3656	(reg_addr << E1000_MDIC_REG_SHIFT) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3657	(phy_addr << E1000_MDIC_PHY_SHIFT) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3658	(E1000_MDIC_OP_WRITE));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3659
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3660	ew32(MDIC, mdic);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3661
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3662	/* Poll the ready bit to see if the MDI read completed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3663	for (i = 0; i < 641; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3664	udelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3665	mdic = er32(MDIC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3666	if (mdic & E1000_MDIC_READY) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3667	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3668	if (!(mdic & E1000_MDIC_READY)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3669	DEBUGOUT("MDI Write did not complete\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3670	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3671	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3672	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3673	/* We'll need to use the SW defined pins to shift the write command
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3674	* out to the PHY. We first send a preamble to the PHY to signal the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3675	* beginning of the MII instruction. This is done by sending 32
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3676	* consecutive "1" bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3677	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3678	e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3679
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3680	/* Now combine the remaining required fields that will indicate a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3681	* write operation. We use this method instead of calling the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3682	* e1000_shift_out_mdi_bits routine for each field in the command. The
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3683	* format of a MII write instruction is as follows:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3684	* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3685	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3686	mdic = ((PHY_TURNAROUND) \| (reg_addr << 2) \| (phy_addr << 7) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3687	(PHY_OP_WRITE << 12) \| (PHY_SOF << 14));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3688	mdic <<= 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3689	mdic \|= (u32)phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3690
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3691	e1000_shift_out_mdi_bits(hw, mdic, 32);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3692	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3693
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3694	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3695	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3696
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3697	static s32 e1000_read_kmrn_reg(struct e1000_hw hw, u32 reg_addr, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3698	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3699	u32 reg_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3700	u16 swfw;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3701	DEBUGFUNC("e1000_read_kmrn_reg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3702
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3703	if ((hw->mac_type == e1000_80003es2lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3704	(er32(STATUS) & E1000_STATUS_FUNC_1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3705	swfw = E1000_SWFW_PHY1_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3706	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3707	swfw = E1000_SWFW_PHY0_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3708	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3709	if (e1000_swfw_sync_acquire(hw, swfw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3710	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3711
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3712	/* Write register address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3713	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3714	E1000_KUMCTRLSTA_OFFSET) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3715	E1000_KUMCTRLSTA_REN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3716	ew32(KUMCTRLSTA, reg_val);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3717	udelay(2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3718
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3719	/* Read the data returned */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3720	reg_val = er32(KUMCTRLSTA);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3721	*data = (u16)reg_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3722
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3723	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3724	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3725	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3726
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3727	static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3728	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3729	u32 reg_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3730	u16 swfw;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3731	DEBUGFUNC("e1000_write_kmrn_reg");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3732
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3733	if ((hw->mac_type == e1000_80003es2lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3734	(er32(STATUS) & E1000_STATUS_FUNC_1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3735	swfw = E1000_SWFW_PHY1_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3736	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3737	swfw = E1000_SWFW_PHY0_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3738	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3739	if (e1000_swfw_sync_acquire(hw, swfw))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3740	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3741
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3742	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3743	E1000_KUMCTRLSTA_OFFSET) \| data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3744	ew32(KUMCTRLSTA, reg_val);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3745	udelay(2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3746
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3747	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3748	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3749	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3750
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3751	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3752	* Returns the PHY to the power-on reset state
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3753	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3754	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3755	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3756	s32 e1000_phy_hw_reset(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3757	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3758	u32 ctrl, ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3759	u32 led_ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3760	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3761	u16 swfw;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3762
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3763	DEBUGFUNC("e1000_phy_hw_reset");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3764
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3765	/* In the case of the phy reset being blocked, it's not an error, we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3766	* simply return success without performing the reset. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3767	ret_val = e1000_check_phy_reset_block(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3768	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3769	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3770
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3771	DEBUGOUT("Resetting Phy...\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3772
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3773	if (hw->mac_type > e1000_82543) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3774	if ((hw->mac_type == e1000_80003es2lan) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3775	(er32(STATUS) & E1000_STATUS_FUNC_1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3776	swfw = E1000_SWFW_PHY1_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3777	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3778	swfw = E1000_SWFW_PHY0_SM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3779	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3780	if (e1000_swfw_sync_acquire(hw, swfw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3781	DEBUGOUT("Unable to acquire swfw sync\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3782	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3783	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3784	/* Read the device control register and assert the E1000_CTRL_PHY_RST
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3785	* bit. Then, take it out of reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3786	* For pre-e1000_82571 hardware, we delay for 10ms between the assert
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3787	* and deassert. For e1000_82571 hardware and later, we instead delay
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3788	* for 50us between and 10ms after the deassertion.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3789	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3790	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3791	ew32(CTRL, ctrl \| E1000_CTRL_PHY_RST);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3792	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3793
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3794	if (hw->mac_type < e1000_82571)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3795	msleep(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3796	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3797	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3798
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3799	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3800	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3801
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3802	if (hw->mac_type >= e1000_82571)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3803	mdelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3804
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3805	e1000_swfw_sync_release(hw, swfw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3806	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3807	/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3808	* bit to put the PHY into reset. Then, take it out of reset.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3809	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3810	ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3811	ctrl_ext \|= E1000_CTRL_EXT_SDP4_DIR;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3812	ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3813	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3814	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3815	msleep(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3816	ctrl_ext \|= E1000_CTRL_EXT_SDP4_DATA;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3817	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3818	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3819	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3820	udelay(150);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3821
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3822	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3823	/* Configure activity LED after PHY reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3824	led_ctrl = er32(LEDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3825	led_ctrl &= IGP_ACTIVITY_LED_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3826	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3827	ew32(LEDCTL, led_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3828	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3829
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3830	/* Wait for FW to finish PHY configuration. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3831	ret_val = e1000_get_phy_cfg_done(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3832	if (ret_val != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3833	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3834	e1000_release_software_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3835
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3836	if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3837	ret_val = e1000_init_lcd_from_nvm(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3838
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3839	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3840	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3841
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3842	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3843	* Resets the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3844	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3845	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3846	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3847	* Sets bit 15 of the MII Control register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3848	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3849	s32 e1000_phy_reset(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3850	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3851	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3852	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3853
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3854	DEBUGFUNC("e1000_phy_reset");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3855
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3856	/* In the case of the phy reset being blocked, it's not an error, we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3857	* simply return success without performing the reset. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3858	ret_val = e1000_check_phy_reset_block(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3859	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3860	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3861
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3862	switch (hw->phy_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3863	case e1000_phy_igp:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3864	case e1000_phy_igp_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3865	case e1000_phy_igp_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3866	case e1000_phy_ife:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3867	ret_val = e1000_phy_hw_reset(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3868	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3869	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3870	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3871	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3872	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3873	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3874	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3875
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3876	phy_data \|= MII_CR_RESET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3877	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3878	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3879	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3880
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3881	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3882	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3883	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3884
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3885	if (hw->phy_type == e1000_phy_igp \|\| hw->phy_type == e1000_phy_igp_2)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3886	e1000_phy_init_script(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3887
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3888	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3889	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3890
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3891	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3892	* Work-around for 82566 power-down: on D3 entry-
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3893	* 1) disable gigabit link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3894	* 2) write VR power-down enable
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3895	* 3) read it back
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3896	* if successful continue, else issue LCD reset and repeat
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3897	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3898	* hw - struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3899	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3900	void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3901	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3902	s32 reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3903	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3904	s32 retry = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3905
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3906	DEBUGFUNC("e1000_phy_powerdown_workaround");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3907
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3908	if (hw->phy_type != e1000_phy_igp_3)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3909	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3910
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3911	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3912	/* Disable link */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3913	reg = er32(PHY_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3914	ew32(PHY_CTRL, reg \| E1000_PHY_CTRL_GBE_DISABLE \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3915	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3916
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3917	/* Write VR power-down enable - bits 9:8 should be 10b */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3918	e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3919	phy_data \|= (1 << 9);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3920	phy_data &= ~(1 << 8);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3921	e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3922
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3923	/* Read it back and test */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3924	e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3925	if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) \|\| retry)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3926	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3927
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3928	/* Issue PHY reset and repeat at most one more time */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3929	reg = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3930	ew32(CTRL, reg \| E1000_CTRL_PHY_RST);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3931	retry++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3932	} while (retry);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3933
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3934	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3935
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3936	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3937
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3938	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3939	* Work-around for 82566 Kumeran PCS lock loss:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3940	* On link status change (i.e. PCI reset, speed change) and link is up and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3941	* speed is gigabit-
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3942	* 0) if workaround is optionally disabled do nothing
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3943	* 1) wait 1ms for Kumeran link to come up
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3944	* 2) check Kumeran Diagnostic register PCS lock loss bit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3945	* 3) if not set the link is locked (all is good), otherwise...
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3946	* 4) reset the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3947	* 5) repeat up to 10 times
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3948	* Note: this is only called for IGP3 copper when speed is 1gb.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3949	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3950	* hw - struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3951	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3952	static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3953	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3954	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3955	s32 reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3956	s32 cnt;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3957	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3958
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3959	if (hw->kmrn_lock_loss_workaround_disabled)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3960	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3961
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3962	/* Make sure link is up before proceeding. If not just return.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3963	* Attempting this while link is negotiating fouled up link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3964	* stability */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3965	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3966	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3967
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3968	if (phy_data & MII_SR_LINK_STATUS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3969	for (cnt = 0; cnt < 10; cnt++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3970	/* read once to clear */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3971	ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3972	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3973	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3974	/* and again to get new status */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3975	ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3976	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3977	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3978
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3979	/* check for PCS lock */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3980	if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3981	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3982
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3983	/* Issue PHY reset */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3984	e1000_phy_hw_reset(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3985	mdelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3986	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3987	/* Disable GigE link negotiation */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3988	reg = er32(PHY_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3989	ew32(PHY_CTRL, reg \| E1000_PHY_CTRL_GBE_DISABLE \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3990	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3991
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3992	/* unable to acquire PCS lock */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3993	return E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3994	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3995
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3996	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3997	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3998
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	3999	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4000	* Probes the expected PHY address for known PHY IDs
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4001	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4002	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4003	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4004	static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4005	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4006	s32 phy_init_status, ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4007	u16 phy_id_high, phy_id_low;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4008	bool match = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4009
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4010	DEBUGFUNC("e1000_detect_gig_phy");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4011
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4012	if (hw->phy_id != 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4013	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4014
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4015	/* The 82571 firmware may still be configuring the PHY. In this
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4016	* case, we cannot access the PHY until the configuration is done. So
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4017	* we explicitly set the PHY values. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4018	if (hw->mac_type == e1000_82571 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4019	hw->mac_type == e1000_82572) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4020	hw->phy_id = IGP01E1000_I_PHY_ID;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4021	hw->phy_type = e1000_phy_igp_2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4022	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4023	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4024
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4025	/* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4026	* around that forces PHY page 0 to be set or the reads fail. The rest of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4027	* the code in this routine uses e1000_read_phy_reg to read the PHY ID.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4028	* So for ESB-2 we need to have this set so our reads won't fail. If the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4029	* attached PHY is not a e1000_phy_gg82563, the routines below will figure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4030	* this out as well. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4031	if (hw->mac_type == e1000_80003es2lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4032	hw->phy_type = e1000_phy_gg82563;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4033
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4034	/* Read the PHY ID Registers to identify which PHY is onboard. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4035	ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4036	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4037	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4038
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4039	hw->phy_id = (u32)(phy_id_high << 16);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4040	udelay(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4041	ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4042	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4043	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4044
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4045	hw->phy_id \|= (u32)(phy_id_low & PHY_REVISION_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4046	hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4047
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4048	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4049	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4050	if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4051	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4052	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4053	if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4054	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4055	case e1000_82540:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4056	case e1000_82545:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4057	case e1000_82545_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4058	case e1000_82546:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4059	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4060	if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4061	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4062	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4063	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4064	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4065	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4066	if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4067	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4068	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4069	if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4070	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4071	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4072	if (hw->phy_id == GG82563_E_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4073	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4074	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4075	if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4076	if (hw->phy_id == IFE_E_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4077	if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4078	if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4079	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4080	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4081	DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4082	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4083	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4084	phy_init_status = e1000_set_phy_type(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4085
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4086	if ((match) && (phy_init_status == E1000_SUCCESS)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4087	DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4088	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4089	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4090	DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4091	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4092	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4093
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4094	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4095	* Resets the PHY's DSP
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4096	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4097	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4098	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4099	static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4100	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4101	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4102	DEBUGFUNC("e1000_phy_reset_dsp");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4103
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4104	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4105	if (hw->phy_type != e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4106	ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4107	if (ret_val) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4108	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4109	ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4110	if (ret_val) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4111	ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4112	if (ret_val) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4113	ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4114	} while (0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4115
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4116	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4117	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4118
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4119	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4120	* Get PHY information from various PHY registers for igp PHY only.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4121	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4122	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4123	* phy_info - PHY information structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4124	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4125	static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4126	struct e1000_phy_info *phy_info)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4127	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4128	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4129	u16 phy_data, min_length, max_length, average;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4130	e1000_rev_polarity polarity;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4131
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4132	DEBUGFUNC("e1000_phy_igp_get_info");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4133
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4134	/* The downshift status is checked only once, after link is established,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4135	* and it stored in the hw->speed_downgraded parameter. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4136	phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4137
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4138	/* IGP01E1000 does not need to support it. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4139	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4140
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4141	/* IGP01E1000 always correct polarity reversal */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4142	phy_info->polarity_correction = e1000_polarity_reversal_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4143
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4144	/* Check polarity status */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4145	ret_val = e1000_check_polarity(hw, &polarity);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4146	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4147	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4148
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4149	phy_info->cable_polarity = polarity;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4150
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4151	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4152	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4153	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4154
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4155	phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4156	IGP01E1000_PSSR_MDIX_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4157
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4158	if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4159	IGP01E1000_PSSR_SPEED_1000MBPS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4160	/* Local/Remote Receiver Information are only valid at 1000 Mbps */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4161	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4162	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4163	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4164
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4165	phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4166	SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4167	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4168	phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4169	SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4170	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4171
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4172	/* Get cable length */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4173	ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4174	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4175	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4176
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4177	/* Translate to old method */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4178	average = (max_length + min_length) / 2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4179
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4180	if (average <= e1000_igp_cable_length_50)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4181	phy_info->cable_length = e1000_cable_length_50;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4182	else if (average <= e1000_igp_cable_length_80)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4183	phy_info->cable_length = e1000_cable_length_50_80;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4184	else if (average <= e1000_igp_cable_length_110)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4185	phy_info->cable_length = e1000_cable_length_80_110;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4186	else if (average <= e1000_igp_cable_length_140)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4187	phy_info->cable_length = e1000_cable_length_110_140;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4188	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4189	phy_info->cable_length = e1000_cable_length_140;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4190	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4191
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4192	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4193	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4194
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4195	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4196	* Get PHY information from various PHY registers for ife PHY only.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4197	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4198	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4199	* phy_info - PHY information structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4200	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4201	static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4202	struct e1000_phy_info *phy_info)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4203	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4204	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4205	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4206	e1000_rev_polarity polarity;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4207
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4208	DEBUGFUNC("e1000_phy_ife_get_info");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4209
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4210	phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4211	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4212
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4213	ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4214	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4215	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4216	phy_info->polarity_correction =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4217	((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4218	IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4219	e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4220
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4221	if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4222	ret_val = e1000_check_polarity(hw, &polarity);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4223	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4224	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4225	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4226	/* Polarity is forced. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4227	polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4228	IFE_PSC_FORCE_POLARITY_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4229	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4230	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4231	phy_info->cable_polarity = polarity;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4232
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4233	ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4234	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4235	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4236
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4237	phy_info->mdix_mode = (e1000_auto_x_mode)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4238	((phy_data & (IFE_PMC_AUTO_MDIX \| IFE_PMC_FORCE_MDIX)) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4239	IFE_PMC_MDIX_MODE_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4240
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4241	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4242	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4243
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4244	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4245	* Get PHY information from various PHY registers fot m88 PHY only.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4246	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4247	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4248	* phy_info - PHY information structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4249	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4250	static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4251	struct e1000_phy_info *phy_info)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4252	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4253	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4254	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4255	e1000_rev_polarity polarity;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4256
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4257	DEBUGFUNC("e1000_phy_m88_get_info");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4258
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4259	/* The downshift status is checked only once, after link is established,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4260	* and it stored in the hw->speed_downgraded parameter. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4261	phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4262
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4263	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4264	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4265	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4266
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4267	phy_info->extended_10bt_distance =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4268	((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4269	M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4270	e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4271
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4272	phy_info->polarity_correction =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4273	((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4274	M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4275	e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4276
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4277	/* Check polarity status */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4278	ret_val = e1000_check_polarity(hw, &polarity);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4279	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4280	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4281	phy_info->cable_polarity = polarity;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4282
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4283	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4284	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4285	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4286
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4287	phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4288	M88E1000_PSSR_MDIX_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4289
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4290	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4291	/* Cable Length Estimation and Local/Remote Receiver Information
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4292	* are only valid at 1000 Mbps.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4293	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4294	if (hw->phy_type != e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4295	phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4296	M88E1000_PSSR_CABLE_LENGTH_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4297	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4298	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4299	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4300	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4301	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4302
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4303	phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4304	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4305
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4306	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4307	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4308	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4309
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4310	phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4311	SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4312	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4313	phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4314	SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4315	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4316
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4317	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4318
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4319	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4320	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4321
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4322	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4323	* Get PHY information from various PHY registers
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4324	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4325	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4326	* phy_info - PHY information structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4327	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4328	s32 e1000_phy_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4329	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4330	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4331	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4332
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4333	DEBUGFUNC("e1000_phy_get_info");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4334
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4335	phy_info->cable_length = e1000_cable_length_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4336	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4337	phy_info->cable_polarity = e1000_rev_polarity_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4338	phy_info->downshift = e1000_downshift_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4339	phy_info->polarity_correction = e1000_polarity_reversal_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4340	phy_info->mdix_mode = e1000_auto_x_mode_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4341	phy_info->local_rx = e1000_1000t_rx_status_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4342	phy_info->remote_rx = e1000_1000t_rx_status_undefined;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4343
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4344	if (hw->media_type != e1000_media_type_copper) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4345	DEBUGOUT("PHY info is only valid for copper media\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4346	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4347	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4348
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4349	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4350	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4351	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4352
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4353	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4354	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4355	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4356
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4357	if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4358	DEBUGOUT("PHY info is only valid if link is up\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4359	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4360	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4361
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4362	if (hw->phy_type == e1000_phy_igp \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4363	hw->phy_type == e1000_phy_igp_3 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4364	hw->phy_type == e1000_phy_igp_2)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4365	return e1000_phy_igp_get_info(hw, phy_info);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4366	else if (hw->phy_type == e1000_phy_ife)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4367	return e1000_phy_ife_get_info(hw, phy_info);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4368	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4369	return e1000_phy_m88_get_info(hw, phy_info);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4370	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4371
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4372	s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4373	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4374	DEBUGFUNC("e1000_validate_mdi_settings");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4375
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4376	if (!hw->autoneg && (hw->mdix == 0 \|\| hw->mdix == 3)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4377	DEBUGOUT("Invalid MDI setting detected\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4378	hw->mdix = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4379	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4380	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4381	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4382	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4383
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4384
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4385	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4386	* Sets up eeprom variables in the hw struct. Must be called after mac_type
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4387	* is configured. Additionally, if this is ICH8, the flash controller GbE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4388	* registers must be mapped, or this will crash.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4389	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4390	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4391	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4392	s32 e1000_init_eeprom_params(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4393	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4394	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4395	u32 eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4396	s32 ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4397	u16 eeprom_size;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4398
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4399	DEBUGFUNC("e1000_init_eeprom_params");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4400
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4401	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4402	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4403	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4404	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4405	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4406	eeprom->type = e1000_eeprom_microwire;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4407	eeprom->word_size = 64;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4408	eeprom->opcode_bits = 3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4409	eeprom->address_bits = 6;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4410	eeprom->delay_usec = 50;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4411	eeprom->use_eerd = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4412	eeprom->use_eewr = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4413	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4414	case e1000_82540:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4415	case e1000_82545:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4416	case e1000_82545_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4417	case e1000_82546:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4418	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4419	eeprom->type = e1000_eeprom_microwire;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4420	eeprom->opcode_bits = 3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4421	eeprom->delay_usec = 50;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4422	if (eecd & E1000_EECD_SIZE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4423	eeprom->word_size = 256;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4424	eeprom->address_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4425	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4426	eeprom->word_size = 64;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4427	eeprom->address_bits = 6;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4428	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4429	eeprom->use_eerd = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4430	eeprom->use_eewr = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4431	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4432	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4433	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4434	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4435	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4436	if (eecd & E1000_EECD_TYPE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4437	eeprom->type = e1000_eeprom_spi;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4438	eeprom->opcode_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4439	eeprom->delay_usec = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4440	if (eecd & E1000_EECD_ADDR_BITS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4441	eeprom->page_size = 32;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4442	eeprom->address_bits = 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4443	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4444	eeprom->page_size = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4445	eeprom->address_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4446	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4447	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4448	eeprom->type = e1000_eeprom_microwire;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4449	eeprom->opcode_bits = 3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4450	eeprom->delay_usec = 50;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4451	if (eecd & E1000_EECD_ADDR_BITS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4452	eeprom->word_size = 256;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4453	eeprom->address_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4454	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4455	eeprom->word_size = 64;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4456	eeprom->address_bits = 6;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4457	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4458	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4459	eeprom->use_eerd = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4460	eeprom->use_eewr = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4461	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4462	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4463	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4464	eeprom->type = e1000_eeprom_spi;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4465	eeprom->opcode_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4466	eeprom->delay_usec = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4467	if (eecd & E1000_EECD_ADDR_BITS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4468	eeprom->page_size = 32;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4469	eeprom->address_bits = 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4470	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4471	eeprom->page_size = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4472	eeprom->address_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4473	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4474	eeprom->use_eerd = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4475	eeprom->use_eewr = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4476	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4477	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4478	eeprom->type = e1000_eeprom_spi;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4479	eeprom->opcode_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4480	eeprom->delay_usec = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4481	if (eecd & E1000_EECD_ADDR_BITS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4482	eeprom->page_size = 32;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4483	eeprom->address_bits = 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4484	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4485	eeprom->page_size = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4486	eeprom->address_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4487	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4488	eeprom->use_eerd = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4489	eeprom->use_eewr = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4490	if (!e1000_is_onboard_nvm_eeprom(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4491	eeprom->type = e1000_eeprom_flash;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4492	eeprom->word_size = 2048;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4493
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4494	/* Ensure that the Autonomous FLASH update bit is cleared due to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4495	* Flash update issue on parts which use a FLASH for NVM. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4496	eecd &= ~E1000_EECD_AUPDEN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4497	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4498	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4499	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4500	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4501	eeprom->type = e1000_eeprom_spi;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4502	eeprom->opcode_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4503	eeprom->delay_usec = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4504	if (eecd & E1000_EECD_ADDR_BITS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4505	eeprom->page_size = 32;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4506	eeprom->address_bits = 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4507	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4508	eeprom->page_size = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4509	eeprom->address_bits = 8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4510	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4511	eeprom->use_eerd = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4512	eeprom->use_eewr = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4513	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4514	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4515	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4516	s32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4517	u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4518
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4519	eeprom->type = e1000_eeprom_ich8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4520	eeprom->use_eerd = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4521	eeprom->use_eewr = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4522	eeprom->word_size = E1000_SHADOW_RAM_WORDS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4523
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4524	/* Zero the shadow RAM structure. But don't load it from NVM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4525	* so as to save time for driver init */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4526	if (hw->eeprom_shadow_ram != NULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4527	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4528	hw->eeprom_shadow_ram[i].modified = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4529	hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4530	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4531	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4532
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4533	hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4534	ICH_FLASH_SECTOR_SIZE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4535
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4536	hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4537	hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4538
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4539	hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4540
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4541	hw->flash_bank_size /= 2 * sizeof(u16);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4542
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4543	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4544	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4545	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4546	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4547	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4548
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4549	if (eeprom->type == e1000_eeprom_spi) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4550	/* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4551	* 32KB (incremented by powers of 2).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4552	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4553	if (hw->mac_type <= e1000_82547_rev_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4554	/* Set to default value for initial eeprom read. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4555	eeprom->word_size = 64;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4556	ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4557	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4558	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4559	eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4560	/* 256B eeprom size was not supported in earlier hardware, so we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4561	* bump eeprom_size up one to ensure that "1" (which maps to 256B)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4562	* is never the result used in the shifting logic below. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4563	if (eeprom_size)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4564	eeprom_size++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4565	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4566	eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4567	E1000_EECD_SIZE_EX_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4568	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4569
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4570	eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4571	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4572	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4573	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4574
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4575	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4576	* Raises the EEPROM's clock input.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4577	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4578	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4579	* eecd - EECD's current value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4580	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4581	static void e1000_raise_ee_clk(struct e1000_hw hw, u32 eecd)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4582	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4583	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4584	* wait <delay> microseconds.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4585	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4586	eecd = eecd \| E1000_EECD_SK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4587	ew32(EECD, *eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4588	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4589	udelay(hw->eeprom.delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4590	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4591
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4592	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4593	* Lowers the EEPROM's clock input.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4594	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4595	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4596	* eecd - EECD's current value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4597	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4598	static void e1000_lower_ee_clk(struct e1000_hw hw, u32 eecd)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4599	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4600	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4601	* wait 50 microseconds.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4602	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4603	eecd = eecd & ~E1000_EECD_SK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4604	ew32(EECD, *eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4605	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4606	udelay(hw->eeprom.delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4607	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4608
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4609	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4610	* Shift data bits out to the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4611	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4612	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4613	* data - data to send to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4614	* count - number of bits to shift out
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4615	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4616	static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4617	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4618	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4619	u32 eecd;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4620	u32 mask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4621
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4622	/* We need to shift "count" bits out to the EEPROM. So, value in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4623	* "data" parameter will be shifted out to the EEPROM one bit at a time.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4624	* In order to do this, "data" must be broken down into bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4625	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4626	mask = 0x01 << (count - 1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4627	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4628	if (eeprom->type == e1000_eeprom_microwire) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4629	eecd &= ~E1000_EECD_DO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4630	} else if (eeprom->type == e1000_eeprom_spi) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4631	eecd \|= E1000_EECD_DO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4632	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4633	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4634	/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4635	* and then raising and then lowering the clock (the SK bit controls
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4636	* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4637	* by setting "DI" to "0" and then raising and then lowering the clock.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4638	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4639	eecd &= ~E1000_EECD_DI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4640
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4641	if (data & mask)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4642	eecd \|= E1000_EECD_DI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4643
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4644	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4645	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4646
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4647	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4648
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4649	e1000_raise_ee_clk(hw, &eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4650	e1000_lower_ee_clk(hw, &eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4651
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4652	mask = mask >> 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4653
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4654	} while (mask);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4655
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4656	/* We leave the "DI" bit set to "0" when we leave this routine. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4657	eecd &= ~E1000_EECD_DI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4658	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4659	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4660
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4661	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4662	* Shift data bits in from the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4663	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4664	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4665	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4666	static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4667	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4668	u32 eecd;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4669	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4670	u16 data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4671
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4672	/* In order to read a register from the EEPROM, we need to shift 'count'
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4673	* bits in from the EEPROM. Bits are "shifted in" by raising the clock
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4674	* input to the EEPROM (setting the SK bit), and then reading the value of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4675	* the "DO" bit. During this "shifting in" process the "DI" bit should
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4676	* always be clear.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4677	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4678
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4679	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4680
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4681	eecd &= ~(E1000_EECD_DO \| E1000_EECD_DI);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4682	data = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4683
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4684	for (i = 0; i < count; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4685	data = data << 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4686	e1000_raise_ee_clk(hw, &eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4687
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4688	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4689
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4690	eecd &= ~(E1000_EECD_DI);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4691	if (eecd & E1000_EECD_DO)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4692	data \|= 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4693
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4694	e1000_lower_ee_clk(hw, &eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4695	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4696
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4697	return data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4698	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4699
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4700	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4701	* Prepares EEPROM for access
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4702	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4703	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4704	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4705	* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4706	* function should be called before issuing a command to the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4707	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4708	static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4709	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4710	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4711	u32 eecd, i=0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4712
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4713	DEBUGFUNC("e1000_acquire_eeprom");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4714
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4715	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4716	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4717	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4718
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4719	if (hw->mac_type != e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4720	/* Request EEPROM Access */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4721	if (hw->mac_type > e1000_82544) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4722	eecd \|= E1000_EECD_REQ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4723	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4724	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4725	while ((!(eecd & E1000_EECD_GNT)) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4726	(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4727	i++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4728	udelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4729	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4730	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4731	if (!(eecd & E1000_EECD_GNT)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4732	eecd &= ~E1000_EECD_REQ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4733	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4734	DEBUGOUT("Could not acquire EEPROM grant\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4735	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4736	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4737	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4738	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4739	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4740
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4741	/* Setup EEPROM for Read/Write */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4742
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4743	if (eeprom->type == e1000_eeprom_microwire) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4744	/* Clear SK and DI */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4745	eecd &= ~(E1000_EECD_DI \| E1000_EECD_SK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4746	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4747
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4748	/* Set CS */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4749	eecd \|= E1000_EECD_CS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4750	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4751	} else if (eeprom->type == e1000_eeprom_spi) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4752	/* Clear SK and CS */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4753	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4754	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4755	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4756	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4757
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4758	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4759	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4760
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4761	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4762	* Returns EEPROM to a "standby" state
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4763	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4764	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4765	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4766	static void e1000_standby_eeprom(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4767	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4768	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4769	u32 eecd;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4770
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4771	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4772
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4773	if (eeprom->type == e1000_eeprom_microwire) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4774	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4775	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4776	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4777	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4778
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4779	/* Clock high */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4780	eecd \|= E1000_EECD_SK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4781	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4782	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4783	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4784
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4785	/* Select EEPROM */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4786	eecd \|= E1000_EECD_CS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4787	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4788	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4789	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4790
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4791	/* Clock low */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4792	eecd &= ~E1000_EECD_SK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4793	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4794	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4795	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4796	} else if (eeprom->type == e1000_eeprom_spi) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4797	/* Toggle CS to flush commands */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4798	eecd \|= E1000_EECD_CS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4799	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4800	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4801	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4802	eecd &= ~E1000_EECD_CS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4803	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4804	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4805	udelay(eeprom->delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4806	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4807	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4808
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4809	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4810	* Terminates a command by inverting the EEPROM's chip select pin
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4811	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4812	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4813	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4814	static void e1000_release_eeprom(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4815	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4816	u32 eecd;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4817
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4818	DEBUGFUNC("e1000_release_eeprom");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4819
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4820	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4821
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4822	if (hw->eeprom.type == e1000_eeprom_spi) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4823	eecd \|= E1000_EECD_CS; /* Pull CS high */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4824	eecd &= ~E1000_EECD_SK; /* Lower SCK */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4825
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4826	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4827
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4828	udelay(hw->eeprom.delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4829	} else if (hw->eeprom.type == e1000_eeprom_microwire) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4830	/* cleanup eeprom */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4831
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4832	/* CS on Microwire is active-high */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4833	eecd &= ~(E1000_EECD_CS \| E1000_EECD_DI);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4834
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4835	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4836
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4837	/* Rising edge of clock */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4838	eecd \|= E1000_EECD_SK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4839	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4840	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4841	udelay(hw->eeprom.delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4842
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4843	/* Falling edge of clock */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4844	eecd &= ~E1000_EECD_SK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4845	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4846	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4847	udelay(hw->eeprom.delay_usec);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4848	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4849
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4850	/* Stop requesting EEPROM access */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4851	if (hw->mac_type > e1000_82544) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4852	eecd &= ~E1000_EECD_REQ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4853	ew32(EECD, eecd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4854	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4855
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4856	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4857	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4858
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4859	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4860	* Reads a 16 bit word from the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4861	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4862	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4863	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4864	static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4865	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4866	u16 retry_count = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4867	u8 spi_stat_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4868
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4869	DEBUGFUNC("e1000_spi_eeprom_ready");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4870
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4871	/* Read "Status Register" repeatedly until the LSB is cleared. The
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4872	* EEPROM will signal that the command has been completed by clearing
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4873	* bit 0 of the internal status register. If it's not cleared within
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4874	* 5 milliseconds, then error out.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4875	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4876	retry_count = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4877	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4878	e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4879	hw->eeprom.opcode_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4880	spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4881	if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4882	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4883
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4884	udelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4885	retry_count += 5;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4886
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4887	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4888	} while (retry_count < EEPROM_MAX_RETRY_SPI);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4889
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4890	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4891	* only 0-5mSec on 5V devices)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4892	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4893	if (retry_count >= EEPROM_MAX_RETRY_SPI) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4894	DEBUGOUT("SPI EEPROM Status error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4895	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4896	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4897
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4898	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4899	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4900
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4901	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4902	* Reads a 16 bit word from the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4903	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4904	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4905	* offset - offset of word in the EEPROM to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4906	* data - word read from the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4907	* words - number of words to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4908	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4909	s32 e1000_read_eeprom(struct e1000_hw hw, u16 offset, u16 words, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4910	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4911	s32 ret;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4912	spin_lock(&e1000_eeprom_lock);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4913	ret = e1000_do_read_eeprom(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4914	spin_unlock(&e1000_eeprom_lock);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4915	return ret;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4916	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4917
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4918	static s32 e1000_do_read_eeprom(struct e1000_hw hw, u16 offset, u16 words, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4919	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4920	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4921	u32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4922
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4923	DEBUGFUNC("e1000_read_eeprom");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4924
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4925	/* If eeprom is not yet detected, do so now */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4926	if (eeprom->word_size == 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4927	e1000_init_eeprom_params(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4928
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4929	/* A check for invalid values: offset too large, too many words, and not
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4930	* enough words.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4931	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4932	if ((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4933	(words == 0)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4934	DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4935	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4936	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4937
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4938	/* EEPROM's that don't use EERD to read require us to bit-bang the SPI
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4939	* directly. In this case, we need to acquire the EEPROM so that
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4940	* FW or other port software does not interrupt.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4941	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4942	if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4943	/* Prepare the EEPROM for bit-bang reading */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4944	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4945	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4946	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4947
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4948	/* Eerd register EEPROM access requires no eeprom aquire/release */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4949	if (eeprom->use_eerd)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4950	return e1000_read_eeprom_eerd(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4951
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4952	/* ICH EEPROM access is done via the ICH flash controller */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4953	if (eeprom->type == e1000_eeprom_ich8)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4954	return e1000_read_eeprom_ich8(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4955
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4956	/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4957	* acquired the EEPROM at this point, so any returns should relase it */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4958	if (eeprom->type == e1000_eeprom_spi) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4959	u16 word_in;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4960	u8 read_opcode = EEPROM_READ_OPCODE_SPI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4961
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4962	if (e1000_spi_eeprom_ready(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4963	e1000_release_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4964	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4965	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4966
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4967	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4968
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4969	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4970	if ((eeprom->address_bits == 8) && (offset >= 128))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4971	read_opcode \|= EEPROM_A8_OPCODE_SPI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4972
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4973	/* Send the READ command (opcode + addr) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4974	e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4975	e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4976
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4977	/* Read the data. The address of the eeprom internally increments with
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4978	* each byte (spi) being read, saving on the overhead of eeprom setup
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4979	* and tear-down. The address counter will roll over if reading beyond
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4980	* the size of the eeprom, thus allowing the entire memory to be read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4981	* starting from any offset. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4982	for (i = 0; i < words; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4983	word_in = e1000_shift_in_ee_bits(hw, 16);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4984	data[i] = (word_in >> 8) \| (word_in << 8);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4985	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4986	} else if (eeprom->type == e1000_eeprom_microwire) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4987	for (i = 0; i < words; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4988	/* Send the READ command (opcode + addr) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4989	e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4990	eeprom->opcode_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4991	e1000_shift_out_ee_bits(hw, (u16)(offset + i),
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4992	eeprom->address_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4993
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4994	/* Read the data. For microwire, each word requires the overhead
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4995	* of eeprom setup and tear-down. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4996	data[i] = e1000_shift_in_ee_bits(hw, 16);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4997	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4998	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	4999	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5000
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5001	/* End this read operation */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5002	e1000_release_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5003
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5004	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5005	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5006
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5007	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5008	* Reads a 16 bit word from the EEPROM using the EERD register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5009	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5010	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5011	* offset - offset of word in the EEPROM to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5012	* data - word read from the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5013	* words - number of words to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5014	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5015	static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5016	u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5017	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5018	u32 i, eerd = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5019	s32 error = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5020
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5021	for (i = 0; i < words; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5022	eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5023	E1000_EEPROM_RW_REG_START;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5024
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5025	ew32(EERD, eerd);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5026	error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5027
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5028	if (error) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5029	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5030	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5031	data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5032
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5033	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5034
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5035	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5036	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5037
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5038	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5039	* Writes a 16 bit word from the EEPROM using the EEWR register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5040	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5041	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5042	* offset - offset of word in the EEPROM to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5043	* data - word read from the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5044	* words - number of words to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5045	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5046	static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5047	u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5048	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5049	u32 register_value = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5050	u32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5051	s32 error = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5052
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5053	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5054	return -E1000_ERR_SWFW_SYNC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5055
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5056	for (i = 0; i < words; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5057	register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5058	((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5059	E1000_EEPROM_RW_REG_START;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5060
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5061	error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5062	if (error) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5063	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5064	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5065
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5066	ew32(EEWR, register_value);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5067
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5068	error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5069
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5070	if (error) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5071	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5072	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5073	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5074
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5075	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5076	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5077	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5078
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5079	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5080	* Polls the status bit (bit 1) of the EERD to determine when the read is done.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5081	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5082	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5083	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5084	static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5085	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5086	u32 attempts = 100000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5087	u32 i, reg = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5088	s32 done = E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5089
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5090	for (i = 0; i < attempts; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5091	if (eerd == E1000_EEPROM_POLL_READ)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5092	reg = er32(EERD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5093	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5094	reg = er32(EEWR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5095
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5096	if (reg & E1000_EEPROM_RW_REG_DONE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5097	done = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5098	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5099	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5100	udelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5101	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5102
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5103	return done;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5104	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5105
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5106	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5107	* Description: Determines if the onboard NVM is FLASH or EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5108	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5109	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5110	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5111	static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5112	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5113	u32 eecd = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5114
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5115	DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5116
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5117	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5118	return false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5119
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5120	if (hw->mac_type == e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5121	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5122
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5123	/* Isolate bits 15 & 16 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5124	eecd = ((eecd >> 15) & 0x03);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5125
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5126	/* If both bits are set, device is Flash type */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5127	if (eecd == 0x03) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5128	return false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5129	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5130	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5131	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5132	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5133
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5134	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5135	* Verifies that the EEPROM has a valid checksum
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5136	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5137	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5138	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5139	* Reads the first 64 16 bit words of the EEPROM and sums the values read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5140	* If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5141	* valid.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5142	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5143	s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5144	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5145	u16 checksum = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5146	u16 i, eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5147
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5148	DEBUGFUNC("e1000_validate_eeprom_checksum");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5149
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5150	if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5151	/* Check bit 4 of word 10h. If it is 0, firmware is done updating
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5152	* 10h-12h. Checksum may need to be fixed. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5153	e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5154	if ((eeprom_data & 0x10) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5155	/* Read 0x23 and check bit 15. This bit is a 1 when the checksum
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5156	* has already been fixed. If the checksum is still wrong and this
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5157	* bit is a 1, we need to return bad checksum. Otherwise, we need
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5158	* to set this bit to a 1 and update the checksum. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5159	e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5160	if ((eeprom_data & 0x8000) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5161	eeprom_data \|= 0x8000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5162	e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5163	e1000_update_eeprom_checksum(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5164	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5165	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5166	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5167
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5168	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5169	/* Drivers must allocate the shadow ram structure for the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5170	* EEPROM checksum to be updated. Otherwise, this bit as well
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5171	* as the checksum must both be set correctly for this
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5172	* validation to pass.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5173	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5174	e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5175	if ((eeprom_data & 0x40) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5176	eeprom_data \|= 0x40;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5177	e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5178	e1000_update_eeprom_checksum(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5179	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5180	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5181
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5182	for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5183	if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5184	DEBUGOUT("EEPROM Read Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5185	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5186	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5187	checksum += eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5188	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5189
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5190	if (checksum == (u16)EEPROM_SUM)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5191	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5192	else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5193	DEBUGOUT("EEPROM Checksum Invalid\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5194	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5195	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5196	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5197
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5198	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5199	* Calculates the EEPROM checksum and writes it to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5200	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5201	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5202	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5203	* Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5204	* Writes the difference to word offset 63 of the EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5205	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5206	s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5207	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5208	u32 ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5209	u16 checksum = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5210	u16 i, eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5211
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5212	DEBUGFUNC("e1000_update_eeprom_checksum");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5213
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5214	for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5215	if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5216	DEBUGOUT("EEPROM Read Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5217	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5218	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5219	checksum += eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5220	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5221	checksum = (u16)EEPROM_SUM - checksum;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5222	if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5223	DEBUGOUT("EEPROM Write Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5224	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5225	} else if (hw->eeprom.type == e1000_eeprom_flash) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5226	e1000_commit_shadow_ram(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5227	} else if (hw->eeprom.type == e1000_eeprom_ich8) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5228	e1000_commit_shadow_ram(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5229	/* Reload the EEPROM, or else modifications will not appear
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5230	* until after next adapter reset. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5231	ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5232	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5233	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5234	msleep(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5235	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5236	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5237	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5238
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5239	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5240	* Parent function for writing words to the different EEPROM types.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5241	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5242	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5243	* offset - offset within the EEPROM to be written to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5244	* words - number of words to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5245	* data - 16 bit word to be written to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5246	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5247	* If e1000_update_eeprom_checksum is not called after this function, the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5248	* EEPROM will most likely contain an invalid checksum.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5249	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5250	s32 e1000_write_eeprom(struct e1000_hw hw, u16 offset, u16 words, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5251	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5252	s32 ret;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5253	spin_lock(&e1000_eeprom_lock);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5254	ret = e1000_do_write_eeprom(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5255	spin_unlock(&e1000_eeprom_lock);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5256	return ret;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5257	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5258
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5259
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5260	static s32 e1000_do_write_eeprom(struct e1000_hw hw, u16 offset, u16 words, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5261	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5262	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5263	s32 status = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5264
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5265	DEBUGFUNC("e1000_write_eeprom");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5266
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5267	/* If eeprom is not yet detected, do so now */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5268	if (eeprom->word_size == 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5269	e1000_init_eeprom_params(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5270
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5271	/* A check for invalid values: offset too large, too many words, and not
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5272	* enough words.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5273	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5274	if ((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5275	(words == 0)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5276	DEBUGOUT("\"words\" parameter out of bounds\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5277	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5278	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5279
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5280	/* 82573 writes only through eewr */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5281	if (eeprom->use_eewr)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5282	return e1000_write_eeprom_eewr(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5283
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5284	if (eeprom->type == e1000_eeprom_ich8)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5285	return e1000_write_eeprom_ich8(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5286
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5287	/* Prepare the EEPROM for writing */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5288	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5289	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5290
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5291	if (eeprom->type == e1000_eeprom_microwire) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5292	status = e1000_write_eeprom_microwire(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5293	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5294	status = e1000_write_eeprom_spi(hw, offset, words, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5295	msleep(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5296	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5297
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5298	/* Done with writing */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5299	e1000_release_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5300
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5301	return status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5302	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5303
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5304	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5305	* Writes a 16 bit word to a given offset in an SPI EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5306	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5307	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5308	* offset - offset within the EEPROM to be written to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5309	* words - number of words to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5310	* data - pointer to array of 8 bit words to be written to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5311	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5312	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5313	static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5314	u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5315	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5316	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5317	u16 widx = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5318
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5319	DEBUGFUNC("e1000_write_eeprom_spi");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5320
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5321	while (widx < words) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5322	u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5323
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5324	if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5325
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5326	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5327
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5328	/* Send the WRITE ENABLE command (8 bit opcode ) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5329	e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5330	eeprom->opcode_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5331
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5332	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5333
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5334	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5335	if ((eeprom->address_bits == 8) && (offset >= 128))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5336	write_opcode \|= EEPROM_A8_OPCODE_SPI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5337
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5338	/* Send the Write command (8-bit opcode + addr) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5339	e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5340
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5341	e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5342	eeprom->address_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5343
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5344	/* Send the data */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5345
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5346	/* Loop to allow for up to whole page write (32 bytes) of eeprom */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5347	while (widx < words) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5348	u16 word_out = data[widx];
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5349	word_out = (word_out >> 8) \| (word_out << 8);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5350	e1000_shift_out_ee_bits(hw, word_out, 16);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5351	widx++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5352
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5353	/* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5354	* operation, while the smaller eeproms are capable of an 8-byte
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5355	* PAGE WRITE operation. Break the inner loop to pass new address
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5356	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5357	if ((((offset + widx)*2) % eeprom->page_size) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5358	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5359	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5360	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5361	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5362	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5363
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5364	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5365	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5366
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5367	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5368	* Writes a 16 bit word to a given offset in a Microwire EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5369	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5370	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5371	* offset - offset within the EEPROM to be written to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5372	* words - number of words to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5373	* data - pointer to array of 16 bit words to be written to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5374	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5375	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5376	static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5377	u16 words, u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5378	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5379	struct e1000_eeprom_info *eeprom = &hw->eeprom;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5380	u32 eecd;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5381	u16 words_written = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5382	u16 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5383
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5384	DEBUGFUNC("e1000_write_eeprom_microwire");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5385
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5386	/* Send the write enable command to the EEPROM (3-bit opcode plus
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5387	* 6/8-bit dummy address beginning with 11). It's less work to include
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5388	* the 11 of the dummy address as part of the opcode than it is to shift
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5389	* it over the correct number of bits for the address. This puts the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5390	* EEPROM into write/erase mode.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5391	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5392	e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5393	(u16)(eeprom->opcode_bits + 2));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5394
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5395	e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5396
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5397	/* Prepare the EEPROM */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5398	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5399
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5400	while (words_written < words) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5401	/* Send the Write command (3-bit opcode + addr) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5402	e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5403	eeprom->opcode_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5404
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5405	e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5406	eeprom->address_bits);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5407
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5408	/* Send the data */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5409	e1000_shift_out_ee_bits(hw, data[words_written], 16);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5410
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5411	/* Toggle the CS line. This in effect tells the EEPROM to execute
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5412	* the previous command.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5413	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5414	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5415
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5416	/* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5417	* signal that the command has been completed by raising the DO signal.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5418	* If DO does not go high in 10 milliseconds, then error out.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5419	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5420	for (i = 0; i < 200; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5421	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5422	if (eecd & E1000_EECD_DO) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5423	udelay(50);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5424	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5425	if (i == 200) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5426	DEBUGOUT("EEPROM Write did not complete\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5427	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5428	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5429
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5430	/* Recover from write */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5431	e1000_standby_eeprom(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5432
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5433	words_written++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5434	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5435
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5436	/* Send the write disable command to the EEPROM (3-bit opcode plus
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5437	* 6/8-bit dummy address beginning with 10). It's less work to include
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5438	* the 10 of the dummy address as part of the opcode than it is to shift
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5439	* it over the correct number of bits for the address. This takes the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5440	* EEPROM out of write/erase mode.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5441	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5442	e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5443	(u16)(eeprom->opcode_bits + 2));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5444
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5445	e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5446
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5447	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5448	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5449
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5450	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5451	* Flushes the cached eeprom to NVM. This is done by saving the modified values
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5452	* in the eeprom cache and the non modified values in the currently active bank
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5453	* to the new bank.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5454	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5455	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5456	* offset - offset of word in the EEPROM to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5457	* data - word read from the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5458	* words - number of words to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5459	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5460	static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5461	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5462	u32 attempts = 100000;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5463	u32 eecd = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5464	u32 flop = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5465	u32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5466	s32 error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5467	u32 old_bank_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5468	u32 new_bank_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5469	u8 low_byte = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5470	u8 high_byte = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5471	bool sector_write_failed = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5472
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5473	if (hw->mac_type == e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5474	/* The flop register will be used to determine if flash type is STM */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5475	flop = er32(FLOP);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5476	for (i=0; i < attempts; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5477	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5478	if ((eecd & E1000_EECD_FLUPD) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5479	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5480	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5481	udelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5482	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5483
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5484	if (i == attempts) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5485	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5486	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5487
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5488	/* If STM opcode located in bits 15:8 of flop, reset firmware */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5489	if ((flop & 0xFF00) == E1000_STM_OPCODE) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5490	ew32(HICR, E1000_HICR_FW_RESET);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5491	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5492
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5493	/* Perform the flash update */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5494	ew32(EECD, eecd \| E1000_EECD_FLUPD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5495
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5496	for (i=0; i < attempts; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5497	eecd = er32(EECD);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5498	if ((eecd & E1000_EECD_FLUPD) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5499	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5500	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5501	udelay(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5502	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5503
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5504	if (i == attempts) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5505	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5506	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5507	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5508
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5509	if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5510	/* We're writing to the opposite bank so if we're on bank 1,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5511	* write to bank 0 etc. We also need to erase the segment that
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5512	* is going to be written */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5513	if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5514	new_bank_offset = hw->flash_bank_size * 2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5515	old_bank_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5516	e1000_erase_ich8_4k_segment(hw, 1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5517	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5518	old_bank_offset = hw->flash_bank_size * 2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5519	new_bank_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5520	e1000_erase_ich8_4k_segment(hw, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5521	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5522
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5523	sector_write_failed = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5524	/* Loop for every byte in the shadow RAM,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5525	* which is in units of words. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5526	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5527	/* Determine whether to write the value stored
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5528	* in the other NVM bank or a modified value stored
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5529	* in the shadow RAM */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5530	if (hw->eeprom_shadow_ram[i].modified) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5531	low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5532	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5533	error = e1000_verify_write_ich8_byte(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5534	(i << 1) + new_bank_offset, low_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5535
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5536	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5537	sector_write_failed = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5538	else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5539	high_byte =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5540	(u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5541	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5542	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5543	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5544	e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5545	&low_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5546	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5547	error = e1000_verify_write_ich8_byte(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5548	(i << 1) + new_bank_offset, low_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5549
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5550	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5551	sector_write_failed = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5552	else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5553	e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5554	&high_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5555	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5556	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5557	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5558
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5559	/* If the write of the low byte was successful, go ahead and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5560	* write the high byte while checking to make sure that if it
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5561	* is the signature byte, then it is handled properly */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5562	if (!sector_write_failed) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5563	/* If the word is 0x13, then make sure the signature bits
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5564	* (15:14) are 11b until the commit has completed.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5565	* This will allow us to write 10b which indicates the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5566	* signature is valid. We want to do this after the write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5567	* has completed so that we don't mark the segment valid
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5568	* while the write is still in progress */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5569	if (i == E1000_ICH_NVM_SIG_WORD)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5570	high_byte = E1000_ICH_NVM_SIG_MASK \| high_byte;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5571
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5572	error = e1000_verify_write_ich8_byte(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5573	(i << 1) + new_bank_offset + 1, high_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5574	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5575	sector_write_failed = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5576
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5577	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5578	/* If the write failed then break from the loop and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5579	* return an error */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5580	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5581	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5582	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5583
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5584	/* Don't bother writing the segment valid bits if sector
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5585	* programming failed. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5586	if (!sector_write_failed) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5587	/* Finally validate the new segment by setting bit 15:14
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5588	* to 10b in word 0x13 , this can be done without an
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5589	* erase as well since these bits are 11 to start with
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5590	* and we need to change bit 14 to 0b */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5591	e1000_read_ich8_byte(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5592	E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5593	&high_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5594	high_byte &= 0xBF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5595	error = e1000_verify_write_ich8_byte(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5596	E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5597	/* And invalidate the previously valid segment by setting
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5598	* its signature word (0x13) high_byte to 0b. This can be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5599	* done without an erase because flash erase sets all bits
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5600	* to 1's. We can write 1's to 0's without an erase */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5601	if (error == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5602	error = e1000_verify_write_ich8_byte(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5603	E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5604	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5605
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5606	/* Clear the now not used entry in the cache */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5607	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5608	hw->eeprom_shadow_ram[i].modified = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5609	hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5610	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5611	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5612	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5613
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5614	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5615	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5616
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5617	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5618	* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5619	* second function of dual function devices
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5620	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5621	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5622	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5623	s32 e1000_read_mac_addr(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5624	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5625	u16 offset;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5626	u16 eeprom_data, i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5627
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5628	DEBUGFUNC("e1000_read_mac_addr");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5629
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5630	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5631	offset = i >> 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5632	if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5633	DEBUGOUT("EEPROM Read Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5634	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5635	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5636	hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5637	hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5638	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5639
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5640	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5641	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5642	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5643	case e1000_82546:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5644	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5645	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5646	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5647	if (er32(STATUS) & E1000_STATUS_FUNC_1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5648	hw->perm_mac_addr[5] ^= 0x01;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5649	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5650	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5651
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5652	for (i = 0; i < NODE_ADDRESS_SIZE; i++)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5653	hw->mac_addr[i] = hw->perm_mac_addr[i];
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5654	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5655	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5656
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5657	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5658	* Initializes receive address filters.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5659	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5660	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5661	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5662	* Places the MAC address in receive address register 0 and clears the rest
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5663	* of the receive addresss registers. Clears the multicast table. Assumes
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5664	* the receiver is in reset when the routine is called.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5665	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5666	static void e1000_init_rx_addrs(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5667	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5668	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5669	u32 rar_num;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5670
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5671	DEBUGFUNC("e1000_init_rx_addrs");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5672
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5673	/* Setup the receive address. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5674	DEBUGOUT("Programming MAC Address into RAR[0]\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5675
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5676	e1000_rar_set(hw, hw->mac_addr, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5677
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5678	rar_num = E1000_RAR_ENTRIES;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5679
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5680	/* Reserve a spot for the Locally Administered Address to work around
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5681	* an 82571 issue in which a reset on one port will reload the MAC on
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5682	* the other port. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5683	if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5684	rar_num -= 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5685	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5686	rar_num = E1000_RAR_ENTRIES_ICH8LAN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5687
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5688	/* Zero out the other 15 receive addresses. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5689	DEBUGOUT("Clearing RAR[1-15]\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5690	for (i = 1; i < rar_num; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5691	E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5692	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5693	E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5694	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5695	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5696	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5697
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5698	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5699	* Hashes an address to determine its location in the multicast table
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5700	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5701	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5702	* mc_addr - the multicast address to hash
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5703	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5704	u32 e1000_hash_mc_addr(struct e1000_hw hw, u8 mc_addr)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5705	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5706	u32 hash_value = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5707
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5708	/* The portion of the address that is used for the hash table is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5709	* determined by the mc_filter_type setting.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5710	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5711	switch (hw->mc_filter_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5712	/* [0] [1] [2] [3] [4] [5]
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5713	* 01 AA 00 12 34 56
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5714	* LSB MSB
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5715	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5716	case 0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5717	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5718	/* [47:38] i.e. 0x158 for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5719	hash_value = ((mc_addr[4] >> 6) \| (((u16)mc_addr[5]) << 2));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5720	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5721	/* [47:36] i.e. 0x563 for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5722	hash_value = ((mc_addr[4] >> 4) \| (((u16)mc_addr[5]) << 4));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5723	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5724	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5725	case 1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5726	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5727	/* [46:37] i.e. 0x2B1 for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5728	hash_value = ((mc_addr[4] >> 5) \| (((u16)mc_addr[5]) << 3));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5729	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5730	/* [46:35] i.e. 0xAC6 for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5731	hash_value = ((mc_addr[4] >> 3) \| (((u16)mc_addr[5]) << 5));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5732	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5733	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5734	case 2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5735	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5736	/[45:36] i.e. 0x163 for above example address /
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5737	hash_value = ((mc_addr[4] >> 4) \| (((u16)mc_addr[5]) << 4));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5738	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5739	/* [45:34] i.e. 0x5D8 for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5740	hash_value = ((mc_addr[4] >> 2) \| (((u16)mc_addr[5]) << 6));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5741	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5742	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5743	case 3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5744	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5745	/* [43:34] i.e. 0x18D for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5746	hash_value = ((mc_addr[4] >> 2) \| (((u16)mc_addr[5]) << 6));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5747	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5748	/* [43:32] i.e. 0x634 for above example address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5749	hash_value = ((mc_addr[4]) \| (((u16)mc_addr[5]) << 8));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5750	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5751	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5752	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5753
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5754	hash_value &= 0xFFF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5755	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5756	hash_value &= 0x3FF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5757
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5758	return hash_value;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5759	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5760
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5761	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5762	* Sets the bit in the multicast table corresponding to the hash value.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5763	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5764	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5765	* hash_value - Multicast address hash value
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5766	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5767	void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5768	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5769	u32 hash_bit, hash_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5770	u32 mta;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5771	u32 temp;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5772
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5773	/* The MTA is a register array of 128 32-bit registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5774	* It is treated like an array of 4096 bits. We want to set
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5775	* bit BitArray[hash_value]. So we figure out what register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5776	* the bit is in, read it, OR in the new bit, then write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5777	* back the new value. The register is determined by the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5778	* upper 7 bits of the hash value and the bit within that
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5779	* register are determined by the lower 5 bits of the value.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5780	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5781	hash_reg = (hash_value >> 5) & 0x7F;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5782	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5783	hash_reg &= 0x1F;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5784
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5785	hash_bit = hash_value & 0x1F;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5786
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5787	mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5788
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5789	mta \|= (1 << hash_bit);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5790
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5791	/* If we are on an 82544 and we are trying to write an odd offset
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5792	* in the MTA, save off the previous entry before writing and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5793	* restore the old value after writing.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5794	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5795	if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5796	temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5797	E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5798	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5799	E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5800	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5801	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5802	E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5803	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5804	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5805	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5806
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5807	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5808	* Puts an ethernet address into a receive address register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5809	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5810	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5811	* addr - Address to put into receive address register
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5812	* index - Receive address register to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5813	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5814	void e1000_rar_set(struct e1000_hw hw, u8 addr, u32 index)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5815	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5816	u32 rar_low, rar_high;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5817
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5818	/* HW expects these in little endian so we reverse the byte order
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5819	* from network order (big endian) to little endian
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5820	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5821	rar_low = ((u32)addr[0] \| ((u32)addr[1] << 8) \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5822	((u32)addr[2] << 16) \| ((u32)addr[3] << 24));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5823	rar_high = ((u32)addr[4] \| ((u32)addr[5] << 8));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5824
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5825	/* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5826	* unit hang.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5827	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5828	* Description:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5829	* If there are any Rx frames queued up or otherwise present in the HW
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5830	* before RSS is enabled, and then we enable RSS, the HW Rx unit will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5831	* hang. To work around this issue, we have to disable receives and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5832	* flush out all Rx frames before we enable RSS. To do so, we modify we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5833	* redirect all Rx traffic to manageability and then reset the HW.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5834	* This flushes away Rx frames, and (since the redirections to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5835	* manageability persists across resets) keeps new ones from coming in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5836	* while we work. Then, we clear the Address Valid AV bit for all MAC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5837	* addresses and undo the re-direction to manageability.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5838	* Now, frames are coming in again, but the MAC won't accept them, so
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5839	* far so good. We now proceed to initialize RSS (if necessary) and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5840	* configure the Rx unit. Last, we re-enable the AV bits and continue
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5841	* on our merry way.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5842	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5843	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5844	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5845	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5846	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5847	if (hw->leave_av_bit_off)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5848	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5849	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5850	/* Indicate to hardware the Address is Valid. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5851	rar_high \|= E1000_RAH_AV;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5852	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5853	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5854
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5855	E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5856	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5857	E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5858	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5859	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5860
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5861	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5862	* Writes a value to the specified offset in the VLAN filter table.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5863	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5864	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5865	* offset - Offset in VLAN filer table to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5866	* value - Value to write into VLAN filter table
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5867	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5868	void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5869	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5870	u32 temp;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5871
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5872	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5873	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5874
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5875	if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5876	temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5877	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5878	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5879	E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5880	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5881	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5882	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5883	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5884	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5885	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5886
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5887	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5888	* Clears the VLAN filer table
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5889	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5890	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5891	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5892	static void e1000_clear_vfta(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5893	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5894	u32 offset;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5895	u32 vfta_value = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5896	u32 vfta_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5897	u32 vfta_bit_in_reg = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5898
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5899	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5900	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5901
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5902	if (hw->mac_type == e1000_82573) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5903	if (hw->mng_cookie.vlan_id != 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5904	/* The VFTA is a 4096b bit-field, each identifying a single VLAN
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5905	* ID. The following operations determine which 32b entry
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5906	* (i.e. offset) into the array we want to set the VLAN ID
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5907	* (i.e. bit) of the manageability unit. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5908	vfta_offset = (hw->mng_cookie.vlan_id >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5909	E1000_VFTA_ENTRY_SHIFT) &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5910	E1000_VFTA_ENTRY_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5911	vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5912	E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5913	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5914	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5915	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5916	/* If the offset we want to clear is the same offset of the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5917	* manageability VLAN ID, then clear all bits except that of the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5918	* manageability unit */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5919	vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5920	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5921	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5922	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5923	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5924
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5925	static s32 e1000_id_led_init(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5926	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5927	u32 ledctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5928	const u32 ledctl_mask = 0x000000FF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5929	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5930	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5931	u16 eeprom_data, i, temp;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5932	const u16 led_mask = 0x0F;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5933
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5934	DEBUGFUNC("e1000_id_led_init");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5935
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5936	if (hw->mac_type < e1000_82540) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5937	/* Nothing to do */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5938	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5939	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5940
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5941	ledctl = er32(LEDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5942	hw->ledctl_default = ledctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5943	hw->ledctl_mode1 = hw->ledctl_default;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5944	hw->ledctl_mode2 = hw->ledctl_default;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5945
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5946	if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5947	DEBUGOUT("EEPROM Read Error\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5948	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5949	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5950
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5951	if ((hw->mac_type == e1000_82573) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5952	(eeprom_data == ID_LED_RESERVED_82573))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5953	eeprom_data = ID_LED_DEFAULT_82573;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5954	else if ((eeprom_data == ID_LED_RESERVED_0000) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5955	(eeprom_data == ID_LED_RESERVED_FFFF)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5956	if (hw->mac_type == e1000_ich8lan)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5957	eeprom_data = ID_LED_DEFAULT_ICH8LAN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5958	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5959	eeprom_data = ID_LED_DEFAULT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5960	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5961
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5962	for (i = 0; i < 4; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5963	temp = (eeprom_data >> (i << 2)) & led_mask;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5964	switch (temp) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5965	case ID_LED_ON1_DEF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5966	case ID_LED_ON1_ON2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5967	case ID_LED_ON1_OFF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5968	hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5969	hw->ledctl_mode1 \|= ledctl_on << (i << 3);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5970	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5971	case ID_LED_OFF1_DEF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5972	case ID_LED_OFF1_ON2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5973	case ID_LED_OFF1_OFF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5974	hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5975	hw->ledctl_mode1 \|= ledctl_off << (i << 3);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5976	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5977	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5978	/* Do nothing */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5979	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5980	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5981	switch (temp) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5982	case ID_LED_DEF1_ON2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5983	case ID_LED_ON1_ON2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5984	case ID_LED_OFF1_ON2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5985	hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5986	hw->ledctl_mode2 \|= ledctl_on << (i << 3);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5987	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5988	case ID_LED_DEF1_OFF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5989	case ID_LED_ON1_OFF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5990	case ID_LED_OFF1_OFF2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5991	hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5992	hw->ledctl_mode2 \|= ledctl_off << (i << 3);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5993	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5994	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5995	/* Do nothing */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5996	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5997	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5998	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	5999	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6000	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6001
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6002	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6003	* Prepares SW controlable LED for use and saves the current state of the LED.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6004	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6005	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6006	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6007	s32 e1000_setup_led(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6008	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6009	u32 ledctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6010	s32 ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6011
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6012	DEBUGFUNC("e1000_setup_led");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6013
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6014	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6015	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6016	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6017	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6018	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6019	/* No setup necessary */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6020	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6021	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6022	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6023	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6024	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6025	/* Turn off PHY Smart Power Down (if enabled) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6026	ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6027	&hw->phy_spd_default);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6028	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6029	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6030	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6031	(u16)(hw->phy_spd_default &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6032	~IGP01E1000_GMII_SPD));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6033	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6034	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6035	/* Fall Through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6036	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6037	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6038	ledctl = er32(LEDCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6039	/* Save current LEDCTL settings */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6040	hw->ledctl_default = ledctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6041	/* Turn off LED0 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6042	ledctl &= ~(E1000_LEDCTL_LED0_IVRT \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6043	E1000_LEDCTL_LED0_BLINK \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6044	E1000_LEDCTL_LED0_MODE_MASK);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6045	ledctl \|= (E1000_LEDCTL_MODE_LED_OFF <<
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6046	E1000_LEDCTL_LED0_MODE_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6047	ew32(LEDCTL, ledctl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6048	} else if (hw->media_type == e1000_media_type_copper)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6049	ew32(LEDCTL, hw->ledctl_mode1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6050	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6051	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6052
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6053	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6054	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6055
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6056
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6057	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6058	* Used on 82571 and later Si that has LED blink bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6059	* Callers must use their own timer and should have already called
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6060	* e1000_id_led_init()
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6061	* Call e1000_cleanup led() to stop blinking
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6062	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6063	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6064	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6065	s32 e1000_blink_led_start(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6066	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6067	s16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6068	u32 ledctl_blink = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6069
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6070	DEBUGFUNC("e1000_id_led_blink_on");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6071
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6072	if (hw->mac_type < e1000_82571) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6073	/* Nothing to do */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6074	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6075	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6076	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6077	/* always blink LED0 for PCI-E fiber */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6078	ledctl_blink = E1000_LEDCTL_LED0_BLINK \|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6079	(E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6080	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6081	/* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6082	ledctl_blink = hw->ledctl_mode2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6083	for (i=0; i < 4; i++)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6084	if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6085	E1000_LEDCTL_MODE_LED_ON)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6086	ledctl_blink \|= (E1000_LEDCTL_LED0_BLINK << (i * 8));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6087	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6088
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6089	ew32(LEDCTL, ledctl_blink);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6090
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6091	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6092	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6093
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6094	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6095	* Restores the saved state of the SW controlable LED.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6096	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6097	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6098	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6099	s32 e1000_cleanup_led(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6100	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6101	s32 ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6102
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6103	DEBUGFUNC("e1000_cleanup_led");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6104
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6105	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6106	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6107	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6108	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6109	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6110	/* No cleanup necessary */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6111	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6112	case e1000_82541:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6113	case e1000_82547:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6114	case e1000_82541_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6115	case e1000_82547_rev_2:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6116	/* Turn on PHY Smart Power Down (if previously enabled) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6117	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6118	hw->phy_spd_default);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6119	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6120	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6121	/* Fall Through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6122	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6123	if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6124	e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6125	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6126	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6127	/* Restore LEDCTL settings */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6128	ew32(LEDCTL, hw->ledctl_default);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6129	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6130	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6131
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6132	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6133	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6134
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6135	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6136	* Turns on the software controllable LED
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6137	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6138	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6139	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6140	s32 e1000_led_on(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6141	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6142	u32 ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6143
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6144	DEBUGFUNC("e1000_led_on");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6145
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6146	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6147	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6148	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6149	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6150	/* Set SW Defineable Pin 0 to turn on the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6151	ctrl \|= E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6152	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6153	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6154	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6155	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6156	/* Set SW Defineable Pin 0 to turn on the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6157	ctrl \|= E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6158	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6159	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6160	/* Clear SW Defineable Pin 0 to turn on the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6161	ctrl &= ~E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6162	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6163	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6164	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6165	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6166	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6167	/* Clear SW Defineable Pin 0 to turn on the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6168	ctrl &= ~E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6169	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6170	} else if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6171	e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6172	(IFE_PSCL_PROBE_MODE \| IFE_PSCL_PROBE_LEDS_ON));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6173	} else if (hw->media_type == e1000_media_type_copper) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6174	ew32(LEDCTL, hw->ledctl_mode2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6175	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6176	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6177	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6178	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6179
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6180	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6181
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6182	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6183	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6184
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6185	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6186	* Turns off the software controllable LED
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6187	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6188	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6189	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6190	s32 e1000_led_off(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6191	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6192	u32 ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6193
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6194	DEBUGFUNC("e1000_led_off");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6195
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6196	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6197	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6198	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6199	case e1000_82543:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6200	/* Clear SW Defineable Pin 0 to turn off the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6201	ctrl &= ~E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6202	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6203	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6204	case e1000_82544:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6205	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6206	/* Clear SW Defineable Pin 0 to turn off the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6207	ctrl &= ~E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6208	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6209	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6210	/* Set SW Defineable Pin 0 to turn off the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6211	ctrl \|= E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6212	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6213	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6214	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6215	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6216	if (hw->media_type == e1000_media_type_fiber) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6217	/* Set SW Defineable Pin 0 to turn off the LED */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6218	ctrl \|= E1000_CTRL_SWDPIN0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6219	ctrl \|= E1000_CTRL_SWDPIO0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6220	} else if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6221	e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6222	(IFE_PSCL_PROBE_MODE \| IFE_PSCL_PROBE_LEDS_OFF));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6223	} else if (hw->media_type == e1000_media_type_copper) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6224	ew32(LEDCTL, hw->ledctl_mode1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6225	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6226	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6227	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6228	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6229
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6230	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6231
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6232	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6233	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6234
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6235	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6236	* Clears all hardware statistics counters.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6237	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6238	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6239	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6240	static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6241	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6242	volatile u32 temp;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6243
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6244	temp = er32(CRCERRS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6245	temp = er32(SYMERRS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6246	temp = er32(MPC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6247	temp = er32(SCC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6248	temp = er32(ECOL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6249	temp = er32(MCC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6250	temp = er32(LATECOL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6251	temp = er32(COLC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6252	temp = er32(DC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6253	temp = er32(SEC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6254	temp = er32(RLEC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6255	temp = er32(XONRXC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6256	temp = er32(XONTXC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6257	temp = er32(XOFFRXC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6258	temp = er32(XOFFTXC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6259	temp = er32(FCRUC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6260
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6261	if (hw->mac_type != e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6262	temp = er32(PRC64);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6263	temp = er32(PRC127);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6264	temp = er32(PRC255);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6265	temp = er32(PRC511);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6266	temp = er32(PRC1023);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6267	temp = er32(PRC1522);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6268	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6269
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6270	temp = er32(GPRC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6271	temp = er32(BPRC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6272	temp = er32(MPRC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6273	temp = er32(GPTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6274	temp = er32(GORCL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6275	temp = er32(GORCH);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6276	temp = er32(GOTCL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6277	temp = er32(GOTCH);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6278	temp = er32(RNBC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6279	temp = er32(RUC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6280	temp = er32(RFC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6281	temp = er32(ROC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6282	temp = er32(RJC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6283	temp = er32(TORL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6284	temp = er32(TORH);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6285	temp = er32(TOTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6286	temp = er32(TOTH);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6287	temp = er32(TPR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6288	temp = er32(TPT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6289
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6290	if (hw->mac_type != e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6291	temp = er32(PTC64);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6292	temp = er32(PTC127);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6293	temp = er32(PTC255);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6294	temp = er32(PTC511);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6295	temp = er32(PTC1023);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6296	temp = er32(PTC1522);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6297	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6298
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6299	temp = er32(MPTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6300	temp = er32(BPTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6301
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6302	if (hw->mac_type < e1000_82543) return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6303
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6304	temp = er32(ALGNERRC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6305	temp = er32(RXERRC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6306	temp = er32(TNCRS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6307	temp = er32(CEXTERR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6308	temp = er32(TSCTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6309	temp = er32(TSCTFC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6310
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6311	if (hw->mac_type <= e1000_82544) return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6312
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6313	temp = er32(MGTPRC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6314	temp = er32(MGTPDC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6315	temp = er32(MGTPTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6316
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6317	if (hw->mac_type <= e1000_82547_rev_2) return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6318
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6319	temp = er32(IAC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6320	temp = er32(ICRXOC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6321
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6322	if (hw->mac_type == e1000_ich8lan) return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6323
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6324	temp = er32(ICRXPTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6325	temp = er32(ICRXATC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6326	temp = er32(ICTXPTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6327	temp = er32(ICTXATC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6328	temp = er32(ICTXQEC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6329	temp = er32(ICTXQMTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6330	temp = er32(ICRXDMTC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6331	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6332
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6333	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6334	* Resets Adaptive IFS to its default state.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6335	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6336	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6337	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6338	* Call this after e1000_init_hw. You may override the IFS defaults by setting
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6339	* hw->ifs_params_forced to true. However, you must initialize hw->
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6340	* current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6341	* before calling this function.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6342	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6343	void e1000_reset_adaptive(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6344	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6345	DEBUGFUNC("e1000_reset_adaptive");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6346
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6347	if (hw->adaptive_ifs) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6348	if (!hw->ifs_params_forced) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6349	hw->current_ifs_val = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6350	hw->ifs_min_val = IFS_MIN;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6351	hw->ifs_max_val = IFS_MAX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6352	hw->ifs_step_size = IFS_STEP;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6353	hw->ifs_ratio = IFS_RATIO;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6354	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6355	hw->in_ifs_mode = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6356	ew32(AIT, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6357	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6358	DEBUGOUT("Not in Adaptive IFS mode!\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6359	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6360	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6361
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6362	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6363	* Called during the callback/watchdog routine to update IFS value based on
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6364	* the ratio of transmits to collisions.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6365	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6366	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6367	* tx_packets - Number of transmits since last callback
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6368	* total_collisions - Number of collisions since last callback
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6369	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6370	void e1000_update_adaptive(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6371	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6372	DEBUGFUNC("e1000_update_adaptive");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6373
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6374	if (hw->adaptive_ifs) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6375	if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6376	if (hw->tx_packet_delta > MIN_NUM_XMITS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6377	hw->in_ifs_mode = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6378	if (hw->current_ifs_val < hw->ifs_max_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6379	if (hw->current_ifs_val == 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6380	hw->current_ifs_val = hw->ifs_min_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6381	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6382	hw->current_ifs_val += hw->ifs_step_size;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6383	ew32(AIT, hw->current_ifs_val);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6384	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6385	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6386	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6387	if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6388	hw->current_ifs_val = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6389	hw->in_ifs_mode = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6390	ew32(AIT, 0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6391	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6392	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6393	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6394	DEBUGOUT("Not in Adaptive IFS mode!\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6395	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6396	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6397
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6398	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6399	* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6400	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6401	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6402	* frame_len - The length of the frame in question
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6403	* mac_addr - The Ethernet destination address of the frame in question
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6404	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6405	void e1000_tbi_adjust_stats(struct e1000_hw hw, struct e1000_hw_stats stats,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6406	u32 frame_len, u8 *mac_addr)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6407	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6408	u64 carry_bit;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6409
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6410	/* First adjust the frame length. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6411	frame_len--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6412	/* We need to adjust the statistics counters, since the hardware
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6413	* counters overcount this packet as a CRC error and undercount
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6414	* the packet as a good packet
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6415	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6416	/* This packet should not be counted as a CRC error. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6417	stats->crcerrs--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6418	/* This packet does count as a Good Packet Received. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6419	stats->gprc++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6420
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6421	/* Adjust the Good Octets received counters */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6422	carry_bit = 0x80000000 & stats->gorcl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6423	stats->gorcl += frame_len;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6424	/* If the high bit of Gorcl (the low 32 bits of the Good Octets
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6425	* Received Count) was one before the addition,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6426	* AND it is zero after, then we lost the carry out,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6427	* need to add one to Gorch (Good Octets Received Count High).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6428	* This could be simplified if all environments supported
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6429	* 64-bit integers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6430	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6431	if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6432	stats->gorch++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6433	/* Is this a broadcast or multicast? Check broadcast first,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6434	* since the test for a multicast frame will test positive on
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6435	* a broadcast frame.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6436	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6437	if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6438	/* Broadcast packet */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6439	stats->bprc++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6440	else if (*mac_addr & 0x01)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6441	/* Multicast packet */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6442	stats->mprc++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6443
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6444	if (frame_len == hw->max_frame_size) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6445	/* In this case, the hardware has overcounted the number of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6446	* oversize frames.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6447	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6448	if (stats->roc > 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6449	stats->roc--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6450	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6451
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6452	/* Adjust the bin counters when the extra byte put the frame in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6453	* wrong bin. Remember that the frame_len was adjusted above.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6454	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6455	if (frame_len == 64) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6456	stats->prc64++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6457	stats->prc127--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6458	} else if (frame_len == 127) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6459	stats->prc127++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6460	stats->prc255--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6461	} else if (frame_len == 255) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6462	stats->prc255++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6463	stats->prc511--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6464	} else if (frame_len == 511) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6465	stats->prc511++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6466	stats->prc1023--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6467	} else if (frame_len == 1023) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6468	stats->prc1023++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6469	stats->prc1522--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6470	} else if (frame_len == 1522) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6471	stats->prc1522++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6472	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6473	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6474
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6475	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6476	* Gets the current PCI bus type, speed, and width of the hardware
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6477	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6478	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6479	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6480	void e1000_get_bus_info(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6481	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6482	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6483	u16 pci_ex_link_status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6484	u32 status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6485
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6486	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6487	case e1000_82542_rev2_0:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6488	case e1000_82542_rev2_1:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6489	hw->bus_type = e1000_bus_type_pci;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6490	hw->bus_speed = e1000_bus_speed_unknown;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6491	hw->bus_width = e1000_bus_width_unknown;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6492	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6493	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6494	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6495	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6496	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6497	hw->bus_type = e1000_bus_type_pci_express;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6498	hw->bus_speed = e1000_bus_speed_2500;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6499	ret_val = e1000_read_pcie_cap_reg(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6500	PCI_EX_LINK_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6501	&pci_ex_link_status);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6502	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6503	hw->bus_width = e1000_bus_width_unknown;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6504	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6505	hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6506	PCI_EX_LINK_WIDTH_SHIFT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6507	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6508	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6509	hw->bus_type = e1000_bus_type_pci_express;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6510	hw->bus_speed = e1000_bus_speed_2500;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6511	hw->bus_width = e1000_bus_width_pciex_1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6512	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6513	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6514	status = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6515	hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6516	e1000_bus_type_pcix : e1000_bus_type_pci;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6517
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6518	if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6519	hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6520	e1000_bus_speed_66 : e1000_bus_speed_120;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6521	} else if (hw->bus_type == e1000_bus_type_pci) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6522	hw->bus_speed = (status & E1000_STATUS_PCI66) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6523	e1000_bus_speed_66 : e1000_bus_speed_33;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6524	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6525	switch (status & E1000_STATUS_PCIX_SPEED) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6526	case E1000_STATUS_PCIX_SPEED_66:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6527	hw->bus_speed = e1000_bus_speed_66;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6528	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6529	case E1000_STATUS_PCIX_SPEED_100:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6530	hw->bus_speed = e1000_bus_speed_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6531	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6532	case E1000_STATUS_PCIX_SPEED_133:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6533	hw->bus_speed = e1000_bus_speed_133;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6534	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6535	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6536	hw->bus_speed = e1000_bus_speed_reserved;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6537	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6538	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6539	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6540	hw->bus_width = (status & E1000_STATUS_BUS64) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6541	e1000_bus_width_64 : e1000_bus_width_32;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6542	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6543	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6544	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6545
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6546	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6547	* Writes a value to one of the devices registers using port I/O (as opposed to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6548	* memory mapped I/O). Only 82544 and newer devices support port I/O.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6549	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6550	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6551	* offset - offset to write to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6552	* value - value to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6553	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6554	static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6555	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6556	unsigned long io_addr = hw->io_base;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6557	unsigned long io_data = hw->io_base + 4;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6558
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6559	e1000_io_write(hw, io_addr, offset);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6560	e1000_io_write(hw, io_data, value);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6561	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6562
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6563	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6564	* Estimates the cable length.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6565	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6566	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6567	* min_length - The estimated minimum length
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6568	* max_length - The estimated maximum length
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6569	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6570	* returns: - E1000_ERR_XXX
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6571	* E1000_SUCCESS
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6572	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6573	* This function always returns a ranged length (minimum & maximum).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6574	* So for M88 phy's, this function interprets the one value returned from the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6575	* register to the minimum and maximum range.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6576	* For IGP phy's, the function calculates the range by the AGC registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6577	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6578	static s32 e1000_get_cable_length(struct e1000_hw hw, u16 min_length,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6579	u16 *max_length)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6580	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6581	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6582	u16 agc_value = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6583	u16 i, phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6584	u16 cable_length;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6585
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6586	DEBUGFUNC("e1000_get_cable_length");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6587
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6588	min_length = max_length = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6589
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6590	/* Use old method for Phy older than IGP */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6591	if (hw->phy_type == e1000_phy_m88) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6592
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6593	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6594	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6595	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6596	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6597	cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6598	M88E1000_PSSR_CABLE_LENGTH_SHIFT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6599
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6600	/* Convert the enum value to ranged values */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6601	switch (cable_length) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6602	case e1000_cable_length_50:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6603	*min_length = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6604	*max_length = e1000_igp_cable_length_50;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6605	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6606	case e1000_cable_length_50_80:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6607	*min_length = e1000_igp_cable_length_50;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6608	*max_length = e1000_igp_cable_length_80;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6609	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6610	case e1000_cable_length_80_110:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6611	*min_length = e1000_igp_cable_length_80;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6612	*max_length = e1000_igp_cable_length_110;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6613	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6614	case e1000_cable_length_110_140:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6615	*min_length = e1000_igp_cable_length_110;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6616	*max_length = e1000_igp_cable_length_140;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6617	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6618	case e1000_cable_length_140:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6619	*min_length = e1000_igp_cable_length_140;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6620	*max_length = e1000_igp_cable_length_170;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6621	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6622	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6623	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6624	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6625	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6626	} else if (hw->phy_type == e1000_phy_gg82563) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6627	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6628	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6629	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6630	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6631	cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6632
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6633	switch (cable_length) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6634	case e1000_gg_cable_length_60:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6635	*min_length = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6636	*max_length = e1000_igp_cable_length_60;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6637	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6638	case e1000_gg_cable_length_60_115:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6639	*min_length = e1000_igp_cable_length_60;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6640	*max_length = e1000_igp_cable_length_115;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6641	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6642	case e1000_gg_cable_length_115_150:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6643	*min_length = e1000_igp_cable_length_115;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6644	*max_length = e1000_igp_cable_length_150;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6645	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6646	case e1000_gg_cable_length_150:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6647	*min_length = e1000_igp_cable_length_150;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6648	*max_length = e1000_igp_cable_length_180;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6649	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6650	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6651	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6652	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6653	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6654	} else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6655	u16 cur_agc_value;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6656	u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6657	u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6658	{IGP01E1000_PHY_AGC_A,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6659	IGP01E1000_PHY_AGC_B,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6660	IGP01E1000_PHY_AGC_C,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6661	IGP01E1000_PHY_AGC_D};
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6662	/* Read the AGC registers for all channels */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6663	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6664
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6665	ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6666	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6667	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6668
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6669	cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6670
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6671	/* Value bound check. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6672	if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6673	(cur_agc_value == 0))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6674	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6675
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6676	agc_value += cur_agc_value;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6677
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6678	/* Update minimal AGC value. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6679	if (min_agc_value > cur_agc_value)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6680	min_agc_value = cur_agc_value;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6681	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6682
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6683	/* Remove the minimal AGC result for length < 50m */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6684	if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6685	agc_value -= min_agc_value;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6686
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6687	/* Get the average length of the remaining 3 channels */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6688	agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6689	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6690	/* Get the average length of all the 4 channels. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6691	agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6692	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6693
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6694	/* Set the range of the calculated length. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6695	*min_length = ((e1000_igp_cable_length_table[agc_value] -
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6696	IGP01E1000_AGC_RANGE) > 0) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6697	(e1000_igp_cable_length_table[agc_value] -
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6698	IGP01E1000_AGC_RANGE) : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6699	*max_length = e1000_igp_cable_length_table[agc_value] +
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6700	IGP01E1000_AGC_RANGE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6701	} else if (hw->phy_type == e1000_phy_igp_2 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6702	hw->phy_type == e1000_phy_igp_3) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6703	u16 cur_agc_index, max_agc_index = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6704	u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6705	u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6706	{IGP02E1000_PHY_AGC_A,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6707	IGP02E1000_PHY_AGC_B,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6708	IGP02E1000_PHY_AGC_C,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6709	IGP02E1000_PHY_AGC_D};
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6710	/* Read the AGC registers for all channels */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6711	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6712	ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6713	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6714	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6715
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6716	/* Getting bits 15:9, which represent the combination of course and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6717	* fine gain values. The result is a number that can be put into
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6718	* the lookup table to obtain the approximate cable length. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6719	cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6720	IGP02E1000_AGC_LENGTH_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6721
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6722	/* Array index bound check. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6723	if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6724	(cur_agc_index == 0))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6725	return -E1000_ERR_PHY;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6726
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6727	/* Remove min & max AGC values from calculation. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6728	if (e1000_igp_2_cable_length_table[min_agc_index] >
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6729	e1000_igp_2_cable_length_table[cur_agc_index])
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6730	min_agc_index = cur_agc_index;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6731	if (e1000_igp_2_cable_length_table[max_agc_index] <
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6732	e1000_igp_2_cable_length_table[cur_agc_index])
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6733	max_agc_index = cur_agc_index;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6734
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6735	agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6736	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6737
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6738	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6739	e1000_igp_2_cable_length_table[max_agc_index]);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6740	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6741
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6742	/* Calculate cable length with the error range of +/- 10 meters. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6743	*min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6744	(agc_value - IGP02E1000_AGC_RANGE) : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6745	*max_length = agc_value + IGP02E1000_AGC_RANGE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6746	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6747
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6748	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6749	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6750
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6751	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6752	* Check the cable polarity
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6753	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6754	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6755	* polarity - output parameter : 0 - Polarity is not reversed
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6756	* 1 - Polarity is reversed.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6757	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6758	* returns: - E1000_ERR_XXX
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6759	* E1000_SUCCESS
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6760	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6761	* For phy's older than IGP, this function simply reads the polarity bit in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6762	* Phy Status register. For IGP phy's, this bit is valid only if link speed is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6763	* 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6764	* return 0. If the link speed is 1000 Mbps the polarity status is in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6765	* IGP01E1000_PHY_PCS_INIT_REG.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6766	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6767	static s32 e1000_check_polarity(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6768	e1000_rev_polarity *polarity)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6769	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6770	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6771	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6772
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6773	DEBUGFUNC("e1000_check_polarity");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6774
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6775	if ((hw->phy_type == e1000_phy_m88) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6776	(hw->phy_type == e1000_phy_gg82563)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6777	/* return the Polarity bit in the Status register. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6778	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6779	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6780	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6781	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6782	*polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6783	M88E1000_PSSR_REV_POLARITY_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6784	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6785
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6786	} else if (hw->phy_type == e1000_phy_igp \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6787	hw->phy_type == e1000_phy_igp_3 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6788	hw->phy_type == e1000_phy_igp_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6789	/* Read the Status register to check the speed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6790	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6791	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6792	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6793	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6794
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6795	/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6796	* find the polarity status */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6797	if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6798	IGP01E1000_PSSR_SPEED_1000MBPS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6799
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6800	/* Read the GIG initialization PCS register (0x00B4) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6801	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6802	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6803	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6804	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6805
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6806	/* Check the polarity bits */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6807	*polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6808	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6809	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6810	/* For 10 Mbps, read the polarity bit in the status register. (for
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6811	* 100 Mbps this bit is always 0) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6812	*polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6813	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6814	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6815	} else if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6816	ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6817	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6818	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6819	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6820	*polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6821	IFE_PESC_POLARITY_REVERSED_SHIFT) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6822	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6823	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6824	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6825	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6826
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6827	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6828	* Check if Downshift occured
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6829	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6830	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6831	* downshift - output parameter : 0 - No Downshift ocured.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6832	* 1 - Downshift ocured.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6833	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6834	* returns: - E1000_ERR_XXX
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6835	* E1000_SUCCESS
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6836	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6837	* For phy's older than IGP, this function reads the Downshift bit in the Phy
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6838	* Specific Status register. For IGP phy's, it reads the Downgrade bit in the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6839	* Link Health register. In IGP this bit is latched high, so the driver must
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6840	* read it immediately after link is established.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6841	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6842	static s32 e1000_check_downshift(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6843	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6844	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6845	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6846
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6847	DEBUGFUNC("e1000_check_downshift");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6848
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6849	if (hw->phy_type == e1000_phy_igp \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6850	hw->phy_type == e1000_phy_igp_3 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6851	hw->phy_type == e1000_phy_igp_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6852	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6853	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6854	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6855	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6856
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6857	hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6858	} else if ((hw->phy_type == e1000_phy_m88) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6859	(hw->phy_type == e1000_phy_gg82563)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6860	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6861	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6862	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6863	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6864
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6865	hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6866	M88E1000_PSSR_DOWNSHIFT_SHIFT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6867	} else if (hw->phy_type == e1000_phy_ife) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6868	/* e1000_phy_ife supports 10/100 speed only */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6869	hw->speed_downgraded = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6870	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6871
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6872	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6873	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6874
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6875	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6876	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6877	* 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6878	* gigabit link is achieved to improve link quality.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6879	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6880	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6881	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6882	* returns: - E1000_ERR_PHY if fail to read/write the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6883	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6884	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6885	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6886
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6887	static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6888	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6889	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6890	u16 phy_data, phy_saved_data, speed, duplex, i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6891	u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6892	{IGP01E1000_PHY_AGC_PARAM_A,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6893	IGP01E1000_PHY_AGC_PARAM_B,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6894	IGP01E1000_PHY_AGC_PARAM_C,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6895	IGP01E1000_PHY_AGC_PARAM_D};
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6896	u16 min_length, max_length;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6897
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6898	DEBUGFUNC("e1000_config_dsp_after_link_change");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6899
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6900	if (hw->phy_type != e1000_phy_igp)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6901	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6902
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6903	if (link_up) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6904	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6905	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6906	DEBUGOUT("Error getting link speed and duplex\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6907	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6908	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6909
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6910	if (speed == SPEED_1000) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6911
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6912	ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6913	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6914	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6915
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6916	if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6917	min_length >= e1000_igp_cable_length_50) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6918
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6919	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6920	ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6921	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6922	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6923	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6924
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6925	phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6926
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6927	ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6928	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6929	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6930	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6931	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6932	hw->dsp_config_state = e1000_dsp_config_activated;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6933	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6934
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6935	if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6936	(min_length < e1000_igp_cable_length_50)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6937
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6938	u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6939	u32 idle_errs = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6940
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6941	/* clear previous idle error counts */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6942	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6943	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6944	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6945	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6946
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6947	for (i = 0; i < ffe_idle_err_timeout; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6948	udelay(1000);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6949	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6950	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6951	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6952	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6953
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6954	idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6955	if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6956	hw->ffe_config_state = e1000_ffe_config_active;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6957
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6958	ret_val = e1000_write_phy_reg(hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6959	IGP01E1000_PHY_DSP_FFE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6960	IGP01E1000_PHY_DSP_FFE_CM_CP);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6961	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6962	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6963	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6964	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6965
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6966	if (idle_errs)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6967	ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6968	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6969	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6970	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6971	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6972	if (hw->dsp_config_state == e1000_dsp_config_activated) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6973	/* Save off the current value of register 0x2F5B to be restored at
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6974	* the end of the routines. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6975	ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6976
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6977	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6978	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6979
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6980	/* Disable the PHY transmitter */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6981	ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6982
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6983	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6984	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6985
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6986	mdelay(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6987
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6988	ret_val = e1000_write_phy_reg(hw, 0x0000,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6989	IGP01E1000_IEEE_FORCE_GIGA);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6990	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6991	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6992	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6993	ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6994	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6995	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6996
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6997	phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6998	phy_data \|= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	6999
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7000	ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7001	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7002	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7003	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7004
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7005	ret_val = e1000_write_phy_reg(hw, 0x0000,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7006	IGP01E1000_IEEE_RESTART_AUTONEG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7007	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7008	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7009
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7010	mdelay(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7011
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7012	/* Now enable the transmitter */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7013	ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7014
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7015	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7016	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7017
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7018	hw->dsp_config_state = e1000_dsp_config_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7019	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7020
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7021	if (hw->ffe_config_state == e1000_ffe_config_active) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7022	/* Save off the current value of register 0x2F5B to be restored at
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7023	* the end of the routines. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7024	ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7025
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7026	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7027	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7028
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7029	/* Disable the PHY transmitter */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7030	ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7031
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7032	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7033	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7034
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7035	mdelay(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7036
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7037	ret_val = e1000_write_phy_reg(hw, 0x0000,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7038	IGP01E1000_IEEE_FORCE_GIGA);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7039	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7040	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7041	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7042	IGP01E1000_PHY_DSP_FFE_DEFAULT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7043	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7044	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7045
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7046	ret_val = e1000_write_phy_reg(hw, 0x0000,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7047	IGP01E1000_IEEE_RESTART_AUTONEG);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7048	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7049	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7050
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7051	mdelay(20);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7052
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7053	/* Now enable the transmitter */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7054	ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7055
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7056	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7057	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7058
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7059	hw->ffe_config_state = e1000_ffe_config_enabled;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7060	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7061	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7062	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7063	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7064
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7065	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7066	* Set PHY to class A mode
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7067	* Assumes the following operations will follow to enable the new class mode.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7068	* 1. Do a PHY soft reset
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7069	* 2. Restart auto-negotiation or force link.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7070	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7071	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7072	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7073	static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7074	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7075	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7076	u16 eeprom_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7077
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7078	DEBUGFUNC("e1000_set_phy_mode");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7079
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7080	if ((hw->mac_type == e1000_82545_rev_3) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7081	(hw->media_type == e1000_media_type_copper)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7082	ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7083	if (ret_val) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7084	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7085	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7086
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7087	if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7088	(eeprom_data & EEPROM_PHY_CLASS_A)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7089	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7090	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7091	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7092	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7093	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7094	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7095
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7096	hw->phy_reset_disable = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7097	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7098	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7099
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7100	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7101	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7102
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7103	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7104	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7105	* This function sets the lplu state according to the active flag. When
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7106	* activating lplu this function also disables smart speed and vise versa.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7107	* lplu will not be activated unless the device autonegotiation advertisment
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7108	* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7109	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7110	* active - true to enable lplu false to disable lplu.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7111	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7112	* returns: - E1000_ERR_PHY if fail to read/write the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7113	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7114	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7115	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7116
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7117	static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7118	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7119	u32 phy_ctrl = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7120	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7121	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7122	DEBUGFUNC("e1000_set_d3_lplu_state");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7123
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7124	if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7125	&& hw->phy_type != e1000_phy_igp_3)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7126	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7127
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7128	/* During driver activity LPLU should not be used or it will attain link
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7129	* from the lowest speeds starting from 10Mbps. The capability is used for
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7130	* Dx transitions and states */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7131	if (hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7132	ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7133	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7134	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7135	} else if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7136	/* MAC writes into PHY register based on the state transition
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7137	* and start auto-negotiation. SW driver can overwrite the settings
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7138	* in CSR PHY power control E1000_PHY_CTRL register. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7139	phy_ctrl = er32(PHY_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7140	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7141	ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7142	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7143	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7144	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7145
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7146	if (!active) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7147	if (hw->mac_type == e1000_82541_rev_2 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7148	hw->mac_type == e1000_82547_rev_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7149	phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7150	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7151	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7152	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7153	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7154	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7155	phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7156	ew32(PHY_CTRL, phy_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7157	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7158	phy_data &= ~IGP02E1000_PM_D3_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7159	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7160	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7161	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7162	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7163	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7164	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7165
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7166	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7167	* Dx states where the power conservation is most important. During
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7168	* driver activity we should enable SmartSpeed, so performance is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7169	* maintained. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7170	if (hw->smart_speed == e1000_smart_speed_on) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7171	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7172	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7173	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7174	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7175
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7176	phy_data \|= IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7177	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7178	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7179	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7180	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7181	} else if (hw->smart_speed == e1000_smart_speed_off) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7182	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7183	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7184	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7185	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7186
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7187	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7188	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7189	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7190	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7191	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7192	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7193
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7194	} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7195	(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7196	(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7197
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7198	if (hw->mac_type == e1000_82541_rev_2 \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7199	hw->mac_type == e1000_82547_rev_2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7200	phy_data \|= IGP01E1000_GMII_FLEX_SPD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7201	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7202	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7203	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7204	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7205	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7206	phy_ctrl \|= E1000_PHY_CTRL_NOND0A_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7207	ew32(PHY_CTRL, phy_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7208	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7209	phy_data \|= IGP02E1000_PM_D3_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7210	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7211	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7212	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7213	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7214	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7215	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7216
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7217	/* When LPLU is enabled we should disable SmartSpeed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7218	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7219	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7220	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7221
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7222	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7223	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7224	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7225	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7226
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7227	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7228	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7229	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7230
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7231	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7232	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7233	* This function sets the lplu d0 state according to the active flag. When
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7234	* activating lplu this function also disables smart speed and vise versa.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7235	* lplu will not be activated unless the device autonegotiation advertisment
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7236	* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7237	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7238	* active - true to enable lplu false to disable lplu.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7239	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7240	* returns: - E1000_ERR_PHY if fail to read/write the PHY
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7241	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7242	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7243	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7244
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7245	static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7246	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7247	u32 phy_ctrl = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7248	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7249	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7250	DEBUGFUNC("e1000_set_d0_lplu_state");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7251
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7252	if (hw->mac_type <= e1000_82547_rev_2)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7253	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7254
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7255	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7256	phy_ctrl = er32(PHY_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7257	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7258	ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7259	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7260	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7261	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7262
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7263	if (!active) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7264	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7265	phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7266	ew32(PHY_CTRL, phy_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7267	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7268	phy_data &= ~IGP02E1000_PM_D0_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7269	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7270	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7271	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7272	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7273
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7274	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7275	* Dx states where the power conservation is most important. During
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7276	* driver activity we should enable SmartSpeed, so performance is
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7277	* maintained. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7278	if (hw->smart_speed == e1000_smart_speed_on) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7279	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7280	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7281	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7282	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7283
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7284	phy_data \|= IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7285	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7286	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7287	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7288	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7289	} else if (hw->smart_speed == e1000_smart_speed_off) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7290	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7291	&phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7292	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7293	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7294
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7295	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7296	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7297	phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7298	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7299	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7300	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7301
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7302
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7303	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7304
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7305	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7306	phy_ctrl \|= E1000_PHY_CTRL_D0A_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7307	ew32(PHY_CTRL, phy_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7308	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7309	phy_data \|= IGP02E1000_PM_D0_LPLU;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7310	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7311	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7312	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7313	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7314
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7315	/* When LPLU is enabled we should disable SmartSpeed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7316	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7317	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7318	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7319
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7320	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7321	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7322	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7323	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7324
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7325	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7326	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7327	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7328
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7329	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7330	* Change VCO speed register to improve Bit Error Rate performance of SERDES.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7331	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7332	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7333	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7334	static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7335	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7336	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7337	u16 default_page = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7338	u16 phy_data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7339
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7340	DEBUGFUNC("e1000_set_vco_speed");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7341
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7342	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7343	case e1000_82545_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7344	case e1000_82546_rev_3:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7345	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7346	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7347	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7348	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7349
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7350	/* Set PHY register 30, page 5, bit 8 to 0 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7351
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7352	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7353	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7354	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7355
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7356	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7357	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7358	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7359
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7360	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7361	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7362	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7363
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7364	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7365	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7366	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7367	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7368
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7369	/* Set PHY register 30, page 4, bit 11 to 1 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7370
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7371	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7372	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7373	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7374
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7375	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7376	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7377	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7378
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7379	phy_data \|= M88E1000_PHY_VCO_REG_BIT11;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7380	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7381	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7382	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7383
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7384	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7385	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7386	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7387
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7388	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7389	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7390
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7391
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7392	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7393	* This function reads the cookie from ARC ram.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7394	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7395	* returns: - E1000_SUCCESS .
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7396	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7397	static s32 e1000_host_if_read_cookie(struct e1000_hw hw, u8 buffer)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7398	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7399	u8 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7400	u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7401	u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7402
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7403	length = (length >> 2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7404	offset = (offset >> 2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7405
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7406	for (i = 0; i < length; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7407	((u32 )buffer + i) =
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7408	E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7409	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7410	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7411	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7412
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7413
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7414	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7415	* This function checks whether the HOST IF is enabled for command operaton
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7416	* and also checks whether the previous command is completed.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7417	* It busy waits in case of previous command is not completed.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7418	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7419	* returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7420	* timeout
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7421	* - E1000_SUCCESS for success.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7422	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7423	static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7424	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7425	u32 hicr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7426	u8 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7427
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7428	/* Check that the host interface is enabled. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7429	hicr = er32(HICR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7430	if ((hicr & E1000_HICR_EN) == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7431	DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7432	return -E1000_ERR_HOST_INTERFACE_COMMAND;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7433	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7434	/* check the previous command is completed */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7435	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7436	hicr = er32(HICR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7437	if (!(hicr & E1000_HICR_C))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7438	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7439	mdelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7440	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7441
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7442	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7443	DEBUGOUT("Previous command timeout failed .\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7444	return -E1000_ERR_HOST_INTERFACE_COMMAND;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7445	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7446	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7447	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7448
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7449	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7450	* This function writes the buffer content at the offset given on the host if.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7451	* It also does alignment considerations to do the writes in most efficient way.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7452	* Also fills up the sum of the buffer in *buffer parameter.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7453	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7454	* returns - E1000_SUCCESS for success.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7455	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7456	static s32 e1000_mng_host_if_write(struct e1000_hw hw, u8 buffer, u16 length,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7457	u16 offset, u8 *sum)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7458	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7459	u8 *tmp;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7460	u8 *bufptr = buffer;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7461	u32 data = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7462	u16 remaining, i, j, prev_bytes;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7463
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7464	/* sum = only sum of the data and it is not checksum */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7465
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7466	if (length == 0 \|\| offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7467	return -E1000_ERR_PARAM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7468	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7469
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7470	tmp = (u8 *)&data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7471	prev_bytes = offset & 0x3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7472	offset &= 0xFFFC;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7473	offset >>= 2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7474
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7475	if (prev_bytes) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7476	data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7477	for (j = prev_bytes; j < sizeof(u32); j++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7478	(tmp + j) = bufptr++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7479	sum += (tmp + j);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7480	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7481	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7482	length -= j - prev_bytes;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7483	offset++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7484	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7485
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7486	remaining = length & 0x3;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7487	length -= remaining;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7488
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7489	/* Calculate length in DWORDs */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7490	length >>= 2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7491
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7492	/* The device driver writes the relevant command block into the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7493	* ram area. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7494	for (i = 0; i < length; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7495	for (j = 0; j < sizeof(u32); j++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7496	(tmp + j) = bufptr++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7497	sum += (tmp + j);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7498	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7499
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7500	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7501	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7502	if (remaining) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7503	for (j = 0; j < sizeof(u32); j++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7504	if (j < remaining)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7505	(tmp + j) = bufptr++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7506	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7507	*(tmp + j) = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7508
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7509	sum += (tmp + j);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7510	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7511	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7512	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7513
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7514	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7515	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7516
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7517
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7518	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7519	* This function writes the command header after does the checksum calculation.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7520	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7521	* returns - E1000_SUCCESS for success.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7522	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7523	static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7524	struct e1000_host_mng_command_header *hdr)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7525	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7526	u16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7527	u8 sum;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7528	u8 *buffer;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7529
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7530	/* Write the whole command header structure which includes sum of
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7531	* the buffer */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7532
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7533	u16 length = sizeof(struct e1000_host_mng_command_header);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7534
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7535	sum = hdr->checksum;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7536	hdr->checksum = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7537
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7538	buffer = (u8 *)hdr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7539	i = length;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7540	while (i--)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7541	sum += buffer[i];
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7542
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7543	hdr->checksum = 0 - sum;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7544
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7545	length >>= 2;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7546	/* The device driver writes the relevant command block into the ram area. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7547	for (i = 0; i < length; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7548	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, ((u32 )hdr + i));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7549	E1000_WRITE_FLUSH();
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7550	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7551
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7552	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7553	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7554
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7555
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7556	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7557	* This function indicates to ARC that a new command is pending which completes
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7558	* one write operation by the driver.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7559	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7560	* returns - E1000_SUCCESS for success.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7561	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7562	static s32 e1000_mng_write_commit(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7563	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7564	u32 hicr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7565
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7566	hicr = er32(HICR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7567	/* Setting this bit tells the ARC that a new command is pending. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7568	ew32(HICR, hicr \| E1000_HICR_C);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7569
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7570	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7571	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7572
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7573
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7574	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7575	* This function checks the mode of the firmware.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7576	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7577	* returns - true when the mode is IAMT or false.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7578	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7579	bool e1000_check_mng_mode(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7580	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7581	u32 fwsm;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7582
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7583	fwsm = er32(FWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7584
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7585	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7586	if ((fwsm & E1000_FWSM_MODE_MASK) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7587	(E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7588	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7589	} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7590	(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7591	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7592
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7593	return false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7594	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7595
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7596
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7597	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7598	* This function writes the dhcp info .
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7599	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7600	s32 e1000_mng_write_dhcp_info(struct e1000_hw hw, u8 buffer, u16 length)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7601	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7602	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7603	struct e1000_host_mng_command_header hdr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7604
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7605	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7606	hdr.command_length = length;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7607	hdr.reserved1 = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7608	hdr.reserved2 = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7609	hdr.checksum = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7610
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7611	ret_val = e1000_mng_enable_host_if(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7612	if (ret_val == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7613	ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7614	&(hdr.checksum));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7615	if (ret_val == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7616	ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7617	if (ret_val == E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7618	ret_val = e1000_mng_write_commit(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7619	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7620	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7621	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7622	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7623
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7624
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7625	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7626	* This function calculates the checksum.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7627	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7628	* returns - checksum of buffer contents.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7629	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7630	static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7631	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7632	u8 sum = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7633	u32 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7634
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7635	if (!buffer)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7636	return 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7637
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7638	for (i=0; i < length; i++)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7639	sum += buffer[i];
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7640
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7641	return (u8)(0 - sum);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7642	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7643
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7644	/*****************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7645	* This function checks whether tx pkt filtering needs to be enabled or not.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7646	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7647	* returns - true for packet filtering or false.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7648	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7649	bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7650	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7651	/* called in init as well as watchdog timer functions */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7652
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7653	s32 ret_val, checksum;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7654	bool tx_filter = false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7655	struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7656	u8 buffer = (u8 ) &(hw->mng_cookie);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7657
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7658	if (e1000_check_mng_mode(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7659	ret_val = e1000_mng_enable_host_if(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7660	if (ret_val == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7661	ret_val = e1000_host_if_read_cookie(hw, buffer);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7662	if (ret_val == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7663	checksum = hdr->checksum;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7664	hdr->checksum = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7665	if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7666	checksum == e1000_calculate_mng_checksum((char *)buffer,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7667	E1000_MNG_DHCP_COOKIE_LENGTH)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7668	if (hdr->status &
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7669	E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7670	tx_filter = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7671	} else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7672	tx_filter = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7673	} else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7674	tx_filter = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7675	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7676	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7677
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7678	hw->tx_pkt_filtering = tx_filter;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7679	return tx_filter;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7680	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7681
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7682	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7683	* Verifies the hardware needs to allow ARPs to be processed by the host
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7684	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7685	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7686	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7687	* returns: - true/false
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7688	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7689	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7690	u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7691	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7692	u32 manc;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7693	u32 fwsm, factps;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7694
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7695	if (hw->asf_firmware_present) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7696	manc = er32(MANC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7697
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7698	if (!(manc & E1000_MANC_RCV_TCO_EN) \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7699	!(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7700	return false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7701	if (e1000_arc_subsystem_valid(hw)) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7702	fwsm = er32(FWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7703	factps = er32(FACTPS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7704
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7705	if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7706	e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7707	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7708	} else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7709	if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7710	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7711	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7712	return false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7713	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7714
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7715	static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7716	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7717	s32 ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7718	u16 mii_status_reg;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7719	u16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7720
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7721	/* Polarity reversal workaround for forced 10F/10H links. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7722
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7723	/* Disable the transmitter on the PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7724
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7725	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7726	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7727	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7728	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7729	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7730	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7731
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7732	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7733	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7734	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7735
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7736	/* This loop will early-out if the NO link condition has been met. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7737	for (i = PHY_FORCE_TIME; i > 0; i--) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7738	/* Read the MII Status Register and wait for Link Status bit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7739	* to be clear.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7740	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7741
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7742	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7743	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7744	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7745
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7746	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7747	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7748	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7749
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7750	if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7751	mdelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7752	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7753
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7754	/* Recommended delay time after link has been lost */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7755	mdelay(1000);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7756
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7757	/* Now we will re-enable th transmitter on the PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7758
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7759	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7760	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7761	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7762	mdelay(50);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7763	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7764	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7765	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7766	mdelay(50);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7767	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7768	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7769	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7770	mdelay(50);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7771	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7772	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7773	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7774
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7775	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7776	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7777	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7778
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7779	/* This loop will early-out if the link condition has been met. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7780	for (i = PHY_FORCE_TIME; i > 0; i--) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7781	/* Read the MII Status Register and wait for Link Status bit
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7782	* to be set.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7783	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7784
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7785	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7786	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7787	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7788
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7789	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7790	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7791	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7792
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7793	if (mii_status_reg & MII_SR_LINK_STATUS) break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7794	mdelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7795	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7796	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7797	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7798
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7799	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7800	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7801	* Disables PCI-Express master access.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7802	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7803	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7804	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7805	* returns: - none.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7806	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7807	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7808	static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7809	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7810	u32 ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7811
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7812	DEBUGFUNC("e1000_set_pci_express_master_disable");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7813
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7814	if (hw->bus_type != e1000_bus_type_pci_express)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7815	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7816
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7817	ctrl = er32(CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7818	ctrl \|= E1000_CTRL_GIO_MASTER_DISABLE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7819	ew32(CTRL, ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7820	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7821
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7822	/*******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7823	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7824	* Disables PCI-Express master access and verifies there are no pending requests
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7825	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7826	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7827	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7828	* returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7829	* caused the master requests to be disabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7830	* E1000_SUCCESS master requests disabled.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7831	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7832	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7833	s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7834	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7835	s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7836
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7837	DEBUGFUNC("e1000_disable_pciex_master");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7838
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7839	if (hw->bus_type != e1000_bus_type_pci_express)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7840	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7841
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7842	e1000_set_pci_express_master_disable(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7843
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7844	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7845	if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7846	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7847	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7848	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7849	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7850	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7851
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7852	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7853	DEBUGOUT("Master requests are pending.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7854	return -E1000_ERR_MASTER_REQUESTS_PENDING;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7855	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7856
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7857	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7858	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7859
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7860	/*******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7861	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7862	* Check for EEPROM Auto Read bit done.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7863	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7864	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7865	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7866	* returns: - E1000_ERR_RESET if fail to reset MAC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7867	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7868	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7869	******************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7870	static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7871	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7872	s32 timeout = AUTO_READ_DONE_TIMEOUT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7873
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7874	DEBUGFUNC("e1000_get_auto_rd_done");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7875
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7876	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7877	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7878	msleep(5);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7879	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7880	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7881	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7882	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7883	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7884	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7885	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7886	if (er32(EECD) & E1000_EECD_AUTO_RD)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7887	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7888	else msleep(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7889	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7890	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7891
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7892	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7893	DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7894	return -E1000_ERR_RESET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7895	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7896	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7897	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7898
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7899	/* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7900	* Need to wait for PHY configuration completion before accessing NVM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7901	* and PHY. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7902	if (hw->mac_type == e1000_82573)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7903	msleep(25);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7904
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7905	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7906	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7907
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7908	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7909	* Checks if the PHY configuration is done
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7910	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7911	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7912	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7913	* returns: - E1000_ERR_RESET if fail to reset MAC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7914	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7915	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7916	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7917	static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7918	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7919	s32 timeout = PHY_CFG_TIMEOUT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7920	u32 cfg_mask = E1000_EEPROM_CFG_DONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7921
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7922	DEBUGFUNC("e1000_get_phy_cfg_done");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7923
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7924	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7925	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7926	mdelay(10);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7927	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7928	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7929	/* Separate _CFG_DONE_ bit for each port */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7930	if (er32(STATUS) & E1000_STATUS_FUNC_1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7931	cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7932	/* Fall Through */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7933	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7934	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7935	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7936	if (er32(EEMNGCTL) & cfg_mask)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7937	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7938	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7939	msleep(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7940	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7941	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7942	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7943	DEBUGOUT("MNG configuration cycle has not completed.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7944	return -E1000_ERR_RESET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7945	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7946	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7947	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7948
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7949	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7950	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7951
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7952	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7953	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7954	* Using the combination of SMBI and SWESMBI semaphore bits when resetting
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7955	* adapter or Eeprom access.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7956	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7957	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7958	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7959	* returns: - E1000_ERR_EEPROM if fail to access EEPROM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7960	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7961	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7962	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7963	static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7964	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7965	s32 timeout;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7966	u32 swsm;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7967
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7968	DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7969
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7970	if (!hw->eeprom_semaphore_present)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7971	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7972
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7973	if (hw->mac_type == e1000_80003es2lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7974	/* Get the SW semaphore. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7975	if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7976	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7977	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7978
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7979	/* Get the FW semaphore. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7980	timeout = hw->eeprom.word_size + 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7981	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7982	swsm = er32(SWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7983	swsm \|= E1000_SWSM_SWESMBI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7984	ew32(SWSM, swsm);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7985	/* if we managed to set the bit we got the semaphore. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7986	swsm = er32(SWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7987	if (swsm & E1000_SWSM_SWESMBI)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7988	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7989
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7990	udelay(50);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7991	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7992	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7993
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7994	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7995	/* Release semaphores */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7996	e1000_put_hw_eeprom_semaphore(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7997	DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7998	return -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	7999	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8000
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8001	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8002	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8003
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8004	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8005	* This function clears HW semaphore bits.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8006	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8007	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8008	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8009	* returns: - None.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8010	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8011	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8012	static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8013	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8014	u32 swsm;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8015
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8016	DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8017
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8018	if (!hw->eeprom_semaphore_present)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8019	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8020
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8021	swsm = er32(SWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8022	if (hw->mac_type == e1000_80003es2lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8023	/* Release both semaphores. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8024	swsm &= ~(E1000_SWSM_SMBI \| E1000_SWSM_SWESMBI);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8025	} else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8026	swsm &= ~(E1000_SWSM_SWESMBI);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8027	ew32(SWSM, swsm);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8028	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8029
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8030	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8031	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8032	* Obtaining software semaphore bit (SMBI) before resetting PHY.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8033	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8034	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8035	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8036	* returns: - E1000_ERR_RESET if fail to obtain semaphore.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8037	* E1000_SUCCESS at any other case.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8038	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8039	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8040	static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8041	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8042	s32 timeout = hw->eeprom.word_size + 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8043	u32 swsm;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8044
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8045	DEBUGFUNC("e1000_get_software_semaphore");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8046
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8047	if (hw->mac_type != e1000_80003es2lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8048	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8049	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8050
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8051	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8052	swsm = er32(SWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8053	/* If SMBI bit cleared, it is now set and we hold the semaphore */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8054	if (!(swsm & E1000_SWSM_SMBI))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8055	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8056	mdelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8057	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8058	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8059
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8060	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8061	DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8062	return -E1000_ERR_RESET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8063	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8064
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8065	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8066	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8067
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8068	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8069	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8070	* Release semaphore bit (SMBI).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8071	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8072	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8073	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8074	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8075	static void e1000_release_software_semaphore(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8076	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8077	u32 swsm;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8078
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8079	DEBUGFUNC("e1000_release_software_semaphore");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8080
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8081	if (hw->mac_type != e1000_80003es2lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8082	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8083	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8084
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8085	swsm = er32(SWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8086	/* Release the SW semaphores.*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8087	swsm &= ~E1000_SWSM_SMBI;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8088	ew32(SWSM, swsm);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8089	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8090
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8091	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8092	* Checks if PHY reset is blocked due to SOL/IDER session, for example.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8093	* Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8094	* the caller to figure out how to deal with it.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8095	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8096	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8097	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8098	* returns: - E1000_BLK_PHY_RESET
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8099	* E1000_SUCCESS
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8100	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8101	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8102	s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8103	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8104	u32 manc = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8105	u32 fwsm = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8106
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8107	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8108	fwsm = er32(FWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8109	return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8110	: E1000_BLK_PHY_RESET;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8111	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8112
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8113	if (hw->mac_type > e1000_82547_rev_2)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8114	manc = er32(MANC);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8115	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8116	E1000_BLK_PHY_RESET : E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8117	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8118
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8119	static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8120	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8121	u32 fwsm;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8122
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8123	/* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8124	* may not be provided a DMA clock when no manageability features are
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8125	* enabled. We do not want to perform any reads/writes to these registers
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8126	* if this is the case. We read FWSM to determine the manageability mode.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8127	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8128	switch (hw->mac_type) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8129	case e1000_82571:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8130	case e1000_82572:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8131	case e1000_82573:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8132	case e1000_80003es2lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8133	fwsm = er32(FWSM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8134	if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8135	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8136	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8137	case e1000_ich8lan:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8138	return true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8139	default:
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8140	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8141	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8142	return false;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8143	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8144
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8145
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8146	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8147	* Configure PCI-Ex no-snoop
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8148	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8149	* hw - Struct containing variables accessed by shared code.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8150	* no_snoop - Bitmap of no-snoop events.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8151	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8152	* returns: E1000_SUCCESS
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8153	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8154	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8155	static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8156	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8157	u32 gcr_reg = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8158
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8159	DEBUGFUNC("e1000_set_pci_ex_no_snoop");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8160
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8161	if (hw->bus_type == e1000_bus_type_unknown)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8162	e1000_get_bus_info(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8163
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8164	if (hw->bus_type != e1000_bus_type_pci_express)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8165	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8166
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8167	if (no_snoop) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8168	gcr_reg = er32(GCR);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8169	gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8170	gcr_reg \|= no_snoop;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8171	ew32(GCR, gcr_reg);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8172	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8173	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8174	u32 ctrl_ext;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8175
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8176	ew32(GCR, PCI_EX_82566_SNOOP_ALL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8177
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8178	ctrl_ext = er32(CTRL_EXT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8179	ctrl_ext \|= E1000_CTRL_EXT_RO_DIS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8180	ew32(CTRL_EXT, ctrl_ext);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8181	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8182
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8183	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8184	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8185
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8186	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8187	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8188	* Get software semaphore FLAG bit (SWFLAG).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8189	* SWFLAG is used to synchronize the access to all shared resource between
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8190	* SW, FW and HW.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8191	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8192	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8193	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8194	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8195	static s32 e1000_get_software_flag(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8196	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8197	s32 timeout = PHY_CFG_TIMEOUT;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8198	u32 extcnf_ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8199
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8200	DEBUGFUNC("e1000_get_software_flag");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8201
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8202	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8203	while (timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8204	extcnf_ctrl = er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8205	extcnf_ctrl \|= E1000_EXTCNF_CTRL_SWFLAG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8206	ew32(EXTCNF_CTRL, extcnf_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8207
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8208	extcnf_ctrl = er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8209	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8210	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8211	mdelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8212	timeout--;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8213	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8214
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8215	if (!timeout) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8216	DEBUGOUT("FW or HW locks the resource too long.\n");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8217	return -E1000_ERR_CONFIG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8218	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8219	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8220
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8221	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8222	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8223
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8224	/***************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8225	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8226	* Release software semaphore FLAG bit (SWFLAG).
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8227	* SWFLAG is used to synchronize the access to all shared resource between
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8228	* SW, FW and HW.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8229	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8230	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8231	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8232	***************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8233	static void e1000_release_software_flag(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8234	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8235	u32 extcnf_ctrl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8236
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8237	DEBUGFUNC("e1000_release_software_flag");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8238
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8239	if (hw->mac_type == e1000_ich8lan) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8240	extcnf_ctrl= er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8241	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8242	ew32(EXTCNF_CTRL, extcnf_ctrl);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8243	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8244
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8245	return;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8246	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8247
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8248	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8249	* Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8250	* register.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8251	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8252	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8253	* offset - offset of word in the EEPROM to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8254	* data - word read from the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8255	* words - number of words to read
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8256	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8257	static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8258	u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8259	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8260	s32 error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8261	u32 flash_bank = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8262	u32 act_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8263	u32 bank_offset = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8264	u16 word = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8265	u16 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8266
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8267	/* We need to know which is the valid flash bank. In the event
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8268	* that we didn't allocate eeprom_shadow_ram, we may not be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8269	* managing flash_bank. So it cannot be trusted and needs
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8270	* to be updated with each read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8271	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8272	/* Value of bit 22 corresponds to the flash bank we're on. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8273	flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8274
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8275	/* Adjust offset appropriately if we're on bank 1 - adjust for word size */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8276	bank_offset = flash_bank * (hw->flash_bank_size * 2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8277
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8278	error = e1000_get_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8279	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8280	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8281
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8282	for (i = 0; i < words; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8283	if (hw->eeprom_shadow_ram != NULL &&
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8284	hw->eeprom_shadow_ram[offset+i].modified) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8285	data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8286	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8287	/* The NVM part needs a byte offset, hence * 2 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8288	act_offset = bank_offset + ((offset + i) * 2);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8289	error = e1000_read_ich8_word(hw, act_offset, &word);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8290	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8291	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8292	data[i] = word;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8293	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8294	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8295
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8296	e1000_release_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8297
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8298	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8299	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8300
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8301	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8302	* Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8303	* register. Actually, writes are written to the shadow ram cache in the hw
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8304	* structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8305	* the NVM, which occurs when the NVM checksum is updated.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8306	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8307	* hw - Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8308	* offset - offset of word in the EEPROM to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8309	* words - number of words to write
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8310	* data - words to write to the EEPROM
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8311	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8312	static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8313	u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8314	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8315	u32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8316	s32 error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8317
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8318	error = e1000_get_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8319	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8320	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8321
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8322	/* A driver can write to the NVM only if it has eeprom_shadow_ram
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8323	* allocated. Subsequent reads to the modified words are read from
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8324	* this cached structure as well. Writes will only go into this
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8325	* cached structure unless it's followed by a call to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8326	* e1000_update_eeprom_checksum() where it will commit the changes
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8327	* and clear the "modified" field.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8328	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8329	if (hw->eeprom_shadow_ram != NULL) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8330	for (i = 0; i < words; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8331	if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8332	hw->eeprom_shadow_ram[offset+i].modified = true;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8333	hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8334	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8335	error = -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8336	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8337	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8338	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8339	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8340	/* Drivers have the option to not allocate eeprom_shadow_ram as long
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8341	* as they don't perform any NVM writes. An attempt in doing so
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8342	* will result in this error.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8343	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8344	error = -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8345	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8346
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8347	e1000_release_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8348
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8349	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8350	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8351
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8352	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8353	* This function does initial flash setup so that a new read/write/erase cycle
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8354	* can be started.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8355	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8356	* hw - The pointer to the hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8357	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8358	static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8359	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8360	union ich8_hws_flash_status hsfsts;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8361	s32 error = E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8362	s32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8363
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8364	DEBUGFUNC("e1000_ich8_cycle_init");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8365
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8366	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8367
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8368	/* May be check the Flash Des Valid bit in Hw status */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8369	if (hsfsts.hsf_status.fldesvalid == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8370	DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8371	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8372	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8373
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8374	/* Clear FCERR in Hw status by writing 1 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8375	/* Clear DAEL in Hw status by writing a 1 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8376	hsfsts.hsf_status.flcerr = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8377	hsfsts.hsf_status.dael = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8378
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8379	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8380
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8381	/* Either we should have a hardware SPI cycle in progress bit to check
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8382	* against, in order to start a new cycle or FDONE bit should be changed
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8383	* in the hardware so that it is 1 after harware reset, which can then be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8384	* used as an indication whether a cycle is in progress or has been
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8385	* completed .. we should also have some software semaphore mechanism to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8386	* guard FDONE or the cycle in progress bit so that two threads access to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8387	* those bits can be sequentiallized or a way so that 2 threads dont
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8388	* start the cycle at the same time */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8389
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8390	if (hsfsts.hsf_status.flcinprog == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8391	/* There is no cycle running at present, so we can start a cycle */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8392	/* Begin by setting Flash Cycle Done. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8393	hsfsts.hsf_status.flcdone = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8394	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8395	error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8396	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8397	/* otherwise poll for sometime so the current cycle has a chance
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8398	* to end before giving up. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8399	for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8400	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8401	if (hsfsts.hsf_status.flcinprog == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8402	error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8403	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8404	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8405	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8406	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8407	if (error == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8408	/* Successful in waiting for previous cycle to timeout,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8409	* now set the Flash Cycle Done. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8410	hsfsts.hsf_status.flcdone = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8411	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8412	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8413	DEBUGOUT("Flash controller busy, cannot get access");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8414	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8415	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8416	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8417	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8418
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8419	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8420	* This function starts a flash cycle and waits for its completion
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8421	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8422	* hw - The pointer to the hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8423	****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8424	static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8425	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8426	union ich8_hws_flash_ctrl hsflctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8427	union ich8_hws_flash_status hsfsts;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8428	s32 error = E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8429	u32 i = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8430
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8431	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8432	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8433	hsflctl.hsf_ctrl.flcgo = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8434	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8435
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8436	/* wait till FDONE bit is set to 1 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8437	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8438	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8439	if (hsfsts.hsf_status.flcdone == 1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8440	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8441	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8442	i++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8443	} while (i < timeout);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8444	if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8445	error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8446	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8447	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8448	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8449
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8450	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8451	* Reads a byte or word from the NVM using the ICH8 flash access registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8452	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8453	* hw - The pointer to the hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8454	* index - The index of the byte or word to read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8455	* size - Size of data to read, 1=byte 2=word
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8456	* data - Pointer to the word to store the value read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8457	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8458	static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8459	u16 *data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8460	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8461	union ich8_hws_flash_status hsfsts;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8462	union ich8_hws_flash_ctrl hsflctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8463	u32 flash_linear_address;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8464	u32 flash_data = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8465	s32 error = -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8466	s32 count = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8467
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8468	DEBUGFUNC("e1000_read_ich8_data");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8469
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8470	if (size < 1 \|\| size > 2 \|\| data == NULL \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8471	index > ICH_FLASH_LINEAR_ADDR_MASK)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8472	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8473
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8474	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8475	hw->flash_base_addr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8476
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8477	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8478	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8479	/* Steps */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8480	error = e1000_ich8_cycle_init(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8481	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8482	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8483
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8484	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8485	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8486	hsflctl.hsf_ctrl.fldbcount = size - 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8487	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8488	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8489
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8490	/* Write the last 24 bits of index into Flash Linear address field in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8491	* Flash Address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8492	/* TODO: TBD maybe check the index against the size of flash */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8493
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8494	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8495
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8496	error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8497
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8498	/* Check if FCERR is set to 1, if set to 1, clear it and try the whole
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8499	* sequence a few more times, else read in (shift in) the Flash Data0,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8500	* the order is least significant byte first msb to lsb */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8501	if (error == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8502	flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8503	if (size == 1) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8504	*data = (u8)(flash_data & 0x000000FF);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8505	} else if (size == 2) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8506	*data = (u16)(flash_data & 0x0000FFFF);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8507	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8508	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8509	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8510	/* If we've gotten here, then things are probably completely hosed,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8511	* but if the error condition is detected, it won't hurt to give
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8512	* it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8513	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8514	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8515	if (hsfsts.hsf_status.flcerr == 1) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8516	/* Repeat for some time before giving up. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8517	continue;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8518	} else if (hsfsts.hsf_status.flcdone == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8519	DEBUGOUT("Timeout error - flash cycle did not complete.");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8520	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8521	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8522	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8523	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8524
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8525	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8526	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8527
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8528	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8529	* Writes One /two bytes to the NVM using the ICH8 flash access registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8530	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8531	* hw - The pointer to the hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8532	* index - The index of the byte/word to read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8533	* size - Size of data to read, 1=byte 2=word
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8534	* data - The byte(s) to write to the NVM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8535	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8536	static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8537	u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8538	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8539	union ich8_hws_flash_status hsfsts;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8540	union ich8_hws_flash_ctrl hsflctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8541	u32 flash_linear_address;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8542	u32 flash_data = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8543	s32 error = -E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8544	s32 count = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8545
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8546	DEBUGFUNC("e1000_write_ich8_data");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8547
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8548	if (size < 1 \|\| size > 2 \|\| data > size * 0xff \|\|
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8549	index > ICH_FLASH_LINEAR_ADDR_MASK)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8550	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8551
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8552	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8553	hw->flash_base_addr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8554
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8555	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8556	udelay(1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8557	/* Steps */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8558	error = e1000_ich8_cycle_init(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8559	if (error != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8560	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8561
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8562	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8563	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8564	hsflctl.hsf_ctrl.fldbcount = size -1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8565	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8566	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8567
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8568	/* Write the last 24 bits of index into Flash Linear address field in
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8569	* Flash Address */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8570	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8571
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8572	if (size == 1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8573	flash_data = (u32)data & 0x00FF;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8574	else
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8575	flash_data = (u32)data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8576
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8577	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8578
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8579	/* check if FCERR is set to 1 , if set to 1, clear it and try the whole
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8580	* sequence a few more times else done */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8581	error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8582	if (error == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8583	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8584	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8585	/* If we're here, then things are most likely completely hosed,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8586	* but if the error condition is detected, it won't hurt to give
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8587	* it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8588	*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8589	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8590	if (hsfsts.hsf_status.flcerr == 1) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8591	/* Repeat for some time before giving up. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8592	continue;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8593	} else if (hsfsts.hsf_status.flcdone == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8594	DEBUGOUT("Timeout error - flash cycle did not complete.");
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8595	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8596	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8597	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8598	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8599
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8600	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8601	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8602
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8603	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8604	* Reads a single byte from the NVM using the ICH8 flash access registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8605	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8606	* hw - pointer to e1000_hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8607	* index - The index of the byte to read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8608	* data - Pointer to a byte to store the value read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8609	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8610	static s32 e1000_read_ich8_byte(struct e1000_hw hw, u32 index, u8 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8611	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8612	s32 status = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8613	u16 word = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8614
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8615	status = e1000_read_ich8_data(hw, index, 1, &word);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8616	if (status == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8617	*data = (u8)word;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8618	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8619
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8620	return status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8621	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8622
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8623	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8624	* Writes a single byte to the NVM using the ICH8 flash access registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8625	* Performs verification by reading back the value and then going through
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8626	* a retry algorithm before giving up.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8627	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8628	* hw - pointer to e1000_hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8629	* index - The index of the byte to write.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8630	* byte - The byte to write to the NVM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8631	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8632	static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8633	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8634	s32 error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8635	s32 program_retries = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8636
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8637	DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8638
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8639	error = e1000_write_ich8_byte(hw, index, byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8640
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8641	if (error != E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8642	for (program_retries = 0; program_retries < 100; program_retries++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8643	DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8644	error = e1000_write_ich8_byte(hw, index, byte);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8645	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8646	if (error == E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8647	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8648	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8649	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8650
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8651	if (program_retries == 100)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8652	error = E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8653
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8654	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8655	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8656
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8657	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8658	* Writes a single byte to the NVM using the ICH8 flash access registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8659	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8660	* hw - pointer to e1000_hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8661	* index - The index of the byte to read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8662	* data - The byte to write to the NVM.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8663	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8664	static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8665	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8666	s32 status = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8667	u16 word = (u16)data;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8668
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8669	status = e1000_write_ich8_data(hw, index, 1, word);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8670
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8671	return status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8672	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8673
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8674	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8675	* Reads a word from the NVM using the ICH8 flash access registers.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8676	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8677	* hw - pointer to e1000_hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8678	* index - The starting byte index of the word to read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8679	* data - Pointer to a word to store the value read.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8680	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8681	static s32 e1000_read_ich8_word(struct e1000_hw hw, u32 index, u16 data)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8682	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8683	s32 status = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8684	status = e1000_read_ich8_data(hw, index, 2, data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8685	return status;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8686	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8687
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8688	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8689	* Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8690	* based.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8691	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8692	* hw - pointer to e1000_hw structure
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8693	* bank - 0 for first bank, 1 for second bank
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8694	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8695	* Note that this function may actually erase as much as 8 or 64 KBytes. The
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8696	* amount of NVM used in each bank is a minimum of 4 KBytes, but in fact the
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8697	* bank size may be 4, 8 or 64 KBytes
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8698	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8699	static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8700	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8701	union ich8_hws_flash_status hsfsts;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8702	union ich8_hws_flash_ctrl hsflctl;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8703	u32 flash_linear_address;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8704	s32 count = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8705	s32 error = E1000_ERR_EEPROM;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8706	s32 iteration;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8707	s32 sub_sector_size = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8708	s32 bank_size;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8709	s32 j = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8710	s32 error_flag = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8711
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8712	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8713
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8714	/* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8715	/* 00: The Hw sector is 256 bytes, hence we need to erase 16
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8716	* consecutive sectors. The start index for the nth Hw sector can be
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8717	* calculated as bank * 4096 + n * 256
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8718	* 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8719	* The start index for the nth Hw sector can be calculated
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8720	* as bank * 4096
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8721	* 10: The HW sector is 8K bytes
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8722	* 11: The Hw sector size is 64K bytes */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8723	if (hsfsts.hsf_status.berasesz == 0x0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8724	/* Hw sector size 256 */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8725	sub_sector_size = ICH_FLASH_SEG_SIZE_256;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8726	bank_size = ICH_FLASH_SECTOR_SIZE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8727	iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8728	} else if (hsfsts.hsf_status.berasesz == 0x1) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8729	bank_size = ICH_FLASH_SEG_SIZE_4K;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8730	iteration = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8731	} else if (hsfsts.hsf_status.berasesz == 0x3) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8732	bank_size = ICH_FLASH_SEG_SIZE_64K;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8733	iteration = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8734	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8735	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8736	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8737
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8738	for (j = 0; j < iteration ; j++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8739	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8740	count++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8741	/* Steps */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8742	error = e1000_ich8_cycle_init(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8743	if (error != E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8744	error_flag = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8745	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8746	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8747
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8748	/* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8749	* Control */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8750	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8751	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8752	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8753
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8754	/* Write the last 24 bits of an index within the block into Flash
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8755	* Linear address field in Flash Address. This probably needs to
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8756	* be calculated here based off the on-chip erase sector size and
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8757	* the software bank size (4, 8 or 64 KBytes) */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8758	flash_linear_address = bank * bank_size + j * sub_sector_size;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8759	flash_linear_address += hw->flash_base_addr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8760	flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8761
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8762	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8763
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8764	error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8765	/* Check if FCERR is set to 1. If 1, clear it and try the whole
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8766	* sequence a few more times else Done */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8767	if (error == E1000_SUCCESS) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8768	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8769	} else {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8770	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8771	if (hsfsts.hsf_status.flcerr == 1) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8772	/* repeat for some time before giving up */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8773	continue;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8774	} else if (hsfsts.hsf_status.flcdone == 0) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8775	error_flag = 1;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8776	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8777	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8778	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8779	} while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8780	if (error_flag == 1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8781	break;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8782	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8783	if (error_flag != 1)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8784	error = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8785	return error;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8786	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8787
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8788	static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8789	u32 cnf_base_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8790	u32 cnf_size)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8791	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8792	u32 ret_val = E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8793	u16 word_addr, reg_data, reg_addr;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8794	u16 i;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8795
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8796	/* cnf_base_addr is in DWORD */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8797	word_addr = (u16)(cnf_base_addr << 1);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8798
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8799	/* cnf_size is returned in size of dwords */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8800	for (i = 0; i < cnf_size; i++) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8801	ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8802	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8803	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8804
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8805	ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8806	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8807	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8808
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8809	ret_val = e1000_get_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8810	if (ret_val != E1000_SUCCESS)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8811	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8812
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8813	ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8814
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8815	e1000_release_software_flag(hw);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8816	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8817
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8818	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8819	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8820
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8821
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8822	/******************************************************************************
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8823	* This function initializes the PHY from the NVM on ICH8 platforms. This
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8824	* is needed due to an issue where the NVM configuration is not properly
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8825	* autoloaded after power transitions. Therefore, after each PHY reset, we
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8826	* will load the configuration data out of the NVM manually.
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8827	*
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8828	* hw: Struct containing variables accessed by shared code
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8829	*****************************************************************************/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8830	static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8831	{
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8832	u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8833
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8834	if (hw->phy_type != e1000_phy_igp_3)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8835	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8836
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8837	/* Check if SW needs configure the PHY */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8838	reg_data = er32(FEXTNVM);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8839	if (!(reg_data & FEXTNVM_SW_CONFIG))
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8840	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8841
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8842	/* Wait for basic configuration completes before proceeding*/
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8843	loop = 0;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8844	do {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8845	reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8846	udelay(100);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8847	loop++;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8848	} while ((!reg_data) && (loop < 50));
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8849
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8850	/* Clear the Init Done bit for the next init event */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8851	reg_data = er32(STATUS);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8852	reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8853	ew32(STATUS, reg_data);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8854
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8855	/* Make sure HW does not configure LCD from PHY extended configuration
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8856	before SW configuration */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8857	reg_data = er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8858	if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8859	reg_data = er32(EXTCNF_SIZE);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8860	cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8861	cnf_size >>= 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8862	if (cnf_size) {
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8863	reg_data = er32(EXTCNF_CTRL);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8864	cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8865	/* cnf_base_addr is in DWORD */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8866	cnf_base_addr >>= 16;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8867
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8868	/* Configure LCD from extended configuration region. */
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8869	ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8870	cnf_size);
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8871	if (ret_val)
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8872	return ret_val;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8873	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8874	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8875
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8876	return E1000_SUCCESS;
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8877	}
7c5dded8e576 Added e1000 port for 2.6.31 Christoph Mathys <ch1010832@ch10pc602> parents: diff changeset	8878

author	Florian Pose <fp@igh-essen.com>
	Thu, 06 Sep 2012 14:47:42 +0200
branch	redundancy
changeset 2418	8cbb68315d29
parent 2313	7c5dded8e576
permissions	-rw-r--r--