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/******************************************************************************

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 *

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 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

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 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; either version 2 of the

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 *  License, or (at your option) any later version.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

    15

 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License

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 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  The right to use EtherCAT Technology is granted and comes free of

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 *  charge under condition of compatibility of product made by

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 *  Licensee. People intending to distribute/sell products based on the

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 *  code, have to sign an agreement to guarantee that products using

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 *  software based on IgH EtherCAT master stay compatible with the actual

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 *  EtherCAT specification (which are released themselves as an open

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 *  standard) as the (only) precondition to have the right to use EtherCAT

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 *  Technology, IP and trade marks.

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 *

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 *****************************************************************************/

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    34

/**

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   \file

    36

   EtherCAT driver for RTL8139-compatible NICs.

    37

*/

    38

    39

/*****************************************************************************/

    40

    41

/*

    42

  Former documentation:

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    44

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45

    46

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    48

    49

	Much code comes from Donald Becker's rtl8139.c driver,

    50

	versions 1.13 and older.  This driver was originally based

    51

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52

    53

	-----<snip>-----

    54

    55

        	Written 1997-2001 by Donald Becker.

    56

		This software may be used and distributed according to the

    57

		terms of the GNU General Public License (GPL), incorporated

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		herein by reference.  Drivers based on or derived from this

    59

		code fall under the GPL and must retain the authorship,

    60

		copyright and license notice.  This file is not a complete

    61

		program and may only be used when the entire operating

    62

		system is licensed under the GPL.

    63

    64

		This driver is for boards based on the RTL8129 and RTL8139

    65

		PCI ethernet chips.

    66

    67

		The author may be reached as becker@scyld.com, or C/O Scyld

    68

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

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		MD 21403

    70

    71

		Support and updates available at

    72

		http://www.scyld.com/network/rtl8139.html

    73

    74

		Twister-tuning table provided by Kinston

    75

		<shangh@realtek.com.tw>.

    76

    77

	-----<snip>-----

    78

    79

	This software may be used and distributed according to the terms

    80

	of the GNU General Public License, incorporated herein by reference.

    81

    82

	Contributors:

    83

    84

		Donald Becker - he wrote the original driver, kudos to him!

    85

		(but please don't e-mail him for support, this isn't his driver)

    86

    87

		Tigran Aivazian - bug fixes, skbuff free cleanup

    88

    89

		Martin Mares - suggestions for PCI cleanup

    90

    91

		David S. Miller - PCI DMA and softnet updates

    92

    93

		Ernst Gill - fixes ported from BSD driver

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    95

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

    97

    98

		Gerard Sharp - bug fix, testing and feedback

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   100

		David Ford - Rx ring wrap fix

   101

   102

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103

		to find and fix a crucial bug on older chipsets.

   104

   105

		Donald Becker/Chris Butterworth/Marcus Westergren -

   106

		Noticed various Rx packet size-related buglets.

   107

   108

		Santiago Garcia Mantinan - testing and feedback

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   110

		Jens David - 2.2.x kernel backports

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   112

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

   114

   115

		Jean-Jacques Michel - bug fix

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   117

		Tobias Ringström - Rx interrupt status checking suggestion

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   119

		Andrew Morton - Clear blocked signals, avoid

   120

		buffer overrun setting current->comm.

   121

   122

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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		"rtl8139-diag -mmmaaavvveefN" output

   129

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130

   131

*/

   132

   133

#define DRV_NAME	"ec_8139too"

   134

#define DRV_VERSION	"0.9.27"

   135

   136

   137

#include <linux/config.h>

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

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#include <linux/init.h>

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#include <linux/ioport.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

   146

#include <linux/rtnetlink.h>

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#include <linux/delay.h>

   148

#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/irq.h>

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   156

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   157

   158

#include "../globals.h"

   159

#include "ecdev.h"

   160

   161

#define RTL8139_DRIVER_NAME DRV_NAME \

   162

                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

   164

   165

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   166

   167

#define PFX DRV_NAME ": "

   168

   169

/* Default Message level */

   170

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   171

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   173

   174

   175

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

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#ifdef CONFIG_8139TOO_PIO

   177

#define USE_IO_OPS 1

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#endif

   179

   180

/* define to 1, 2 or 3 to enable copious debugging info */

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#define RTL8139_DEBUG 0

   182

   183

/* define to 1 to disable lightweight runtime debugging checks */

   184

#undef RTL8139_NDEBUG

   185

   186

   187

#if RTL8139_DEBUG

   188

/* note: prints function name for you */

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#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

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#else

   191

#  define DPRINTK(fmt, args...)

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#endif

   193

   194

#ifdef RTL8139_NDEBUG

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#  define assert(expr) do {} while (0)

   196

#else

   197

#  define assert(expr) \

   198

        if(unlikely(!(expr))) {				        \

   199

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

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        }

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#endif

   203

   204

   205

/* A few user-configurable values. */

   206

/* media options */

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#define MAX_UNITS 8

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static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   209

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   210

   211

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   212

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   213

static int multicast_filter_limit = 32;

   214

   215

/* bitmapped message enable number */

   216

static int debug = -1;

   217

   218

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   219

   220

static int ec_device_index = -1;

   221

static int ec_device_master_index = 0;

   222

static ec_device_t *rtl_ec_dev;

   223

struct net_device *rtl_ec_net_dev = NULL;

   224

   225

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   226

   227

/*

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 * Receive ring size 

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 * Warning: 64K ring has hardware issues and may lock up.

   230

 */

   231

#if defined(CONFIG_SH_DREAMCAST)

   232

#define RX_BUF_IDX	1	/* 16K ring */

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#else

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#define RX_BUF_IDX	2	/* 32K ring */

   235

#endif

   236

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   237

#define RX_BUF_PAD	16

   238

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   239

   240

#if RX_BUF_LEN == 65536

   241

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   242

#else

   243

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   244

#endif

   245

   246

/* Number of Tx descriptor registers. */

   247

#define NUM_TX_DESC	4

   248

   249

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   250

#define MAX_ETH_FRAME_SIZE	1536

   251

   252

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   253

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   254

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   255

   256

/* PCI Tuning Parameters

   257

   Threshold is bytes transferred to chip before transmission starts. */

   258

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   259

   260

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   261

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   262

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   263

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   264

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   265

   266

/* Operational parameters that usually are not changed. */

   267

/* Time in jiffies before concluding the transmitter is hung. */

   268

#define TX_TIMEOUT  (6*HZ)

   269

   270

   271

enum {

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	HAS_MII_XCVR = 0x010000,

   273

	HAS_CHIP_XCVR = 0x020000,

   274

	HAS_LNK_CHNG = 0x040000,

   275

};

   276

   277

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   278

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   279

#define RTL_MIN_IO_SIZE 0x80

   280

#define RTL8139B_IO_SIZE 256

   281

   282

#define RTL8129_CAPS	HAS_MII_XCVR

   283

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   284

   285

typedef enum {

   286

	RTL8139 = 0,

   287

	RTL8129,

   288

} board_t;

   289

   290

   291

/* indexed by board_t, above */

   292

static const struct {

   293

	const char *name;

   294

	u32 hw_flags;

   295

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

   297

	{ "RealTek RTL8129", RTL8129_CAPS },

   298

};

   299

   300

   301

static struct pci_device_id rtl8139_pci_tbl[] = {

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	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   309

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   310

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   312

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   313

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   314

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   315

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   316

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   317

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   318

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   319

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   320

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   321

   322

#ifdef CONFIG_SH_SECUREEDGE5410

   323

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   328

#endif

   329

   330

	/* some crazy cards report invalid vendor ids like

   331

	 * 0x0001 here.  The other ids are valid and constant,

   332

	 * so we simply don't match on the main vendor id.

   333

	 */

   334

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   335

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   336

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   337

   338

	{0,}

   339

};

   340

   341

/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   342

   343

/* prevent driver from being loaded automatically */

   344

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   345

   346

/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   347

   348

static struct {

   349

	const char str[ETH_GSTRING_LEN];

   350

} ethtool_stats_keys[] = {

   351

	{ "early_rx" },

   352

	{ "tx_buf_mapped" },

   353

	{ "tx_timeouts" },

   354

	{ "rx_lost_in_ring" },

   355

};

   356

   357

/* The rest of these values should never change. */

   358

   359

/* Symbolic offsets to registers. */

   360

enum RTL8139_registers {

   361

	MAC0 = 0,		/* Ethernet hardware address. */

   362

	MAR0 = 8,		/* Multicast filter. */

   363

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   364

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   365

	RxBuf = 0x30,

   366

	ChipCmd = 0x37,

   367

	RxBufPtr = 0x38,

   368

	RxBufAddr = 0x3A,

   369

	IntrMask = 0x3C,

   370

	IntrStatus = 0x3E,

   371

	TxConfig = 0x40,

   372

	RxConfig = 0x44,

   373

	Timer = 0x48,		/* A general-purpose counter. */

   374

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   375

	Cfg9346 = 0x50,

   376

	Config0 = 0x51,

   377

	Config1 = 0x52,

   378

	FlashReg = 0x54,

   379

	MediaStatus = 0x58,

   380

	Config3 = 0x59,

   381

	Config4 = 0x5A,		/* absent on RTL-8139A */

   382

	HltClk = 0x5B,

   383

	MultiIntr = 0x5C,

   384

	TxSummary = 0x60,

   385

	BasicModeCtrl = 0x62,

   386

	BasicModeStatus = 0x64,

   387

	NWayAdvert = 0x66,

   388

	NWayLPAR = 0x68,

   389

	NWayExpansion = 0x6A,

   390

	/* Undocumented registers, but required for proper operation. */

   391

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   392

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   393

	PARA78 = 0x78,

   394

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   395

	Config5 = 0xD8,		/* absent on RTL-8139A */

   396

};

   397

   398

enum ClearBitMasks {

   399

	MultiIntrClear = 0xF000,

   400

	ChipCmdClear = 0xE2,

   401

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   402

};

   403

   404

enum ChipCmdBits {

   405

	CmdReset = 0x10,

   406

	CmdRxEnb = 0x08,

   407

	CmdTxEnb = 0x04,

   408

	RxBufEmpty = 0x01,

   409

};

   410

   411

/* Interrupt register bits, using my own meaningful names. */

   412

enum IntrStatusBits {

   413

	PCIErr = 0x8000,

   414

	PCSTimeout = 0x4000,

   415

	RxFIFOOver = 0x40,

   416

	RxUnderrun = 0x20,

   417

	RxOverflow = 0x10,

   418

	TxErr = 0x08,

   419

	TxOK = 0x04,

   420

	RxErr = 0x02,

   421

	RxOK = 0x01,

   422

   423

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   424

};

   425

   426

enum TxStatusBits {

   427

	TxHostOwns = 0x2000,

   428

	TxUnderrun = 0x4000,

   429

	TxStatOK = 0x8000,

   430

	TxOutOfWindow = 0x20000000,

   431

	TxAborted = 0x40000000,

   432

	TxCarrierLost = 0x80000000,

   433

};

   434

enum RxStatusBits {

   435

	RxMulticast = 0x8000,

   436

	RxPhysical = 0x4000,

   437

	RxBroadcast = 0x2000,

   438

	RxBadSymbol = 0x0020,

   439

	RxRunt = 0x0010,

   440

	RxTooLong = 0x0008,

   441

	RxCRCErr = 0x0004,

   442

	RxBadAlign = 0x0002,

   443

	RxStatusOK = 0x0001,

   444

};

   445

   446

/* Bits in RxConfig. */

   447

enum rx_mode_bits {

   448

	AcceptErr = 0x20,

   449

	AcceptRunt = 0x10,

   450

	AcceptBroadcast = 0x08,

   451

	AcceptMulticast = 0x04,

   452

	AcceptMyPhys = 0x02,

   453

	AcceptAllPhys = 0x01,

   454

};

   455

   456

/* Bits in TxConfig. */

   457

enum tx_config_bits {

   458

   459

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   460

        TxIFGShift = 24,

   461

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   462

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   463

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   464

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   465

   466

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   467

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   468

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   469

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   470

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   471

   472

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   473

};

   474

   475

/* Bits in Config1 */

   476

enum Config1Bits {

   477

	Cfg1_PM_Enable = 0x01,

   478

	Cfg1_VPD_Enable = 0x02,

   479

	Cfg1_PIO = 0x04,

   480

	Cfg1_MMIO = 0x08,

   481

	LWAKE = 0x10,		/* not on 8139, 8139A */

   482

	Cfg1_Driver_Load = 0x20,

   483

	Cfg1_LED0 = 0x40,

   484

	Cfg1_LED1 = 0x80,

   485

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   486

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   487

};

   488

   489

/* Bits in Config3 */

   490

enum Config3Bits {

   491

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   492

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   493

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   494

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   495

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   496

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   497

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   498

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   499

};

   500

   501

/* Bits in Config4 */

   502

enum Config4Bits {

   503

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   504

};

   505

   506

/* Bits in Config5 */

   507

enum Config5Bits {

   508

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   509

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   510

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   511

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   512

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   513

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   514

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   515

};

   516

   517

enum RxConfigBits {

   518

	/* rx fifo threshold */

   519

	RxCfgFIFOShift = 13,

   520

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   521

   522

	/* Max DMA burst */

   523

	RxCfgDMAShift = 8,

   524

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   525

   526

	/* rx ring buffer length */

   527

	RxCfgRcv8K = 0,

   528

	RxCfgRcv16K = (1 << 11),

   529

	RxCfgRcv32K = (1 << 12),