1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 */

    10

    11

#include <linux/module.h>

    12

#include <linux/moduleparam.h>

    13

#include <linux/pci.h>

    14

#include <linux/netdevice.h>

    15

#include <linux/etherdevice.h>

    16

#include <linux/delay.h>

    17

#include <linux/ethtool.h>

    18

#include <linux/mii.h>

    19

#include <linux/if_vlan.h>

    20

#include <linux/crc32.h>

    21

#include <linux/in.h>

    22

#include <linux/ip.h>

    23

#include <linux/tcp.h>

    24

#include <linux/init.h>

    25

#include <linux/dma-mapping.h>

    26

    27

#include <asm/system.h>

    28

#include <asm/io.h>

    29

#include <asm/irq.h>

    30

    31

#define RTL8169_VERSION "2.3LK-NAPI"

    32

#define MODULENAME "r8169"

    33

#define PFX MODULENAME ": "

    34

    35

#ifdef RTL8169_DEBUG

    36

#define assert(expr) \

    37

	if (!(expr)) {					\

    38

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    39

		#expr,__FILE__,__func__,__LINE__);		\

    40

	}

    41

#define dprintk(fmt, args...) \

    42

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    43

#else

    44

#define assert(expr) do {} while (0)

    45

#define dprintk(fmt, args...)	do {} while (0)

    46

#endif /* RTL8169_DEBUG */

    47

    48

#define R8169_MSG_DEFAULT \

    49

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    50

    51

#define TX_BUFFS_AVAIL(tp) \

    52

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    53

    54

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    55

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    56

static const int multicast_filter_limit = 32;

    57

    58

/* MAC address length */

    59

#define MAC_ADDR_LEN	6

    60

    61

#define MAX_READ_REQUEST_SHIFT	12

    62

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

    63

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    64

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    65

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

    66

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    67

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    68

    69

#define R8169_REGS_SIZE		256

    70

#define R8169_NAPI_WEIGHT	64

    71

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    72

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    73

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    74

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    75

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    76

    77

#define RTL8169_TX_TIMEOUT	(6*HZ)

    78

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    79

    80

#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)

    81

#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)

    82

#define RTL_EEPROM_SIG_ADDR	0x0000

    83

    84

/* write/read MMIO register */

    85

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

    86

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

    87

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

    88

#define RTL_R8(reg)		readb (ioaddr + (reg))

    89

#define RTL_R16(reg)		readw (ioaddr + (reg))

    90

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

    91

    92

enum mac_version {

    93

	RTL_GIGA_MAC_NONE   = 0x00,

    94

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

    95

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

    96

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

    97

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

    98

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

    99

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

   100

	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e

   101

	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e

   102

	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e

   103

	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e

   104

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   105

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be

   106

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb

   107

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?

   108

	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?

   109

	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec

   110

	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf

   111

	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP

   112

	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C

   113

	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C

   114

	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C

   115

	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C

   116

	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP

   117

	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP

   118

	RTL_GIGA_MAC_VER_25 = 0x19, // 8168D

   119

	RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D

   120

	RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP

   121

};

   122

   123

#define _R(NAME,MAC,MASK) \

   124

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   125

   126

static const struct {

   127

	const char *name;

   128

	u8 mac_version;

   129

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   130

} rtl_chip_info[] = {

   131

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   132

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   133

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   134

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   135

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   136

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   137

	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E

   138

	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E

   139

	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E

   140

	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E

   141

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   142

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   143

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   144

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   145

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139

   146

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E

   147

	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E

   148

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E

   149

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E

   150

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E

   151

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E

   152

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E

   153

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E

   154

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E

   155

	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E

   156

	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E

   157

	_R("RTL8168dp/8111dp",	RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E

   158

};

   159

#undef _R

   160

   161

enum cfg_version {

   162

	RTL_CFG_0 = 0x00,

   163

	RTL_CFG_1,

   164

	RTL_CFG_2

   165

};

   166

   167

static void rtl_hw_start_8169(struct net_device *);

   168

static void rtl_hw_start_8168(struct net_device *);

   169

static void rtl_hw_start_8101(struct net_device *);

   170

   171

static struct pci_device_id rtl8169_pci_tbl[] = {

   172

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   173

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   174

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   175

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   176

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   177

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   178

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   179

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   180

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   181

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   182

	{ 0x0001,				0x8168,

   183

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   184

	{0,},

   185

};

   186

   187

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   188

   189

static int rx_copybreak = 200;

   190

static int use_dac;

   191

static struct {

   192

	u32 msg_enable;

   193

} debug = { -1 };

   194

   195

enum rtl_registers {

   196

	MAC0		= 0,	/* Ethernet hardware address. */

   197

	MAC4		= 4,

   198

	MAR0		= 8,	/* Multicast filter. */

   199

	CounterAddrLow		= 0x10,

   200

	CounterAddrHigh		= 0x14,

   201

	TxDescStartAddrLow	= 0x20,

   202

	TxDescStartAddrHigh	= 0x24,

   203

	TxHDescStartAddrLow	= 0x28,

   204

	TxHDescStartAddrHigh	= 0x2c,

   205

	FLASH		= 0x30,

   206

	ERSR		= 0x36,

   207

	ChipCmd		= 0x37,

   208

	TxPoll		= 0x38,

   209

	IntrMask	= 0x3c,

   210

	IntrStatus	= 0x3e,

   211

	TxConfig	= 0x40,

   212

	RxConfig	= 0x44,

   213

	RxMissed	= 0x4c,

   214

	Cfg9346		= 0x50,

   215

	Config0		= 0x51,

   216

	Config1		= 0x52,

   217

	Config2		= 0x53,

   218

	Config3		= 0x54,

   219

	Config4		= 0x55,

   220

	Config5		= 0x56,

   221

	MultiIntr	= 0x5c,

   222

	PHYAR		= 0x60,

   223

	PHYstatus	= 0x6c,

   224

	RxMaxSize	= 0xda,

   225

	CPlusCmd	= 0xe0,

   226

	IntrMitigate	= 0xe2,

   227

	RxDescAddrLow	= 0xe4,

   228

	RxDescAddrHigh	= 0xe8,

   229

	EarlyTxThres	= 0xec,

   230

	FuncEvent	= 0xf0,

   231

	FuncEventMask	= 0xf4,

   232

	FuncPresetState	= 0xf8,

   233

	FuncForceEvent	= 0xfc,

   234

};

   235

   236

enum rtl8110_registers {

   237

	TBICSR			= 0x64,

   238

	TBI_ANAR		= 0x68,

   239

	TBI_LPAR		= 0x6a,

   240

};

   241

   242

enum rtl8168_8101_registers {

   243

	CSIDR			= 0x64,

   244

	CSIAR			= 0x68,

   245

#define	CSIAR_FLAG			0x80000000

   246

#define	CSIAR_WRITE_CMD			0x80000000

   247

#define	CSIAR_BYTE_ENABLE		0x0f

   248

#define	CSIAR_BYTE_ENABLE_SHIFT		12

   249

#define	CSIAR_ADDR_MASK			0x0fff

   250

   251

	EPHYAR			= 0x80,

   252

#define	EPHYAR_FLAG			0x80000000

   253

#define	EPHYAR_WRITE_CMD		0x80000000

   254

#define	EPHYAR_REG_MASK			0x1f

   255

#define	EPHYAR_REG_SHIFT		16

   256

#define	EPHYAR_DATA_MASK		0xffff

   257

	DBG_REG			= 0xd1,

   258

#define	FIX_NAK_1			(1 << 4)

   259

#define	FIX_NAK_2			(1 << 3)

   260

	EFUSEAR			= 0xdc,

   261

#define	EFUSEAR_FLAG			0x80000000

   262

#define	EFUSEAR_WRITE_CMD		0x80000000

   263

#define	EFUSEAR_READ_CMD		0x00000000

   264

#define	EFUSEAR_REG_MASK		0x03ff

   265

#define	EFUSEAR_REG_SHIFT		8

   266

#define	EFUSEAR_DATA_MASK		0xff

   267

};

   268

   269

enum rtl_register_content {

   270

	/* InterruptStatusBits */

   271

	SYSErr		= 0x8000,

   272

	PCSTimeout	= 0x4000,

   273

	SWInt		= 0x0100,

   274

	TxDescUnavail	= 0x0080,

   275

	RxFIFOOver	= 0x0040,

   276

	LinkChg		= 0x0020,

   277

	RxOverflow	= 0x0010,

   278

	TxErr		= 0x0008,

   279

	TxOK		= 0x0004,

   280

	RxErr		= 0x0002,

   281

	RxOK		= 0x0001,

   282

   283

	/* RxStatusDesc */

   284

	RxFOVF	= (1 << 23),

   285

	RxRWT	= (1 << 22),

   286

	RxRES	= (1 << 21),

   287

	RxRUNT	= (1 << 20),

   288

	RxCRC	= (1 << 19),

   289

   290

	/* ChipCmdBits */

   291

	CmdReset	= 0x10,

   292

	CmdRxEnb	= 0x08,

   293

	CmdTxEnb	= 0x04,

   294

	RxBufEmpty	= 0x01,

   295

   296

	/* TXPoll register p.5 */

   297

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   298

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   299

	FSWInt		= 0x01,		/* Forced software interrupt */

   300

   301

	/* Cfg9346Bits */

   302

	Cfg9346_Lock	= 0x00,

   303

	Cfg9346_Unlock	= 0xc0,

   304

   305

	/* rx_mode_bits */

   306

	AcceptErr	= 0x20,

   307

	AcceptRunt	= 0x10,

   308

	AcceptBroadcast	= 0x08,

   309

	AcceptMulticast	= 0x04,

   310

	AcceptMyPhys	= 0x02,

   311

	AcceptAllPhys	= 0x01,

   312

   313

	/* RxConfigBits */

   314

	RxCfgFIFOShift	= 13,

   315

	RxCfgDMAShift	=  8,

   316

   317

	/* TxConfigBits */

   318

	TxInterFrameGapShift = 24,

   319

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   320

   321

	/* Config1 register p.24 */

   322

	LEDS1		= (1 << 7),

   323

	LEDS0		= (1 << 6),

   324

	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */

   325

	Speed_down	= (1 << 4),

   326

	MEMMAP		= (1 << 3),

   327

	IOMAP		= (1 << 2),

   328

	VPD		= (1 << 1),

   329

	PMEnable	= (1 << 0),	/* Power Management Enable */

   330

   331

	/* Config2 register p. 25 */

   332

	PCI_Clock_66MHz = 0x01,

   333

	PCI_Clock_33MHz = 0x00,

   334

   335

	/* Config3 register p.25 */

   336

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   337

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   338

	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */

   339

   340

	/* Config5 register p.27 */

   341

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   342

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   343

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   344

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   345

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   346

   347

	/* TBICSR p.28 */

   348

	TBIReset	= 0x80000000,

   349

	TBILoopback	= 0x40000000,

   350

	TBINwEnable	= 0x20000000,

   351

	TBINwRestart	= 0x10000000,

   352

	TBILinkOk	= 0x02000000,

   353

	TBINwComplete	= 0x01000000,

   354

   355

	/* CPlusCmd p.31 */

   356

	EnableBist	= (1 << 15),	// 8168 8101

   357

	Mac_dbgo_oe	= (1 << 14),	// 8168 8101

   358

	Normal_mode	= (1 << 13),	// unused

   359

	Force_half_dup	= (1 << 12),	// 8168 8101

   360

	Force_rxflow_en	= (1 << 11),	// 8168 8101

   361

	Force_txflow_en	= (1 << 10),	// 8168 8101

   362

	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101

   363

	ASF		= (1 << 8),	// 8168 8101

   364

	PktCntrDisable	= (1 << 7),	// 8168 8101

   365

	Mac_dbgo_sel	= 0x001c,	// 8168

   366

	RxVlan		= (1 << 6),

   367

	RxChkSum	= (1 << 5),

   368

	PCIDAC		= (1 << 4),

   369

	PCIMulRW	= (1 << 3),

   370

	INTT_0		= 0x0000,	// 8168

   371

	INTT_1		= 0x0001,	// 8168

   372

	INTT_2		= 0x0002,	// 8168

   373

	INTT_3		= 0x0003,	// 8168

   374

   375

	/* rtl8169_PHYstatus */

   376

	TBI_Enable	= 0x80,

   377

	TxFlowCtrl	= 0x40,

   378

	RxFlowCtrl	= 0x20,

   379

	_1000bpsF	= 0x10,

   380

	_100bps		= 0x08,

   381

	_10bps		= 0x04,

   382

	LinkStatus	= 0x02,

   383

	FullDup		= 0x01,

   384

   385

	/* _TBICSRBit */

   386

	TBILinkOK	= 0x02000000,

   387

   388

	/* DumpCounterCommand */

   389

	CounterDump	= 0x8,

   390

};

   391

   392

enum desc_status_bit {

   393

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   394

	RingEnd		= (1 << 30), /* End of descriptor ring */

   395

	FirstFrag	= (1 << 29), /* First segment of a packet */

   396

	LastFrag	= (1 << 28), /* Final segment of a packet */

   397

   398

	/* Tx private */

   399

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   400

	MSSShift	= 16,        /* MSS value position */

   401

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   402

	IPCS		= (1 << 18), /* Calculate IP checksum */

   403

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   404

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   405

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   406

   407

	/* Rx private */

   408

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   409

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   410

   411

#define RxProtoUDP	(PID1)

   412

#define RxProtoTCP	(PID0)

   413

#define RxProtoIP	(PID1 | PID0)

   414

#define RxProtoMask	RxProtoIP

   415

   416

	IPFail		= (1 << 16), /* IP checksum failed */

   417

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   418

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   419

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   420

};

   421

   422

#define RsvdMask	0x3fffc000

   423

   424

struct TxDesc {

   425

	__le32 opts1;

   426

	__le32 opts2;

   427

	__le64 addr;

   428

};

   429

   430

struct RxDesc {

   431

	__le32 opts1;

   432

	__le32 opts2;

   433

	__le64 addr;

   434

};

   435

   436

struct ring_info {

   437

	struct sk_buff	*skb;

   438

	u32		len;

   439

	u8		__pad[sizeof(void *) - sizeof(u32)];

   440

};

   441

   442

enum features {

   443

	RTL_FEATURE_WOL		= (1 << 0),

   444

	RTL_FEATURE_MSI		= (1 << 1),

   445

	RTL_FEATURE_GMII	= (1 << 2),

   446

};

   447

   448

struct rtl8169_counters {

   449

	__le64	tx_packets;

   450

	__le64	rx_packets;

   451

	__le64	tx_errors;

   452

	__le32	rx_errors;

   453

	__le16	rx_missed;

   454

	__le16	align_errors;

   455

	__le32	tx_one_collision;

   456

	__le32	tx_multi_collision;

   457

	__le64	rx_unicast;

   458

	__le64	rx_broadcast;

   459

	__le32	rx_multicast;

   460

	__le16	tx_aborted;

   461

	__le16	tx_underun;

   462

};

   463

   464

struct rtl8169_private {

   465

	void __iomem *mmio_addr;	/* memory map physical address */

   466

	struct pci_dev *pci_dev;	/* Index of PCI device */

   467

	struct net_device *dev;

   468

	struct napi_struct napi;

   469

	spinlock_t lock;		/* spin lock flag */

   470

	u32 msg_enable;

   471

	int chipset;

   472

	int mac_version;

   473

	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   474

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   475

	u32 dirty_rx;

   476

	u32 dirty_tx;

   477

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   478

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   479

	dma_addr_t TxPhyAddr;

   480

	dma_addr_t RxPhyAddr;

   481

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   482

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

   483

	unsigned align;

   484

	unsigned rx_buf_sz;

   485

	struct timer_list timer;

   486

	u16 cp_cmd;

   487

	u16 intr_event;

   488

	u16 napi_event;

   489

	u16 intr_mask;

   490

	int phy_1000_ctrl_reg;

   491

#ifdef CONFIG_R8169_VLAN

   492

	struct vlan_group *vlgrp;

   493

#endif

   494

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   495

	int (*get_settings)(struct net_device *, struct ethtool_cmd *);

   496

	void (*phy_reset_enable)(void __iomem *);

   497

	void (*hw_start)(struct net_device *);

   498

	unsigned int (*phy_reset_pending)(void __iomem *);

   499

	unsigned int (*link_ok)(void __iomem *);

   500

	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);

   501

	int pcie_cap;

   502

	struct delayed_work task;

   503

	unsigned features;

   504

   505

	struct mii_if_info mii;

   506

	struct rtl8169_counters counters;

   507

};

   508

   509

MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");

   510

MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");

   511

module_param(rx_copybreak, int, 0);

   512

MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

   513

module_param(use_dac, int, 0);

   514

MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

   515

module_param_named(debug, debug.msg_enable, int, 0);

   516

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   517

MODULE_LICENSE("GPL");

   518

MODULE_VERSION(RTL8169_VERSION);

   519

   520

static int rtl8169_open(struct net_device *dev);

   521

static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,

   522

				      struct net_device *dev);

   523

static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);

   524

static int rtl8169_init_ring(struct net_device *dev);

   525

static void rtl_hw_start(struct net_device *dev);

   526

static int rtl8169_close(struct net_device *dev);

   527

static void rtl_set_rx_mode(struct net_device *dev);

   528

static void rtl8169_tx_timeout(struct net_device *dev);

   529

static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);

   530

static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,