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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2012 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

    28

    29

/* 80003ES2LAN Gigabit Ethernet Controller (Copper)

    30

 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    31

 */

    32

    33

#include "e1000.h"

    34

    35

#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00

    36

#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02

    37

#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10

    38

#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F

    39

    40

#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008

    41

#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800

    42

#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010

    43

    44

#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

    45

#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000

    46

#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000

    47

    48

#define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C

    49

#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004

    50

    51

#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

    52

#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000

    53

    54

#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8

    55

#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9

    56

    57

/* GG82563 PHY Specific Status Register (Page 0, Register 16 */

    58

#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */

    59

#define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060

    60

#define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */

    61

#define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */

    62

#define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */

    63

    64

/* PHY Specific Control Register 2 (Page 0, Register 26) */

    65

#define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000

    66

						/* 1=Reverse Auto-Negotiation */

    67

    68

/* MAC Specific Control Register (Page 2, Register 21) */

    69

/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

    70

#define GG82563_MSCR_TX_CLK_MASK		 0x0007

    71

#define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004

    72

#define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005

    73

#define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007

    74

    75

#define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */

    76

    77

/* DSP Distance Register (Page 5, Register 26) */

    78

#define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M

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							   1 = 50-80M

    80

							   2 = 80-110M

    81

							   3 = 110-140M

    82

							   4 = >140M

    83

							*/

    84

    85

/* Kumeran Mode Control Register (Page 193, Register 16) */

    86

#define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800

    87

    88

/* Max number of times Kumeran read/write should be validated */

    89

#define GG82563_MAX_KMRN_RETRY  0x5

    90

    91

/* Power Management Control Register (Page 193, Register 20) */

    92

#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001

    93

					   /* 1=Enable SERDES Electrical Idle */

    94

    95

/* In-Band Control Register (Page 194, Register 18) */

    96

#define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */

    97

    98

/* A table for the GG82563 cable length where the range is defined

    99

 * with a lower bound at "index" and the upper bound at

   100

 * "index + 5".

   101

 */

   102

static const u16 e1000_gg82563_cable_length_table[] = {

   103

	 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };

   104

#define GG82563_CABLE_LENGTH_TABLE_SIZE \

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		ARRAY_SIZE(e1000_gg82563_cable_length_table)

   106

   107

static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

   108

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   109

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   110

static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

   111

static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

   112

static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

   113

static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

   114

static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);

   115

static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   116

                                            u16 *data);

   117

static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   118

                                             u16 data);

   119

static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);

   120

   121

/**

   122

 *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

   123

 *  @hw: pointer to the HW structure

   124

 **/

   125

static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

   126

{

   127

	struct e1000_phy_info *phy = &hw->phy;

   128

	s32 ret_val;

   129

   130

	if (hw->phy.media_type != e1000_media_type_copper) {

   131

		phy->type	= e1000_phy_none;

   132

		return 0;

   133

	} else {

   134

		phy->ops.power_up = e1000_power_up_phy_copper;

   135

		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

   136

	}

   137

   138

	phy->addr		= 1;

   139

	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

   140

	phy->reset_delay_us      = 100;

   141

	phy->type		= e1000_phy_gg82563;

   142

   143

	/* This can only be done after all function pointers are setup. */

   144

	ret_val = e1000e_get_phy_id(hw);

   145

   146

	/* Verify phy id */

   147

	if (phy->id != GG82563_E_PHY_ID)

   148

		return -E1000_ERR_PHY;

   149

   150

	return ret_val;

   151

}

   152

   153

/**

   154

 *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

   155

 *  @hw: pointer to the HW structure

   156

 **/

   157

static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

   158

{

   159

	struct e1000_nvm_info *nvm = &hw->nvm;

   160

	u32 eecd = er32(EECD);

   161

	u16 size;

   162

   163

	nvm->opcode_bits	= 8;

   164

	nvm->delay_usec	 = 1;

   165

	switch (nvm->override) {

   166

	case e1000_nvm_override_spi_large:

   167

		nvm->page_size    = 32;

   168

		nvm->address_bits = 16;

   169

		break;

   170

	case e1000_nvm_override_spi_small:

   171

		nvm->page_size    = 8;

   172

		nvm->address_bits = 8;

   173

		break;

   174

	default:

   175

		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   176

		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   177

		break;

   178

	}

   179

   180

	nvm->type = e1000_nvm_eeprom_spi;

   181

   182

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   183

			  E1000_EECD_SIZE_EX_SHIFT);

   184

   185

	/* Added to a constant, "size" becomes the left-shift value

   186

	 * for setting word_size.

   187

	 */

   188

	size += NVM_WORD_SIZE_BASE_SHIFT;

   189

   190

	/* EEPROM access above 16k is unsupported */

   191

	if (size > 14)

   192

		size = 14;

   193

	nvm->word_size	= 1 << size;

   194

   195

	return 0;

   196

}

   197

   198

/**

   199

 *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   200

 *  @hw: pointer to the HW structure

   201

 **/

   202

static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)

   203

{

   204

	struct e1000_mac_info *mac = &hw->mac;

   205

   206

	/* Set media type and media-dependent function pointers */

   207

	switch (hw->adapter->pdev->device) {

   208

	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   209

		hw->phy.media_type = e1000_media_type_internal_serdes;

   210

		mac->ops.check_for_link = e1000e_check_for_serdes_link;

   211

		mac->ops.setup_physical_interface =

   212

		    e1000e_setup_fiber_serdes_link;

   213

		break;

   214

	default:

   215

		hw->phy.media_type = e1000_media_type_copper;

   216

		mac->ops.check_for_link = e1000e_check_for_copper_link;

   217

		mac->ops.setup_physical_interface =

   218

		    e1000_setup_copper_link_80003es2lan;

   219

		break;

   220

	}

   221

   222

	/* Set mta register count */

   223

	mac->mta_reg_count = 128;

   224

	/* Set rar entry count */

   225

	mac->rar_entry_count = E1000_RAR_ENTRIES;

   226

	/* FWSM register */

   227

	mac->has_fwsm = true;

   228

	/* ARC supported; valid only if manageability features are enabled. */

   229

	mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);

   230

	/* Adaptive IFS not supported */

   231

	mac->adaptive_ifs = false;

   232

   233

	/* set lan id for port to determine which phy lock to use */

   234

	hw->mac.ops.set_lan_id(hw);

   235

   236

	return 0;

   237

}

   238

   239

static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   240

{

   241

	struct e1000_hw *hw = &adapter->hw;

   242

	s32 rc;

   243

   244

	rc = e1000_init_mac_params_80003es2lan(hw);

   245

	if (rc)

   246

		return rc;

   247

   248

	rc = e1000_init_nvm_params_80003es2lan(hw);

   249

	if (rc)

   250

		return rc;

   251

   252

	rc = e1000_init_phy_params_80003es2lan(hw);

   253

	if (rc)

   254

		return rc;

   255

   256

	return 0;

   257

}

   258

   259

/**

   260

 *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   261

 *  @hw: pointer to the HW structure

   262

 *

   263

 *  A wrapper to acquire access rights to the correct PHY.

   264

 **/

   265

static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   266

{

   267

	u16 mask;

   268

   269

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   270

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   271

}

   272

   273

/**

   274

 *  e1000_release_phy_80003es2lan - Release rights to access PHY

   275

 *  @hw: pointer to the HW structure

   276

 *

   277

 *  A wrapper to release access rights to the correct PHY.

   278

 **/

   279

static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   280

{

   281

	u16 mask;

   282

   283

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   284

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   285

}

   286

   287

/**

   288

 *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register

   289

 *  @hw: pointer to the HW structure

   290

 *

   291

 *  Acquire the semaphore to access the Kumeran interface.

   292

 *

   293

 **/

   294

static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   295

{

   296

	u16 mask;

   297

   298

	mask = E1000_SWFW_CSR_SM;

   299

   300

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   301

}

   302

   303

/**

   304

 *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register

   305

 *  @hw: pointer to the HW structure

   306

 *

   307

 *  Release the semaphore used to access the Kumeran interface

   308

 **/

   309

static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   310

{

   311

	u16 mask;

   312

   313

	mask = E1000_SWFW_CSR_SM;

   314

   315

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   316

}

   317

   318

/**

   319

 *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   320

 *  @hw: pointer to the HW structure

   321

 *

   322

 *  Acquire the semaphore to access the EEPROM.

   323

 **/

   324

static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   325

{

   326

	s32 ret_val;

   327

   328

	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   329

	if (ret_val)

   330

		return ret_val;

   331

   332

	ret_val = e1000e_acquire_nvm(hw);

   333

   334

	if (ret_val)

   335

		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   336

   337

	return ret_val;

   338

}

   339

   340

/**

   341

 *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   342

 *  @hw: pointer to the HW structure

   343

 *

   344

 *  Release the semaphore used to access the EEPROM.

   345

 **/

   346

static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   347

{

   348

	e1000e_release_nvm(hw);

   349

	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   350

}

   351

   352

/**

   353

 *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   354

 *  @hw: pointer to the HW structure

   355

 *  @mask: specifies which semaphore to acquire

   356

 *

   357

 *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   358

 *  will also specify which port we're acquiring the lock for.

   359

 **/

   360

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   361

{

   362

	u32 swfw_sync;

   363

	u32 swmask = mask;

   364

	u32 fwmask = mask << 16;

   365

	s32 i = 0;

   366

	s32 timeout = 50;

   367

   368

	while (i < timeout) {

   369

		if (e1000e_get_hw_semaphore(hw))

   370

			return -E1000_ERR_SWFW_SYNC;

   371

   372

		swfw_sync = er32(SW_FW_SYNC);

   373

		if (!(swfw_sync & (fwmask | swmask)))

   374

			break;

   375

   376

		/* Firmware currently using resource (fwmask)

   377

		 * or other software thread using resource (swmask)

   378

		 */

   379

		e1000e_put_hw_semaphore(hw);

   380

		mdelay(5);

   381

		i++;

   382

	}

   383

   384

	if (i == timeout) {

   385

		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");

   386

		return -E1000_ERR_SWFW_SYNC;

   387

	}

   388

   389

	swfw_sync |= swmask;

   390

	ew32(SW_FW_SYNC, swfw_sync);

   391

   392

	e1000e_put_hw_semaphore(hw);

   393

   394

	return 0;

   395

}

   396

   397

/**

   398

 *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   399

 *  @hw: pointer to the HW structure

   400

 *  @mask: specifies which semaphore to acquire

   401

 *

   402

 *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   403

 *  will also specify which port we're releasing the lock for.

   404

 **/

   405

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   406

{

   407

	u32 swfw_sync;

   408

   409

	while (e1000e_get_hw_semaphore(hw) != 0)

   410

		; /* Empty */

   411

   412

	swfw_sync = er32(SW_FW_SYNC);

   413

	swfw_sync &= ~mask;

   414

	ew32(SW_FW_SYNC, swfw_sync);

   415

   416

	e1000e_put_hw_semaphore(hw);

   417

}

   418

   419

/**

   420

 *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   421

 *  @hw: pointer to the HW structure

   422

 *  @offset: offset of the register to read

   423

 *  @data: pointer to the data returned from the operation

   424

 *

   425

 *  Read the GG82563 PHY register.

   426

 **/

   427

static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   428

						  u32 offset, u16 *data)

   429

{

   430

	s32 ret_val;

   431

	u32 page_select;

   432

	u16 temp;

   433

   434

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   435

	if (ret_val)

   436

		return ret_val;

   437

   438

	/* Select Configuration Page */

   439

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   440

		page_select = GG82563_PHY_PAGE_SELECT;

   441

	} else {

   442

		/* Use Alternative Page Select register to access

   443

		 * registers 30 and 31

   444

		 */

   445

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   446

	}

   447

   448

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   449

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   450

	if (ret_val) {

   451

		e1000_release_phy_80003es2lan(hw);

   452

		return ret_val;

   453

	}

   454

   455

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   456

		/* The "ready" bit in the MDIC register may be incorrectly set

   457

		 * before the device has completed the "Page Select" MDI

   458

		 * transaction.  So we wait 200us after each MDI command...

   459

		 */

   460

		udelay(200);

   461

   462

		/* ...and verify the command was successful. */

   463

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   464

   465

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   466

			e1000_release_phy_80003es2lan(hw);

   467

			return -E1000_ERR_PHY;

   468

		}

   469

   470

		udelay(200);

   471

   472

		ret_val = e1000e_read_phy_reg_mdic(hw,

   473

		                                  MAX_PHY_REG_ADDRESS & offset,

   474

		                                  data);

   475

   476

		udelay(200);

   477

	} else {

   478

		ret_val = e1000e_read_phy_reg_mdic(hw,

   479

		                                  MAX_PHY_REG_ADDRESS & offset,

   480

		                                  data);

   481

	}

   482

   483

	e1000_release_phy_80003es2lan(hw);

   484

   485

	return ret_val;

   486

}

   487

   488

/**

   489

 *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   490

 *  @hw: pointer to the HW structure

   491

 *  @offset: offset of the register to read

   492

 *  @data: value to write to the register

   493

 *

   494

 *  Write to the GG82563 PHY register.

   495

 **/

   496

static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   497

						   u32 offset, u16 data)

   498

{

   499

	s32 ret_val;

   500

	u32 page_select;

   501

	u16 temp;

   502

   503

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   504

	if (ret_val)

   505

		return ret_val;

   506

   507

	/* Select Configuration Page */

   508

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   509

		page_select = GG82563_PHY_PAGE_SELECT;

   510

	} else {

   511

		/* Use Alternative Page Select register to access

   512

		 * registers 30 and 31

   513

		 */

   514

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   515

	}

   516

   517

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   518

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   519

	if (ret_val) {

   520

		e1000_release_phy_80003es2lan(hw);

   521

		return ret_val;

   522

	}

   523

   524

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   525

		/* The "ready" bit in the MDIC register may be incorrectly set

   526

		 * before the device has completed the "Page Select" MDI

   527

		 * transaction.  So we wait 200us after each MDI command...

   528

		 */

   529

		udelay(200);

   530