1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2006 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

 */

    28

    29

/* e1000_hw.c

    30

 * Shared functions for accessing and configuring the MAC

    31

 */

    32

    33

#include "e1000.h"

    34

    35

static s32 e1000_check_downshift(struct e1000_hw *hw);

    36

static s32 e1000_check_polarity(struct e1000_hw *hw,

    37

				e1000_rev_polarity *polarity);

    38

static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39

static void e1000_clear_vfta(struct e1000_hw *hw);

    40

static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41

					      bool link_up);

    42

static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43

static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44

static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45

static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46

				  u16 *max_length);

    47

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48

static s32 e1000_id_led_init(struct e1000_hw *hw);

    49

static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50

static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51

				  struct e1000_phy_info *phy_info);

    52

static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53

				  struct e1000_phy_info *phy_info);

    54

static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56

static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57

static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58

static void e1000_phy_init_script(struct e1000_hw *hw);

    59

static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60

static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61

static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63

static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64

static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65

static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66

static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67

static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68

static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69

static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70

				  u16 words, u16 *data);

    71

static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72

					u16 words, u16 *data);

    73

static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74

static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75

static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76

static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77

static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78

				  u16 phy_data);

    79

static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80

				 u16 *phy_data);

    81

static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82

static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83

static void e1000_release_eeprom(struct e1000_hw *hw);

    84

static void e1000_standby_eeprom(struct e1000_hw *hw);

    85

static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86

static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87

static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88

static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89

				u16 *data);

    90

static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91

				 u16 *data);

    92

    93

/* IGP cable length table */

    94

static const

    95

u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96

	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97

	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98

	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99

	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100

	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101

	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102

	    100,

   103

	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104

	    110, 110,

   105

	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106

	    120, 120

   107

};

   108

   109

static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110

static DEFINE_SPINLOCK(e1000_phy_lock);

   111

   112

/**

   113

 * e1000_set_phy_type - Set the phy type member in the hw struct.

   114

 * @hw: Struct containing variables accessed by shared code

   115

 */

   116

static s32 e1000_set_phy_type(struct e1000_hw *hw)

   117

{

   118

	if (hw->mac_type == e1000_undefined)

   119

		return -E1000_ERR_PHY_TYPE;

   120

   121

	switch (hw->phy_id) {

   122

	case M88E1000_E_PHY_ID:

   123

	case M88E1000_I_PHY_ID:

   124

	case M88E1011_I_PHY_ID:

   125

	case M88E1111_I_PHY_ID:

   126

	case M88E1118_E_PHY_ID:

   127

		hw->phy_type = e1000_phy_m88;

   128

		break;

   129

	case IGP01E1000_I_PHY_ID:

   130

		if (hw->mac_type == e1000_82541 ||

   131

		    hw->mac_type == e1000_82541_rev_2 ||

   132

		    hw->mac_type == e1000_82547 ||

   133

		    hw->mac_type == e1000_82547_rev_2)

   134

			hw->phy_type = e1000_phy_igp;

   135

		break;

   136

	case RTL8211B_PHY_ID:

   137

		hw->phy_type = e1000_phy_8211;

   138

		break;

   139

	case RTL8201N_PHY_ID:

   140

		hw->phy_type = e1000_phy_8201;

   141

		break;

   142

	default:

   143

		/* Should never have loaded on this device */

   144

		hw->phy_type = e1000_phy_undefined;

   145

		return -E1000_ERR_PHY_TYPE;

   146

	}

   147

   148

	return E1000_SUCCESS;

   149

}

   150

   151

/**

   152

 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   153

 * @hw: Struct containing variables accessed by shared code

   154

 */

   155

static void e1000_phy_init_script(struct e1000_hw *hw)

   156

{

   157

	u32 ret_val;

   158

	u16 phy_saved_data;

   159

   160

	if (hw->phy_init_script) {

   161

		msleep(20);

   162

   163

		/* Save off the current value of register 0x2F5B to be restored

   164

		 * at the end of this routine.

   165

		 */

   166

		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   167

   168

		/* Disabled the PHY transmitter */

   169

		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   170

		msleep(20);

   171

   172

		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   173

		msleep(5);

   174

   175

		switch (hw->mac_type) {

   176

		case e1000_82541:

   177

		case e1000_82547:

   178

			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   179

			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   180

			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   181

			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   182

			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   183

			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   184

			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   185

			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   186

			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   187

			break;

   188

   189

		case e1000_82541_rev_2:

   190

		case e1000_82547_rev_2:

   191

			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   192

			break;

   193

		default:

   194

			break;

   195

		}

   196

   197

		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   198

		msleep(20);

   199

   200

		/* Now enable the transmitter */

   201

		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   202

   203

		if (hw->mac_type == e1000_82547) {

   204

			u16 fused, fine, coarse;

   205

   206

			/* Move to analog registers page */

   207

			e1000_read_phy_reg(hw,

   208

					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   209

					   &fused);

   210

   211

			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   212

				e1000_read_phy_reg(hw,

   213

						   IGP01E1000_ANALOG_FUSE_STATUS,

   214

						   &fused);

   215

   216

				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   217

				coarse =

   218

				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   219

   220

				if (coarse >

   221

				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   222

					coarse -=

   223

					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   224

					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   225

				} else if (coarse ==

   226

					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   227

					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   228

   229

				fused =

   230

				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   231

				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   232

				    (coarse &

   233

				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   234

   235

				e1000_write_phy_reg(hw,

   236

						    IGP01E1000_ANALOG_FUSE_CONTROL,

   237

						    fused);

   238

				e1000_write_phy_reg(hw,

   239

						    IGP01E1000_ANALOG_FUSE_BYPASS,

   240

						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   241

			}

   242

		}

   243

	}

   244

}

   245

   246

/**

   247

 * e1000_set_mac_type - Set the mac type member in the hw struct.

   248

 * @hw: Struct containing variables accessed by shared code

   249

 */

   250

s32 e1000_set_mac_type(struct e1000_hw *hw)

   251

{

   252

	switch (hw->device_id) {

   253

	case E1000_DEV_ID_82542:

   254

		switch (hw->revision_id) {

   255

		case E1000_82542_2_0_REV_ID:

   256

			hw->mac_type = e1000_82542_rev2_0;

   257

			break;

   258

		case E1000_82542_2_1_REV_ID:

   259

			hw->mac_type = e1000_82542_rev2_1;

   260

			break;

   261

		default:

   262

			/* Invalid 82542 revision ID */

   263

			return -E1000_ERR_MAC_TYPE;

   264

		}

   265

		break;

   266

	case E1000_DEV_ID_82543GC_FIBER:

   267

	case E1000_DEV_ID_82543GC_COPPER:

   268

		hw->mac_type = e1000_82543;

   269

		break;

   270

	case E1000_DEV_ID_82544EI_COPPER:

   271

	case E1000_DEV_ID_82544EI_FIBER:

   272

	case E1000_DEV_ID_82544GC_COPPER:

   273

	case E1000_DEV_ID_82544GC_LOM:

   274

		hw->mac_type = e1000_82544;

   275

		break;

   276

	case E1000_DEV_ID_82540EM:

   277

	case E1000_DEV_ID_82540EM_LOM:

   278

	case E1000_DEV_ID_82540EP:

   279

	case E1000_DEV_ID_82540EP_LOM:

   280

	case E1000_DEV_ID_82540EP_LP:

   281

		hw->mac_type = e1000_82540;

   282

		break;

   283

	case E1000_DEV_ID_82545EM_COPPER:

   284

	case E1000_DEV_ID_82545EM_FIBER:

   285

		hw->mac_type = e1000_82545;

   286

		break;

   287

	case E1000_DEV_ID_82545GM_COPPER:

   288

	case E1000_DEV_ID_82545GM_FIBER:

   289

	case E1000_DEV_ID_82545GM_SERDES:

   290

		hw->mac_type = e1000_82545_rev_3;

   291

		break;

   292

	case E1000_DEV_ID_82546EB_COPPER:

   293

	case E1000_DEV_ID_82546EB_FIBER:

   294

	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   295

		hw->mac_type = e1000_82546;

   296

		break;

   297

	case E1000_DEV_ID_82546GB_COPPER:

   298

	case E1000_DEV_ID_82546GB_FIBER:

   299

	case E1000_DEV_ID_82546GB_SERDES:

   300

	case E1000_DEV_ID_82546GB_PCIE:

   301

	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   302

	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   303

		hw->mac_type = e1000_82546_rev_3;

   304

		break;

   305

	case E1000_DEV_ID_82541EI:

   306

	case E1000_DEV_ID_82541EI_MOBILE:

   307

	case E1000_DEV_ID_82541ER_LOM:

   308

		hw->mac_type = e1000_82541;

   309

		break;

   310

	case E1000_DEV_ID_82541ER:

   311

	case E1000_DEV_ID_82541GI:

   312

	case E1000_DEV_ID_82541GI_LF:

   313

	case E1000_DEV_ID_82541GI_MOBILE:

   314

		hw->mac_type = e1000_82541_rev_2;

   315

		break;

   316

	case E1000_DEV_ID_82547EI:

   317

	case E1000_DEV_ID_82547EI_MOBILE:

   318

		hw->mac_type = e1000_82547;

   319

		break;

   320

	case E1000_DEV_ID_82547GI:

   321

		hw->mac_type = e1000_82547_rev_2;

   322

		break;

   323

	case E1000_DEV_ID_INTEL_CE4100_GBE:

   324

		hw->mac_type = e1000_ce4100;

   325

		break;

   326

	default:

   327

		/* Should never have loaded on this device */

   328

		return -E1000_ERR_MAC_TYPE;

   329

	}

   330

   331

	switch (hw->mac_type) {

   332

	case e1000_82541:

   333

	case e1000_82547:

   334

	case e1000_82541_rev_2:

   335

	case e1000_82547_rev_2:

   336

		hw->asf_firmware_present = true;

   337

		break;

   338

	default:

   339

		break;

   340

	}

   341

   342

	/* The 82543 chip does not count tx_carrier_errors properly in

   343

	 * FD mode

   344

	 */

   345

	if (hw->mac_type == e1000_82543)

   346

		hw->bad_tx_carr_stats_fd = true;

   347

   348

	if (hw->mac_type > e1000_82544)

   349

		hw->has_smbus = true;

   350

   351

	return E1000_SUCCESS;

   352

}

   353

   354

/**

   355

 * e1000_set_media_type - Set media type and TBI compatibility.

   356

 * @hw: Struct containing variables accessed by shared code

   357

 */

   358

void e1000_set_media_type(struct e1000_hw *hw)

   359

{

   360

	u32 status;

   361

   362

	if (hw->mac_type != e1000_82543) {

   363

		/* tbi_compatibility is only valid on 82543 */

   364

		hw->tbi_compatibility_en = false;

   365

	}

   366

   367

	switch (hw->device_id) {

   368

	case E1000_DEV_ID_82545GM_SERDES:

   369

	case E1000_DEV_ID_82546GB_SERDES:

   370

		hw->media_type = e1000_media_type_internal_serdes;

   371

		break;

   372

	default:

   373

		switch (hw->mac_type) {

   374

		case e1000_82542_rev2_0:

   375

		case e1000_82542_rev2_1:

   376

			hw->media_type = e1000_media_type_fiber;

   377

			break;

   378

		case e1000_ce4100:

   379

			hw->media_type = e1000_media_type_copper;

   380

			break;

   381

		default:

   382

			status = er32(STATUS);

   383

			if (status & E1000_STATUS_TBIMODE) {

   384

				hw->media_type = e1000_media_type_fiber;

   385

				/* tbi_compatibility not valid on fiber */

   386

				hw->tbi_compatibility_en = false;

   387

			} else {

   388

				hw->media_type = e1000_media_type_copper;

   389

			}

   390

			break;

   391

		}

   392

	}

   393

}

   394

   395

/**

   396

 * e1000_reset_hw - reset the hardware completely

   397

 * @hw: Struct containing variables accessed by shared code

   398

 *

   399

 * Reset the transmit and receive units; mask and clear all interrupts.

   400

 */

   401

s32 e1000_reset_hw(struct e1000_hw *hw)

   402

{

   403

	u32 ctrl;

   404

	u32 ctrl_ext;

   405

	u32 icr;

   406

	u32 manc;

   407

	u32 led_ctrl;

   408

	s32 ret_val;

   409

   410

	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   411

	if (hw->mac_type == e1000_82542_rev2_0) {

   412

		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   413

		e1000_pci_clear_mwi(hw);

   414

	}

   415

   416

	/* Clear interrupt mask to stop board from generating interrupts */

   417

	e_dbg("Masking off all interrupts\n");

   418

	ew32(IMC, 0xffffffff);

   419

   420

	/* Disable the Transmit and Receive units.  Then delay to allow

   421

	 * any pending transactions to complete before we hit the MAC with

   422

	 * the global reset.

   423

	 */

   424

	ew32(RCTL, 0);

   425

	ew32(TCTL, E1000_TCTL_PSP);

   426

	E1000_WRITE_FLUSH();

   427

   428

	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   429

	hw->tbi_compatibility_on = false;

   430

   431

	/* Delay to allow any outstanding PCI transactions to complete before

   432

	 * resetting the device

   433

	 */

   434

	msleep(10);

   435

   436

	ctrl = er32(CTRL);

   437

   438

	/* Must reset the PHY before resetting the MAC */

   439

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   440

		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   441

		E1000_WRITE_FLUSH();

   442

		msleep(5);

   443

	}

   444

   445

	/* Issue a global reset to the MAC.  This will reset the chip's

   446

	 * transmit, receive, DMA, and link units.  It will not effect

   447

	 * the current PCI configuration.  The global reset bit is self-

   448

	 * clearing, and should clear within a microsecond.

   449

	 */

   450

	e_dbg("Issuing a global reset to MAC\n");

   451

   452

	switch (hw->mac_type) {

   453

	case e1000_82544:

   454

	case e1000_82540:

   455

	case e1000_82545:

   456

	case e1000_82546:

   457

	case e1000_82541:

   458

	case e1000_82541_rev_2:

   459

		/* These controllers can't ack the 64-bit write when issuing the

   460

		 * reset, so use IO-mapping as a workaround to issue the reset

   461

		 */

   462

		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   463

		break;

   464

	case e1000_82545_rev_3:

   465

	case e1000_82546_rev_3:

   466

		/* Reset is performed on a shadow of the control register */

   467

		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   468

		break;

   469

	case e1000_ce4100:

   470

	default:

   471

		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   472

		break;

   473

	}

   474

   475

	/* After MAC reset, force reload of EEPROM to restore power-on settings

   476

	 * to device.  Later controllers reload the EEPROM automatically, so

   477

	 * just wait for reload to complete.

   478

	 */

   479

	switch (hw->mac_type) {

   480

	case e1000_82542_rev2_0:

   481

	case e1000_82542_rev2_1:

   482

	case e1000_82543:

   483

	case e1000_82544:

   484

		/* Wait for reset to complete */

   485

		udelay(10);

   486

		ctrl_ext = er32(CTRL_EXT);

   487

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   488

		ew32(CTRL_EXT, ctrl_ext);

   489

		E1000_WRITE_FLUSH();

   490

		/* Wait for EEPROM reload */

   491

		msleep(2);

   492

		break;

   493

	case e1000_82541:

   494

	case e1000_82541_rev_2:

   495

	case e1000_82547:

   496

	case e1000_82547_rev_2:

   497

		/* Wait for EEPROM reload */

   498

		msleep(20);

   499

		break;

   500

	default:

   501

		/* Auto read done will delay 5ms or poll based on mac type */

   502

		ret_val = e1000_get_auto_rd_done(hw);

   503

		if (ret_val)

   504

			return ret_val;

   505

		break;

   506

	}

   507

   508

	/* Disable HW ARPs on ASF enabled adapters */

   509

	if (hw->mac_type >= e1000_82540) {

   510

		manc = er32(MANC);

   511

		manc &= ~(E1000_MANC_ARP_EN);

   512

		ew32(MANC, manc);

   513

	}

   514

   515

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   516

		e1000_phy_init_script(hw);

   517

   518

		/* Configure activity LED after PHY reset */

   519

		led_ctrl = er32(LEDCTL);

   520

		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   521

		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   522

		ew32(LEDCTL, led_ctrl);

   523

	}

   524

   525

	/* Clear interrupt mask to stop board from generating interrupts */

   526

	e_dbg("Masking off all interrupts\n");

   527

	ew32(IMC, 0xffffffff);

   528

   529

	/* Clear any pending interrupt events. */

   530