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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2012 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

#include "e1000-3.6-ethercat.h"

    30

    31

/**

    32

 *  e1000e_get_bus_info_pcie - Get PCIe bus information

    33

 *  @hw: pointer to the HW structure

    34

 *

    35

 *  Determines and stores the system bus information for a particular

    36

 *  network interface.  The following bus information is determined and stored:

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 *  bus speed, bus width, type (PCIe), and PCIe function.

    38

 **/

    39

s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)

    40

{

    41

	struct e1000_mac_info *mac = &hw->mac;

    42

	struct e1000_bus_info *bus = &hw->bus;

    43

	struct e1000_adapter *adapter = hw->adapter;

    44

	u16 pcie_link_status, cap_offset;

    45

    46

	cap_offset = adapter->pdev->pcie_cap;

    47

	if (!cap_offset) {

    48

		bus->width = e1000_bus_width_unknown;

    49

	} else {

    50

		pci_read_config_word(adapter->pdev,

    51

				     cap_offset + PCIE_LINK_STATUS,

    52

				     &pcie_link_status);

    53

		bus->width = (enum e1000_bus_width)((pcie_link_status &

    54

						     PCIE_LINK_WIDTH_MASK) >>

    55

						    PCIE_LINK_WIDTH_SHIFT);

    56

	}

    57

    58

	mac->ops.set_lan_id(hw);

    59

    60

	return 0;

    61

}

    62

    63

/**

    64

 *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices

    65

 *

    66

 *  @hw: pointer to the HW structure

    67

 *

    68

 *  Determines the LAN function id by reading memory-mapped registers

    69

 *  and swaps the port value if requested.

    70

 **/

    71

void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)

    72

{

    73

	struct e1000_bus_info *bus = &hw->bus;

    74

	u32 reg;

    75

    76

	/*

    77

	 * The status register reports the correct function number

    78

	 * for the device regardless of function swap state.

    79

	 */

    80

	reg = er32(STATUS);

    81

	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

    82

}

    83

    84

/**

    85

 *  e1000_set_lan_id_single_port - Set LAN id for a single port device

    86

 *  @hw: pointer to the HW structure

    87

 *

    88

 *  Sets the LAN function id to zero for a single port device.

    89

 **/

    90

void e1000_set_lan_id_single_port(struct e1000_hw *hw)

    91

{

    92

	struct e1000_bus_info *bus = &hw->bus;

    93

    94

	bus->func = 0;

    95

}

    96

    97

/**

    98

 *  e1000_clear_vfta_generic - Clear VLAN filter table

    99

 *  @hw: pointer to the HW structure

   100

 *

   101

 *  Clears the register array which contains the VLAN filter table by

   102

 *  setting all the values to 0.

   103

 **/

   104

void e1000_clear_vfta_generic(struct e1000_hw *hw)

   105

{

   106

	u32 offset;

   107

   108

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

   109

		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);

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		e1e_flush();

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	}

   112

}

   113

   114

/**

   115

 *  e1000_write_vfta_generic - Write value to VLAN filter table

   116

 *  @hw: pointer to the HW structure

   117

 *  @offset: register offset in VLAN filter table

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 *  @value: register value written to VLAN filter table

   119

 *

   120

 *  Writes value at the given offset in the register array which stores

   121

 *  the VLAN filter table.

   122

 **/

   123

void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)

   124

{

   125

	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);

   126

	e1e_flush();

   127

}

   128

   129

/**

   130

 *  e1000e_init_rx_addrs - Initialize receive address's

   131

 *  @hw: pointer to the HW structure

   132

 *  @rar_count: receive address registers

   133

 *

   134

 *  Setup the receive address registers by setting the base receive address

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 *  register to the devices MAC address and clearing all the other receive

   136

 *  address registers to 0.

   137

 **/

   138

void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   139

{

   140

	u32 i;

   141

	u8 mac_addr[ETH_ALEN] = { 0 };

   142

   143

	/* Setup the receive address */

   144

	e_dbg("Programming MAC Address into RAR[0]\n");

   145

   146

	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);

   147

   148

	/* Zero out the other (rar_entry_count - 1) receive addresses */

   149

	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);

   150

	for (i = 1; i < rar_count; i++)

   151

		hw->mac.ops.rar_set(hw, mac_addr, i);

   152

}

   153

   154

/**

   155

 *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr

   156

 *  @hw: pointer to the HW structure

   157

 *

   158

 *  Checks the nvm for an alternate MAC address.  An alternate MAC address

   159

 *  can be setup by pre-boot software and must be treated like a permanent

   160

 *  address and must override the actual permanent MAC address. If an

   161

 *  alternate MAC address is found it is programmed into RAR0, replacing

   162

 *  the permanent address that was installed into RAR0 by the Si on reset.

   163

 *  This function will return SUCCESS unless it encounters an error while

   164

 *  reading the EEPROM.

   165

 **/

   166

s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)

   167

{

   168

	u32 i;

   169

	s32 ret_val = 0;

   170

	u16 offset, nvm_alt_mac_addr_offset, nvm_data;

   171

	u8 alt_mac_addr[ETH_ALEN];

   172

   173

	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);

   174

	if (ret_val)

   175

		return ret_val;

   176

   177

	/* not supported on 82573 */

   178

	if (hw->mac.type == e1000_82573)

   179

		return 0;

   180

   181

	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,

   182

				 &nvm_alt_mac_addr_offset);

   183

	if (ret_val) {

   184

		e_dbg("NVM Read Error\n");

   185

		return ret_val;

   186

	}

   187

   188

	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||

   189

	    (nvm_alt_mac_addr_offset == 0x0000))

   190

		/* There is no Alternate MAC Address */

   191

		return 0;

   192

   193

	if (hw->bus.func == E1000_FUNC_1)

   194

		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;

   195

	for (i = 0; i < ETH_ALEN; i += 2) {

   196

		offset = nvm_alt_mac_addr_offset + (i >> 1);

   197

		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);

   198

		if (ret_val) {

   199

			e_dbg("NVM Read Error\n");

   200

			return ret_val;

   201

		}

   202

   203

		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);

   204

		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);

   205

	}

   206

   207

	/* if multicast bit is set, the alternate address will not be used */

   208

	if (is_multicast_ether_addr(alt_mac_addr)) {

   209

		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");

   210

		return 0;

   211

	}

   212

   213

	/*

   214

	 * We have a valid alternate MAC address, and we want to treat it the

   215

	 * same as the normal permanent MAC address stored by the HW into the

   216

	 * RAR. Do this by mapping this address into RAR0.

   217

	 */

   218

	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);

   219

   220

	return 0;

   221

}

   222

   223

/**

   224

 *  e1000e_rar_set_generic - Set receive address register

   225

 *  @hw: pointer to the HW structure

   226

 *  @addr: pointer to the receive address

   227

 *  @index: receive address array register

   228

 *

   229

 *  Sets the receive address array register at index to the address passed

   230

 *  in by addr.

   231

 **/

   232

void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)

   233

{

   234

	u32 rar_low, rar_high;

   235

   236

	/*

   237

	 * HW expects these in little endian so we reverse the byte order

   238

	 * from network order (big endian) to little endian

   239

	 */

   240

	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |

   241

		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));

   242

   243

	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));

   244

   245

	/* If MAC address zero, no need to set the AV bit */

   246

	if (rar_low || rar_high)

   247

		rar_high |= E1000_RAH_AV;

   248

   249

	/*

   250

	 * Some bridges will combine consecutive 32-bit writes into

   251

	 * a single burst write, which will malfunction on some parts.

   252

	 * The flushes avoid this.

   253

	 */

   254

	ew32(RAL(index), rar_low);

   255

	e1e_flush();

   256

	ew32(RAH(index), rar_high);

   257

	e1e_flush();

   258

}

   259

   260

/**

   261

 *  e1000_hash_mc_addr - Generate a multicast hash value

   262

 *  @hw: pointer to the HW structure

   263

 *  @mc_addr: pointer to a multicast address

   264

 *

   265

 *  Generates a multicast address hash value which is used to determine

   266

 *  the multicast filter table array address and new table value.

   267

 **/

   268

static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   269

{

   270

	u32 hash_value, hash_mask;

   271

	u8 bit_shift = 0;

   272

   273

	/* Register count multiplied by bits per register */

   274

	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   275

   276

	/*

   277

	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts

   278

	 * where 0xFF would still fall within the hash mask.

   279

	 */

   280

	while (hash_mask >> bit_shift != 0xFF)

   281

		bit_shift++;

   282

   283

	/*

   284

	 * The portion of the address that is used for the hash table

   285

	 * is determined by the mc_filter_type setting.

   286

	 * The algorithm is such that there is a total of 8 bits of shifting.

   287

	 * The bit_shift for a mc_filter_type of 0 represents the number of

   288

	 * left-shifts where the MSB of mc_addr[5] would still fall within

   289

	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   290

	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   291

	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   292

	 * cases are a variation of this algorithm...essentially raising the

   293

	 * number of bits to shift mc_addr[5] left, while still keeping the

   294

	 * 8-bit shifting total.

   295

	 *

   296

	 * For example, given the following Destination MAC Address and an

   297

	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   298

	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   299

	 * values resulting from each mc_filter_type...

   300

	 * [0] [1] [2] [3] [4] [5]

   301

	 * 01  AA  00  12  34  56

   302

	 * LSB           MSB

   303

	 *

   304

	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   305

	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   306

	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   307

	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   308

	 */

   309

	switch (hw->mac.mc_filter_type) {

   310

	default:

   311

	case 0:

   312

		break;

   313

	case 1:

   314

		bit_shift += 1;

   315

		break;

   316

	case 2:

   317

		bit_shift += 2;

   318

		break;

   319

	case 3:

   320

		bit_shift += 4;

   321

		break;

   322

	}

   323

   324

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   325

				   (((u16)mc_addr[5]) << bit_shift)));

   326

   327

	return hash_value;

   328

}

   329

   330

/**

   331

 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses

   332

 *  @hw: pointer to the HW structure

   333

 *  @mc_addr_list: array of multicast addresses to program

   334

 *  @mc_addr_count: number of multicast addresses to program

   335

 *

   336

 *  Updates entire Multicast Table Array.

   337

 *  The caller must have a packed mc_addr_list of multicast addresses.

   338

 **/

   339

void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,

   340

					u8 *mc_addr_list, u32 mc_addr_count)

   341

{

   342

	u32 hash_value, hash_bit, hash_reg;

   343

	int i;

   344

   345

	/* clear mta_shadow */

   346

	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

   347

   348

	/* update mta_shadow from mc_addr_list */

   349

	for (i = 0; (u32)i < mc_addr_count; i++) {

   350

		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);

   351

   352

		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   353

		hash_bit = hash_value & 0x1F;

   354

   355

		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);

   356

		mc_addr_list += (ETH_ALEN);

   357

	}

   358

   359

	/* replace the entire MTA table */

   360

	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)

   361

		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);

   362

	e1e_flush();

   363

}

   364

   365

/**

   366

 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters

   367

 *  @hw: pointer to the HW structure

   368

 *

   369

 *  Clears the base hardware counters by reading the counter registers.

   370

 **/

   371

void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)

   372

{

   373

	er32(CRCERRS);

   374

	er32(SYMERRS);

   375

	er32(MPC);

   376

	er32(SCC);

   377

	er32(ECOL);

   378

	er32(MCC);

   379

	er32(LATECOL);

   380

	er32(COLC);

   381

	er32(DC);

   382

	er32(SEC);

   383

	er32(RLEC);

   384

	er32(XONRXC);

   385

	er32(XONTXC);

   386

	er32(XOFFRXC);

   387

	er32(XOFFTXC);

   388

	er32(FCRUC);

   389

	er32(GPRC);

   390

	er32(BPRC);

   391

	er32(MPRC);

   392

	er32(GPTC);

   393

	er32(GORCL);

   394

	er32(GORCH);

   395

	er32(GOTCL);

   396

	er32(GOTCH);

   397

	er32(RNBC);

   398

	er32(RUC);

   399

	er32(RFC);

   400

	er32(ROC);

   401

	er32(RJC);

   402

	er32(TORL);

   403

	er32(TORH);

   404

	er32(TOTL);

   405

	er32(TOTH);

   406

	er32(TPR);

   407

	er32(TPT);

   408

	er32(MPTC);

   409

	er32(BPTC);

   410

}

   411

   412

/**

   413

 *  e1000e_check_for_copper_link - Check for link (Copper)

   414

 *  @hw: pointer to the HW structure

   415

 *

   416

 *  Checks to see of the link status of the hardware has changed.  If a

   417

 *  change in link status has been detected, then we read the PHY registers

   418

 *  to get the current speed/duplex if link exists.

   419

 **/

   420

s32 e1000e_check_for_copper_link(struct e1000_hw *hw)

   421

{

   422

	struct e1000_mac_info *mac = &hw->mac;

   423

	s32 ret_val;

   424

	bool link;

   425

   426

	/*

   427

	 * We only want to go out to the PHY registers to see if Auto-Neg

   428

	 * has completed and/or if our link status has changed.  The

   429

	 * get_link_status flag is set upon receiving a Link Status

   430

	 * Change or Rx Sequence Error interrupt.

   431

	 */

   432

	if (!mac->get_link_status)

   433

		return 0;

   434

   435

	/*

   436

	 * First we want to see if the MII Status Register reports

   437

	 * link.  If so, then we want to get the current speed/duplex

   438

	 * of the PHY.

   439

	 */

   440

	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   441

	if (ret_val)

   442

		return ret_val;

   443

   444

	if (!link)

   445

		return 0;	/* No link detected */

   446

   447

	mac->get_link_status = false;

   448

   449

	/*

   450

	 * Check if there was DownShift, must be checked

   451

	 * immediately after link-up

   452

	 */

   453

	e1000e_check_downshift(hw);

   454

   455

	/*

   456

	 * If we are forcing speed/duplex, then we simply return since

   457

	 * we have already determined whether we have link or not.

   458

	 */

   459

	if (!mac->autoneg)

   460

		return -E1000_ERR_CONFIG;

   461

   462

	/*

   463

	 * Auto-Neg is enabled.  Auto Speed Detection takes care

   464

	 * of MAC speed/duplex configuration.  So we only need to

   465

	 * configure Collision Distance in the MAC.

   466

	 */

   467

	mac->ops.config_collision_dist(hw);

   468

   469

	/*

   470

	 * Configure Flow Control now that Auto-Neg has completed.

   471

	 * First, we need to restore the desired flow control

   472

	 * settings because we may have had to re-autoneg with a

   473

	 * different link partner.

   474

	 */

   475

	ret_val = e1000e_config_fc_after_link_up(hw);

   476

	if (ret_val)

   477

		e_dbg("Error configuring flow control\n");

   478

   479

	return ret_val;

   480

}

   481

   482

/**

   483

 *  e1000e_check_for_fiber_link - Check for link (Fiber)

   484

 *  @hw: pointer to the HW structure

   485

 *

   486

 *  Checks for link up on the hardware.  If link is not up and we have

   487

 *  a signal, then we need to force link up.

   488

 **/

   489

s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)

   490

{

   491

	struct e1000_mac_info *mac = &hw->mac;

   492

	u32 rxcw;

   493

	u32 ctrl;

   494

	u32 status;

   495

	s32 ret_val;

   496

   497

	ctrl = er32(CTRL);

   498

	status = er32(STATUS);

   499

	rxcw = er32(RXCW);

   500

   501

	/*

   502

	 * If we don't have link (auto-negotiation failed or link partner

   503

	 * cannot auto-negotiate), the cable is plugged in (we have signal),

   504

	 * and our link partner is not trying to auto-negotiate with us (we

   505

	 * are receiving idles or data), we need to force link up. We also

   506

	 * need to give auto-negotiation time to complete, in case the cable

   507

	 * was just plugged in. The autoneg_failed flag does this.

   508

	 */

   509

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   510

	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&

   511

	    !(rxcw & E1000_RXCW_C)) {

   512

		if (!mac->autoneg_failed) {

   513

			mac->autoneg_failed = true;

   514

			return 0;

   515

		}

   516

		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");

   517

   518

		/* Disable auto-negotiation in the TXCW register */

   519

		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   520

   521

		/* Force link-up and also force full-duplex. */

   522

		ctrl = er32(CTRL);

   523

		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   524

		ew32(CTRL, ctrl);

   525

   526

		/* Configure Flow Control after forcing link up. */

   527

		ret_val = e1000e_config_fc_after_link_up(hw);

   528

		if (ret_val) {

   529

			e_dbg("Error configuring flow control\n");

   530