1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2006 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

 */

    28

    29

/* e1000_hw.c

    30

 * Shared functions for accessing and configuring the MAC

    31

 */

    32

    33

#include "e1000_hw-2.6.33-ethercat.h"

    34

    35

static s32 e1000_check_downshift(struct e1000_hw *hw);

    36

static s32 e1000_check_polarity(struct e1000_hw *hw,

    37

				e1000_rev_polarity *polarity);

    38

static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39

static void e1000_clear_vfta(struct e1000_hw *hw);

    40

static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41

					      bool link_up);

    42

static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43

static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44

static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45

static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46

				  u16 *max_length);

    47

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48

static s32 e1000_id_led_init(struct e1000_hw *hw);

    49

static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50

static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51

				  struct e1000_phy_info *phy_info);

    52

static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53

				  struct e1000_phy_info *phy_info);

    54

static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56

static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57

static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58

static void e1000_phy_init_script(struct e1000_hw *hw);

    59

static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60

static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61

static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63

static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64

static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65

static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66

static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67

static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68

static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69

static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70

				  u16 words, u16 *data);

    71

static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72

					u16 words, u16 *data);

    73

static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74

static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75

static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76

static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77

static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78

				  u16 phy_data);

    79

static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

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				 u16 *phy_data);

    81

static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82

static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83

static void e1000_release_eeprom(struct e1000_hw *hw);

    84

static void e1000_standby_eeprom(struct e1000_hw *hw);

    85

static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86

static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87

static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88

static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89

				u16 *data);

    90

static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91

				 u16 *data);

    92

    93

/* IGP cable length table */

    94

static const

    95

u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96

	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

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	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98

	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99

	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100

	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101

	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102

	    100,

   103

	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104

	    110, 110,

   105

	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106

	    120, 120

   107

};

   108

   109

static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110

   111

/**

   112

 * e1000_set_phy_type - Set the phy type member in the hw struct.

   113

 * @hw: Struct containing variables accessed by shared code

   114

 */

   115

static s32 e1000_set_phy_type(struct e1000_hw *hw)

   116

{

   117

	DEBUGFUNC("e1000_set_phy_type");

   118

   119

	if (hw->mac_type == e1000_undefined)

   120

		return -E1000_ERR_PHY_TYPE;

   121

   122

	switch (hw->phy_id) {

   123

	case M88E1000_E_PHY_ID:

   124

	case M88E1000_I_PHY_ID:

   125

	case M88E1011_I_PHY_ID:

   126

	case M88E1111_I_PHY_ID:

   127

		hw->phy_type = e1000_phy_m88;

   128

		break;

   129

	case IGP01E1000_I_PHY_ID:

   130

		if (hw->mac_type == e1000_82541 ||

   131

		    hw->mac_type == e1000_82541_rev_2 ||

   132

		    hw->mac_type == e1000_82547 ||

   133

		    hw->mac_type == e1000_82547_rev_2) {

   134

			hw->phy_type = e1000_phy_igp;

   135

			break;

   136

		}

   137

	default:

   138

		/* Should never have loaded on this device */

   139

		hw->phy_type = e1000_phy_undefined;

   140

		return -E1000_ERR_PHY_TYPE;

   141

	}

   142

   143

	return E1000_SUCCESS;

   144

}

   145

   146

/**

   147

 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   148

 * @hw: Struct containing variables accessed by shared code

   149

 */

   150

static void e1000_phy_init_script(struct e1000_hw *hw)

   151

{

   152

	u32 ret_val;

   153

	u16 phy_saved_data;

   154

   155

	DEBUGFUNC("e1000_phy_init_script");

   156

   157

	if (hw->phy_init_script) {

   158

		msleep(20);

   159

   160

		/* Save off the current value of register 0x2F5B to be restored at

   161

		 * the end of this routine. */

   162

		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   163

   164

		/* Disabled the PHY transmitter */

   165

		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   166

		msleep(20);

   167

   168

		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   169

		msleep(5);

   170

   171

		switch (hw->mac_type) {

   172

		case e1000_82541:

   173

		case e1000_82547:

   174

			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   175

			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   176

			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   177

			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   178

			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   179

			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   180

			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   181

			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   182

			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   183

			break;

   184

   185

		case e1000_82541_rev_2:

   186

		case e1000_82547_rev_2:

   187

			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   188

			break;

   189

		default:

   190

			break;

   191

		}

   192

   193

		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   194

		msleep(20);

   195

   196

		/* Now enable the transmitter */

   197

		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   198

   199

		if (hw->mac_type == e1000_82547) {

   200

			u16 fused, fine, coarse;

   201

   202

			/* Move to analog registers page */

   203

			e1000_read_phy_reg(hw,

   204

					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   205

					   &fused);

   206

   207

			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   208

				e1000_read_phy_reg(hw,

   209

						   IGP01E1000_ANALOG_FUSE_STATUS,

   210

						   &fused);

   211

   212

				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   213

				coarse =

   214

				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   215

   216

				if (coarse >

   217

				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   218

					coarse -=

   219

					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   220

					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   221

				} else if (coarse ==

   222

					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   223

					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   224

   225

				fused =

   226

				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   227

				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   228

				    (coarse &

   229

				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   230

   231

				e1000_write_phy_reg(hw,

   232

						    IGP01E1000_ANALOG_FUSE_CONTROL,

   233

						    fused);

   234

				e1000_write_phy_reg(hw,

   235

						    IGP01E1000_ANALOG_FUSE_BYPASS,

   236

						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   237

			}

   238

		}

   239

	}

   240

}

   241

   242

/**

   243

 * e1000_set_mac_type - Set the mac type member in the hw struct.

   244

 * @hw: Struct containing variables accessed by shared code

   245

 */

   246

s32 e1000_set_mac_type(struct e1000_hw *hw)

   247

{

   248

	DEBUGFUNC("e1000_set_mac_type");

   249

   250

	switch (hw->device_id) {

   251

	case E1000_DEV_ID_82542:

   252

		switch (hw->revision_id) {

   253

		case E1000_82542_2_0_REV_ID:

   254

			hw->mac_type = e1000_82542_rev2_0;

   255

			break;

   256

		case E1000_82542_2_1_REV_ID:

   257

			hw->mac_type = e1000_82542_rev2_1;

   258

			break;

   259

		default:

   260

			/* Invalid 82542 revision ID */

   261

			return -E1000_ERR_MAC_TYPE;

   262

		}

   263

		break;

   264

	case E1000_DEV_ID_82543GC_FIBER:

   265

	case E1000_DEV_ID_82543GC_COPPER:

   266

		hw->mac_type = e1000_82543;

   267

		break;

   268

	case E1000_DEV_ID_82544EI_COPPER:

   269

	case E1000_DEV_ID_82544EI_FIBER:

   270

	case E1000_DEV_ID_82544GC_COPPER:

   271

	case E1000_DEV_ID_82544GC_LOM:

   272

		hw->mac_type = e1000_82544;

   273

		break;

   274

	case E1000_DEV_ID_82540EM:

   275

	case E1000_DEV_ID_82540EM_LOM:

   276

	case E1000_DEV_ID_82540EP:

   277

	case E1000_DEV_ID_82540EP_LOM:

   278

	case E1000_DEV_ID_82540EP_LP:

   279

		hw->mac_type = e1000_82540;

   280

		break;

   281

	case E1000_DEV_ID_82545EM_COPPER:

   282

	case E1000_DEV_ID_82545EM_FIBER:

   283

		hw->mac_type = e1000_82545;

   284

		break;

   285

	case E1000_DEV_ID_82545GM_COPPER:

   286

	case E1000_DEV_ID_82545GM_FIBER:

   287

	case E1000_DEV_ID_82545GM_SERDES:

   288

		hw->mac_type = e1000_82545_rev_3;

   289

		break;

   290

	case E1000_DEV_ID_82546EB_COPPER:

   291

	case E1000_DEV_ID_82546EB_FIBER:

   292

	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   293

		hw->mac_type = e1000_82546;

   294

		break;

   295

	case E1000_DEV_ID_82546GB_COPPER:

   296

	case E1000_DEV_ID_82546GB_FIBER:

   297

	case E1000_DEV_ID_82546GB_SERDES:

   298

	case E1000_DEV_ID_82546GB_PCIE:

   299

	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   300

	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   301

		hw->mac_type = e1000_82546_rev_3;

   302

		break;

   303

	case E1000_DEV_ID_82541EI:

   304

	case E1000_DEV_ID_82541EI_MOBILE:

   305

	case E1000_DEV_ID_82541ER_LOM:

   306

		hw->mac_type = e1000_82541;

   307

		break;

   308

	case E1000_DEV_ID_82541ER:

   309

	case E1000_DEV_ID_82541GI:

   310

	case E1000_DEV_ID_82541GI_LF:

   311

	case E1000_DEV_ID_82541GI_MOBILE:

   312

		hw->mac_type = e1000_82541_rev_2;

   313

		break;

   314

	case E1000_DEV_ID_82547EI:

   315

	case E1000_DEV_ID_82547EI_MOBILE:

   316

		hw->mac_type = e1000_82547;

   317

		break;

   318

	case E1000_DEV_ID_82547GI:

   319

		hw->mac_type = e1000_82547_rev_2;

   320

		break;

   321

	default:

   322

		/* Should never have loaded on this device */

   323

		return -E1000_ERR_MAC_TYPE;

   324

	}

   325

   326

	switch (hw->mac_type) {

   327

	case e1000_82541:

   328

	case e1000_82547:

   329

	case e1000_82541_rev_2:

   330

	case e1000_82547_rev_2:

   331

		hw->asf_firmware_present = true;

   332

		break;

   333

	default:

   334

		break;

   335

	}

   336

   337

	/* The 82543 chip does not count tx_carrier_errors properly in

   338

	 * FD mode

   339

	 */

   340

	if (hw->mac_type == e1000_82543)

   341

		hw->bad_tx_carr_stats_fd = true;

   342

   343

	if (hw->mac_type > e1000_82544)

   344

		hw->has_smbus = true;

   345

   346

	return E1000_SUCCESS;

   347

}

   348

   349

/**

   350

 * e1000_set_media_type - Set media type and TBI compatibility.

   351

 * @hw: Struct containing variables accessed by shared code

   352

 */

   353

void e1000_set_media_type(struct e1000_hw *hw)

   354

{

   355

	u32 status;

   356

   357

	DEBUGFUNC("e1000_set_media_type");

   358

   359

	if (hw->mac_type != e1000_82543) {

   360

		/* tbi_compatibility is only valid on 82543 */

   361

		hw->tbi_compatibility_en = false;

   362

	}

   363

   364

	switch (hw->device_id) {

   365

	case E1000_DEV_ID_82545GM_SERDES:

   366

	case E1000_DEV_ID_82546GB_SERDES:

   367

		hw->media_type = e1000_media_type_internal_serdes;

   368

		break;

   369

	default:

   370

		switch (hw->mac_type) {

   371

		case e1000_82542_rev2_0:

   372

		case e1000_82542_rev2_1:

   373

			hw->media_type = e1000_media_type_fiber;

   374

			break;

   375

		default:

   376

			status = er32(STATUS);

   377

			if (status & E1000_STATUS_TBIMODE) {

   378

				hw->media_type = e1000_media_type_fiber;

   379

				/* tbi_compatibility not valid on fiber */

   380

				hw->tbi_compatibility_en = false;

   381

			} else {

   382

				hw->media_type = e1000_media_type_copper;

   383

			}

   384

			break;

   385

		}

   386

	}

   387

}

   388

   389

/**

   390

 * e1000_reset_hw: reset the hardware completely

   391

 * @hw: Struct containing variables accessed by shared code

   392

 *

   393

 * Reset the transmit and receive units; mask and clear all interrupts.

   394

 */

   395

s32 e1000_reset_hw(struct e1000_hw *hw)

   396

{

   397

	u32 ctrl;

   398

	u32 ctrl_ext;

   399

	u32 icr;

   400

	u32 manc;

   401

	u32 led_ctrl;

   402

	s32 ret_val;

   403

   404

	DEBUGFUNC("e1000_reset_hw");

   405

   406

	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   407

	if (hw->mac_type == e1000_82542_rev2_0) {

   408

		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   409

		e1000_pci_clear_mwi(hw);

   410

	}

   411

   412

	/* Clear interrupt mask to stop board from generating interrupts */

   413

	DEBUGOUT("Masking off all interrupts\n");

   414

	ew32(IMC, 0xffffffff);

   415

   416

	/* Disable the Transmit and Receive units.  Then delay to allow

   417

	 * any pending transactions to complete before we hit the MAC with

   418

	 * the global reset.

   419

	 */

   420

	ew32(RCTL, 0);

   421

	ew32(TCTL, E1000_TCTL_PSP);

   422

	E1000_WRITE_FLUSH();

   423

   424

	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   425

	hw->tbi_compatibility_on = false;

   426

   427

	/* Delay to allow any outstanding PCI transactions to complete before

   428

	 * resetting the device

   429

	 */

   430

	msleep(10);

   431

   432

	ctrl = er32(CTRL);

   433

   434

	/* Must reset the PHY before resetting the MAC */

   435

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   436

		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   437

		msleep(5);

   438

	}

   439

   440

	/* Issue a global reset to the MAC.  This will reset the chip's

   441

	 * transmit, receive, DMA, and link units.  It will not effect

   442

	 * the current PCI configuration.  The global reset bit is self-

   443

	 * clearing, and should clear within a microsecond.

   444

	 */

   445

	DEBUGOUT("Issuing a global reset to MAC\n");

   446

   447

	switch (hw->mac_type) {

   448

	case e1000_82544:

   449

	case e1000_82540:

   450

	case e1000_82545:

   451

	case e1000_82546:

   452

	case e1000_82541:

   453

	case e1000_82541_rev_2:

   454

		/* These controllers can't ack the 64-bit write when issuing the

   455

		 * reset, so use IO-mapping as a workaround to issue the reset */

   456

		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   457

		break;

   458

	case e1000_82545_rev_3:

   459

	case e1000_82546_rev_3:

   460

		/* Reset is performed on a shadow of the control register */

   461

		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   462

		break;

   463

	default:

   464

		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   465

		break;

   466

	}

   467

   468

	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   469

	 * device.  Later controllers reload the EEPROM automatically, so just wait

   470

	 * for reload to complete.

   471

	 */

   472

	switch (hw->mac_type) {

   473

	case e1000_82542_rev2_0:

   474

	case e1000_82542_rev2_1:

   475

	case e1000_82543:

   476

	case e1000_82544:

   477

		/* Wait for reset to complete */

   478

		udelay(10);

   479

		ctrl_ext = er32(CTRL_EXT);

   480

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   481

		ew32(CTRL_EXT, ctrl_ext);

   482

		E1000_WRITE_FLUSH();

   483

		/* Wait for EEPROM reload */

   484

		msleep(2);

   485

		break;

   486

	case e1000_82541:

   487

	case e1000_82541_rev_2:

   488

	case e1000_82547:

   489

	case e1000_82547_rev_2:

   490

		/* Wait for EEPROM reload */

   491

		msleep(20);

   492

		break;

   493

	default:

   494

		/* Auto read done will delay 5ms or poll based on mac type */

   495

		ret_val = e1000_get_auto_rd_done(hw);

   496

		if (ret_val)

   497

			return ret_val;

   498

		break;

   499

	}

   500

   501

	/* Disable HW ARPs on ASF enabled adapters */

   502

	if (hw->mac_type >= e1000_82540) {

   503

		manc = er32(MANC);

   504

		manc &= ~(E1000_MANC_ARP_EN);

   505

		ew32(MANC, manc);

   506

	}

   507

   508

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   509

		e1000_phy_init_script(hw);

   510

   511

		/* Configure activity LED after PHY reset */

   512

		led_ctrl = er32(LEDCTL);

   513

		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   514

		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   515

		ew32(LEDCTL, led_ctrl);

   516

	}

   517

   518

	/* Clear interrupt mask to stop board from generating interrupts */

   519

	DEBUGOUT("Masking off all interrupts\n");

   520

	ew32(IMC, 0xffffffff);

   521

   522

	/* Clear any pending interrupt events. */

   523

	icr = er32(ICR);

   524

   525

	/* If MWI was previously enabled, reenable it. */

   526

	if (hw->mac_type == e1000_82542_rev2_0) {

   527

		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   528

			e1000_pci_set_mwi(hw);

   529

	}

   530