| author | Florian Pose <fp@igh-essen.com> |
| Thu, 03 Jun 2010 14:36:41 +0200 | |
| changeset 1940 | 6da49560e675 |
| parent 1376 | 6b51a2201d41 |
| child 2251 | 5023ce75fe91 |
| permissions | -rw-r--r-- |
| 1353 | 1 |
/* |
2 |
* r8169.c: RealTek 8169/8168/8101 ethernet driver. |
|
3 |
* |
|
4 |
* Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
|
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* Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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* Copyright (c) a lot of people too. Please respect their work. |
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* |
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* See MAINTAINERS file for support contact information. |
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* |
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* vim: noexpandtab |
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*/ |
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12 |
||
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#include <linux/module.h> |
|
14 |
#include <linux/moduleparam.h> |
|
15 |
#include <linux/pci.h> |
|
16 |
#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/delay.h> |
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#include <linux/ethtool.h> |
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#include <linux/mii.h> |
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#include <linux/if_vlan.h> |
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#include <linux/crc32.h> |
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#include <linux/in.h> |
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#include <linux/ip.h> |
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#include <linux/tcp.h> |
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#include <linux/init.h> |
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#include <linux/dma-mapping.h> |
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28 |
||
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#include <asm/system.h> |
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#include <asm/io.h> |
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#include <asm/irq.h> |
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32 |
||
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#include "../globals.h" |
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#include "ecdev.h" |
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||
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#ifdef CONFIG_R8169_NAPI |
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#define NAPI_SUFFIX "-NAPI" |
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#else |
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#define NAPI_SUFFIX "" |
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#endif |
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||
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#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX |
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#define MODULENAME "ec_r8169" |
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#define PFX MODULENAME ": " |
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45 |
||
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#ifdef RTL8169_DEBUG |
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#define assert(expr) \ |
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if (!(expr)) { \
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printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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#expr,__FILE__,__FUNCTION__,__LINE__); \ |
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} |
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#define dprintk(fmt, args...) \ |
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do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
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#else |
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#define assert(expr) do {} while (0)
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#define dprintk(fmt, args...) do {} while (0)
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#endif /* RTL8169_DEBUG */ |
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||
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#define R8169_MSG_DEFAULT \ |
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(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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61 |
||
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#define TX_BUFFS_AVAIL(tp) \ |
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(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
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||
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#ifdef CONFIG_R8169_NAPI |
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#define rtl8169_rx_skb netif_receive_skb |
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#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb |
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#define rtl8169_rx_quota(count, quota) min(count, quota) |
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#else |
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#define rtl8169_rx_skb netif_rx |
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#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx |
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#define rtl8169_rx_quota(count, quota) count |
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#endif |
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||
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/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
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static const int max_interrupt_work = 20; |
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/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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static const int multicast_filter_limit = 32; |
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||
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/* MAC address length */ |
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#define MAC_ADDR_LEN 6 |
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||
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#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
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#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
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#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
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#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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||
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#define R8169_REGS_SIZE 256 |
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#define R8169_NAPI_WEIGHT 64 |
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#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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#define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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||
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#define RTL8169_TX_TIMEOUT (6*HZ) |
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#define RTL8169_PHY_TIMEOUT (10*HZ) |
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||
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/* write/read MMIO register */ |
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#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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#define RTL_R8(reg) readb (ioaddr + (reg)) |
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#define RTL_R16(reg) readw (ioaddr + (reg)) |
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#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
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||
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enum mac_version {
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RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
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RTL_GIGA_MAC_VER_02 = 0x02, // 8169S |
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RTL_GIGA_MAC_VER_03 = 0x03, // 8110S |
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RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB |
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RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd |
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RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
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RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
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RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
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RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb |
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RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? |
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RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? |
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RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec |
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RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf |
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RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP |
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RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
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RTL_GIGA_MAC_VER_20 = 0x14 // 8168C |
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}; |
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||
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#define _R(NAME,MAC,MASK) \ |
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{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
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||
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static const struct {
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const char *name; |
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u8 mac_version; |
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u32 RxConfigMask; /* Clears the bits supported by this chip */ |
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} rtl_chip_info[] = {
|
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_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
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_R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
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_R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
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_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
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}; |
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#undef _R |
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||
158 |
enum cfg_version {
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RTL_CFG_0 = 0x00, |
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RTL_CFG_1, |
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RTL_CFG_2 |
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}; |
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||
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static void rtl_hw_start_8169(struct net_device *); |
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static void rtl_hw_start_8168(struct net_device *); |
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static void rtl_hw_start_8101(struct net_device *); |
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||
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static struct pci_device_id rtl8169_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
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{ PCI_VENDOR_ID_LINKSYS, 0x1032,
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PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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{ 0x0001, 0x8168,
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PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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{0,},
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}; |
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||
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/* prevent driver from being loaded automatically */ |
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//MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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||
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static int rx_copybreak = 200; |
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static int use_dac; |
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static struct {
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u32 msg_enable; |
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} debug = { -1 };
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enum rtl_registers {
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MAC0 = 0, /* Ethernet hardware address. */ |
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MAC4 = 4, |
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MAR0 = 8, /* Multicast filter. */ |
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CounterAddrLow = 0x10, |
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CounterAddrHigh = 0x14, |
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TxDescStartAddrLow = 0x20, |
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TxDescStartAddrHigh = 0x24, |
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TxHDescStartAddrLow = 0x28, |
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TxHDescStartAddrHigh = 0x2c, |
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FLASH = 0x30, |
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ERSR = 0x36, |
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ChipCmd = 0x37, |
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TxPoll = 0x38, |
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IntrMask = 0x3c, |
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IntrStatus = 0x3e, |
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TxConfig = 0x40, |
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RxConfig = 0x44, |
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RxMissed = 0x4c, |
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Cfg9346 = 0x50, |
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Config0 = 0x51, |
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Config1 = 0x52, |
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Config2 = 0x53, |
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Config3 = 0x54, |
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Config4 = 0x55, |
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Config5 = 0x56, |
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MultiIntr = 0x5c, |
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PHYAR = 0x60, |
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TBICSR = 0x64, |
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TBI_ANAR = 0x68, |
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TBI_LPAR = 0x6a, |
|
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PHYstatus = 0x6c, |
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RxMaxSize = 0xda, |
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CPlusCmd = 0xe0, |
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IntrMitigate = 0xe2, |
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RxDescAddrLow = 0xe4, |
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RxDescAddrHigh = 0xe8, |
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EarlyTxThres = 0xec, |
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FuncEvent = 0xf0, |
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FuncEventMask = 0xf4, |
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FuncPresetState = 0xf8, |
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FuncForceEvent = 0xfc, |
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}; |
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||
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enum rtl_register_content {
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|
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/* InterruptStatusBits */ |
|
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SYSErr = 0x8000, |
|
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PCSTimeout = 0x4000, |
|
241 |
SWInt = 0x0100, |
|
242 |
TxDescUnavail = 0x0080, |
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243 |
RxFIFOOver = 0x0040, |
|
244 |
LinkChg = 0x0020, |
|
245 |
RxOverflow = 0x0010, |
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TxErr = 0x0008, |
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247 |
TxOK = 0x0004, |
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248 |
RxErr = 0x0002, |
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RxOK = 0x0001, |
|
250 |
||
251 |
/* RxStatusDesc */ |
|
252 |
RxFOVF = (1 << 23), |
|
253 |
RxRWT = (1 << 22), |
|
254 |
RxRES = (1 << 21), |
|
255 |
RxRUNT = (1 << 20), |
|
256 |
RxCRC = (1 << 19), |
|
257 |
||
258 |
/* ChipCmdBits */ |
|
259 |
CmdReset = 0x10, |
|
260 |
CmdRxEnb = 0x08, |
|
261 |
CmdTxEnb = 0x04, |
|
262 |
RxBufEmpty = 0x01, |
|
263 |
||
264 |
/* TXPoll register p.5 */ |
|
265 |
HPQ = 0x80, /* Poll cmd on the high prio queue */ |
|
266 |
NPQ = 0x40, /* Poll cmd on the low prio queue */ |
|
267 |
FSWInt = 0x01, /* Forced software interrupt */ |
|
268 |
||
269 |
/* Cfg9346Bits */ |
|
270 |
Cfg9346_Lock = 0x00, |
|
271 |
Cfg9346_Unlock = 0xc0, |
|
272 |
||
273 |
/* rx_mode_bits */ |
|
274 |
AcceptErr = 0x20, |
|
275 |
AcceptRunt = 0x10, |
|
276 |
AcceptBroadcast = 0x08, |
|
277 |
AcceptMulticast = 0x04, |
|
278 |
AcceptMyPhys = 0x02, |
|
279 |
AcceptAllPhys = 0x01, |
|
280 |
||
281 |
/* RxConfigBits */ |
|
282 |
RxCfgFIFOShift = 13, |
|
283 |
RxCfgDMAShift = 8, |
|
284 |
||
285 |
/* TxConfigBits */ |
|
286 |
TxInterFrameGapShift = 24, |
|
287 |
TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
|
288 |
||
289 |
/* Config1 register p.24 */ |
|
290 |
MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
|
291 |
PMEnable = (1 << 0), /* Power Management Enable */ |
|
292 |
||
293 |
/* Config2 register p. 25 */ |
|
294 |
PCI_Clock_66MHz = 0x01, |
|
295 |
PCI_Clock_33MHz = 0x00, |
|
296 |
||
297 |
/* Config3 register p.25 */ |
|
298 |
MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
|
299 |
LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
|
300 |
||
301 |
/* Config5 register p.27 */ |
|
302 |
BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
|
303 |
MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
|
304 |
UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
|
305 |
LanWake = (1 << 1), /* LanWake enable/disable */ |
|
306 |
PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
|
307 |
||
308 |
/* TBICSR p.28 */ |
|
309 |
TBIReset = 0x80000000, |
|
310 |
TBILoopback = 0x40000000, |
|
311 |
TBINwEnable = 0x20000000, |
|
312 |
TBINwRestart = 0x10000000, |
|
313 |
TBILinkOk = 0x02000000, |
|
314 |
TBINwComplete = 0x01000000, |
|
315 |
||
316 |
/* CPlusCmd p.31 */ |
|
317 |
PktCntrDisable = (1 << 7), // 8168 |
|
318 |
RxVlan = (1 << 6), |
|
319 |
RxChkSum = (1 << 5), |
|
320 |
PCIDAC = (1 << 4), |
|
321 |
PCIMulRW = (1 << 3), |
|
322 |
INTT_0 = 0x0000, // 8168 |
|
323 |
INTT_1 = 0x0001, // 8168 |
|
324 |
INTT_2 = 0x0002, // 8168 |
|
325 |
INTT_3 = 0x0003, // 8168 |
|
326 |
||
327 |
/* rtl8169_PHYstatus */ |
|
328 |
TBI_Enable = 0x80, |
|
329 |
TxFlowCtrl = 0x40, |
|
330 |
RxFlowCtrl = 0x20, |
|
331 |
_1000bpsF = 0x10, |
|
332 |
_100bps = 0x08, |
|
333 |
_10bps = 0x04, |
|
334 |
LinkStatus = 0x02, |
|
335 |
FullDup = 0x01, |
|
336 |
||
337 |
/* _TBICSRBit */ |
|
338 |
TBILinkOK = 0x02000000, |
|
339 |
||
340 |
/* DumpCounterCommand */ |
|
341 |
CounterDump = 0x8, |
|
342 |
}; |
|
343 |
||
344 |
enum desc_status_bit {
|
|
345 |
DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
|
346 |
RingEnd = (1 << 30), /* End of descriptor ring */ |
|
347 |
FirstFrag = (1 << 29), /* First segment of a packet */ |
|
348 |
LastFrag = (1 << 28), /* Final segment of a packet */ |
|
349 |
||
350 |
/* Tx private */ |
|
351 |
LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
|
352 |
MSSShift = 16, /* MSS value position */ |
|
353 |
MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ |
|
354 |
IPCS = (1 << 18), /* Calculate IP checksum */ |
|
355 |
UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ |
|
356 |
TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ |
|
357 |
TxVlanTag = (1 << 17), /* Add VLAN tag */ |
|
358 |
||
359 |
/* Rx private */ |
|
360 |
PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
|
361 |
PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
|
362 |
||
363 |
#define RxProtoUDP (PID1) |
|
364 |
#define RxProtoTCP (PID0) |
|
365 |
#define RxProtoIP (PID1 | PID0) |
|
366 |
#define RxProtoMask RxProtoIP |
|
367 |
||
368 |
IPFail = (1 << 16), /* IP checksum failed */ |
|
369 |
UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
370 |
TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
371 |
RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
372 |
}; |
|
373 |
||
374 |
#define RsvdMask 0x3fffc000 |
|
375 |
||
376 |
struct TxDesc {
|
|
377 |
__le32 opts1; |
|
378 |
__le32 opts2; |
|
379 |
__le64 addr; |
|
380 |
}; |
|
381 |
||
382 |
struct RxDesc {
|
|
383 |
__le32 opts1; |
|
384 |
__le32 opts2; |
|
385 |
__le64 addr; |
|
386 |
}; |
|
387 |
||
388 |
struct ring_info {
|
|
389 |
struct sk_buff *skb; |
|
390 |
u32 len; |
|
391 |
u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
392 |
}; |
|
393 |
||
394 |
enum features {
|
|
395 |
RTL_FEATURE_WOL = (1 << 0), |
|
396 |
RTL_FEATURE_MSI = (1 << 1), |
|
397 |
}; |
|
398 |
||
399 |
struct rtl8169_private {
|
|
400 |
void __iomem *mmio_addr; /* memory map physical address */ |
|
401 |
struct pci_dev *pci_dev; /* Index of PCI device */ |
|
402 |
struct net_device *dev; |
|
403 |
#ifdef CONFIG_R8169_NAPI |
|
404 |
struct napi_struct napi; |
|
405 |
#endif |
|
406 |
spinlock_t lock; /* spin lock flag */ |
|
407 |
u32 msg_enable; |
|
408 |
int chipset; |
|
409 |
int mac_version; |
|
410 |
u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
411 |
u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
412 |
u32 dirty_rx; |
|
413 |
u32 dirty_tx; |
|
414 |
struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
415 |
struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
416 |
dma_addr_t TxPhyAddr; |
|
417 |
dma_addr_t RxPhyAddr; |
|
418 |
struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
419 |
struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
420 |
unsigned align; |
|
421 |
unsigned rx_buf_sz; |
|
422 |
struct timer_list timer; |
|
423 |
u16 cp_cmd; |
|
424 |
u16 intr_event; |
|
425 |
u16 napi_event; |
|
426 |
u16 intr_mask; |
|
427 |
int phy_auto_nego_reg; |
|
428 |
int phy_1000_ctrl_reg; |
|
429 |
#ifdef CONFIG_R8169_VLAN |
|
430 |
struct vlan_group *vlgrp; |
|
431 |
#endif |
|
432 |
int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); |
|
433 |
void (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
434 |
void (*phy_reset_enable)(void __iomem *); |
|
435 |
void (*hw_start)(struct net_device *); |
|
436 |
unsigned int (*phy_reset_pending)(void __iomem *); |
|
437 |
unsigned int (*link_ok)(void __iomem *); |
|
438 |
struct delayed_work task; |
|
439 |
unsigned features; |
|
440 |
||
441 |
ec_device_t *ecdev; |
|
442 |
unsigned long ec_watchdog_jiffies; |
|
443 |
}; |
|
444 |
||
445 |
MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");
|
|
446 |
MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver");
|
|
447 |
module_param(rx_copybreak, int, 0); |
|
448 |
MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
|
449 |
module_param(use_dac, int, 0); |
|
450 |
MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
451 |
module_param_named(debug, debug.msg_enable, int, 0); |
|
452 |
MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
453 |
MODULE_LICENSE("GPL");
|
|
454 |
MODULE_VERSION(EC_MASTER_VERSION); |
|
455 |
||
456 |
static int rtl8169_open(struct net_device *dev); |
|
457 |
static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); |
|
458 |
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
459 |
static int rtl8169_init_ring(struct net_device *dev); |
|
460 |
static void rtl_hw_start(struct net_device *dev); |
|
461 |
static int rtl8169_close(struct net_device *dev); |
|
462 |
static void rtl_set_rx_mode(struct net_device *dev); |
|
463 |
static void rtl8169_tx_timeout(struct net_device *dev); |
|
464 |
static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
|
465 |
static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
466 |
void __iomem *, u32 budget); |
|
467 |
static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
|
468 |
static void rtl8169_down(struct net_device *dev); |
|
469 |
static void rtl8169_rx_clear(struct rtl8169_private *tp); |
|
470 |
||
471 |
#ifdef CONFIG_R8169_NAPI |
|
472 |
static int rtl8169_poll(struct napi_struct *napi, int budget); |
|
473 |
#endif |
|
474 |
||
475 |
static const unsigned int rtl8169_rx_config = |
|
476 |
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
|
477 |
||
478 |
static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
479 |
{
|
|
480 |
int i; |
|
481 |
||
482 |
RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
483 |
||
484 |
for (i = 20; i > 0; i--) {
|
|
485 |
/* |
|
486 |
* Check if the RTL8169 has completed writing to the specified |
|
487 |
* MII register. |
|
488 |
*/ |
|
489 |
if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
490 |
break; |
|
491 |
udelay(25); |
|
492 |
} |
|
493 |
} |
|
494 |
||
495 |
static int mdio_read(void __iomem *ioaddr, int reg_addr) |
|
496 |
{
|
|
497 |
int i, value = -1; |
|
498 |
||
499 |
RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
500 |
||
501 |
for (i = 20; i > 0; i--) {
|
|
502 |
/* |
|
503 |
* Check if the RTL8169 has completed retrieving data from |
|
504 |
* the specified MII register. |
|
505 |
*/ |
|
506 |
if (RTL_R32(PHYAR) & 0x80000000) {
|
|
507 |
value = RTL_R32(PHYAR) & 0xffff; |
|
508 |
break; |
|
509 |
} |
|
510 |
udelay(25); |
|
511 |
} |
|
512 |
return value; |
|
513 |
} |
|
514 |
||
515 |
static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
|
516 |
{
|
|
517 |
RTL_W16(IntrMask, 0x0000); |
|
518 |
||
519 |
RTL_W16(IntrStatus, 0xffff); |
|
520 |
} |
|
521 |
||
522 |
static void rtl8169_asic_down(void __iomem *ioaddr) |
|
523 |
{
|
|
524 |
RTL_W8(ChipCmd, 0x00); |
|
525 |
rtl8169_irq_mask_and_ack(ioaddr); |
|
526 |
RTL_R16(CPlusCmd); |
|
527 |
} |
|
528 |
||
529 |
static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) |
|
530 |
{
|
|
531 |
return RTL_R32(TBICSR) & TBIReset; |
|
532 |
} |
|
533 |
||
534 |
static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) |
|
535 |
{
|
|
536 |
return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
|
537 |
} |
|
538 |
||
539 |
static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
540 |
{
|
|
541 |
return RTL_R32(TBICSR) & TBILinkOk; |
|
542 |
} |
|
543 |
||
544 |
static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
545 |
{
|
|
546 |
return RTL_R8(PHYstatus) & LinkStatus; |
|
547 |
} |
|
548 |
||
549 |
static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) |
|
550 |
{
|
|
551 |
RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
552 |
} |
|
553 |
||
554 |
static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) |
|
555 |
{
|
|
556 |
unsigned int val; |
|
557 |
||
558 |
val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
|
559 |
mdio_write(ioaddr, MII_BMCR, val & 0xffff); |
|
560 |
} |
|
561 |
||
562 |
static void rtl8169_check_link_status(struct net_device *dev, |
|
563 |
struct rtl8169_private *tp, |
|
564 |
void __iomem *ioaddr) |
|
565 |
{
|
|
566 |
unsigned long flags; |
|
567 |
||
568 |
if (tp->ecdev) {
|
|
569 |
ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
570 |
} else {
|
|
571 |
spin_lock_irqsave(&tp->lock, flags); |
|
572 |
if (tp->link_ok(ioaddr)) {
|
|
573 |
netif_carrier_on(dev); |
|
574 |
if (netif_msg_ifup(tp)) |
|
575 |
printk(KERN_INFO PFX "%s: link up\n", dev->name); |
|
576 |
} else {
|
|
577 |
if (netif_msg_ifdown(tp)) |
|
578 |
printk(KERN_INFO PFX "%s: link down\n", dev->name); |
|
579 |
netif_carrier_off(dev); |
|
580 |
} |
|
581 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
582 |
} |
|
583 |
} |
|
584 |
||
585 |
static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
586 |
{
|
|
587 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
588 |
void __iomem *ioaddr = tp->mmio_addr; |
|
589 |
u8 options; |
|
590 |
||
591 |
wol->wolopts = 0; |
|
592 |
||
593 |
#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
594 |
wol->supported = WAKE_ANY; |
|
595 |
||
596 |
spin_lock_irq(&tp->lock); |
|
597 |
||
598 |
options = RTL_R8(Config1); |
|
599 |
if (!(options & PMEnable)) |
|
600 |
goto out_unlock; |
|
601 |
||
602 |
options = RTL_R8(Config3); |
|
603 |
if (options & LinkUp) |
|
604 |
wol->wolopts |= WAKE_PHY; |
|
605 |
if (options & MagicPacket) |
|
606 |
wol->wolopts |= WAKE_MAGIC; |
|
607 |
||
608 |
options = RTL_R8(Config5); |
|
609 |
if (options & UWF) |
|
610 |
wol->wolopts |= WAKE_UCAST; |
|
611 |
if (options & BWF) |
|
612 |
wol->wolopts |= WAKE_BCAST; |
|
613 |
if (options & MWF) |
|
614 |
wol->wolopts |= WAKE_MCAST; |
|
615 |
||
616 |
out_unlock: |
|
617 |
spin_unlock_irq(&tp->lock); |
|
618 |
} |
|
619 |
||
620 |
static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
621 |
{
|
|
622 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
623 |
void __iomem *ioaddr = tp->mmio_addr; |
|
624 |
unsigned int i; |
|
625 |
static struct {
|
|
626 |
u32 opt; |
|
627 |
u16 reg; |
|
628 |
u8 mask; |
|
629 |
} cfg[] = {
|
|
630 |
{ WAKE_ANY, Config1, PMEnable },
|
|
631 |
{ WAKE_PHY, Config3, LinkUp },
|
|
632 |
{ WAKE_MAGIC, Config3, MagicPacket },
|
|
633 |
{ WAKE_UCAST, Config5, UWF },
|
|
634 |
{ WAKE_BCAST, Config5, BWF },
|
|
635 |
{ WAKE_MCAST, Config5, MWF },
|
|
636 |
{ WAKE_ANY, Config5, LanWake }
|
|
637 |
}; |
|
638 |
||
639 |
spin_lock_irq(&tp->lock); |
|
640 |
||
641 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
642 |
||
643 |
for (i = 0; i < ARRAY_SIZE(cfg); i++) {
|
|
644 |
u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
645 |
if (wol->wolopts & cfg[i].opt) |
|
646 |
options |= cfg[i].mask; |
|
647 |
RTL_W8(cfg[i].reg, options); |
|
648 |
} |
|
649 |
||
650 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
|
651 |
||
652 |
if (wol->wolopts) |
|
653 |
tp->features |= RTL_FEATURE_WOL; |
|
654 |
else |
|
655 |
tp->features &= ~RTL_FEATURE_WOL; |
|
656 |
||
657 |
spin_unlock_irq(&tp->lock); |
|
658 |
||
659 |
return 0; |
|
660 |
} |
|
661 |
||
662 |
static void rtl8169_get_drvinfo(struct net_device *dev, |
|
663 |
struct ethtool_drvinfo *info) |
|
664 |
{
|
|
665 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
666 |
||
667 |
strcpy(info->driver, MODULENAME); |
|
668 |
strcpy(info->version, RTL8169_VERSION); |
|
669 |
strcpy(info->bus_info, pci_name(tp->pci_dev)); |
|
670 |
} |
|
671 |
||
672 |
static int rtl8169_get_regs_len(struct net_device *dev) |
|
673 |
{
|
|
674 |
return R8169_REGS_SIZE; |
|
675 |
} |
|
676 |
||
677 |
static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
678 |
u8 autoneg, u16 speed, u8 duplex) |
|
679 |
{
|
|
680 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
681 |
void __iomem *ioaddr = tp->mmio_addr; |
|
682 |
int ret = 0; |
|
683 |
u32 reg; |
|
684 |
||
685 |
reg = RTL_R32(TBICSR); |
|
686 |
if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
687 |
(duplex == DUPLEX_FULL)) {
|
|
688 |
RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
689 |
} else if (autoneg == AUTONEG_ENABLE) |
|
690 |
RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
691 |
else {
|
|
692 |
if (netif_msg_link(tp)) {
|
|
693 |
printk(KERN_WARNING "%s: " |
|
694 |
"incorrect speed setting refused in TBI mode\n", |
|
695 |
dev->name); |
|
696 |
} |
|
697 |
ret = -EOPNOTSUPP; |
|
698 |
} |
|
699 |
||
700 |
return ret; |
|
701 |
} |
|
702 |
||
703 |
static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
704 |
u8 autoneg, u16 speed, u8 duplex) |
|
705 |
{
|
|
706 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
707 |
void __iomem *ioaddr = tp->mmio_addr; |
|
708 |
int auto_nego, giga_ctrl; |
|
709 |
||
710 |
auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
|
711 |
auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
712 |
ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
713 |
giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
|
714 |
giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
715 |
||
716 |
if (autoneg == AUTONEG_ENABLE) {
|
|
717 |
auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
718 |
ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
719 |
giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
720 |
} else {
|
|
721 |
if (speed == SPEED_10) |
|
722 |
auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
|
723 |
else if (speed == SPEED_100) |
|
724 |
auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
|
725 |
else if (speed == SPEED_1000) |
|
726 |
giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
727 |
||
728 |
if (duplex == DUPLEX_HALF) |
|
729 |
auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); |
|
730 |
||
731 |
if (duplex == DUPLEX_FULL) |
|
732 |
auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); |
|
733 |
||
734 |
/* This tweak comes straight from Realtek's driver. */ |
|
735 |
if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && |
|
736 |
((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
737 |
(tp->mac_version == RTL_GIGA_MAC_VER_16))) {
|
|
738 |
auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; |
|
739 |
} |
|
740 |
} |
|
741 |
||
742 |
/* The 8100e/8101e do Fast Ethernet only. */ |
|
743 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
744 |
(tp->mac_version == RTL_GIGA_MAC_VER_14) || |
|
745 |
(tp->mac_version == RTL_GIGA_MAC_VER_15) || |
|
746 |
(tp->mac_version == RTL_GIGA_MAC_VER_16)) {
|
|
747 |
if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && |
|
748 |
netif_msg_link(tp)) {
|
|
749 |
printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
|
750 |
dev->name); |
|
751 |
} |
|
752 |
giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
753 |
} |
|
754 |
||
755 |
auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
756 |
||
757 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
758 |
(tp->mac_version == RTL_GIGA_MAC_VER_17)) {
|
|
759 |
/* Vendor specific (0x1f) and reserved (0x0e) MII registers. */ |
|
760 |
mdio_write(ioaddr, 0x1f, 0x0000); |
|
761 |
mdio_write(ioaddr, 0x0e, 0x0000); |
|
762 |
} |
|
763 |
||
764 |
tp->phy_auto_nego_reg = auto_nego; |
|
765 |
tp->phy_1000_ctrl_reg = giga_ctrl; |
|
766 |
||
767 |
mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
|
768 |
mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); |
|
769 |
mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); |
|
770 |
return 0; |
|
771 |
} |
|
772 |
||
773 |
static int rtl8169_set_speed(struct net_device *dev, |
|
774 |
u8 autoneg, u16 speed, u8 duplex) |
|
775 |
{
|
|
776 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
777 |
int ret; |
|
778 |
||
779 |
ret = tp->set_speed(dev, autoneg, speed, duplex); |
|
780 |
||
781 |
if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
782 |
mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
783 |
||
784 |
return ret; |
|
785 |
} |
|
786 |
||
787 |
static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
788 |
{
|
|
789 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
790 |
unsigned long flags; |
|
791 |
int ret; |
|
792 |
||
793 |
spin_lock_irqsave(&tp->lock, flags); |
|
794 |
ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); |
|
795 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
796 |
||
797 |
return ret; |
|
798 |
} |
|
799 |
||
800 |
static u32 rtl8169_get_rx_csum(struct net_device *dev) |
|
801 |
{
|
|
802 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
803 |
||
804 |
return tp->cp_cmd & RxChkSum; |
|
805 |
} |
|
806 |
||
807 |
static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) |
|
808 |
{
|
|
809 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
810 |
void __iomem *ioaddr = tp->mmio_addr; |
|
811 |
unsigned long flags; |
|
812 |
||
813 |
spin_lock_irqsave(&tp->lock, flags); |
|
814 |
||
815 |
if (data) |
|
816 |
tp->cp_cmd |= RxChkSum; |
|
817 |
else |
|
818 |
tp->cp_cmd &= ~RxChkSum; |
|
819 |
||
820 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
821 |
RTL_R16(CPlusCmd); |
|
822 |
||
823 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
824 |
||
825 |
return 0; |
|
826 |
} |
|
827 |
||
828 |
#ifdef CONFIG_R8169_VLAN |
|
829 |
||
830 |
static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
831 |
struct sk_buff *skb) |
|
832 |
{
|
|
833 |
return (tp->vlgrp && vlan_tx_tag_present(skb)) ? |
|
834 |
TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
835 |
} |
|
836 |
||
837 |
static void rtl8169_vlan_rx_register(struct net_device *dev, |
|
838 |
struct vlan_group *grp) |
|
839 |
{
|
|
840 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
841 |
void __iomem *ioaddr = tp->mmio_addr; |
|
842 |
unsigned long flags; |
|
843 |
||
844 |
spin_lock_irqsave(&tp->lock, flags); |
|
845 |
tp->vlgrp = grp; |
|
846 |
if (tp->vlgrp) |
|
847 |
tp->cp_cmd |= RxVlan; |
|
848 |
else |
|
849 |
tp->cp_cmd &= ~RxVlan; |
|
850 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
851 |
RTL_R16(CPlusCmd); |
|
852 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
853 |
} |
|
854 |
||
855 |
static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
856 |
struct sk_buff *skb) |
|
857 |
{
|
|
858 |
u32 opts2 = le32_to_cpu(desc->opts2); |
|
859 |
int ret; |
|
860 |
||
861 |
if (tp->vlgrp && (opts2 & RxVlanTag)) {
|
|
862 |
rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff)); |
|
863 |
ret = 0; |
|
864 |
} else |
|
865 |
ret = -1; |
|
866 |
desc->opts2 = 0; |
|
867 |
return ret; |
|
868 |
} |
|
869 |
||
870 |
#else /* !CONFIG_R8169_VLAN */ |
|
871 |
||
872 |
static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
873 |
struct sk_buff *skb) |
|
874 |
{
|
|
875 |
return 0; |
|
876 |
} |
|
877 |
||
878 |
static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
879 |
struct sk_buff *skb) |
|
880 |
{
|
|
881 |
return -1; |
|
882 |
} |
|
883 |
||
884 |
#endif |
|
885 |
||
886 |
static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
887 |
{
|
|
888 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
889 |
void __iomem *ioaddr = tp->mmio_addr; |
|
890 |
u32 status; |
|
891 |
||
892 |
cmd->supported = |
|
893 |
SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
894 |
cmd->port = PORT_FIBRE; |
|
895 |
cmd->transceiver = XCVR_INTERNAL; |
|
896 |
||
897 |
status = RTL_R32(TBICSR); |
|
898 |
cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
899 |
cmd->autoneg = !!(status & TBINwEnable); |
|
900 |
||
901 |
cmd->speed = SPEED_1000; |
|
902 |
cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
903 |
} |
|
904 |
||
905 |
static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
906 |
{
|
|
907 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
908 |
void __iomem *ioaddr = tp->mmio_addr; |
|
909 |
u8 status; |
|
910 |
||
911 |
cmd->supported = SUPPORTED_10baseT_Half | |
|
912 |
SUPPORTED_10baseT_Full | |
|
913 |
SUPPORTED_100baseT_Half | |
|
914 |
SUPPORTED_100baseT_Full | |
|
915 |
SUPPORTED_1000baseT_Full | |
|
916 |
SUPPORTED_Autoneg | |
|
917 |
SUPPORTED_TP; |
|
918 |
||
919 |
cmd->autoneg = 1; |
|
920 |
cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg; |
|
921 |
||
922 |
if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) |
|
923 |
cmd->advertising |= ADVERTISED_10baseT_Half; |
|
924 |
if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) |
|
925 |
cmd->advertising |= ADVERTISED_10baseT_Full; |
|
926 |
if (tp->phy_auto_nego_reg & ADVERTISE_100HALF) |
|
927 |
cmd->advertising |= ADVERTISED_100baseT_Half; |
|
928 |
if (tp->phy_auto_nego_reg & ADVERTISE_100FULL) |
|
929 |
cmd->advertising |= ADVERTISED_100baseT_Full; |
|
930 |
if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) |
|
931 |
cmd->advertising |= ADVERTISED_1000baseT_Full; |
|
932 |
||
933 |
status = RTL_R8(PHYstatus); |
|
934 |
||
935 |
if (status & _1000bpsF) |
|
936 |
cmd->speed = SPEED_1000; |
|
937 |
else if (status & _100bps) |
|
938 |
cmd->speed = SPEED_100; |
|
939 |
else if (status & _10bps) |
|
940 |
cmd->speed = SPEED_10; |
|
941 |
||
942 |
if (status & TxFlowCtrl) |
|
943 |
cmd->advertising |= ADVERTISED_Asym_Pause; |
|
944 |
if (status & RxFlowCtrl) |
|
945 |
cmd->advertising |= ADVERTISED_Pause; |
|
946 |
||
947 |
cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ? |
|
948 |
DUPLEX_FULL : DUPLEX_HALF; |
|
949 |
} |
|
950 |
||
951 |
static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
952 |
{
|
|
953 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
954 |
unsigned long flags; |
|
955 |
||
956 |
spin_lock_irqsave(&tp->lock, flags); |
|
957 |
||
958 |
tp->get_settings(dev, cmd); |
|
959 |
||
960 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
961 |
return 0; |
|
962 |
} |
|
963 |
||
964 |
static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
965 |
void *p) |
|
966 |
{
|
|
967 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
968 |
unsigned long flags; |
|
969 |
||
970 |
if (regs->len > R8169_REGS_SIZE) |
|
971 |
regs->len = R8169_REGS_SIZE; |
|
972 |
||
973 |
spin_lock_irqsave(&tp->lock, flags); |
|
974 |
memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
975 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
976 |
} |
|
977 |
||
978 |
static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
979 |
{
|
|
980 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
981 |
||
982 |
return tp->msg_enable; |
|
983 |
} |
|
984 |
||
985 |
static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
986 |
{
|
|
987 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
988 |
||
989 |
tp->msg_enable = value; |
|
990 |
} |
|
991 |
||
992 |
static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
|
|
993 |
"tx_packets", |
|
994 |
"rx_packets", |
|
995 |
"tx_errors", |
|
996 |
"rx_errors", |
|
997 |
"rx_missed", |
|
998 |
"align_errors", |
|
999 |
"tx_single_collisions", |
|
1000 |
"tx_multi_collisions", |
|
1001 |
"unicast", |
|
1002 |
"broadcast", |
|
1003 |
"multicast", |
|
1004 |
"tx_aborted", |
|
1005 |
"tx_underrun", |
|
1006 |
}; |
|
1007 |
||
1008 |
struct rtl8169_counters {
|
|
1009 |
__le64 tx_packets; |
|
1010 |
__le64 rx_packets; |
|
1011 |
__le64 tx_errors; |
|
1012 |
__le32 rx_errors; |
|
1013 |
__le16 rx_missed; |
|
1014 |
__le16 align_errors; |
|
1015 |
__le32 tx_one_collision; |
|
1016 |
__le32 tx_multi_collision; |
|
1017 |
__le64 rx_unicast; |
|
1018 |
__le64 rx_broadcast; |
|
1019 |
__le32 rx_multicast; |
|
1020 |
__le16 tx_aborted; |
|
1021 |
__le16 tx_underun; |
|
1022 |
}; |
|
1023 |
||
1024 |
static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1025 |
{
|
|
1026 |
switch (sset) {
|
|
1027 |
case ETH_SS_STATS: |
|
1028 |
return ARRAY_SIZE(rtl8169_gstrings); |
|
1029 |
default: |
|
1030 |
return -EOPNOTSUPP; |
|
1031 |
} |
|
1032 |
} |
|
1033 |
||
1034 |
static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1035 |
struct ethtool_stats *stats, u64 *data) |
|
1036 |
{
|
|
1037 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1038 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1039 |
struct rtl8169_counters *counters; |
|
1040 |
dma_addr_t paddr; |
|
1041 |
u32 cmd; |
|
1042 |
||
1043 |
ASSERT_RTNL(); |
|
1044 |
||
1045 |
counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); |
|
1046 |
if (!counters) |
|
1047 |
return; |
|
1048 |
||
1049 |
RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1050 |
cmd = (u64)paddr & DMA_32BIT_MASK; |
|
1051 |
RTL_W32(CounterAddrLow, cmd); |
|
1052 |
RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1053 |
||
1054 |
while (RTL_R32(CounterAddrLow) & CounterDump) {
|
|
1055 |
if (msleep_interruptible(1)) |
|
1056 |
break; |
|
1057 |
} |
|
1058 |
||
1059 |
RTL_W32(CounterAddrLow, 0); |
|
1060 |
RTL_W32(CounterAddrHigh, 0); |
|
1061 |
||
1062 |
data[0] = le64_to_cpu(counters->tx_packets); |
|
1063 |
data[1] = le64_to_cpu(counters->rx_packets); |
|
1064 |
data[2] = le64_to_cpu(counters->tx_errors); |
|
1065 |
data[3] = le32_to_cpu(counters->rx_errors); |
|
1066 |
data[4] = le16_to_cpu(counters->rx_missed); |
|
1067 |
data[5] = le16_to_cpu(counters->align_errors); |
|
1068 |
data[6] = le32_to_cpu(counters->tx_one_collision); |
|
1069 |
data[7] = le32_to_cpu(counters->tx_multi_collision); |
|
1070 |
data[8] = le64_to_cpu(counters->rx_unicast); |
|
1071 |
data[9] = le64_to_cpu(counters->rx_broadcast); |
|
1072 |
data[10] = le32_to_cpu(counters->rx_multicast); |
|
1073 |
data[11] = le16_to_cpu(counters->tx_aborted); |
|
1074 |
data[12] = le16_to_cpu(counters->tx_underun); |
|
1075 |
||
1076 |
pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); |
|
1077 |
} |
|
1078 |
||
1079 |
static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1080 |
{
|
|
1081 |
switch(stringset) {
|
|
1082 |
case ETH_SS_STATS: |
|
1083 |
memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1084 |
break; |
|
1085 |
} |
|
1086 |
} |
|
1087 |
||
1088 |
static const struct ethtool_ops rtl8169_ethtool_ops = {
|
|
1089 |
.get_drvinfo = rtl8169_get_drvinfo, |
|
1090 |
.get_regs_len = rtl8169_get_regs_len, |
|
1091 |
.get_link = ethtool_op_get_link, |
|
1092 |
.get_settings = rtl8169_get_settings, |
|
1093 |
.set_settings = rtl8169_set_settings, |
|
1094 |
.get_msglevel = rtl8169_get_msglevel, |
|
1095 |
.set_msglevel = rtl8169_set_msglevel, |
|
1096 |
.get_rx_csum = rtl8169_get_rx_csum, |
|
1097 |
.set_rx_csum = rtl8169_set_rx_csum, |
|
1098 |
.set_tx_csum = ethtool_op_set_tx_csum, |
|
1099 |
.set_sg = ethtool_op_set_sg, |
|
1100 |
.set_tso = ethtool_op_set_tso, |
|
1101 |
.get_regs = rtl8169_get_regs, |
|
1102 |
.get_wol = rtl8169_get_wol, |
|
1103 |
.set_wol = rtl8169_set_wol, |
|
1104 |
.get_strings = rtl8169_get_strings, |
|
1105 |
.get_sset_count = rtl8169_get_sset_count, |
|
1106 |
.get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1107 |
}; |
|
1108 |
||
1109 |
static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
|
1110 |
int bitnum, int bitval) |
|
1111 |
{
|
|
1112 |
int val; |
|
1113 |
||
1114 |
val = mdio_read(ioaddr, reg); |
|
1115 |
val = (bitval == 1) ? |
|
1116 |
val | (bitval << bitnum) : val & ~(0x0001 << bitnum); |
|
1117 |
mdio_write(ioaddr, reg, val & 0xffff); |
|
1118 |
} |
|
1119 |
||
1120 |
static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1121 |
void __iomem *ioaddr) |
|
1122 |
{
|
|
1123 |
/* |
|
1124 |
* The driver currently handles the 8168Bf and the 8168Be identically |
|
1125 |
* but they can be identified more specifically through the test below |
|
1126 |
* if needed: |
|
1127 |
* |
|
1128 |
* (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1129 |
* |
|
1130 |
* Same thing for the 8101Eb and the 8101Ec: |
|
1131 |
* |
|
1132 |
* (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1133 |
*/ |
|
1134 |
const struct {
|
|
1135 |
u32 mask; |
|
1136 |
u32 val; |
|
1137 |
int mac_version; |
|
1138 |
} mac_info[] = {
|
|
1139 |
/* 8168B family. */ |
|
1140 |
{ 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
|
|
1141 |
{ 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
|
|
1142 |
{ 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
|
|
1143 |
{ 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
|
|
1144 |
||
1145 |
/* 8168B family. */ |
|
1146 |
{ 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
|
|
1147 |
{ 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
|
|
1148 |
{ 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
|
|
1149 |
{ 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
|
|
1150 |
||
1151 |
/* 8101 family. */ |
|
1152 |
{ 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
|
|
1153 |
{ 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
|
|
1154 |
{ 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
|
|
1155 |
/* FIXME: where did these entries come from ? -- FR */ |
|
1156 |
{ 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
|
|
1157 |
{ 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
|
|
1158 |
||
1159 |
/* 8110 family. */ |
|
1160 |
{ 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
|
|
1161 |
{ 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
|
|
1162 |
{ 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
|
|
1163 |
{ 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
|
|
1164 |
{ 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
|
|
1165 |
{ 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
|
|
1166 |
||
1167 |
{ 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
|
|
1168 |
}, *p = mac_info; |
|
1169 |
u32 reg; |
|
1170 |
||
1171 |
reg = RTL_R32(TxConfig); |
|
1172 |
while ((reg & p->mask) != p->val) |
|
1173 |
p++; |
|
1174 |
tp->mac_version = p->mac_version; |
|
1175 |
||
1176 |
if (p->mask == 0x00000000) {
|
|
1177 |
struct pci_dev *pdev = tp->pci_dev; |
|
1178 |
||
1179 |
dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg); |
|
1180 |
} |
|
1181 |
} |
|
1182 |
||
1183 |
static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1184 |
{
|
|
1185 |
dprintk("mac_version = 0x%02x\n", tp->mac_version);
|
|
1186 |
} |
|
1187 |
||
1188 |
struct phy_reg {
|
|
1189 |
u16 reg; |
|
1190 |
u16 val; |
|
1191 |
}; |
|
1192 |
||
1193 |
static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) |
|
1194 |
{
|
|
1195 |
while (len-- > 0) {
|
|
1196 |
mdio_write(ioaddr, regs->reg, regs->val); |
|
1197 |
regs++; |
|
1198 |
} |
|
1199 |
} |
|
1200 |
||
1201 |
static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
|
1202 |
{
|
|
1203 |
struct {
|
|
1204 |
u16 regs[5]; /* Beware of bit-sign propagation */ |
|
1205 |
} phy_magic[5] = { {
|
|
1206 |
{ 0x0000, //w 4 15 12 0
|
|
1207 |
0x00a1, //w 3 15 0 00a1 |
|
1208 |
0x0008, //w 2 15 0 0008 |
|
1209 |
0x1020, //w 1 15 0 1020 |
|
1210 |
0x1000 } },{ //w 0 15 0 1000
|
|
1211 |
{ 0x7000, //w 4 15 12 7
|
|
1212 |
0xff41, //w 3 15 0 ff41 |
|
1213 |
0xde60, //w 2 15 0 de60 |
|
1214 |
0x0140, //w 1 15 0 0140 |
|
1215 |
0x0077 } },{ //w 0 15 0 0077
|
|
1216 |
{ 0xa000, //w 4 15 12 a
|
|
1217 |
0xdf01, //w 3 15 0 df01 |
|
1218 |
0xdf20, //w 2 15 0 df20 |
|
1219 |
0xff95, //w 1 15 0 ff95 |
|
1220 |
0xfa00 } },{ //w 0 15 0 fa00
|
|
1221 |
{ 0xb000, //w 4 15 12 b
|
|
1222 |
0xff41, //w 3 15 0 ff41 |
|
1223 |
0xde20, //w 2 15 0 de20 |
|
1224 |
0x0140, //w 1 15 0 0140 |
|
1225 |
0x00bb } },{ //w 0 15 0 00bb
|
|
1226 |
{ 0xf000, //w 4 15 12 f
|
|
1227 |
0xdf01, //w 3 15 0 df01 |
|
1228 |
0xdf20, //w 2 15 0 df20 |
|
1229 |
0xff95, //w 1 15 0 ff95 |
|
1230 |
0xbf00 } //w 0 15 0 bf00 |
|
1231 |
} |
|
1232 |
}, *p = phy_magic; |
|
1233 |
unsigned int i; |
|
1234 |
||
1235 |
mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 |
|
1236 |
mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 |
|
1237 |
mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 |
|
1238 |
rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1239 |
||
1240 |
for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
|
|
1241 |
int val, pos = 4; |
|
1242 |
||
1243 |
val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); |
|
1244 |
mdio_write(ioaddr, pos, val); |
|
1245 |
while (--pos >= 0) |
|
1246 |
mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); |
|
1247 |
rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 |
|
1248 |
rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1249 |
} |
|
1250 |
mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 |
|
1251 |
} |
|
1252 |
||
1253 |
static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
|
1254 |
{
|
|
1255 |
struct phy_reg phy_reg_init[] = {
|
|
1256 |
{ 0x1f, 0x0002 },
|
|
1257 |
{ 0x01, 0x90d0 },
|
|
1258 |
{ 0x1f, 0x0000 }
|
|
1259 |
}; |
|
1260 |
||
1261 |
rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1262 |
} |
|
1263 |
||
1264 |
static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) |
|
1265 |
{
|
|
1266 |
struct phy_reg phy_reg_init[] = {
|
|
1267 |
{ 0x1f, 0x0000 },
|
|
1268 |
{ 0x1d, 0x0f00 },
|
|
1269 |
{ 0x1f, 0x0002 },
|
|
1270 |
{ 0x0c, 0x1ec8 },
|
|
1271 |
{ 0x1f, 0x0000 }
|
|
1272 |
}; |
|
1273 |
||
1274 |
rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1275 |
} |
|
1276 |
||
1277 |
static void rtl8168c_hw_phy_config(void __iomem *ioaddr) |
|
1278 |
{
|
|
1279 |
struct phy_reg phy_reg_init[] = {
|
|
1280 |
{ 0x1f, 0x0001 },
|
|
1281 |
{ 0x12, 0x2300 },
|
|
1282 |
{ 0x1f, 0x0002 },
|
|
1283 |
{ 0x00, 0x88d4 },
|
|
1284 |
{ 0x01, 0x82b1 },
|
|
1285 |
{ 0x03, 0x7002 },
|
|
1286 |
{ 0x08, 0x9e30 },
|
|
1287 |
{ 0x09, 0x01f0 },
|
|
1288 |
{ 0x0a, 0x5500 },
|
|
1289 |
{ 0x0c, 0x00c8 },
|
|
1290 |
{ 0x1f, 0x0003 },
|
|
1291 |
{ 0x12, 0xc096 },
|
|
1292 |
{ 0x16, 0x000a },
|
|
1293 |
{ 0x1f, 0x0000 }
|
|
1294 |
}; |
|
1295 |
||
1296 |
rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1297 |
} |
|
1298 |
||
1299 |
static void rtl8168cx_hw_phy_config(void __iomem *ioaddr) |
|
1300 |
{
|
|
1301 |
struct phy_reg phy_reg_init[] = {
|
|
1302 |
{ 0x1f, 0x0000 },
|
|
1303 |
{ 0x12, 0x2300 },
|
|
1304 |
{ 0x1f, 0x0003 },
|
|
1305 |
{ 0x16, 0x0f0a },
|
|
1306 |
{ 0x1f, 0x0000 },
|
|
1307 |
{ 0x1f, 0x0002 },
|
|
1308 |
{ 0x0c, 0x7eb8 },
|
|
1309 |
{ 0x1f, 0x0000 }
|
|
1310 |
}; |
|
1311 |
||
1312 |
rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1313 |
} |
|
1314 |
||
1315 |
static void rtl_hw_phy_config(struct net_device *dev) |
|
1316 |
{
|
|
1317 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1318 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1319 |
||
1320 |
rtl8169_print_mac_version(tp); |
|
1321 |
||
1322 |
switch (tp->mac_version) {
|
|
1323 |
case RTL_GIGA_MAC_VER_01: |
|
1324 |
break; |
|
1325 |
case RTL_GIGA_MAC_VER_02: |
|
1326 |
case RTL_GIGA_MAC_VER_03: |
|
1327 |
rtl8169s_hw_phy_config(ioaddr); |
|
1328 |
break; |
|
1329 |
case RTL_GIGA_MAC_VER_04: |
|
1330 |
rtl8169sb_hw_phy_config(ioaddr); |
|
1331 |
break; |
|
1332 |
case RTL_GIGA_MAC_VER_18: |
|
1333 |
rtl8168cp_hw_phy_config(ioaddr); |
|
1334 |
break; |
|
1335 |
case RTL_GIGA_MAC_VER_19: |
|
1336 |
rtl8168c_hw_phy_config(ioaddr); |
|
1337 |
break; |
|
1338 |
case RTL_GIGA_MAC_VER_20: |
|
1339 |
rtl8168cx_hw_phy_config(ioaddr); |
|
1340 |
break; |
|
1341 |
default: |
|
1342 |
break; |
|
1343 |
} |
|
1344 |
} |
|
1345 |
||
1346 |
static void rtl8169_phy_timer(unsigned long __opaque) |
|
1347 |
{
|
|
1348 |
struct net_device *dev = (struct net_device *)__opaque; |
|
1349 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1350 |
struct timer_list *timer = &tp->timer; |
|
1351 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1352 |
unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
1353 |
||
1354 |
assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
1355 |
||
1356 |
if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
1357 |
return; |
|
1358 |
||
1359 |
if (!tp->ecdev) |
|
1360 |
spin_lock_irq(&tp->lock); |
|
1361 |
||
1362 |
if (tp->phy_reset_pending(ioaddr)) {
|
|
1363 |
/* |
|
1364 |
* A busy loop could burn quite a few cycles on nowadays CPU. |
|
1365 |
* Let's delay the execution of the timer for a few ticks. |
|
1366 |
*/ |
|
1367 |
timeout = HZ/10; |
|
1368 |
goto out_mod_timer; |
|
1369 |
} |
|
1370 |
||
1371 |
if (tp->link_ok(ioaddr)) |
|
1372 |
goto out_unlock; |
|
1373 |
||
1374 |
if (netif_msg_link(tp)) |
|
1375 |
printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); |
|
1376 |
||
1377 |
tp->phy_reset_enable(ioaddr); |
|
1378 |
||
1379 |
out_mod_timer: |
|
1380 |
if (!tp->ecdev) |
|
1381 |
mod_timer(timer, jiffies + timeout); |
|
1382 |
out_unlock: |
|
1383 |
if (!tp->ecdev) |
|
1384 |
spin_unlock_irq(&tp->lock); |
|
1385 |
} |
|
1386 |
||
1387 |
static inline void rtl8169_delete_timer(struct net_device *dev) |
|
1388 |
{
|
|
1389 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1390 |
struct timer_list *timer = &tp->timer; |
|
1391 |
||
1392 |
if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1393 |
return; |
|
1394 |
||
1395 |
del_timer_sync(timer); |
|
1396 |
} |
|
1397 |
||
1398 |
static inline void rtl8169_request_timer(struct net_device *dev) |
|
1399 |
{
|
|
1400 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1401 |
struct timer_list *timer = &tp->timer; |
|
1402 |
||
1403 |
if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1404 |
return; |
|
1405 |
||
1406 |
mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1407 |
} |
|
1408 |
||
1409 |
static void ec_poll(struct net_device *dev) |
|
1410 |
{
|
|
1411 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1412 |
struct pci_dev *pdev = tp->pci_dev; |
|
1413 |
||
1414 |
rtl8169_interrupt(pdev->irq, dev); |
|
1415 |
||
1416 |
if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) {
|
|
1417 |
rtl8169_phy_timer((unsigned long) dev); |
|
1418 |
tp->ec_watchdog_jiffies = jiffies; |
|
1419 |
} |
|
1420 |
} |
|
1421 |
||
1422 |
#ifdef CONFIG_NET_POLL_CONTROLLER |
|
1423 |
/* |
|
1424 |
* Polling 'interrupt' - used by things like netconsole to send skbs |
|
1425 |
* without having to re-enable interrupts. It's not called while |
|
1426 |
* the interrupt routine is executing. |
|
1427 |
*/ |
|
1428 |
static void rtl8169_netpoll(struct net_device *dev) |
|
1429 |
{
|
|
1430 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1431 |
struct pci_dev *pdev = tp->pci_dev; |
|
1432 |
||
1433 |
disable_irq(pdev->irq); |
|
1434 |
rtl8169_interrupt(pdev->irq, dev); |
|
1435 |
enable_irq(pdev->irq); |
|
1436 |
} |
|
1437 |
#endif |
|
1438 |
||
1439 |
static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
1440 |
void __iomem *ioaddr) |
|
1441 |
{
|
|
1442 |
iounmap(ioaddr); |
|
1443 |
pci_release_regions(pdev); |
|
1444 |
pci_disable_device(pdev); |
|
1445 |
free_netdev(dev); |
|
1446 |
} |
|
1447 |
||
1448 |
static void rtl8169_phy_reset(struct net_device *dev, |
|
1449 |
struct rtl8169_private *tp) |
|
1450 |
{
|
|
1451 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1452 |
unsigned int i; |
|
1453 |
||
1454 |
tp->phy_reset_enable(ioaddr); |
|
1455 |
for (i = 0; i < 100; i++) {
|
|
1456 |
if (!tp->phy_reset_pending(ioaddr)) |
|
1457 |
return; |
|
1458 |
msleep(1); |
|
1459 |
} |
|
1460 |
if (netif_msg_link(tp)) |
|
1461 |
printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); |
|
1462 |
} |
|
1463 |
||
1464 |
static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
1465 |
{
|
|
1466 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1467 |
||
1468 |
rtl_hw_phy_config(dev); |
|
1469 |
||
1470 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
|
|
1471 |
RTL_W8(0x82, 0x01); |
|
1472 |
||
1473 |
pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
1474 |
||
1475 |
if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
1476 |
pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
1477 |
||
1478 |
if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
|
|
1479 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
|
|
1480 |
RTL_W8(0x82, 0x01); |
|
1481 |
dprintk("Set PHY Reg 0x0bh = 0x00h\n");
|
|
1482 |
mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
1483 |
} |
|
1484 |
||
1485 |
rtl8169_phy_reset(dev, tp); |
|
1486 |
||
1487 |
/* |
|
1488 |
* rtl8169_set_speed_xmii takes good care of the Fast Ethernet |
|
1489 |
* only 8101. Don't panic. |
|
1490 |
*/ |
|
1491 |
rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); |
|
1492 |
||
1493 |
if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) |
|
1494 |
printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); |
|
1495 |
} |
|
1496 |
||
1497 |
static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
1498 |
{
|
|
1499 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1500 |
u32 high; |
|
1501 |
u32 low; |
|
1502 |
||
1503 |
low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
1504 |
high = addr[4] | (addr[5] << 8); |
|
1505 |
||
1506 |
spin_lock_irq(&tp->lock); |
|
1507 |
||
1508 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1509 |
RTL_W32(MAC0, low); |
|
1510 |
RTL_W32(MAC4, high); |
|
1511 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1512 |
||
1513 |
spin_unlock_irq(&tp->lock); |
|
1514 |
} |
|
1515 |
||
1516 |
static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
1517 |
{
|
|
1518 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1519 |
struct sockaddr *addr = p; |
|
1520 |
||
1521 |
if (!is_valid_ether_addr(addr->sa_data)) |
|
1522 |
return -EADDRNOTAVAIL; |
|
1523 |
||
1524 |
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
1525 |
||
1526 |
rtl_rar_set(tp, dev->dev_addr); |
|
1527 |
||
1528 |
return 0; |
|
1529 |
} |
|
1530 |
||
1531 |
static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
1532 |
{
|
|
1533 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1534 |
struct mii_ioctl_data *data = if_mii(ifr); |
|
1535 |
||
1536 |
if (!netif_running(dev)) |
|
1537 |
return -ENODEV; |
|
1538 |
||
1539 |
switch (cmd) {
|
|
1540 |
case SIOCGMIIPHY: |
|
1541 |
data->phy_id = 32; /* Internal PHY */ |
|
1542 |
return 0; |
|
1543 |
||
1544 |
case SIOCGMIIREG: |
|
1545 |
data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); |
|
1546 |
return 0; |
|
1547 |
||
1548 |
case SIOCSMIIREG: |
|
1549 |
if (!capable(CAP_NET_ADMIN)) |
|
1550 |
return -EPERM; |
|
1551 |
mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
|
1552 |
return 0; |
|
1553 |
} |
|
1554 |
return -EOPNOTSUPP; |
|
1555 |
} |
|
1556 |
||
1557 |
static const struct rtl_cfg_info {
|
|
1558 |
void (*hw_start)(struct net_device *); |
|
1559 |
unsigned int region; |
|
1560 |
unsigned int align; |
|
1561 |
u16 intr_event; |
|
1562 |
u16 napi_event; |
|
1563 |
unsigned msi; |
|
1564 |
} rtl_cfg_infos [] = {
|
|
1565 |
[RTL_CFG_0] = {
|
|
1566 |
.hw_start = rtl_hw_start_8169, |
|
1567 |
.region = 1, |
|
1568 |
.align = 0, |
|
1569 |
.intr_event = SYSErr | LinkChg | RxOverflow | |
|
1570 |
RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1571 |
.napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
1572 |
.msi = 0 |
|
1573 |
}, |
|
1574 |
[RTL_CFG_1] = {
|
|
1575 |
.hw_start = rtl_hw_start_8168, |
|
1576 |
.region = 2, |
|
1577 |
.align = 8, |
|
1578 |
.intr_event = SYSErr | LinkChg | RxOverflow | |
|
1579 |
TxErr | TxOK | RxOK | RxErr, |
|
1580 |
.napi_event = TxErr | TxOK | RxOK | RxOverflow, |
|
1581 |
.msi = RTL_FEATURE_MSI |
|
1582 |
}, |
|
1583 |
[RTL_CFG_2] = {
|
|
1584 |
.hw_start = rtl_hw_start_8101, |
|
1585 |
.region = 2, |
|
1586 |
.align = 8, |
|
1587 |
.intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
1588 |
RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1589 |
.napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
1590 |
.msi = RTL_FEATURE_MSI |
|
1591 |
} |
|
1592 |
}; |
|
1593 |
||
1594 |
/* Cfg9346_Unlock assumed. */ |
|
1595 |
static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, |
|
1596 |
const struct rtl_cfg_info *cfg) |
|
1597 |
{
|
|
1598 |
unsigned msi = 0; |
|
1599 |
u8 cfg2; |
|
1600 |
||
1601 |
cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
1602 |
if (cfg->msi) {
|
|
1603 |
if (pci_enable_msi(pdev)) {
|
|
1604 |
dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); |
|
1605 |
} else {
|
|
1606 |
cfg2 |= MSIEnable; |
|
1607 |
msi = RTL_FEATURE_MSI; |
|
1608 |
} |
|
1609 |
} |
|
1610 |
RTL_W8(Config2, cfg2); |
|
1611 |
return msi; |
|
1612 |
} |
|
1613 |
||
1614 |
static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
1615 |
{
|
|
1616 |
if (tp->features & RTL_FEATURE_MSI) {
|
|
1617 |
pci_disable_msi(pdev); |
|
1618 |
tp->features &= ~RTL_FEATURE_MSI; |
|
1619 |
} |
|
1620 |
} |
|
1621 |
||
1622 |
static int __devinit |
|
1623 |
rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
1624 |
{
|
|
1625 |
const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
1626 |
const unsigned int region = cfg->region; |
|
1627 |
struct rtl8169_private *tp; |
|
1628 |
struct net_device *dev; |
|
1629 |
void __iomem *ioaddr; |
|
1630 |
unsigned int i; |
|
1631 |
int rc; |
|
1632 |
||
1633 |
if (netif_msg_drv(&debug)) {
|
|
1634 |
printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
1635 |
MODULENAME, RTL8169_VERSION); |
|
1636 |
} |
|
1637 |
||
1638 |
dev = alloc_etherdev(sizeof (*tp)); |
|
1639 |
if (!dev) {
|
|
1640 |
if (netif_msg_drv(&debug)) |
|
1641 |
dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
1642 |
rc = -ENOMEM; |
|
1643 |
goto out; |
|
1644 |
} |
|
1645 |
||
1646 |
SET_NETDEV_DEV(dev, &pdev->dev); |
|
1647 |
tp = netdev_priv(dev); |
|
1648 |
tp->dev = dev; |
|
1649 |
tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
1650 |
||
1651 |
/* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
1652 |
rc = pci_enable_device(pdev); |
|
1653 |
if (rc < 0) {
|
|
1654 |
if (netif_msg_probe(tp)) |
|
1655 |
dev_err(&pdev->dev, "enable failure\n"); |
|
1656 |
goto err_out_free_dev_1; |
|
1657 |
} |
|
1658 |
||
1659 |
rc = pci_set_mwi(pdev); |
|
1660 |
if (rc < 0) |
|
1661 |
goto err_out_disable_2; |
|
1662 |
||
1663 |
/* make sure PCI base addr 1 is MMIO */ |
|
1664 |
if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
|
|
1665 |
if (netif_msg_probe(tp)) {
|
|
1666 |
dev_err(&pdev->dev, |
|
1667 |
"region #%d not an MMIO resource, aborting\n", |
|
1668 |
region); |
|
1669 |
} |
|
1670 |
rc = -ENODEV; |
|
1671 |
goto err_out_mwi_3; |
|
1672 |
} |
|
1673 |
||
1674 |
/* check for weird/broken PCI region reporting */ |
|
1675 |
if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
|
|
1676 |
if (netif_msg_probe(tp)) {
|
|
1677 |
dev_err(&pdev->dev, |
|
1678 |
"Invalid PCI region size(s), aborting\n"); |
|
1679 |
} |
|
1680 |
rc = -ENODEV; |
|
1681 |
goto err_out_mwi_3; |
|
1682 |
} |
|
1683 |
||
1684 |
rc = pci_request_regions(pdev, MODULENAME); |
|
1685 |
if (rc < 0) {
|
|
1686 |
if (netif_msg_probe(tp)) |
|
1687 |
dev_err(&pdev->dev, "could not request regions.\n"); |
|
1688 |
goto err_out_mwi_3; |
|
1689 |
} |
|
1690 |
||
1691 |
tp->cp_cmd = PCIMulRW | RxChkSum; |
|
1692 |
||
1693 |
if ((sizeof(dma_addr_t) > 4) && |
|
1694 |
!pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
|
|
1695 |
tp->cp_cmd |= PCIDAC; |
|
1696 |
dev->features |= NETIF_F_HIGHDMA; |
|
1697 |
} else {
|
|
1698 |
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
|
1699 |
if (rc < 0) {
|
|
1700 |
if (netif_msg_probe(tp)) {
|
|
1701 |
dev_err(&pdev->dev, |
|
1702 |
"DMA configuration failed.\n"); |
|
1703 |
} |
|
1704 |
goto err_out_free_res_4; |
|
1705 |
} |
|
1706 |
} |
|
1707 |
||
1708 |
pci_set_master(pdev); |
|
1709 |
||
1710 |
/* ioremap MMIO region */ |
|
1711 |
ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
1712 |
if (!ioaddr) {
|
|
1713 |
if (netif_msg_probe(tp)) |
|
1714 |
dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
|
1715 |
rc = -EIO; |
|
1716 |
goto err_out_free_res_4; |
|
1717 |
} |
|
1718 |
||
1719 |
/* Unneeded ? Don't mess with Mrs. Murphy. */ |
|
1720 |
rtl8169_irq_mask_and_ack(ioaddr); |
|
1721 |
||
1722 |
/* Soft reset the chip. */ |
|
1723 |
RTL_W8(ChipCmd, CmdReset); |
|
1724 |
||
1725 |
/* Check that the chip has finished the reset. */ |
|
1726 |
for (i = 0; i < 100; i++) {
|
|
1727 |
if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
1728 |
break; |
|
1729 |
msleep_interruptible(1); |
|
1730 |
} |
|
1731 |
||
1732 |
/* Identify chip attached to board */ |
|
1733 |
rtl8169_get_mac_version(tp, ioaddr); |
|
1734 |
||
1735 |
rtl8169_print_mac_version(tp); |
|
1736 |
||
1737 |
for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
|
|
1738 |
if (tp->mac_version == rtl_chip_info[i].mac_version) |
|
1739 |
break; |
|
1740 |
} |
|
1741 |
if (i < 0) {
|
|
1742 |
/* Unknown chip: assume array element #0, original RTL-8169 */ |
|
1743 |
if (netif_msg_probe(tp)) {
|
|
1744 |
dev_printk(KERN_DEBUG, &pdev->dev, |
|
1745 |
"unknown chip version, assuming %s\n", |
|
1746 |
rtl_chip_info[0].name); |
|
1747 |
} |
|
1748 |
i++; |
|
1749 |
} |
|
1750 |
tp->chipset = i; |
|
1751 |
||
1752 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1753 |
RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
1754 |
RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
1755 |
tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
|
1756 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1757 |
||
1758 |
if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
|
1759 |
(RTL_R8(PHYstatus) & TBI_Enable)) {
|
|
1760 |
tp->set_speed = rtl8169_set_speed_tbi; |
|
1761 |
tp->get_settings = rtl8169_gset_tbi; |
|
1762 |
tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
1763 |
tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
1764 |
tp->link_ok = rtl8169_tbi_link_ok; |
|
1765 |
||
1766 |
tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
|
1767 |
} else {
|
|
1768 |
tp->set_speed = rtl8169_set_speed_xmii; |
|
1769 |
tp->get_settings = rtl8169_gset_xmii; |
|
1770 |
tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
1771 |
tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
1772 |
tp->link_ok = rtl8169_xmii_link_ok; |
|
1773 |
||
1774 |
dev->do_ioctl = rtl8169_ioctl; |
|
1775 |
} |
|
1776 |
||
1777 |
/* Get MAC address. FIXME: read EEPROM */ |
|
1778 |
for (i = 0; i < MAC_ADDR_LEN; i++) |
|
1779 |
dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
1780 |
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
1781 |
||
1782 |
dev->open = rtl8169_open; |
|
1783 |
dev->hard_start_xmit = rtl8169_start_xmit; |
|
1784 |
dev->get_stats = rtl8169_get_stats; |
|
1785 |
SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
1786 |
dev->stop = rtl8169_close; |
|
1787 |
dev->tx_timeout = rtl8169_tx_timeout; |
|
1788 |
dev->set_multicast_list = rtl_set_rx_mode; |
|
1789 |
dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
1790 |
dev->irq = pdev->irq; |
|
1791 |
dev->base_addr = (unsigned long) ioaddr; |
|
1792 |
dev->change_mtu = rtl8169_change_mtu; |
|
1793 |
dev->set_mac_address = rtl_set_mac_address; |
|
1794 |
||
1795 |
#ifdef CONFIG_R8169_NAPI |
|
1796 |
netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
1797 |
#endif |
|
1798 |
||
1799 |
#ifdef CONFIG_R8169_VLAN |
|
1800 |
dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
1801 |
dev->vlan_rx_register = rtl8169_vlan_rx_register; |
|
1802 |
#endif |
|
1803 |
||
1804 |
#ifdef CONFIG_NET_POLL_CONTROLLER |
|
1805 |
dev->poll_controller = rtl8169_netpoll; |
|
1806 |
#endif |
|
1807 |
||
1808 |
tp->intr_mask = 0xffff; |
|
1809 |
tp->pci_dev = pdev; |
|
1810 |
tp->mmio_addr = ioaddr; |
|
1811 |
tp->align = cfg->align; |
|
1812 |
tp->hw_start = cfg->hw_start; |
|
1813 |
tp->intr_event = cfg->intr_event; |
|
1814 |
tp->napi_event = cfg->napi_event; |
|
1815 |
||
1816 |
init_timer(&tp->timer); |
|
1817 |
tp->timer.data = (unsigned long) dev; |
|
1818 |
tp->timer.function = rtl8169_phy_timer; |
|
1819 |
||
1820 |
spin_lock_init(&tp->lock); |
|
1821 |
||
1822 |
// offer device to EtherCAT master module |
|
1823 |
tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); |
|
1824 |
||
1825 |
if (!tp->ecdev) {
|
|
1826 |
rc = register_netdev(dev); |
|
1827 |
if (rc < 0) |
|
1828 |
goto err_out_msi_5; |
|
1829 |
} |
|
1830 |
||
1831 |
pci_set_drvdata(pdev, dev); |
|
1832 |
||
1833 |
if (netif_msg_probe(tp)) {
|
|
1834 |
u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
|
1835 |
||
1836 |
printk(KERN_INFO "%s: %s at 0x%lx, " |
|
1837 |
"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
|
1838 |
"XID %08x IRQ %d\n", |
|
1839 |
dev->name, |
|
1840 |
rtl_chip_info[tp->chipset].name, |
|
1841 |
dev->base_addr, |
|
1842 |
dev->dev_addr[0], dev->dev_addr[1], |
|
1843 |
dev->dev_addr[2], dev->dev_addr[3], |
|
1844 |
dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
|
1845 |
} |
|
1846 |
||
1847 |
rtl8169_init_phy(dev, tp); |
|
1848 |
||
1849 |
if (tp->ecdev && ecdev_open(tp->ecdev)) {
|
|
1850 |
ecdev_withdraw(tp->ecdev); |
|
1851 |
goto err_out_msi_5; |
|
1852 |
} |
|
1853 |
||
1854 |
out: |
|
1855 |
return rc; |
|
1856 |
||
1857 |
err_out_msi_5: |
|
1858 |
rtl_disable_msi(pdev, tp); |
|
1859 |
iounmap(ioaddr); |
|
1860 |
err_out_free_res_4: |
|
1861 |
pci_release_regions(pdev); |
|
1862 |
err_out_mwi_3: |
|
1863 |
pci_clear_mwi(pdev); |
|
1864 |
err_out_disable_2: |
|
1865 |
pci_disable_device(pdev); |
|
1866 |
err_out_free_dev_1: |
|
1867 |
free_netdev(dev); |
|
1868 |
goto out; |
|
1869 |
} |
|
1870 |
||
1871 |
static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
1872 |
{
|
|
1873 |
struct net_device *dev = pci_get_drvdata(pdev); |
|
1874 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1875 |
||
1876 |
flush_scheduled_work(); |
|
1877 |
||
1878 |
if (tp->ecdev) {
|
|
1879 |
ecdev_close(tp->ecdev); |
|
1880 |
ecdev_withdraw(tp->ecdev); |
|
1881 |
} else {
|
|
1882 |
unregister_netdev(dev); |
|
1883 |
} |
|
1884 |
rtl_disable_msi(pdev, tp); |
|
1885 |
rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
1886 |
pci_set_drvdata(pdev, NULL); |
|
1887 |
} |
|
1888 |
||
1889 |
static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
|
1890 |
struct net_device *dev) |
|
1891 |
{
|
|
1892 |
unsigned int mtu = dev->mtu; |
|
1893 |
||
1894 |
tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; |
|
1895 |
} |
|
1896 |
||
1897 |
static int rtl8169_open(struct net_device *dev) |
|
1898 |
{
|
|
1899 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1900 |
struct pci_dev *pdev = tp->pci_dev; |
|
1901 |
int retval = -ENOMEM; |
|
1902 |
||
1903 |
||
1904 |
rtl8169_set_rxbufsize(tp, dev); |
|
1905 |
||
1906 |
/* |
|
1907 |
* Rx and Tx desscriptors needs 256 bytes alignment. |
|
1908 |
* pci_alloc_consistent provides more. |
|
1909 |
*/ |
|
1910 |
tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, |
|
1911 |
&tp->TxPhyAddr); |
|
1912 |
if (!tp->TxDescArray) |
|
1913 |
goto out; |
|
1914 |
||
1915 |
tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, |
|
1916 |
&tp->RxPhyAddr); |
|
1917 |
if (!tp->RxDescArray) |
|
1918 |
goto err_free_tx_0; |
|
1919 |
||
1920 |
retval = rtl8169_init_ring(dev); |
|
1921 |
if (retval < 0) |
|
1922 |
goto err_free_rx_1; |
|
1923 |
||
1924 |
INIT_DELAYED_WORK(&tp->task, NULL); |
|
1925 |
||
1926 |
smp_mb(); |
|
1927 |
||
1928 |
if (!tp->ecdev) {
|
|
1929 |
retval = request_irq(dev->irq, rtl8169_interrupt, |
|
1930 |
(tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
1931 |
dev->name, dev); |
|
1932 |
if (retval < 0) |
|
1933 |
goto err_release_ring_2; |
|
1934 |
||
1935 |
#ifdef CONFIG_R8169_NAPI |
|
1936 |
napi_enable(&tp->napi); |
|
1937 |
#endif |
|
1938 |
} |
|
1939 |
||
1940 |
rtl_hw_start(dev); |
|
1941 |
||
1942 |
rtl8169_request_timer(dev); |
|
1943 |
||
1944 |
rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
1945 |
out: |
|
1946 |
return retval; |
|
1947 |
||
1948 |
err_release_ring_2: |
|
1949 |
rtl8169_rx_clear(tp); |
|
1950 |
err_free_rx_1: |
|
1951 |
pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
1952 |
tp->RxPhyAddr); |
|
1953 |
err_free_tx_0: |
|
1954 |
pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
1955 |
tp->TxPhyAddr); |
|
1956 |
goto out; |
|
1957 |
} |
|
1958 |
||
1959 |
static void rtl8169_hw_reset(void __iomem *ioaddr) |
|
1960 |
{
|
|
1961 |
/* Disable interrupts */ |
|
1962 |
rtl8169_irq_mask_and_ack(ioaddr); |
|
1963 |
||
1964 |
/* Reset the chipset */ |
|
1965 |
RTL_W8(ChipCmd, CmdReset); |
|
1966 |
||
1967 |
/* PCI commit */ |
|
1968 |
RTL_R8(ChipCmd); |
|
1969 |
} |
|
1970 |
||
1971 |
static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
1972 |
{
|
|
1973 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1974 |
u32 cfg = rtl8169_rx_config; |
|
1975 |
||
1976 |
cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
1977 |
RTL_W32(RxConfig, cfg); |
|
1978 |
||
1979 |
/* Set DMA burst size and Interframe Gap Time */ |
|
1980 |
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
1981 |
(InterFrameGap << TxInterFrameGapShift)); |
|
1982 |
} |
|
1983 |
||
1984 |
static void rtl_hw_start(struct net_device *dev) |
|
1985 |
{
|
|
1986 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
1987 |
void __iomem *ioaddr = tp->mmio_addr; |
|
1988 |
unsigned int i; |
|
1989 |
||
1990 |
/* Soft reset the chip. */ |
|
1991 |
RTL_W8(ChipCmd, CmdReset); |
|
1992 |
||
1993 |
/* Check that the chip has finished the reset. */ |
|
1994 |
for (i = 0; i < 100; i++) {
|
|
1995 |
if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
1996 |
break; |
|
1997 |
msleep_interruptible(1); |
|
1998 |
} |
|
1999 |
||
2000 |
tp->hw_start(dev); |
|
2001 |
||
2002 |
if (!tp->ecdev) |
|
2003 |
netif_start_queue(dev); |
|
2004 |
} |
|
2005 |
||
2006 |
||
2007 |
static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
2008 |
void __iomem *ioaddr) |
|
2009 |
{
|
|
2010 |
/* |
|
2011 |
* Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
2012 |
* register to be written before TxDescAddrLow to work. |
|
2013 |
* Switching from MMIO to I/O access fixes the issue as well. |
|
2014 |
*/ |
|
2015 |
RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
2016 |
RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); |
|
2017 |
RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
2018 |
RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); |
|
2019 |
} |
|
2020 |
||
2021 |
static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
2022 |
{
|
|
2023 |
u16 cmd; |
|
2024 |
||
2025 |
cmd = RTL_R16(CPlusCmd); |
|
2026 |
RTL_W16(CPlusCmd, cmd); |
|
2027 |
return cmd; |
|
2028 |
} |
|
2029 |
||
2030 |
static void rtl_set_rx_max_size(void __iomem *ioaddr) |
|
2031 |
{
|
|
2032 |
/* Low hurts. Let's disable the filtering. */ |
|
2033 |
RTL_W16(RxMaxSize, 16383); |
|
2034 |
} |
|
2035 |
||
2036 |
static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
2037 |
{
|
|
2038 |
struct {
|
|
2039 |
u32 mac_version; |
|
2040 |
u32 clk; |
|
2041 |
u32 val; |
|
2042 |
} cfg2_info [] = {
|
|
2043 |
{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
|
|
2044 |
{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
|
|
2045 |
{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
|
|
2046 |
{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
|
|
2047 |
}, *p = cfg2_info; |
|
2048 |
unsigned int i; |
|
2049 |
u32 clk; |
|
2050 |
||
2051 |
clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
2052 |
for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
|
|
2053 |
if ((p->mac_version == mac_version) && (p->clk == clk)) {
|
|
2054 |
RTL_W32(0x7c, p->val); |
|
2055 |
break; |
|
2056 |
} |
|
2057 |
} |
|
2058 |
} |
|
2059 |
||
2060 |
static void rtl_hw_start_8169(struct net_device *dev) |
|
2061 |
{
|
|
2062 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2063 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2064 |
struct pci_dev *pdev = tp->pci_dev; |
|
2065 |
||
2066 |
if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
|
|
2067 |
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
2068 |
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
2069 |
} |
|
2070 |
||
2071 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2072 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
2073 |
(tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2074 |
(tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
2075 |
(tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
2076 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2077 |
||
2078 |
RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2079 |
||
2080 |
rtl_set_rx_max_size(ioaddr); |
|
2081 |
||
2082 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
2083 |
(tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2084 |
(tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
2085 |
(tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
2086 |
rtl_set_rx_tx_config_registers(tp); |
|
2087 |
||
2088 |
tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2089 |
||
2090 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2091 |
(tp->mac_version == RTL_GIGA_MAC_VER_03)) {
|
|
2092 |
dprintk("Set MAC Reg C+CR Offset 0xE0. "
|
|
2093 |
"Bit-3 and bit-14 MUST be 1\n"); |
|
2094 |
tp->cp_cmd |= (1 << 14); |
|
2095 |
} |
|
2096 |
||
2097 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2098 |
||
2099 |
rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
2100 |
||
2101 |
/* |
|
2102 |
* Undocumented corner. Supposedly: |
|
2103 |
* (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
2104 |
*/ |
|
2105 |
RTL_W16(IntrMitigate, 0x0000); |
|
2106 |
||
2107 |
rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2108 |
||
2109 |
if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
|
2110 |
(tp->mac_version != RTL_GIGA_MAC_VER_02) && |
|
2111 |
(tp->mac_version != RTL_GIGA_MAC_VER_03) && |
|
2112 |
(tp->mac_version != RTL_GIGA_MAC_VER_04)) {
|
|
2113 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2114 |
rtl_set_rx_tx_config_registers(tp); |
|
2115 |
} |
|
2116 |
||
2117 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2118 |
||
2119 |
/* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
2120 |
RTL_R8(IntrMask); |
|
2121 |
||
2122 |
RTL_W32(RxMissed, 0); |
|
2123 |
||
2124 |
rtl_set_rx_mode(dev); |
|
2125 |
||
2126 |
/* no early-rx interrupts */ |
|
2127 |
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2128 |
||
2129 |
/* Enable all known interrupts by setting the interrupt mask. */ |
|
2130 |
if (!tp->ecdev) |
|
2131 |
RTL_W16(IntrMask, tp->intr_event); |
|
2132 |
} |
|
2133 |
||
2134 |
static void rtl_hw_start_8168(struct net_device *dev) |
|
2135 |
{
|
|
2136 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2137 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2138 |
struct pci_dev *pdev = tp->pci_dev; |
|
2139 |
u8 ctl; |
|
2140 |
||
2141 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2142 |
||
2143 |
RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2144 |
||
2145 |
rtl_set_rx_max_size(ioaddr); |
|
2146 |
||
2147 |
rtl_set_rx_tx_config_registers(tp); |
|
2148 |
||
2149 |
tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
2150 |
||
2151 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2152 |
||
2153 |
/* Tx performance tweak. */ |
|
2154 |
pci_read_config_byte(pdev, 0x69, &ctl); |
|
2155 |
ctl = (ctl & ~0x70) | 0x50; |
|
2156 |
pci_write_config_byte(pdev, 0x69, ctl); |
|
2157 |
||
2158 |
RTL_W16(IntrMitigate, 0x5151); |
|
2159 |
||
2160 |
/* Work around for RxFIFO overflow. */ |
|
2161 |
if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
|
|
2162 |
tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
2163 |
tp->intr_event &= ~RxOverflow; |
|
2164 |
} |
|
2165 |
||
2166 |
rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2167 |
||
2168 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2169 |
||
2170 |
RTL_R8(IntrMask); |
|
2171 |
||
2172 |
RTL_W32(RxMissed, 0); |
|
2173 |
||
2174 |
rtl_set_rx_mode(dev); |
|
2175 |
||
2176 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2177 |
||
2178 |
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2179 |
||
2180 |
if (!tp->ecdev) |
|
2181 |
RTL_W16(IntrMask, tp->intr_event); |
|
2182 |
} |
|
2183 |
||
2184 |
static void rtl_hw_start_8101(struct net_device *dev) |
|
2185 |
{
|
|
2186 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2187 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2188 |
struct pci_dev *pdev = tp->pci_dev; |
|
2189 |
||
2190 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
2191 |
(tp->mac_version == RTL_GIGA_MAC_VER_16)) {
|
|
2192 |
pci_write_config_word(pdev, 0x68, 0x00); |
|
2193 |
pci_write_config_word(pdev, 0x69, 0x08); |
|
2194 |
} |
|
2195 |
||
2196 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2197 |
||
2198 |
RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2199 |
||
2200 |
rtl_set_rx_max_size(ioaddr); |
|
2201 |
||
2202 |
tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2203 |
||
2204 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2205 |
||
2206 |
RTL_W16(IntrMitigate, 0x0000); |
|
2207 |
||
2208 |
rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2209 |
||
2210 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2211 |
rtl_set_rx_tx_config_registers(tp); |
|
2212 |
||
2213 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2214 |
||
2215 |
RTL_R8(IntrMask); |
|
2216 |
||
2217 |
RTL_W32(RxMissed, 0); |
|
2218 |
||
2219 |
rtl_set_rx_mode(dev); |
|
2220 |
||
2221 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2222 |
||
2223 |
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
2224 |
||
2225 |
if (!tp->ecdev) |
|
2226 |
RTL_W16(IntrMask, tp->intr_event); |
|
2227 |
} |
|
2228 |
||
2229 |
static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
2230 |
{
|
|
2231 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2232 |
int ret = 0; |
|
2233 |
||
2234 |
if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
|
2235 |
return -EINVAL; |
|
2236 |
||
2237 |
dev->mtu = new_mtu; |
|
2238 |
||
2239 |
if (!netif_running(dev)) |
|
2240 |
goto out; |
|
2241 |
||
2242 |
rtl8169_down(dev); |
|
2243 |
||
2244 |
rtl8169_set_rxbufsize(tp, dev); |
|
2245 |
||
2246 |
ret = rtl8169_init_ring(dev); |
|
2247 |
if (ret < 0) |
|
2248 |
goto out; |
|
2249 |
||
2250 |
#ifdef CONFIG_R8169_NAPI |
|
2251 |
napi_enable(&tp->napi); |
|
2252 |
#endif |
|
2253 |
||
2254 |
rtl_hw_start(dev); |
|
2255 |
||
2256 |
rtl8169_request_timer(dev); |
|
2257 |
||
2258 |
out: |
|
2259 |
return ret; |
|
2260 |
} |
|
2261 |
||
2262 |
static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
2263 |
{
|
|
2264 |
desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
2265 |
desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
2266 |
} |
|
2267 |
||
2268 |
static void rtl8169_free_rx_skb(struct rtl8169_private *tp, |
|
2269 |
struct sk_buff **sk_buff, struct RxDesc *desc) |
|
2270 |
{
|
|
2271 |
struct pci_dev *pdev = tp->pci_dev; |
|
2272 |
||
2273 |
pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, |
|
2274 |
PCI_DMA_FROMDEVICE); |
|
2275 |
dev_kfree_skb(*sk_buff); |
|
2276 |
*sk_buff = NULL; |
|
2277 |
rtl8169_make_unusable_by_asic(desc); |
|
2278 |
} |
|
2279 |
||
2280 |
static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
2281 |
{
|
|
2282 |
u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
2283 |
||
2284 |
desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
2285 |
} |
|
2286 |
||
2287 |
static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
2288 |
u32 rx_buf_sz) |
|
2289 |
{
|
|
2290 |
desc->addr = cpu_to_le64(mapping); |
|
2291 |
wmb(); |
|
2292 |
rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
2293 |
} |
|
2294 |
||
2295 |
static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
|
2296 |
struct net_device *dev, |
|
2297 |
struct RxDesc *desc, int rx_buf_sz, |
|
2298 |
unsigned int align) |
|
2299 |
{
|
|
2300 |
struct sk_buff *skb; |
|
2301 |
dma_addr_t mapping; |
|
2302 |
unsigned int pad; |
|
2303 |
||
2304 |
pad = align ? align : NET_IP_ALIGN; |
|
2305 |
||
2306 |
skb = netdev_alloc_skb(dev, rx_buf_sz + pad); |
|
2307 |
if (!skb) |
|
2308 |
goto err_out; |
|
2309 |
||
2310 |
skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
|
2311 |
||
2312 |
mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
|
2313 |
PCI_DMA_FROMDEVICE); |
|
2314 |
||
2315 |
rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
2316 |
out: |
|
2317 |
return skb; |
|
2318 |
||
2319 |
err_out: |
|
2320 |
rtl8169_make_unusable_by_asic(desc); |
|
2321 |
goto out; |
|
2322 |
} |
|
2323 |
||
2324 |
static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
2325 |
{
|
|
2326 |
unsigned int i; |
|
2327 |
||
2328 |
for (i = 0; i < NUM_RX_DESC; i++) {
|
|
2329 |
if (tp->Rx_skbuff[i]) {
|
|
2330 |
rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, |
|
2331 |
tp->RxDescArray + i); |
|
2332 |
} |
|
2333 |
} |
|
2334 |
} |
|
2335 |
||
2336 |
static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, |
|
2337 |
u32 start, u32 end) |
|
2338 |
{
|
|
2339 |
u32 cur; |
|
2340 |
||
2341 |
for (cur = start; end - cur != 0; cur++) {
|
|
2342 |
struct sk_buff *skb; |
|
2343 |
unsigned int i = cur % NUM_RX_DESC; |
|
2344 |
||
2345 |
WARN_ON((s32)(end - cur) < 0); |
|
2346 |
||
2347 |
if (tp->Rx_skbuff[i]) |
|
2348 |
continue; |
|
2349 |
||
2350 |
skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
|
2351 |
tp->RxDescArray + i, |
|
2352 |
tp->rx_buf_sz, tp->align); |
|
2353 |
if (!skb) |
|
2354 |
break; |
|
2355 |
||
2356 |
tp->Rx_skbuff[i] = skb; |
|
2357 |
} |
|
2358 |
return cur - start; |
|
2359 |
} |
|
2360 |
||
2361 |
static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
2362 |
{
|
|
2363 |
desc->opts1 |= cpu_to_le32(RingEnd); |
|
2364 |
} |
|
2365 |
||
2366 |
static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
2367 |
{
|
|
2368 |
tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
2369 |
} |
|
2370 |
||
2371 |
static int rtl8169_init_ring(struct net_device *dev) |
|
2372 |
{
|
|
2373 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2374 |
||
2375 |
rtl8169_init_ring_indexes(tp); |
|
2376 |
||
2377 |
memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
2378 |
memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); |
|
2379 |
||
2380 |
if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) |
|
2381 |
goto err_out; |
|
2382 |
||
2383 |
rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
2384 |
||
2385 |
return 0; |
|
2386 |
||
2387 |
err_out: |
|
2388 |
rtl8169_rx_clear(tp); |
|
2389 |
return -ENOMEM; |
|
2390 |
} |
|
2391 |
||
2392 |
static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, |
|
2393 |
struct TxDesc *desc) |
|
2394 |
{
|
|
2395 |
unsigned int len = tx_skb->len; |
|
2396 |
||
2397 |
pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); |
|
2398 |
desc->opts1 = 0x00; |
|
2399 |
desc->opts2 = 0x00; |
|
2400 |
desc->addr = 0x00; |
|
2401 |
tx_skb->len = 0; |
|
2402 |
} |
|
2403 |
||
2404 |
static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
2405 |
{
|
|
2406 |
unsigned int i; |
|
2407 |
||
2408 |
for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
|
|
2409 |
unsigned int entry = i % NUM_TX_DESC; |
|
2410 |
struct ring_info *tx_skb = tp->tx_skb + entry; |
|
2411 |
unsigned int len = tx_skb->len; |
|
2412 |
||
2413 |
if (len) {
|
|
2414 |
struct sk_buff *skb = tx_skb->skb; |
|
2415 |
||
2416 |
rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, |
|
2417 |
tp->TxDescArray + entry); |
|
2418 |
if (skb) {
|
|
2419 |
if (!tp->ecdev) |
|
2420 |
dev_kfree_skb(skb); |
|
2421 |
tx_skb->skb = NULL; |
|
2422 |
} |
|
2423 |
tp->dev->stats.tx_dropped++; |
|
2424 |
} |
|
2425 |
} |
|
2426 |
tp->cur_tx = tp->dirty_tx = 0; |
|
2427 |
} |
|
2428 |
||
2429 |
static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
2430 |
{
|
|
2431 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2432 |
||
2433 |
PREPARE_DELAYED_WORK(&tp->task, task); |
|
2434 |
schedule_delayed_work(&tp->task, 4); |
|
2435 |
} |
|
2436 |
||
2437 |
static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
2438 |
{
|
|
2439 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2440 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2441 |
||
2442 |
synchronize_irq(dev->irq); |
|
2443 |
||
2444 |
/* Wait for any pending NAPI task to complete */ |
|
2445 |
#ifdef CONFIG_R8169_NAPI |
|
2446 |
napi_disable(&tp->napi); |
|
2447 |
#endif |
|
2448 |
||
2449 |
rtl8169_irq_mask_and_ack(ioaddr); |
|
2450 |
||
2451 |
#ifdef CONFIG_R8169_NAPI |
|
2452 |
tp->intr_mask = 0xffff; |
|
2453 |
RTL_W16(IntrMask, tp->intr_event); |
|
2454 |
napi_enable(&tp->napi); |
|
2455 |
#endif |
|
2456 |
} |
|
2457 |
||
2458 |
static void rtl8169_reinit_task(struct work_struct *work) |
|
2459 |
{
|
|
2460 |
struct rtl8169_private *tp = |
|
2461 |
container_of(work, struct rtl8169_private, task.work); |
|
2462 |
struct net_device *dev = tp->dev; |
|
2463 |
int ret; |
|
2464 |
||
2465 |
rtnl_lock(); |
|
2466 |
||
2467 |
if (!netif_running(dev)) |
|
2468 |
goto out_unlock; |
|
2469 |
||
2470 |
rtl8169_wait_for_quiescence(dev); |
|
2471 |
rtl8169_close(dev); |
|
2472 |
||
2473 |
ret = rtl8169_open(dev); |
|
2474 |
if (unlikely(ret < 0)) {
|
|
2475 |
if (net_ratelimit() && netif_msg_drv(tp)) {
|
|
2476 |
printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
|
2477 |
" Rescheduling.\n", dev->name, ret); |
|
2478 |
} |
|
2479 |
rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
2480 |
} |
|
2481 |
||
2482 |
out_unlock: |
|
2483 |
rtnl_unlock(); |
|
2484 |
} |
|
2485 |
||
2486 |
static void rtl8169_reset_task(struct work_struct *work) |
|
2487 |
{
|
|
2488 |
struct rtl8169_private *tp = |
|
2489 |
container_of(work, struct rtl8169_private, task.work); |
|
2490 |
struct net_device *dev = tp->dev; |
|
2491 |
||
2492 |
rtnl_lock(); |
|
2493 |
||
2494 |
if (!netif_running(dev)) |
|
2495 |
goto out_unlock; |
|
2496 |
||
2497 |
rtl8169_wait_for_quiescence(dev); |
|
2498 |
||
2499 |
rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
|
2500 |
rtl8169_tx_clear(tp); |
|
2501 |
||
2502 |
if (tp->dirty_rx == tp->cur_rx) {
|
|
2503 |
rtl8169_init_ring_indexes(tp); |
|
2504 |
rtl_hw_start(dev); |
|
2505 |
netif_wake_queue(dev); |
|
2506 |
rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
2507 |
} else {
|
|
2508 |
if (net_ratelimit() && netif_msg_intr(tp)) {
|
|
2509 |
printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
|
2510 |
dev->name); |
|
2511 |
} |
|
2512 |
rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2513 |
} |
|
2514 |
||
2515 |
out_unlock: |
|
2516 |
rtnl_unlock(); |
|
2517 |
} |
|
2518 |
||
2519 |
static void rtl8169_tx_timeout(struct net_device *dev) |
|
2520 |
{
|
|
2521 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2522 |
||
2523 |
if (tp->ecdev) |
|
2524 |
return; |
|
2525 |
||
2526 |
rtl8169_hw_reset(tp->mmio_addr); |
|
2527 |
||
2528 |
/* Let's wait a bit while any (async) irq lands on */ |
|
2529 |
rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2530 |
} |
|
2531 |
||
2532 |
static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
2533 |
u32 opts1) |
|
2534 |
{
|
|
2535 |
struct skb_shared_info *info = skb_shinfo(skb); |
|
2536 |
unsigned int cur_frag, entry; |
|
2537 |
struct TxDesc * uninitialized_var(txd); |
|
2538 |
||
2539 |
entry = tp->cur_tx; |
|
2540 |
for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
|
|
2541 |
skb_frag_t *frag = info->frags + cur_frag; |
|
2542 |
dma_addr_t mapping; |
|
2543 |
u32 status, len; |
|
2544 |
void *addr; |
|
2545 |
||
2546 |
entry = (entry + 1) % NUM_TX_DESC; |
|
2547 |
||
2548 |
txd = tp->TxDescArray + entry; |
|
2549 |
len = frag->size; |
|
2550 |
addr = ((void *) page_address(frag->page)) + frag->page_offset; |
|
2551 |
mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); |
|
2552 |
||
2553 |
/* anti gcc 2.95.3 bugware (sic) */ |
|
2554 |
status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
2555 |
||
2556 |
txd->opts1 = cpu_to_le32(status); |
|
2557 |
txd->addr = cpu_to_le64(mapping); |
|
2558 |
||
2559 |
tp->tx_skb[entry].len = len; |
|
2560 |
} |
|
2561 |
||
2562 |
if (cur_frag) {
|
|
2563 |
tp->tx_skb[entry].skb = skb; |
|
2564 |
txd->opts1 |= cpu_to_le32(LastFrag); |
|
2565 |
} |
|
2566 |
||
2567 |
return cur_frag; |
|
2568 |
} |
|
2569 |
||
2570 |
static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) |
|
2571 |
{
|
|
2572 |
if (dev->features & NETIF_F_TSO) {
|
|
2573 |
u32 mss = skb_shinfo(skb)->gso_size; |
|
2574 |
||
2575 |
if (mss) |
|
2576 |
return LargeSend | ((mss & MSSMask) << MSSShift); |
|
2577 |
} |
|
2578 |
if (skb->ip_summed == CHECKSUM_PARTIAL) {
|
|
2579 |
const struct iphdr *ip = ip_hdr(skb); |
|
2580 |
||
2581 |
if (ip->protocol == IPPROTO_TCP) |
|
2582 |
return IPCS | TCPCS; |
|
2583 |
else if (ip->protocol == IPPROTO_UDP) |
|
2584 |
return IPCS | UDPCS; |
|
2585 |
WARN_ON(1); /* we need a WARN() */ |
|
2586 |
} |
|
2587 |
return 0; |
|
2588 |
} |
|
2589 |
||
2590 |
static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
2591 |
{
|
|
2592 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2593 |
unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; |
|
2594 |
struct TxDesc *txd = tp->TxDescArray + entry; |
|
2595 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2596 |
dma_addr_t mapping; |
|
2597 |
u32 status, len; |
|
2598 |
u32 opts1; |
|
2599 |
int ret = NETDEV_TX_OK; |
|
2600 |
||
2601 |
if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
|
|
2602 |
if (netif_msg_drv(tp)) {
|
|
2603 |
printk(KERN_ERR |
|
2604 |
"%s: BUG! Tx Ring full when queue awake!\n", |
|
2605 |
dev->name); |
|
2606 |
} |
|
2607 |
goto err_stop; |
|
2608 |
} |
|
2609 |
||
2610 |
if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
2611 |
goto err_stop; |
|
2612 |
||
2613 |
opts1 = DescOwn | rtl8169_tso_csum(skb, dev); |
|
2614 |
||
2615 |
frags = rtl8169_xmit_frags(tp, skb, opts1); |
|
2616 |
if (frags) {
|
|
2617 |
len = skb_headlen(skb); |
|
2618 |
opts1 |= FirstFrag; |
|
2619 |
} else {
|
|
2620 |
len = skb->len; |
|
2621 |
||
2622 |
if (unlikely(len < ETH_ZLEN)) {
|
|
2623 |
if (skb_padto(skb, ETH_ZLEN)) |
|
2624 |
goto err_update_stats; |
|
2625 |
len = ETH_ZLEN; |
|
2626 |
} |
|
2627 |
||
2628 |
opts1 |= FirstFrag | LastFrag; |
|
2629 |
tp->tx_skb[entry].skb = skb; |
|
2630 |
} |
|
2631 |
||
2632 |
mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
|
2633 |
||
2634 |
tp->tx_skb[entry].len = len; |
|
2635 |
txd->addr = cpu_to_le64(mapping); |
|
2636 |
txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
2637 |
||
2638 |
wmb(); |
|
2639 |
||
2640 |
/* anti gcc 2.95.3 bugware (sic) */ |
|
2641 |
status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
2642 |
txd->opts1 = cpu_to_le32(status); |
|
2643 |
||
2644 |
dev->trans_start = jiffies; |
|
2645 |
||
2646 |
tp->cur_tx += frags + 1; |
|
2647 |
||
2648 |
smp_wmb(); |
|
2649 |
||
2650 |
RTL_W8(TxPoll, NPQ); /* set polling bit */ |
|
2651 |
||
2652 |
if (!tp->ecdev) {
|
|
2653 |
if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
|
|
2654 |
netif_stop_queue(dev); |
|
2655 |
smp_rmb(); |
|
2656 |
if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
2657 |
netif_wake_queue(dev); |
|
2658 |
} |
|
2659 |
} |
|
2660 |
||
2661 |
out: |
|
2662 |
return ret; |
|
2663 |
||
2664 |
err_stop: |
|
2665 |
if (!tp->ecdev) |
|
2666 |
netif_stop_queue(dev); |
|
2667 |
ret = NETDEV_TX_BUSY; |
|
2668 |
err_update_stats: |
|
2669 |
dev->stats.tx_dropped++; |
|
2670 |
goto out; |
|
2671 |
} |
|
2672 |
||
2673 |
static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
2674 |
{
|
|
2675 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2676 |
struct pci_dev *pdev = tp->pci_dev; |
|
2677 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2678 |
u16 pci_status, pci_cmd; |
|
2679 |
||
2680 |
pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
2681 |
pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
2682 |
||
2683 |
if (netif_msg_intr(tp)) {
|
|
2684 |
printk(KERN_ERR |
|
2685 |
"%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", |
|
2686 |
dev->name, pci_cmd, pci_status); |
|
2687 |
} |
|
2688 |
||
2689 |
/* |
|
2690 |
* The recovery sequence below admits a very elaborated explanation: |
|
2691 |
* - it seems to work; |
|
2692 |
* - I did not see what else could be done; |
|
2693 |
* - it makes iop3xx happy. |
|
2694 |
* |
|
2695 |
* Feel free to adjust to your needs. |
|
2696 |
*/ |
|
2697 |
if (pdev->broken_parity_status) |
|
2698 |
pci_cmd &= ~PCI_COMMAND_PARITY; |
|
2699 |
else |
|
2700 |
pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
2701 |
||
2702 |
pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
2703 |
||
2704 |
pci_write_config_word(pdev, PCI_STATUS, |
|
2705 |
pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
2706 |
PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
2707 |
PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
2708 |
||
2709 |
/* The infamous DAC f*ckup only happens at boot time */ |
|
2710 |
if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
|
|
2711 |
if (netif_msg_intr(tp)) |
|
2712 |
printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); |
|
2713 |
tp->cp_cmd &= ~PCIDAC; |
|
2714 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2715 |
dev->features &= ~NETIF_F_HIGHDMA; |
|
2716 |
} |
|
2717 |
||
2718 |
rtl8169_hw_reset(ioaddr); |
|
2719 |
||
2720 |
rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
2721 |
} |
|
2722 |
||
2723 |
static void rtl8169_tx_interrupt(struct net_device *dev, |
|
2724 |
struct rtl8169_private *tp, |
|
2725 |
void __iomem *ioaddr) |
|
2726 |
{
|
|
2727 |
unsigned int dirty_tx, tx_left; |
|
2728 |
||
2729 |
dirty_tx = tp->dirty_tx; |
|
2730 |
smp_rmb(); |
|
2731 |
tx_left = tp->cur_tx - dirty_tx; |
|
2732 |
||
2733 |
while (tx_left > 0) {
|
|
2734 |
unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
2735 |
struct ring_info *tx_skb = tp->tx_skb + entry; |
|
2736 |
u32 len = tx_skb->len; |
|
2737 |
u32 status; |
|
2738 |
||
2739 |
rmb(); |
|
2740 |
status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
2741 |
if (status & DescOwn) |
|
2742 |
break; |
|
2743 |
||
2744 |
dev->stats.tx_bytes += len; |
|
2745 |
dev->stats.tx_packets++; |
|
2746 |
||
2747 |
rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); |
|
2748 |
||
2749 |
if (status & LastFrag) {
|
|
2750 |
if (!tp->ecdev) |
|
2751 |
dev_kfree_skb_irq(tx_skb->skb); |
|
2752 |
tx_skb->skb = NULL; |
|
2753 |
} |
|
2754 |
dirty_tx++; |
|
2755 |
tx_left--; |
|
2756 |
} |
|
2757 |
||
2758 |
if (tp->dirty_tx != dirty_tx) {
|
|
2759 |
tp->dirty_tx = dirty_tx; |
|
2760 |
smp_wmb(); |
|
2761 |
if (!tp->ecdev && netif_queue_stopped(dev) && |
|
2762 |
(TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
|
|
2763 |
netif_wake_queue(dev); |
|
2764 |
} |
|
2765 |
/* |
|
2766 |
* 8168 hack: TxPoll requests are lost when the Tx packets are |
|
2767 |
* too close. Let's kick an extra TxPoll request when a burst |
|
2768 |
* of start_xmit activity is detected (if it is not detected, |
|
2769 |
* it is slow enough). -- FR |
|
2770 |
*/ |
|
2771 |
smp_rmb(); |
|
2772 |
if (tp->cur_tx != dirty_tx) |
|
2773 |
RTL_W8(TxPoll, NPQ); |
|
2774 |
} |
|
2775 |
} |
|
2776 |
||
2777 |
static inline int rtl8169_fragmented_frame(u32 status) |
|
2778 |
{
|
|
2779 |
return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
2780 |
} |
|
2781 |
||
2782 |
static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
|
2783 |
{
|
|
2784 |
u32 opts1 = le32_to_cpu(desc->opts1); |
|
2785 |
u32 status = opts1 & RxProtoMask; |
|
2786 |
||
2787 |
if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
2788 |
((status == RxProtoUDP) && !(opts1 & UDPFail)) || |
|
2789 |
((status == RxProtoIP) && !(opts1 & IPFail))) |
|
2790 |
skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
2791 |
else |
|
2792 |
skb->ip_summed = CHECKSUM_NONE; |
|
2793 |
} |
|
2794 |
||
2795 |
static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
|
2796 |
struct rtl8169_private *tp, int pkt_size, |
|
2797 |
dma_addr_t addr) |
|
2798 |
{
|
|
2799 |
struct sk_buff *skb; |
|
2800 |
bool done = false; |
|
2801 |
||
2802 |
if (pkt_size >= rx_copybreak) |
|
2803 |
goto out; |
|
2804 |
||
2805 |
skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
|
2806 |
if (!skb) |
|
2807 |
goto out; |
|
2808 |
||
2809 |
pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
|
2810 |
PCI_DMA_FROMDEVICE); |
|
2811 |
skb_reserve(skb, NET_IP_ALIGN); |
|
2812 |
skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
|
2813 |
*sk_buff = skb; |
|
2814 |
done = true; |
|
2815 |
out: |
|
2816 |
return done; |
|
2817 |
} |
|
2818 |
||
2819 |
static int rtl8169_rx_interrupt(struct net_device *dev, |
|
2820 |
struct rtl8169_private *tp, |
|
2821 |
void __iomem *ioaddr, u32 budget) |
|
2822 |
{
|
|
2823 |
unsigned int cur_rx, rx_left; |
|
2824 |
unsigned int delta, count; |
|
2825 |
||
2826 |
cur_rx = tp->cur_rx; |
|
2827 |
rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
2828 |
rx_left = rtl8169_rx_quota(rx_left, budget); |
|
2829 |
||
2830 |
for (; rx_left > 0; rx_left--, cur_rx++) {
|
|
2831 |
unsigned int entry = cur_rx % NUM_RX_DESC; |
|
2832 |
struct RxDesc *desc = tp->RxDescArray + entry; |
|
2833 |
u32 status; |
|
2834 |
||
2835 |
rmb(); |
|
2836 |
status = le32_to_cpu(desc->opts1); |
|
2837 |
||
2838 |
if (status & DescOwn) |
|
2839 |
break; |
|
2840 |
if (unlikely(status & RxRES)) {
|
|
2841 |
if (netif_msg_rx_err(tp)) {
|
|
2842 |
printk(KERN_INFO |
|
2843 |
"%s: Rx ERROR. status = %08x\n", |
|
2844 |
dev->name, status); |
|
2845 |
} |
|
2846 |
dev->stats.rx_errors++; |
|
2847 |
if (status & (RxRWT | RxRUNT)) |
|
2848 |
dev->stats.rx_length_errors++; |
|
2849 |
if (status & RxCRC) |
|
2850 |
dev->stats.rx_crc_errors++; |
|
2851 |
if (status & RxFOVF) {
|
|
2852 |
if (!tp->ecdev) |
|
2853 |
rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2854 |
dev->stats.rx_fifo_errors++; |
|
2855 |
} |
|
2856 |
rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2857 |
} else {
|
|
2858 |
struct sk_buff *skb = tp->Rx_skbuff[entry]; |
|
2859 |
dma_addr_t addr = le64_to_cpu(desc->addr); |
|
2860 |
int pkt_size = (status & 0x00001FFF) - 4; |
|
2861 |
struct pci_dev *pdev = tp->pci_dev; |
|
2862 |
||
2863 |
/* |
|
2864 |
* The driver does not support incoming fragmented |
|
2865 |
* frames. They are seen as a symptom of over-mtu |
|
2866 |
* sized frames. |
|
2867 |
*/ |
|
2868 |
if (unlikely(rtl8169_fragmented_frame(status))) {
|
|
2869 |
dev->stats.rx_dropped++; |
|
2870 |
dev->stats.rx_length_errors++; |
|
2871 |
rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2872 |
continue; |
|
2873 |
} |
|
2874 |
||
2875 |
rtl8169_rx_csum(skb, desc); |
|
2876 |
||
2877 |
if (tp->ecdev) {
|
|
2878 |
pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, |
|
2879 |
PCI_DMA_FROMDEVICE); |
|
2880 |
||
2881 |
ecdev_receive(tp->ecdev, skb->data, pkt_size); |
|
2882 |
||
2883 |
pci_dma_sync_single_for_device(pdev, addr, |
|
2884 |
pkt_size, PCI_DMA_FROMDEVICE); |
|
2885 |
rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2886 |
||
2887 |
// No need to detect link status as |
|
2888 |
// long as frames are received: Reset watchdog. |
|
2889 |
tp->ec_watchdog_jiffies = jiffies; |
|
2890 |
} else {
|
|
2891 |
if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
|
|
2892 |
pci_dma_sync_single_for_device(pdev, addr, |
|
2893 |
pkt_size, PCI_DMA_FROMDEVICE); |
|
2894 |
rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2895 |
} else {
|
|
2896 |
pci_unmap_single(pdev, addr, pkt_size, |
|
2897 |
PCI_DMA_FROMDEVICE); |
|
2898 |
tp->Rx_skbuff[entry] = NULL; |
|
2899 |
} |
|
2900 |
||
2901 |
skb_put(skb, pkt_size); |
|
2902 |
skb->protocol = eth_type_trans(skb, dev); |
|
2903 |
||
2904 |
if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) |
|
2905 |
rtl8169_rx_skb(skb); |
|
2906 |
} |
|
2907 |
||
2908 |
dev->last_rx = jiffies; |
|
2909 |
dev->stats.rx_bytes += pkt_size; |
|
2910 |
dev->stats.rx_packets++; |
|
2911 |
} |
|
2912 |
||
2913 |
/* Work around for AMD plateform. */ |
|
2914 |
if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
2915 |
(tp->mac_version == RTL_GIGA_MAC_VER_05)) {
|
|
2916 |
desc->opts2 = 0; |
|
2917 |
cur_rx++; |
|
2918 |
} |
|
2919 |
} |
|
2920 |
||
2921 |
count = cur_rx - tp->cur_rx; |
|
2922 |
tp->cur_rx = cur_rx; |
|
2923 |
||
2924 |
if (tp->ecdev) {
|
|
2925 |
/* descriptors are cleaned up immediately. */ |
|
2926 |
tp->dirty_rx = tp->cur_rx; |
|
2927 |
} else {
|
|
2928 |
delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); |
|
2929 |
if (!delta && count && netif_msg_intr(tp)) |
|
2930 |
printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
|
2931 |
tp->dirty_rx += delta; |
|
2932 |
||
2933 |
/* |
|
2934 |
* FIXME: until there is periodic timer to try and refill the ring, |
|
2935 |
* a temporary shortage may definitely kill the Rx process. |
|
2936 |
* - disable the asic to try and avoid an overflow and kick it again |
|
2937 |
* after refill ? |
|
2938 |
* - how do others driver handle this condition (Uh oh...). |
|
2939 |
*/ |
|
2940 |
if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
|
2941 |
printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
|
2942 |
} |
|
2943 |
||
2944 |
return count; |
|
2945 |
} |
|
2946 |
||
2947 |
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
2948 |
{
|
|
2949 |
struct net_device *dev = dev_instance; |
|
2950 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
2951 |
int boguscnt = max_interrupt_work; |
|
2952 |
void __iomem *ioaddr = tp->mmio_addr; |
|
2953 |
int status; |
|
2954 |
int handled = 0; |
|
2955 |
||
2956 |
do {
|
|
2957 |
status = RTL_R16(IntrStatus); |
|
2958 |
||
2959 |
/* hotplug/major error/no more work/shared irq */ |
|
2960 |
if ((status == 0xFFFF) || !status) |
|
2961 |
break; |
|
2962 |
||
2963 |
handled = 1; |
|
2964 |
||
2965 |
if (unlikely(!tp->ecdev && !netif_running(dev))) {
|
|
2966 |
rtl8169_asic_down(ioaddr); |
|
2967 |
goto out; |
|
2968 |
} |
|
2969 |
||
2970 |
status &= tp->intr_mask; |
|
2971 |
RTL_W16(IntrStatus, |
|
2972 |
(status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
2973 |
||
2974 |
if (!(status & tp->intr_event)) |
|
2975 |
break; |
|
2976 |
||
2977 |
/* Work around for rx fifo overflow */ |
|
2978 |
if (!tp->ecdev && unlikely(status & RxFIFOOver) && |
|
2979 |
(tp->mac_version == RTL_GIGA_MAC_VER_11)) {
|
|
2980 |
netif_stop_queue(dev); |
|
2981 |
rtl8169_tx_timeout(dev); |
|
2982 |
break; |
|
2983 |
} |
|
2984 |
||
2985 |
if (unlikely(!tp->ecdev && (status & SYSErr))) {
|
|
2986 |
rtl8169_pcierr_interrupt(dev); |
|
2987 |
break; |
|
2988 |
} |
|
2989 |
||
2990 |
if (status & LinkChg) |
|
2991 |
rtl8169_check_link_status(dev, tp, ioaddr); |
|
2992 |
||
2993 |
#ifdef CONFIG_R8169_NAPI |
|
|
1376
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
2994 |
if (tp->ecdev) {
|
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
2995 |
/* Rx interrupt */ |
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
2996 |
if (status & (RxOK | RxOverflow | RxFIFOOver)) |
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
2997 |
rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0); |
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
2998 |
|
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
2999 |
/* Tx interrupt */ |
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
3000 |
if (status & (TxOK | TxErr)) |
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
3001 |
rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
3002 |
|
|
6b51a2201d41
Fixed r8169 frame reception if NAPI is enabled.
Florian Pose <fp@igh-essen.com>
parents:
1353
diff
changeset
|
3003 |
} else if (status & tp->napi_event) {
|
| 1353 | 3004 |
RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
3005 |
tp->intr_mask = ~tp->napi_event; |
|
3006 |
||
3007 |
if (likely(netif_rx_schedule_prep(dev, &tp->napi))) |
|
3008 |
__netif_rx_schedule(dev, &tp->napi); |
|
3009 |
else if (netif_msg_intr(tp)) {
|
|
3010 |
printk(KERN_INFO "%s: interrupt %04x in poll\n", |
|
3011 |
dev->name, status); |
|
3012 |
} |
|
3013 |
} |
|
3014 |
break; |
|
3015 |
#else |
|
3016 |
/* Rx interrupt */ |
|
3017 |
if (status & (RxOK | RxOverflow | RxFIFOOver)) |
|
3018 |
rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0); |
|
3019 |
||
3020 |
/* Tx interrupt */ |
|
3021 |
if (status & (TxOK | TxErr)) |
|
3022 |
rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
3023 |
#endif |
|
3024 |
||
3025 |
boguscnt--; |
|
3026 |
} while (boguscnt > 0); |
|
3027 |
||
3028 |
if (!tp->ecdev) {
|
|
3029 |
if (boguscnt <= 0) {
|
|
3030 |
if (netif_msg_intr(tp) && net_ratelimit() ) {
|
|
3031 |
printk(KERN_WARNING |
|
3032 |
"%s: Too much work at interrupt!\n", dev->name); |
|
3033 |
} |
|
3034 |
/* Clear all interrupt sources. */ |
|
3035 |
RTL_W16(IntrStatus, 0xffff); |
|
3036 |
} |
|
3037 |
} |
|
3038 |
out: |
|
3039 |
return IRQ_RETVAL(handled); |
|
3040 |
} |
|
3041 |
||
3042 |
#ifdef CONFIG_R8169_NAPI |
|
3043 |
static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
3044 |
{
|
|
3045 |
struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
3046 |
struct net_device *dev = tp->dev; |
|
3047 |
void __iomem *ioaddr = tp->mmio_addr; |
|
3048 |
int work_done; |
|
3049 |
||
3050 |
work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
|
3051 |
rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
3052 |
||
3053 |
if (work_done < budget) {
|
|
3054 |
netif_rx_complete(dev, napi); |
|
3055 |
tp->intr_mask = 0xffff; |
|
3056 |
/* |
|
3057 |
* 20040426: the barrier is not strictly required but the |
|
3058 |
* behavior of the irq handler could be less predictable |
|
3059 |
* without it. Btw, the lack of flush for the posted pci |
|
3060 |
* write is safe - FR |
|
3061 |
*/ |
|
3062 |
smp_wmb(); |
|
3063 |
RTL_W16(IntrMask, tp->intr_event); |
|
3064 |
} |
|
3065 |
||
3066 |
return work_done; |
|
3067 |
} |
|
3068 |
#endif |
|
3069 |
||
3070 |
static void rtl8169_down(struct net_device *dev) |
|
3071 |
{
|
|
3072 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
3073 |
void __iomem *ioaddr = tp->mmio_addr; |
|
3074 |
unsigned int intrmask; |
|
3075 |
||
3076 |
rtl8169_delete_timer(dev); |
|
3077 |
||
3078 |
if (!tp->ecdev) {
|
|
3079 |
netif_stop_queue(dev); |
|
3080 |
||
3081 |
#ifdef CONFIG_R8169_NAPI |
|
3082 |
napi_disable(&tp->napi); |
|
3083 |
#endif |
|
3084 |
} |
|
3085 |
||
3086 |
core_down: |
|
3087 |
if (!tp->ecdev) |
|
3088 |
spin_lock_irq(&tp->lock); |
|
3089 |
||
3090 |
rtl8169_asic_down(ioaddr); |
|
3091 |
||
3092 |
/* Update the error counts. */ |
|
3093 |
dev->stats.rx_missed_errors += RTL_R32(RxMissed); |
|
3094 |
RTL_W32(RxMissed, 0); |
|
3095 |
||
3096 |
if (!tp->ecdev) |
|
3097 |
spin_unlock_irq(&tp->lock); |
|
3098 |
||
3099 |
if (!tp->ecdev) |
|
3100 |
synchronize_irq(dev->irq); |
|
3101 |
||
3102 |
/* Give a racing hard_start_xmit a few cycles to complete. */ |
|
3103 |
synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
3104 |
||
3105 |
/* |
|
3106 |
* And now for the 50k$ question: are IRQ disabled or not ? |
|
3107 |
* |
|
3108 |
* Two paths lead here: |
|
3109 |
* 1) dev->close |
|
3110 |
* -> netif_running() is available to sync the current code and the |
|
3111 |
* IRQ handler. See rtl8169_interrupt for details. |
|
3112 |
* 2) dev->change_mtu |
|
3113 |
* -> rtl8169_poll can not be issued again and re-enable the |
|
3114 |
* interruptions. Let's simply issue the IRQ down sequence again. |
|
3115 |
* |
|
3116 |
* No loop if hotpluged or major error (0xffff). |
|
3117 |
*/ |
|
3118 |
intrmask = RTL_R16(IntrMask); |
|
3119 |
if (intrmask && (intrmask != 0xffff)) |
|
3120 |
goto core_down; |
|
3121 |
||
3122 |
rtl8169_tx_clear(tp); |
|
3123 |
||
3124 |
rtl8169_rx_clear(tp); |
|
3125 |
} |
|
3126 |
||
3127 |
static int rtl8169_close(struct net_device *dev) |
|
3128 |
{
|
|
3129 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
3130 |
struct pci_dev *pdev = tp->pci_dev; |
|
3131 |
||
3132 |
rtl8169_down(dev); |
|
3133 |
||
3134 |
if (!tp->ecdev) |
|
3135 |
free_irq(dev->irq, dev); |
|
3136 |
||
3137 |
pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
3138 |
tp->RxPhyAddr); |
|
3139 |
pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
3140 |
tp->TxPhyAddr); |
|
3141 |
tp->TxDescArray = NULL; |
|
3142 |
tp->RxDescArray = NULL; |
|
3143 |
||
3144 |
return 0; |
|
3145 |
} |
|
3146 |
||
3147 |
static void rtl_set_rx_mode(struct net_device *dev) |
|
3148 |
{
|
|
3149 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
3150 |
void __iomem *ioaddr = tp->mmio_addr; |
|
3151 |
unsigned long flags; |
|
3152 |
u32 mc_filter[2]; /* Multicast hash filter */ |
|
3153 |
int rx_mode; |
|
3154 |
u32 tmp = 0; |
|
3155 |
||
3156 |
if (dev->flags & IFF_PROMISC) {
|
|
3157 |
/* Unconditionally log net taps. */ |
|
3158 |
if (netif_msg_link(tp)) {
|
|
3159 |
printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", |
|
3160 |
dev->name); |
|
3161 |
} |
|
3162 |
rx_mode = |
|
3163 |
AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
3164 |
AcceptAllPhys; |
|
3165 |
mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3166 |
} else if ((dev->mc_count > multicast_filter_limit) |
|
3167 |
|| (dev->flags & IFF_ALLMULTI)) {
|
|
3168 |
/* Too many to filter perfectly -- accept all multicasts. */ |
|
3169 |
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
3170 |
mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3171 |
} else {
|
|
3172 |
struct dev_mc_list *mclist; |
|
3173 |
unsigned int i; |
|
3174 |
||
3175 |
rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
3176 |
mc_filter[1] = mc_filter[0] = 0; |
|
3177 |
for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; |
|
3178 |
i++, mclist = mclist->next) {
|
|
3179 |
int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; |
|
3180 |
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
3181 |
rx_mode |= AcceptMulticast; |
|
3182 |
} |
|
3183 |
} |
|
3184 |
||
3185 |
spin_lock_irqsave(&tp->lock, flags); |
|
3186 |
||
3187 |
tmp = rtl8169_rx_config | rx_mode | |
|
3188 |
(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
3189 |
||
3190 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
|
3191 |
(tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
3192 |
(tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
3193 |
(tp->mac_version == RTL_GIGA_MAC_VER_14) || |
|
3194 |
(tp->mac_version == RTL_GIGA_MAC_VER_15) || |
|
3195 |
(tp->mac_version == RTL_GIGA_MAC_VER_16) || |
|
3196 |
(tp->mac_version == RTL_GIGA_MAC_VER_17)) {
|
|
3197 |
mc_filter[0] = 0xffffffff; |
|
3198 |
mc_filter[1] = 0xffffffff; |
|
3199 |
} |
|
3200 |
||
3201 |
RTL_W32(MAR0 + 0, mc_filter[0]); |
|
3202 |
RTL_W32(MAR0 + 4, mc_filter[1]); |
|
3203 |
||
3204 |
RTL_W32(RxConfig, tmp); |
|
3205 |
||
3206 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
3207 |
} |
|
3208 |
||
3209 |
/** |
|
3210 |
* rtl8169_get_stats - Get rtl8169 read/write statistics |
|
3211 |
* @dev: The Ethernet Device to get statistics for |
|
3212 |
* |
|
3213 |
* Get TX/RX statistics for rtl8169 |
|
3214 |
*/ |
|
3215 |
static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
3216 |
{
|
|
3217 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
3218 |
void __iomem *ioaddr = tp->mmio_addr; |
|
3219 |
unsigned long flags; |
|
3220 |
||
3221 |
if (netif_running(dev)) {
|
|
3222 |
spin_lock_irqsave(&tp->lock, flags); |
|
3223 |
dev->stats.rx_missed_errors += RTL_R32(RxMissed); |
|
3224 |
RTL_W32(RxMissed, 0); |
|
3225 |
spin_unlock_irqrestore(&tp->lock, flags); |
|
3226 |
} |
|
3227 |
||
3228 |
return &dev->stats; |
|
3229 |
} |
|
3230 |
||
3231 |
#ifdef CONFIG_PM |
|
3232 |
||
3233 |
static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) |
|
3234 |
{
|
|
3235 |
struct net_device *dev = pci_get_drvdata(pdev); |
|
3236 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
3237 |
void __iomem *ioaddr = tp->mmio_addr; |
|
3238 |
||
3239 |
if (tp->ecdev) |
|
3240 |
return; |
|
3241 |
||
3242 |
if (!netif_running(dev)) |
|
3243 |
goto out_pci_suspend; |
|
3244 |
||
3245 |
netif_device_detach(dev); |
|
3246 |
netif_stop_queue(dev); |
|
3247 |
||
3248 |
spin_lock_irq(&tp->lock); |
|
3249 |
||
3250 |
rtl8169_asic_down(ioaddr); |
|
3251 |
||
3252 |
dev->stats.rx_missed_errors += RTL_R32(RxMissed); |
|
3253 |
RTL_W32(RxMissed, 0); |
|
3254 |
||
3255 |
spin_unlock_irq(&tp->lock); |
|
3256 |
||
3257 |
out_pci_suspend: |
|
3258 |
pci_save_state(pdev); |
|
3259 |
pci_enable_wake(pdev, pci_choose_state(pdev, state), |
|
3260 |
(tp->features & RTL_FEATURE_WOL) ? 1 : 0); |
|
3261 |
pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
|
3262 |
||
3263 |
return 0; |
|
3264 |
} |
|
3265 |
||
3266 |
static int rtl8169_resume(struct pci_dev *pdev) |
|
3267 |
{
|
|
3268 |
struct net_device *dev = pci_get_drvdata(pdev); |
|
3269 |
struct rtl8169_private *tp = netdev_priv(dev); |
|
3270 |
||
3271 |
if (tp->ecdev) |
|
3272 |
return; |
|
3273 |
||
3274 |
pci_set_power_state(pdev, PCI_D0); |
|
3275 |
pci_restore_state(pdev); |
|
3276 |
pci_enable_wake(pdev, PCI_D0, 0); |
|
3277 |
||
3278 |
if (!netif_running(dev)) |
|
3279 |
goto out; |
|
3280 |
||
3281 |
netif_device_attach(dev); |
|
3282 |
||
3283 |
rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3284 |
out: |
|
3285 |
return 0; |
|
3286 |
} |
|
3287 |
||
3288 |
#endif /* CONFIG_PM */ |
|
3289 |
||
3290 |
static struct pci_driver rtl8169_pci_driver = {
|
|
3291 |
.name = MODULENAME, |
|
3292 |
.id_table = rtl8169_pci_tbl, |
|
3293 |
.probe = rtl8169_init_one, |
|
3294 |
.remove = __devexit_p(rtl8169_remove_one), |
|
3295 |
#ifdef CONFIG_PM |
|
3296 |
.suspend = rtl8169_suspend, |
|
3297 |
.resume = rtl8169_resume, |
|
3298 |
#endif |
|
3299 |
}; |
|
3300 |
||
3301 |
static int __init rtl8169_init_module(void) |
|
3302 |
{
|
|
3303 |
return pci_register_driver(&rtl8169_pci_driver); |
|
3304 |
} |
|
3305 |
||
3306 |
static void __exit rtl8169_cleanup_module(void) |
|
3307 |
{
|
|
3308 |
pci_unregister_driver(&rtl8169_pci_driver); |
|
3309 |
} |
|
3310 |
||
3311 |
module_init(rtl8169_init_module); |
|
3312 |
module_exit(rtl8169_cleanup_module); |