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/******************************************************************************

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 *

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 *  $Id$

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 *

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 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

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 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; either version 2 of the

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 *  License, or (at your option) any later version.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

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 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License

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 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  The right to use EtherCAT Technology is granted and comes free of

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 *  charge under condition of compatibility of product made by

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 *  Licensee. People intending to distribute/sell products based on the

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 *  code, have to sign an agreement to guarantee that products using

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 *  software based on IgH EtherCAT master stay compatible with the actual

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 *  EtherCAT specification (which are released themselves as an open

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 *  standard) as the (only) precondition to have the right to use EtherCAT

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 *  Technology, IP and trade marks.

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 *

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 *****************************************************************************/

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    34

/*

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 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

    36

 *

    37

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

    38

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

    39

 * Copyright (c) a lot of people too. Please respect their work.

    40

 *

    41

 * See MAINTAINERS file for support contact information.

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 */

    43

    44

#include <linux/module.h>

    45

#include <linux/moduleparam.h>

    46

#include <linux/pci.h>

    47

#include <linux/netdevice.h>

    48

#include <linux/etherdevice.h>

    49

#include <linux/delay.h>

    50

#include <linux/ethtool.h>

    51

#include <linux/mii.h>

    52

#include <linux/if_vlan.h>

    53

#include <linux/crc32.h>

    54

#include <linux/in.h>

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#include <linux/ip.h>

    56

#include <linux/tcp.h>

    57

#include <linux/init.h>

    58

#include <linux/dma-mapping.h>

    59

    60

#include <asm/system.h>

    61

#include <asm/io.h>

    62

#include <asm/irq.h>

    63

    64

#ifdef CONFIG_R8169_NAPI

    65

#define NAPI_SUFFIX	"-NAPI"

    66

#else

    67

#define NAPI_SUFFIX	""

    68

#endif

    69

    70

#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX

    71

#define MODULENAME "r8169"

    72

#define PFX MODULENAME ": "

    73

    74

#include "../globals.h"

    75

#include "ecdev.h"

    76

    77

#ifdef RTL8169_DEBUG

    78

#define assert(expr) \

    79

	if (!(expr)) {					\

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		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

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		#expr,__FILE__,__FUNCTION__,__LINE__);		\

    82

	}

    83

#define dprintk(fmt, args...)	do { printk(PFX fmt, ## args); } while (0)

    84

#else

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#define assert(expr) do {} while (0)

    86

#define dprintk(fmt, args...)	do {} while (0)

    87

#endif /* RTL8169_DEBUG */

    88

    89

#define R8169_MSG_DEFAULT \

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	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    91

    92

#define TX_BUFFS_AVAIL(tp) \

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	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    94

    95

#ifdef CONFIG_R8169_NAPI

    96

#define rtl8169_rx_skb			netif_receive_skb

    97

#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_receive_skb

    98

#define rtl8169_rx_quota(count, quota)	min(count, quota)

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#else

   100

#define rtl8169_rx_skb			netif_rx

   101

#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_rx

   102

#define rtl8169_rx_quota(count, quota)	count

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#endif

   104

   105

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

   106

static const int max_interrupt_work = 20;

   107

   108

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   109

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

   110

static const int multicast_filter_limit = 32;

   111

   112

/* MAC address length */

   113

#define MAC_ADDR_LEN	6

   114

   115

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

   116

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   117

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   118

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

   119

#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */

   120

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

   121

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

   122

   123

#define R8169_REGS_SIZE		256

   124

#define R8169_NAPI_WEIGHT	64

   125

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

   126

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

   127

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

   128

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

   129

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

   130

   131

#define RTL8169_TX_TIMEOUT	(6*HZ)

   132

#define RTL8169_PHY_TIMEOUT	(10*HZ)

   133

   134

/* write/read MMIO register */

   135

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

   136

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

   137

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

   138

#define RTL_R8(reg)		readb (ioaddr + (reg))

   139

#define RTL_R16(reg)		readw (ioaddr + (reg))

   140

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

   141

   142

enum mac_version {

   143

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

   144

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

   145

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

   146

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

   147

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

   148

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

   149

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   150

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf

   151

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec

   152

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101

   153

	RTL_GIGA_MAC_VER_15 = 0x0f  // 8101

   154

};

   155

   156

enum phy_version {

   157

	RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */

   158

	RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */

   159

	RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */

   160

	RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */

   161

	RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */

   162

	RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */

   163

};

   164

   165

#define _R(NAME,MAC,MASK) \

   166

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   167

   168

static const struct {

   169

	const char *name;

   170

	u8 mac_version;

   171

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   172

} rtl_chip_info[] = {

   173

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   174

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   175

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   176

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   177

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   178

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   179

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   180

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   181

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   182

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   183

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139

   184

};

   185

#undef _R

   186

   187

enum cfg_version {

   188

	RTL_CFG_0 = 0x00,

   189

	RTL_CFG_1,

   190

	RTL_CFG_2

   191

};

   192

   193

static void rtl_hw_start_8169(struct net_device *);

   194

static void rtl_hw_start_8168(struct net_device *);

   195

static void rtl_hw_start_8101(struct net_device *);

   196

   197

static struct pci_device_id rtl8169_pci_tbl[] = {

   198

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   199

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   201

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   202

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   203

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   204

	{ PCI_DEVICE(0x1259,			0xc107), 0, 0, RTL_CFG_0 },

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	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   206

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   207

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   208

	{0,},

   209

};

   210

   211

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   212

   213

static int rx_copybreak = 200;

   214

static int use_dac;

   215

static struct {

   216

	u32 msg_enable;

   217

} debug = { -1 };

   218

   219

enum rtl_registers {

   220

	MAC0		= 0,	/* Ethernet hardware address. */

   221

	MAC4		= 4,

   222

	MAR0		= 8,	/* Multicast filter. */

   223

	CounterAddrLow		= 0x10,

   224

	CounterAddrHigh		= 0x14,

   225

	TxDescStartAddrLow	= 0x20,

   226

	TxDescStartAddrHigh	= 0x24,

   227

	TxHDescStartAddrLow	= 0x28,

   228

	TxHDescStartAddrHigh	= 0x2c,

   229

	FLASH		= 0x30,

   230

	ERSR		= 0x36,

   231

	ChipCmd		= 0x37,

   232

	TxPoll		= 0x38,

   233

	IntrMask	= 0x3c,

   234

	IntrStatus	= 0x3e,

   235

	TxConfig	= 0x40,

   236

	RxConfig	= 0x44,

   237

	RxMissed	= 0x4c,

   238

	Cfg9346		= 0x50,

   239

	Config0		= 0x51,

   240

	Config1		= 0x52,

   241

	Config2		= 0x53,

   242

	Config3		= 0x54,

   243

	Config4		= 0x55,

   244

	Config5		= 0x56,

   245

	MultiIntr	= 0x5c,

   246

	PHYAR		= 0x60,

   247

	TBICSR		= 0x64,

   248

	TBI_ANAR	= 0x68,

   249

	TBI_LPAR	= 0x6a,

   250

	PHYstatus	= 0x6c,

   251

	RxMaxSize	= 0xda,

   252

	CPlusCmd	= 0xe0,

   253

	IntrMitigate	= 0xe2,

   254

	RxDescAddrLow	= 0xe4,

   255

	RxDescAddrHigh	= 0xe8,

   256

	EarlyTxThres	= 0xec,

   257

	FuncEvent	= 0xf0,

   258

	FuncEventMask	= 0xf4,

   259

	FuncPresetState	= 0xf8,

   260

	FuncForceEvent	= 0xfc,

   261

};

   262

   263

enum rtl_register_content {

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	/* InterruptStatusBits */

   265

	SYSErr		= 0x8000,

   266

	PCSTimeout	= 0x4000,

   267

	SWInt		= 0x0100,

   268

	TxDescUnavail	= 0x0080,

   269

	RxFIFOOver	= 0x0040,

   270

	LinkChg		= 0x0020,

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	RxOverflow	= 0x0010,

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	TxErr		= 0x0008,

   273

	TxOK		= 0x0004,

   274

	RxErr		= 0x0002,

   275

	RxOK		= 0x0001,

   276

   277

	/* RxStatusDesc */

   278

	RxFOVF	= (1 << 23),

   279

	RxRWT	= (1 << 22),

   280

	RxRES	= (1 << 21),

   281

	RxRUNT	= (1 << 20),

   282

	RxCRC	= (1 << 19),

   283

   284

	/* ChipCmdBits */

   285

	CmdReset	= 0x10,

   286

	CmdRxEnb	= 0x08,

   287

	CmdTxEnb	= 0x04,

   288

	RxBufEmpty	= 0x01,

   289

   290

	/* TXPoll register p.5 */

   291

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   292

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   293

	FSWInt		= 0x01,		/* Forced software interrupt */

   294

   295

	/* Cfg9346Bits */

   296

	Cfg9346_Lock	= 0x00,

   297

	Cfg9346_Unlock	= 0xc0,

   298

   299

	/* rx_mode_bits */

   300

	AcceptErr	= 0x20,

   301

	AcceptRunt	= 0x10,

   302

	AcceptBroadcast	= 0x08,

   303

	AcceptMulticast	= 0x04,

   304

	AcceptMyPhys	= 0x02,

   305

	AcceptAllPhys	= 0x01,

   306

   307

	/* RxConfigBits */

   308

	RxCfgFIFOShift	= 13,

   309

	RxCfgDMAShift	=  8,

   310

   311

	/* TxConfigBits */

   312

	TxInterFrameGapShift = 24,

   313

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   314

   315

	/* Config1 register p.24 */

   316

	PMEnable	= (1 << 0),	/* Power Management Enable */

   317

   318

	/* Config2 register p. 25 */

   319

	PCI_Clock_66MHz = 0x01,

   320

	PCI_Clock_33MHz = 0x00,

   321

   322

	/* Config3 register p.25 */

   323

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   324

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   325

   326

	/* Config5 register p.27 */

   327

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   328

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   329

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   330

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   331

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   332

   333

	/* TBICSR p.28 */

   334

	TBIReset	= 0x80000000,

   335

	TBILoopback	= 0x40000000,

   336

	TBINwEnable	= 0x20000000,

   337

	TBINwRestart	= 0x10000000,

   338

	TBILinkOk	= 0x02000000,

   339

	TBINwComplete	= 0x01000000,

   340

   341

	/* CPlusCmd p.31 */

   342

	PktCntrDisable	= (1 << 7),	// 8168

   343

	RxVlan		= (1 << 6),

   344

	RxChkSum	= (1 << 5),

   345

	PCIDAC		= (1 << 4),

   346

	PCIMulRW	= (1 << 3),

   347

	INTT_0		= 0x0000,	// 8168

   348

	INTT_1		= 0x0001,	// 8168

   349

	INTT_2		= 0x0002,	// 8168

   350

	INTT_3		= 0x0003,	// 8168

   351

   352

	/* rtl8169_PHYstatus */

   353

	TBI_Enable	= 0x80,

   354

	TxFlowCtrl	= 0x40,

   355

	RxFlowCtrl	= 0x20,

   356

	_1000bpsF	= 0x10,

   357

	_100bps		= 0x08,

   358

	_10bps		= 0x04,

   359

	LinkStatus	= 0x02,

   360

	FullDup		= 0x01,

   361

   362

	/* _TBICSRBit */

   363

	TBILinkOK	= 0x02000000,

   364

   365

	/* DumpCounterCommand */

   366

	CounterDump	= 0x8,

   367

};

   368

   369

enum desc_status_bit {

   370

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   371

	RingEnd		= (1 << 30), /* End of descriptor ring */

   372

	FirstFrag	= (1 << 29), /* First segment of a packet */

   373

	LastFrag	= (1 << 28), /* Final segment of a packet */

   374

   375

	/* Tx private */

   376

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   377

	MSSShift	= 16,        /* MSS value position */

   378

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   379

	IPCS		= (1 << 18), /* Calculate IP checksum */

   380

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   381

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   382

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   383

   384

	/* Rx private */

   385

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   386

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   387

   388

#define RxProtoUDP	(PID1)

   389

#define RxProtoTCP	(PID0)

   390

#define RxProtoIP	(PID1 | PID0)

   391

#define RxProtoMask	RxProtoIP

   392

   393

	IPFail		= (1 << 16), /* IP checksum failed */

   394

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   395

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   396

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   397

};

   398

   399

#define RsvdMask	0x3fffc000

   400

   401

struct TxDesc {

   402

	__le32 opts1;

   403

	__le32 opts2;

   404

	__le64 addr;

   405

};

   406

   407

struct RxDesc {

   408

	__le32 opts1;

   409

	__le32 opts2;

   410

	__le64 addr;

   411

};

   412

   413

struct ring_info {

   414

	struct sk_buff	*skb;

   415

	u32		len;

   416

	u8		__pad[sizeof(void *) - sizeof(u32)];

   417

};

   418

   419

struct rtl8169_private {

   420

	void __iomem *mmio_addr;	/* memory map physical address */

   421

	struct pci_dev *pci_dev;	/* Index of PCI device */

   422

	struct net_device *dev;

   423

	struct net_device_stats stats;	/* statistics of net device */

   424

	spinlock_t lock;		/* spin lock flag */

   425

	u32 msg_enable;

   426

	int chipset;

   427

	int mac_version;

   428

	int phy_version;

   429

	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   430

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   431

	u32 dirty_rx;

   432

	u32 dirty_tx;

   433

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   434

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   435

	dma_addr_t TxPhyAddr;

   436

	dma_addr_t RxPhyAddr;

   437

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   438

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

   439

	unsigned align;

   440

	unsigned rx_buf_sz;

   441

	struct timer_list timer;

   442

	u16 cp_cmd;

   443

	u16 intr_event;

   444

	u16 napi_event;

   445

	u16 intr_mask;

   446

	int phy_auto_nego_reg;

   447

	int phy_1000_ctrl_reg;

   448

#ifdef CONFIG_R8169_VLAN

   449

	struct vlan_group *vlgrp;

   450

#endif

   451

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   452

	void (*get_settings)(struct net_device *, struct ethtool_cmd *);

   453

	void (*phy_reset_enable)(void __iomem *);

   454

	void (*hw_start)(struct net_device *);

   455

	unsigned int (*phy_reset_pending)(void __iomem *);

   456

	unsigned int (*link_ok)(void __iomem *);

   457

	struct delayed_work task;

   458

	unsigned wol_enabled : 1;

   459

   460

	ec_device_t *ecdev;

   461

};

   462

   463

MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");

   464

MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet/EtherCAT driver");

   465

module_param(rx_copybreak, int, 0);

   466

MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

   467

module_param(use_dac, int, 0);

   468

MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

   469

module_param_named(debug, debug.msg_enable, int, 0);

   470

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   471

MODULE_LICENSE("GPL");

   472

MODULE_VERSION(RTL8169_VERSION);

   473

   474

void ec_poll(struct net_device *);

   475

   476

static int rtl8169_open(struct net_device *dev);

   477

static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);

   478

static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);

   479

static int rtl8169_init_ring(struct net_device *dev);

   480

static void rtl_hw_start(struct net_device *dev);

   481

static int rtl8169_close(struct net_device *dev);

   482

static void rtl_set_rx_mode(struct net_device *dev);

   483

static void rtl8169_tx_timeout(struct net_device *dev);

   484

static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);

   485

static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,

   486

				void __iomem *);

   487

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);

   488

static void rtl8169_down(struct net_device *dev);

   489

static void rtl8169_rx_clear(struct rtl8169_private *tp);

   490

   491

#ifdef CONFIG_R8169_NAPI

   492

static int rtl8169_poll(struct net_device *dev, int *budget);

   493

#endif

   494

   495

static const unsigned int rtl8169_rx_config =

   496

	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);

   497

   498

static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)

   499

{

   500

	int i;

   501

   502

	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);

   503

   504

	for (i = 20; i > 0; i--) {

   505

		/*

   506

		 * Check if the RTL8169 has completed writing to the specified

   507

		 * MII register.

   508

		 */

   509

		if (!(RTL_R32(PHYAR) & 0x80000000))

   510

			break;

   511

		udelay(25);

   512

	}

   513

}

   514

   515

static int mdio_read(void __iomem *ioaddr, int reg_addr)

   516

{

   517

	int i, value = -1;

   518

   519

	RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);

   520

   521

	for (i = 20; i > 0; i--) {

   522

		/*

   523

		 * Check if the RTL8169 has completed retrieving data from

   524

		 * the specified MII register.

   525

		 */

   526

		if (RTL_R32(PHYAR) & 0x80000000) {

   527

			value = (int) (RTL_R32(PHYAR) & 0xFFFF);

   528

			break;

   529

		}

   530

		udelay(25);