1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 */

    10

    11

#include <linux/module.h>

    12

#include <linux/moduleparam.h>

    13

#include <linux/pci.h>

    14

#include <linux/netdevice.h>

    15

#include <linux/etherdevice.h>

    16

#include <linux/delay.h>

    17

#include <linux/ethtool.h>

    18

#include <linux/mii.h>

    19

#include <linux/if_vlan.h>

    20

#include <linux/crc32.h>

    21

#include <linux/in.h>

    22

#include <linux/ip.h>

    23

#include <linux/tcp.h>

    24

#include <linux/init.h>

    25

#include <linux/dma-mapping.h>

    26

    27

#include <asm/system.h>

    28

#include <asm/io.h>

    29

#include <asm/irq.h>

    30

    31

#ifdef CONFIG_R8169_NAPI

    32

#define NAPI_SUFFIX	"-NAPI"

    33

#else

    34

#define NAPI_SUFFIX	""

    35

#endif

    36

    37

#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX

    38

#define MODULENAME "r8169"

    39

#define PFX MODULENAME ": "

    40

    41

#ifdef RTL8169_DEBUG

    42

#define assert(expr) \

    43

	if (!(expr)) {					\

    44

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    45

		#expr,__FILE__,__FUNCTION__,__LINE__);		\

    46

	}

    47

#define dprintk(fmt, args...) \

    48

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    49

#else

    50

#define assert(expr) do {} while (0)

    51

#define dprintk(fmt, args...)	do {} while (0)

    52

#endif /* RTL8169_DEBUG */

    53

    54

#define R8169_MSG_DEFAULT \

    55

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    56

    57

#define TX_BUFFS_AVAIL(tp) \

    58

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    59

    60

#ifdef CONFIG_R8169_NAPI

    61

#define rtl8169_rx_skb			netif_receive_skb

    62

#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_receive_skb

    63

#define rtl8169_rx_quota(count, quota)	min(count, quota)

    64

#else

    65

#define rtl8169_rx_skb			netif_rx

    66

#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_rx

    67

#define rtl8169_rx_quota(count, quota)	count

    68

#endif

    69

    70

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

    71

static const int max_interrupt_work = 20;

    72

    73

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    74

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    75

static const int multicast_filter_limit = 32;

    76

    77

/* MAC address length */

    78

#define MAC_ADDR_LEN	6

    79

    80

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

    81

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    82

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    83

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

    84

#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */

    85

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    86

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    87

    88

#define R8169_REGS_SIZE		256

    89

#define R8169_NAPI_WEIGHT	64

    90

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    91

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    92

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    93

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    94

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    95

    96

#define RTL8169_TX_TIMEOUT	(6*HZ)

    97

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    98

    99

/* write/read MMIO register */

   100

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

   101

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

   102

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

   103

#define RTL_R8(reg)		readb (ioaddr + (reg))

   104

#define RTL_R16(reg)		readw (ioaddr + (reg))

   105

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

   106

   107

enum mac_version {

   108

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

   109

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

   110

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

   111

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

   112

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

   113

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

   114

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   115

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be

   116

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb

   117

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?

   118

	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?

   119

	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec

   120

	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf

   121

	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP

   122

	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C

   123

	RTL_GIGA_MAC_VER_20 = 0x14  // 8168C

   124

};

   125

   126

#define _R(NAME,MAC,MASK) \

   127

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   128

   129

static const struct {

   130

	const char *name;

   131

	u8 mac_version;

   132

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   133

} rtl_chip_info[] = {

   134

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   135

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   136

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   137

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   138

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   139

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   140

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   141

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   142

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   143

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   144

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139

   145

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E

   146

	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E

   147

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E

   148

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E

   149

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E

   150

};

   151

#undef _R

   152

   153

enum cfg_version {

   154

	RTL_CFG_0 = 0x00,

   155

	RTL_CFG_1,

   156

	RTL_CFG_2

   157

};

   158

   159

static void rtl_hw_start_8169(struct net_device *);

   160

static void rtl_hw_start_8168(struct net_device *);

   161

static void rtl_hw_start_8101(struct net_device *);

   162

   163

static struct pci_device_id rtl8169_pci_tbl[] = {

   164

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   165

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   166

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   167

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   168

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   169

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   170

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   171

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   172

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   173

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   174

	{ 0x0001,				0x8168,

   175

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   176

	{0,},

   177

};

   178

   179

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   180

   181

static int rx_copybreak = 200;

   182

static int use_dac;

   183

static struct {

   184

	u32 msg_enable;

   185

} debug = { -1 };

   186

   187

enum rtl_registers {

   188

	MAC0		= 0,	/* Ethernet hardware address. */

   189

	MAC4		= 4,

   190

	MAR0		= 8,	/* Multicast filter. */

   191

	CounterAddrLow		= 0x10,

   192

	CounterAddrHigh		= 0x14,

   193

	TxDescStartAddrLow	= 0x20,

   194

	TxDescStartAddrHigh	= 0x24,

   195

	TxHDescStartAddrLow	= 0x28,

   196

	TxHDescStartAddrHigh	= 0x2c,

   197

	FLASH		= 0x30,

   198

	ERSR		= 0x36,

   199

	ChipCmd		= 0x37,

   200

	TxPoll		= 0x38,

   201

	IntrMask	= 0x3c,

   202

	IntrStatus	= 0x3e,

   203

	TxConfig	= 0x40,

   204

	RxConfig	= 0x44,

   205

	RxMissed	= 0x4c,

   206

	Cfg9346		= 0x50,

   207

	Config0		= 0x51,

   208

	Config1		= 0x52,

   209

	Config2		= 0x53,

   210

	Config3		= 0x54,

   211

	Config4		= 0x55,

   212

	Config5		= 0x56,

   213

	MultiIntr	= 0x5c,

   214

	PHYAR		= 0x60,

   215

	TBICSR		= 0x64,

   216

	TBI_ANAR	= 0x68,

   217

	TBI_LPAR	= 0x6a,

   218

	PHYstatus	= 0x6c,

   219

	RxMaxSize	= 0xda,

   220

	CPlusCmd	= 0xe0,

   221

	IntrMitigate	= 0xe2,

   222

	RxDescAddrLow	= 0xe4,

   223

	RxDescAddrHigh	= 0xe8,

   224

	EarlyTxThres	= 0xec,

   225

	FuncEvent	= 0xf0,

   226

	FuncEventMask	= 0xf4,

   227

	FuncPresetState	= 0xf8,

   228

	FuncForceEvent	= 0xfc,

   229

};

   230

   231

enum rtl_register_content {

   232

	/* InterruptStatusBits */

   233

	SYSErr		= 0x8000,

   234

	PCSTimeout	= 0x4000,

   235

	SWInt		= 0x0100,

   236

	TxDescUnavail	= 0x0080,

   237

	RxFIFOOver	= 0x0040,

   238

	LinkChg		= 0x0020,

   239

	RxOverflow	= 0x0010,

   240

	TxErr		= 0x0008,

   241

	TxOK		= 0x0004,

   242

	RxErr		= 0x0002,

   243

	RxOK		= 0x0001,

   244

   245

	/* RxStatusDesc */

   246

	RxFOVF	= (1 << 23),

   247

	RxRWT	= (1 << 22),

   248

	RxRES	= (1 << 21),

   249

	RxRUNT	= (1 << 20),

   250

	RxCRC	= (1 << 19),

   251

   252

	/* ChipCmdBits */

   253

	CmdReset	= 0x10,

   254

	CmdRxEnb	= 0x08,

   255

	CmdTxEnb	= 0x04,

   256

	RxBufEmpty	= 0x01,

   257

   258

	/* TXPoll register p.5 */

   259

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   260

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   261

	FSWInt		= 0x01,		/* Forced software interrupt */

   262

   263

	/* Cfg9346Bits */

   264

	Cfg9346_Lock	= 0x00,

   265

	Cfg9346_Unlock	= 0xc0,

   266

   267

	/* rx_mode_bits */

   268

	AcceptErr	= 0x20,

   269

	AcceptRunt	= 0x10,

   270

	AcceptBroadcast	= 0x08,

   271

	AcceptMulticast	= 0x04,

   272

	AcceptMyPhys	= 0x02,

   273

	AcceptAllPhys	= 0x01,

   274

   275

	/* RxConfigBits */

   276

	RxCfgFIFOShift	= 13,

   277

	RxCfgDMAShift	=  8,

   278

   279

	/* TxConfigBits */

   280

	TxInterFrameGapShift = 24,

   281

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   282

   283

	/* Config1 register p.24 */

   284

	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */

   285

	PMEnable	= (1 << 0),	/* Power Management Enable */

   286

   287

	/* Config2 register p. 25 */

   288

	PCI_Clock_66MHz = 0x01,

   289

	PCI_Clock_33MHz = 0x00,

   290

   291

	/* Config3 register p.25 */

   292

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   293

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   294

   295

	/* Config5 register p.27 */

   296

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   297

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   298

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   299

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   300

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   301

   302

	/* TBICSR p.28 */

   303

	TBIReset	= 0x80000000,

   304

	TBILoopback	= 0x40000000,

   305

	TBINwEnable	= 0x20000000,

   306

	TBINwRestart	= 0x10000000,

   307

	TBILinkOk	= 0x02000000,

   308

	TBINwComplete	= 0x01000000,

   309

   310

	/* CPlusCmd p.31 */

   311

	PktCntrDisable	= (1 << 7),	// 8168

   312

	RxVlan		= (1 << 6),

   313

	RxChkSum	= (1 << 5),

   314

	PCIDAC		= (1 << 4),

   315

	PCIMulRW	= (1 << 3),

   316

	INTT_0		= 0x0000,	// 8168

   317

	INTT_1		= 0x0001,	// 8168

   318

	INTT_2		= 0x0002,	// 8168

   319

	INTT_3		= 0x0003,	// 8168

   320

   321

	/* rtl8169_PHYstatus */

   322

	TBI_Enable	= 0x80,

   323

	TxFlowCtrl	= 0x40,

   324

	RxFlowCtrl	= 0x20,

   325

	_1000bpsF	= 0x10,

   326

	_100bps		= 0x08,

   327

	_10bps		= 0x04,

   328

	LinkStatus	= 0x02,

   329

	FullDup		= 0x01,

   330

   331

	/* _TBICSRBit */

   332

	TBILinkOK	= 0x02000000,

   333

   334

	/* DumpCounterCommand */

   335

	CounterDump	= 0x8,

   336

};

   337

   338

enum desc_status_bit {

   339

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   340

	RingEnd		= (1 << 30), /* End of descriptor ring */

   341

	FirstFrag	= (1 << 29), /* First segment of a packet */

   342

	LastFrag	= (1 << 28), /* Final segment of a packet */

   343

   344

	/* Tx private */

   345

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   346

	MSSShift	= 16,        /* MSS value position */

   347

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   348

	IPCS		= (1 << 18), /* Calculate IP checksum */

   349

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   350

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   351

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   352

   353

	/* Rx private */

   354

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   355

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   356

   357

#define RxProtoUDP	(PID1)

   358

#define RxProtoTCP	(PID0)

   359

#define RxProtoIP	(PID1 | PID0)

   360

#define RxProtoMask	RxProtoIP

   361

   362

	IPFail		= (1 << 16), /* IP checksum failed */

   363

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   364

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   365

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   366

};

   367

   368

#define RsvdMask	0x3fffc000

   369

   370

struct TxDesc {

   371

	__le32 opts1;

   372

	__le32 opts2;

   373

	__le64 addr;

   374

};

   375

   376

struct RxDesc {

   377

	__le32 opts1;

   378

	__le32 opts2;

   379

	__le64 addr;

   380

};

   381

   382

struct ring_info {

   383

	struct sk_buff	*skb;

   384

	u32		len;

   385

	u8		__pad[sizeof(void *) - sizeof(u32)];

   386

};

   387

   388

enum features {

   389

	RTL_FEATURE_WOL	= (1 << 0),

   390

	RTL_FEATURE_MSI	= (1 << 1),

   391

};

   392

   393

struct rtl8169_private {

   394

	void __iomem *mmio_addr;	/* memory map physical address */

   395

	struct pci_dev *pci_dev;	/* Index of PCI device */

   396

	struct net_device *dev;

   397

#ifdef CONFIG_R8169_NAPI

   398

	struct napi_struct napi;

   399

#endif

   400

	spinlock_t lock;		/* spin lock flag */

   401

	u32 msg_enable;

   402

	int chipset;

   403

	int mac_version;

   404

	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   405

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   406

	u32 dirty_rx;

   407

	u32 dirty_tx;

   408

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   409

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   410

	dma_addr_t TxPhyAddr;

   411

	dma_addr_t RxPhyAddr;

   412

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   413

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

   414

	unsigned align;

   415

	unsigned rx_buf_sz;

   416

	struct timer_list timer;

   417

	u16 cp_cmd;

   418

	u16 intr_event;

   419

	u16 napi_event;

   420

	u16 intr_mask;

   421

	int phy_auto_nego_reg;

   422

	int phy_1000_ctrl_reg;

   423

#ifdef CONFIG_R8169_VLAN

   424

	struct vlan_group *vlgrp;

   425

#endif

   426

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   427

	void (*get_settings)(struct net_device *, struct ethtool_cmd *);

   428

	void (*phy_reset_enable)(void __iomem *);

   429

	void (*hw_start)(struct net_device *);

   430

	unsigned int (*phy_reset_pending)(void __iomem *);

   431

	unsigned int (*link_ok)(void __iomem *);

   432

	struct delayed_work task;

   433

	unsigned features;

   434

};

   435

   436

MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");

   437

MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");

   438

module_param(rx_copybreak, int, 0);

   439

MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

   440

module_param(use_dac, int, 0);

   441

MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

   442

module_param_named(debug, debug.msg_enable, int, 0);

   443

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   444

MODULE_LICENSE("GPL");

   445

MODULE_VERSION(RTL8169_VERSION);

   446

   447

static int rtl8169_open(struct net_device *dev);

   448

static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);

   449

static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);

   450

static int rtl8169_init_ring(struct net_device *dev);

   451

static void rtl_hw_start(struct net_device *dev);

   452

static int rtl8169_close(struct net_device *dev);

   453

static void rtl_set_rx_mode(struct net_device *dev);

   454

static void rtl8169_tx_timeout(struct net_device *dev);

   455

static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);

   456

static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,

   457

				void __iomem *, u32 budget);

   458

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);

   459

static void rtl8169_down(struct net_device *dev);

   460

static void rtl8169_rx_clear(struct rtl8169_private *tp);

   461

   462

#ifdef CONFIG_R8169_NAPI

   463

static int rtl8169_poll(struct napi_struct *napi, int budget);

   464

#endif

   465

   466

static const unsigned int rtl8169_rx_config =

   467

	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);

   468

   469

static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)

   470

{

   471

	int i;

   472

   473

	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));

   474

   475

	for (i = 20; i > 0; i--) {

   476

		/*

   477

		 * Check if the RTL8169 has completed writing to the specified

   478

		 * MII register.

   479

		 */

   480

		if (!(RTL_R32(PHYAR) & 0x80000000))

   481

			break;

   482

		udelay(25);

   483

	}

   484

}

   485

   486

static int mdio_read(void __iomem *ioaddr, int reg_addr)

   487

{

   488

	int i, value = -1;

   489

   490

	RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);

   491

   492

	for (i = 20; i > 0; i--) {

   493

		/*

   494

		 * Check if the RTL8169 has completed retrieving data from

   495

		 * the specified MII register.

   496

		 */

   497

		if (RTL_R32(PHYAR) & 0x80000000) {

   498

			value = RTL_R32(PHYAR) & 0xffff;

   499

			break;

   500

		}

   501

		udelay(25);

   502

	}

   503

	return value;

   504

}

   505

   506

static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)

   507

{

   508

	RTL_W16(IntrMask, 0x0000);

   509

   510

	RTL_W16(IntrStatus, 0xffff);

   511

}

   512

   513

static void rtl8169_asic_down(void __iomem *ioaddr)

   514

{

   515

	RTL_W8(ChipCmd, 0x00);

   516

	rtl8169_irq_mask_and_ack(ioaddr);

   517

	RTL_R16(CPlusCmd);

   518

}

   519

   520

static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)

   521

{

   522

	return RTL_R32(TBICSR) & TBIReset;

   523

}

   524

   525

static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)

   526

{

   527

	return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;

   528

}

   529

   530