1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 *

    10

 * vim: noexpandtab

    11

 */

    12

    13

#include <linux/module.h>

    14

#include <linux/moduleparam.h>

    15

#include <linux/pci.h>

    16

#include <linux/netdevice.h>

    17

#include <linux/etherdevice.h>

    18

#include <linux/delay.h>

    19

#include <linux/ethtool.h>

    20

#include <linux/mii.h>

    21

#include <linux/if_vlan.h>

    22

#include <linux/crc32.h>

    23

#include <linux/in.h>

    24

#include <linux/ip.h>

    25

#include <linux/tcp.h>

    26

#include <linux/init.h>

    27

#include <linux/dma-mapping.h>

    28

    29

#include <asm/system.h>

    30

#include <asm/io.h>

    31

#include <asm/irq.h>

    32

    33

#include "../globals.h"

    34

#include "ecdev.h"

    35

    36

#ifdef CONFIG_R8169_NAPI

    37

#define NAPI_SUFFIX	"-NAPI"

    38

#else

    39

#define NAPI_SUFFIX	""

    40

#endif

    41

    42

#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX

    43

#define MODULENAME "ec_r8169"

    44

#define PFX MODULENAME ": "

    45

    46

#ifdef RTL8169_DEBUG

    47

#define assert(expr) \

    48

	if (!(expr)) {					\

    49

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    50

		#expr,__FILE__,__FUNCTION__,__LINE__);		\

    51

	}

    52

#define dprintk(fmt, args...) \

    53

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    54

#else

    55

#define assert(expr) do {} while (0)

    56

#define dprintk(fmt, args...)	do {} while (0)

    57

#endif /* RTL8169_DEBUG */

    58

    59

#define R8169_MSG_DEFAULT \

    60

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    61

    62

#define TX_BUFFS_AVAIL(tp) \

    63

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    64

    65

#ifdef CONFIG_R8169_NAPI

    66

#define rtl8169_rx_skb			netif_receive_skb

    67

#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_receive_skb

    68

#define rtl8169_rx_quota(count, quota)	min(count, quota)

    69

#else

    70

#define rtl8169_rx_skb			netif_rx

    71

#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_rx

    72

#define rtl8169_rx_quota(count, quota)	count

    73

#endif

    74

    75

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

    76

static const int max_interrupt_work = 20;

    77

    78

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    79

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    80

static const int multicast_filter_limit = 32;

    81

    82

/* MAC address length */

    83

#define MAC_ADDR_LEN	6

    84

    85

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

    86

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    87

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    88

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

    89

#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */

    90

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    91

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    92

    93

#define R8169_REGS_SIZE		256

    94

#define R8169_NAPI_WEIGHT	64

    95

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    96

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    97

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    98

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    99

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

   100

   101

#define RTL8169_TX_TIMEOUT	(6*HZ)

   102

#define RTL8169_PHY_TIMEOUT	(10*HZ)

   103

   104

/* write/read MMIO register */

   105

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

   106

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

   107

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

   108

#define RTL_R8(reg)		readb (ioaddr + (reg))

   109

#define RTL_R16(reg)		readw (ioaddr + (reg))

   110

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

   111

   112

enum mac_version {

   113

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

   114

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

   115

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

   116

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

   117

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

   118

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

   119

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   120

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be

   121

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb

   122

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?

   123

	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?

   124

	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec

   125

	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf

   126

	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP

   127

	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C

   128

	RTL_GIGA_MAC_VER_20 = 0x14  // 8168C

   129

};

   130

   131

#define _R(NAME,MAC,MASK) \

   132

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   133

   134

static const struct {

   135

	const char *name;

   136

	u8 mac_version;

   137

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   138

} rtl_chip_info[] = {

   139

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   140

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   141

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   142

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   143

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   144

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   145

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   146

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   147

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   148

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   149

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139

   150

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E

   151

	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E

   152

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E

   153

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E

   154

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E

   155

};

   156

#undef _R

   157

   158

enum cfg_version {

   159

	RTL_CFG_0 = 0x00,

   160

	RTL_CFG_1,

   161

	RTL_CFG_2

   162

};

   163

   164

static void rtl_hw_start_8169(struct net_device *);

   165

static void rtl_hw_start_8168(struct net_device *);

   166

static void rtl_hw_start_8101(struct net_device *);

   167

   168

static struct pci_device_id rtl8169_pci_tbl[] = {

   169

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   170

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   171

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   172

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   173

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   174

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   175

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   176

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   177

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   178

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   179

	{ 0x0001,				0x8168,

   180

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   181

	{0,},

   182

};

   183

   184

/* prevent driver from being loaded automatically */

   185

//MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   186

   187

static int rx_copybreak = 200;

   188

static int use_dac;

   189

static struct {

   190

	u32 msg_enable;

   191

} debug = { -1 };

   192

   193

enum rtl_registers {

   194

	MAC0		= 0,	/* Ethernet hardware address. */

   195

	MAC4		= 4,

   196

	MAR0		= 8,	/* Multicast filter. */

   197

	CounterAddrLow		= 0x10,

   198

	CounterAddrHigh		= 0x14,

   199

	TxDescStartAddrLow	= 0x20,

   200

	TxDescStartAddrHigh	= 0x24,

   201

	TxHDescStartAddrLow	= 0x28,

   202

	TxHDescStartAddrHigh	= 0x2c,

   203

	FLASH		= 0x30,

   204

	ERSR		= 0x36,

   205

	ChipCmd		= 0x37,

   206

	TxPoll		= 0x38,

   207

	IntrMask	= 0x3c,

   208

	IntrStatus	= 0x3e,

   209

	TxConfig	= 0x40,

   210

	RxConfig	= 0x44,

   211

	RxMissed	= 0x4c,

   212

	Cfg9346		= 0x50,

   213

	Config0		= 0x51,

   214

	Config1		= 0x52,

   215

	Config2		= 0x53,

   216

	Config3		= 0x54,

   217

	Config4		= 0x55,

   218

	Config5		= 0x56,

   219

	MultiIntr	= 0x5c,

   220

	PHYAR		= 0x60,

   221

	TBICSR		= 0x64,

   222

	TBI_ANAR	= 0x68,

   223

	TBI_LPAR	= 0x6a,

   224

	PHYstatus	= 0x6c,

   225

	RxMaxSize	= 0xda,

   226

	CPlusCmd	= 0xe0,

   227

	IntrMitigate	= 0xe2,

   228

	RxDescAddrLow	= 0xe4,

   229

	RxDescAddrHigh	= 0xe8,

   230

	EarlyTxThres	= 0xec,

   231

	FuncEvent	= 0xf0,

   232

	FuncEventMask	= 0xf4,

   233

	FuncPresetState	= 0xf8,

   234

	FuncForceEvent	= 0xfc,

   235

};

   236

   237

enum rtl_register_content {

   238

	/* InterruptStatusBits */

   239

	SYSErr		= 0x8000,

   240

	PCSTimeout	= 0x4000,

   241

	SWInt		= 0x0100,

   242

	TxDescUnavail	= 0x0080,

   243

	RxFIFOOver	= 0x0040,

   244

	LinkChg		= 0x0020,

   245

	RxOverflow	= 0x0010,

   246

	TxErr		= 0x0008,

   247

	TxOK		= 0x0004,

   248

	RxErr		= 0x0002,

   249

	RxOK		= 0x0001,

   250

   251

	/* RxStatusDesc */

   252

	RxFOVF	= (1 << 23),

   253

	RxRWT	= (1 << 22),

   254

	RxRES	= (1 << 21),

   255

	RxRUNT	= (1 << 20),

   256

	RxCRC	= (1 << 19),

   257

   258

	/* ChipCmdBits */

   259

	CmdReset	= 0x10,

   260

	CmdRxEnb	= 0x08,

   261

	CmdTxEnb	= 0x04,

   262

	RxBufEmpty	= 0x01,

   263

   264

	/* TXPoll register p.5 */

   265

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   266

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   267

	FSWInt		= 0x01,		/* Forced software interrupt */

   268

   269

	/* Cfg9346Bits */

   270

	Cfg9346_Lock	= 0x00,

   271

	Cfg9346_Unlock	= 0xc0,

   272

   273

	/* rx_mode_bits */

   274

	AcceptErr	= 0x20,

   275

	AcceptRunt	= 0x10,

   276

	AcceptBroadcast	= 0x08,

   277

	AcceptMulticast	= 0x04,

   278

	AcceptMyPhys	= 0x02,

   279

	AcceptAllPhys	= 0x01,

   280

   281

	/* RxConfigBits */

   282

	RxCfgFIFOShift	= 13,

   283

	RxCfgDMAShift	=  8,

   284

   285

	/* TxConfigBits */

   286

	TxInterFrameGapShift = 24,

   287

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   288

   289

	/* Config1 register p.24 */

   290

	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */

   291

	PMEnable	= (1 << 0),	/* Power Management Enable */

   292

   293

	/* Config2 register p. 25 */

   294

	PCI_Clock_66MHz = 0x01,

   295

	PCI_Clock_33MHz = 0x00,

   296

   297

	/* Config3 register p.25 */

   298

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   299

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   300

   301

	/* Config5 register p.27 */

   302

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   303

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   304

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   305

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   306

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   307

   308

	/* TBICSR p.28 */

   309

	TBIReset	= 0x80000000,

   310

	TBILoopback	= 0x40000000,

   311

	TBINwEnable	= 0x20000000,

   312

	TBINwRestart	= 0x10000000,

   313

	TBILinkOk	= 0x02000000,

   314

	TBINwComplete	= 0x01000000,

   315

   316

	/* CPlusCmd p.31 */

   317

	PktCntrDisable	= (1 << 7),	// 8168

   318

	RxVlan		= (1 << 6),

   319

	RxChkSum	= (1 << 5),

   320

	PCIDAC		= (1 << 4),

   321

	PCIMulRW	= (1 << 3),

   322

	INTT_0		= 0x0000,	// 8168

   323

	INTT_1		= 0x0001,	// 8168

   324

	INTT_2		= 0x0002,	// 8168

   325

	INTT_3		= 0x0003,	// 8168

   326

   327

	/* rtl8169_PHYstatus */

   328

	TBI_Enable	= 0x80,

   329

	TxFlowCtrl	= 0x40,

   330

	RxFlowCtrl	= 0x20,

   331

	_1000bpsF	= 0x10,

   332

	_100bps		= 0x08,

   333

	_10bps		= 0x04,

   334

	LinkStatus	= 0x02,

   335

	FullDup		= 0x01,

   336

   337

	/* _TBICSRBit */

   338

	TBILinkOK	= 0x02000000,

   339

   340

	/* DumpCounterCommand */

   341

	CounterDump	= 0x8,

   342

};

   343

   344

enum desc_status_bit {

   345

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   346

	RingEnd		= (1 << 30), /* End of descriptor ring */

   347

	FirstFrag	= (1 << 29), /* First segment of a packet */

   348

	LastFrag	= (1 << 28), /* Final segment of a packet */

   349

   350

	/* Tx private */

   351

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   352

	MSSShift	= 16,        /* MSS value position */

   353

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   354

	IPCS		= (1 << 18), /* Calculate IP checksum */

   355

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   356

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   357

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   358

   359

	/* Rx private */

   360

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   361

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   362

   363

#define RxProtoUDP	(PID1)

   364

#define RxProtoTCP	(PID0)

   365

#define RxProtoIP	(PID1 | PID0)

   366

#define RxProtoMask	RxProtoIP

   367

   368

	IPFail		= (1 << 16), /* IP checksum failed */

   369

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   370

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   371

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   372

};

   373

   374

#define RsvdMask	0x3fffc000

   375

   376

struct TxDesc {

   377

	__le32 opts1;

   378

	__le32 opts2;

   379

	__le64 addr;

   380

};

   381

   382

struct RxDesc {

   383

	__le32 opts1;

   384

	__le32 opts2;

   385

	__le64 addr;

   386

};

   387

   388

struct ring_info {

   389

	struct sk_buff	*skb;

   390

	u32		len;

   391

	u8		__pad[sizeof(void *) - sizeof(u32)];

   392

};

   393

   394

enum features {

   395

	RTL_FEATURE_WOL	= (1 << 0),

   396

	RTL_FEATURE_MSI	= (1 << 1),

   397

};

   398

   399

struct rtl8169_private {

   400

	void __iomem *mmio_addr;	/* memory map physical address */

   401

	struct pci_dev *pci_dev;	/* Index of PCI device */

   402

	struct net_device *dev;

   403

#ifdef CONFIG_R8169_NAPI

   404

	struct napi_struct napi;

   405

#endif

   406

	spinlock_t lock;		/* spin lock flag */

   407

	u32 msg_enable;

   408

	int chipset;

   409

	int mac_version;

   410

	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   411

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   412

	u32 dirty_rx;

   413

	u32 dirty_tx;

   414

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   415

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   416

	dma_addr_t TxPhyAddr;

   417

	dma_addr_t RxPhyAddr;

   418

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   419

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

   420

	unsigned align;

   421

	unsigned rx_buf_sz;

   422

	struct timer_list timer;

   423

	u16 cp_cmd;

   424

	u16 intr_event;

   425

	u16 napi_event;

   426

	u16 intr_mask;

   427

	int phy_auto_nego_reg;

   428

	int phy_1000_ctrl_reg;

   429

#ifdef CONFIG_R8169_VLAN

   430

	struct vlan_group *vlgrp;

   431

#endif

   432

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   433

	void (*get_settings)(struct net_device *, struct ethtool_cmd *);

   434

	void (*phy_reset_enable)(void __iomem *);

   435

	void (*hw_start)(struct net_device *);

   436

	unsigned int (*phy_reset_pending)(void __iomem *);

   437

	unsigned int (*link_ok)(void __iomem *);

   438

	struct delayed_work task;

   439

	unsigned features;

   440

   441

	ec_device_t *ecdev;

   442

	unsigned long ec_watchdog_jiffies;

   443

};

   444

   445

MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   446

MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver");

   447

module_param(rx_copybreak, int, 0);

   448

MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

   449

module_param(use_dac, int, 0);

   450

MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

   451

module_param_named(debug, debug.msg_enable, int, 0);

   452

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   453

MODULE_LICENSE("GPL");

   454

MODULE_VERSION(EC_MASTER_VERSION);

   455

   456

static int rtl8169_open(struct net_device *dev);

   457

static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);

   458

static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);

   459

static int rtl8169_init_ring(struct net_device *dev);

   460

static void rtl_hw_start(struct net_device *dev);

   461

static int rtl8169_close(struct net_device *dev);

   462

static void rtl_set_rx_mode(struct net_device *dev);

   463

static void rtl8169_tx_timeout(struct net_device *dev);

   464

static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);

   465

static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,

   466

				void __iomem *, u32 budget);

   467

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);

   468

static void rtl8169_down(struct net_device *dev);

   469

static void rtl8169_rx_clear(struct rtl8169_private *tp);

   470

   471

#ifdef CONFIG_R8169_NAPI

   472

static int rtl8169_poll(struct napi_struct *napi, int budget);

   473

#endif

   474

   475

static const unsigned int rtl8169_rx_config =

   476

	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);

   477

   478

static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)

   479

{

   480

	int i;

   481

   482

	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));

   483

   484

	for (i = 20; i > 0; i--) {

   485

		/*

   486

		 * Check if the RTL8169 has completed writing to the specified

   487

		 * MII register.

   488

		 */

   489

		if (!(RTL_R32(PHYAR) & 0x80000000))

   490

			break;

   491

		udelay(25);

   492

	}

   493

}

   494

   495

static int mdio_read(void __iomem *ioaddr, int reg_addr)

   496

{

   497

	int i, value = -1;

   498

   499

	RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);

   500

   501

	for (i = 20; i > 0; i--) {

   502

		/*

   503

		 * Check if the RTL8169 has completed retrieving data from

   504

		 * the specified MII register.

   505

		 */

   506

		if (RTL_R32(PHYAR) & 0x80000000) {

   507

			value = RTL_R32(PHYAR) & 0xffff;

   508

			break;

   509

		}

   510

		udelay(25);

   511

	}

   512

	return value;

   513

}

   514

   515

static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)

   516

{

   517

	RTL_W16(IntrMask, 0x0000);

   518

   519

	RTL_W16(IntrStatus, 0xffff);

   520

}

   521

   522

static void rtl8169_asic_down(void __iomem *ioaddr)

   523

{

   524

	RTL_W8(ChipCmd, 0x00);

   525

	rtl8169_irq_mask_and_ack(ioaddr);

   526

	RTL_R16(CPlusCmd);

   527

}

   528

   529

static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)

   530