1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2011 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

#include <linux/delay.h>

    30

    31

#include "e1000.h"

    32

    33

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    34

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    35

static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);

    36

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    37

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);

    38

static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,

    39

					  u16 *data, bool read, bool page_set);

    40

static u32 e1000_get_phy_addr_for_hv_page(u32 page);

    41

static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,

    42

                                          u16 *data, bool read);

    43

    44

/* Cable length tables */

    45

static const u16 e1000_m88_cable_length_table[] = {

    46

	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };

    47

#define M88E1000_CABLE_LENGTH_TABLE_SIZE \

    48

		ARRAY_SIZE(e1000_m88_cable_length_table)

    49

    50

static const u16 e1000_igp_2_cable_length_table[] = {

    51

	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,

    52

	6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,

    53

	26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,

    54

	44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,

    55

	66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,

    56

	87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,

    57

	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,

    58

	124};

    59

#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \

    60

		ARRAY_SIZE(e1000_igp_2_cable_length_table)

    61

    62

#define BM_PHY_REG_PAGE(offset) \

    63

	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))

    64

#define BM_PHY_REG_NUM(offset) \

    65

	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\

    66

	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\

    67

		~MAX_PHY_REG_ADDRESS)))

    68

    69

#define HV_INTC_FC_PAGE_START             768

    70

#define I82578_ADDR_REG                   29

    71

#define I82577_ADDR_REG                   16

    72

#define I82577_CFG_REG                    22

    73

#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)

    74

#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */

    75

#define I82577_CTRL_REG                   23

    76

    77

/* 82577 specific PHY registers */

    78

#define I82577_PHY_CTRL_2            18

    79

#define I82577_PHY_STATUS_2          26

    80

#define I82577_PHY_DIAG_STATUS       31

    81

    82

/* I82577 PHY Status 2 */

    83

#define I82577_PHY_STATUS2_REV_POLARITY   0x0400

    84

#define I82577_PHY_STATUS2_MDIX           0x0800

    85

#define I82577_PHY_STATUS2_SPEED_MASK     0x0300

    86

#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200

    87

    88

/* I82577 PHY Control 2 */

    89

#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400

    90

#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200

    91

    92

/* I82577 PHY Diagnostics Status */

    93

#define I82577_DSTATUS_CABLE_LENGTH       0x03FC

    94

#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2

    95

    96

/* BM PHY Copper Specific Control 1 */

    97

#define BM_CS_CTRL1                       16

    98

    99

#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)

   100

#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400

   101

#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004

   102

   103

/**

   104

 *  e1000e_check_reset_block_generic - Check if PHY reset is blocked

   105

 *  @hw: pointer to the HW structure

   106

 *

   107

 *  Read the PHY management control register and check whether a PHY reset

   108

 *  is blocked.  If a reset is not blocked return 0, otherwise

   109

 *  return E1000_BLK_PHY_RESET (12).

   110

 **/

   111

s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)

   112

{

   113

	u32 manc;

   114

   115

	manc = er32(MANC);

   116

   117

	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?

   118

	       E1000_BLK_PHY_RESET : 0;

   119

}

   120

   121

/**

   122

 *  e1000e_get_phy_id - Retrieve the PHY ID and revision

   123

 *  @hw: pointer to the HW structure

   124

 *

   125

 *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   126

 *  revision in the hardware structure.

   127

 **/

   128

s32 e1000e_get_phy_id(struct e1000_hw *hw)

   129

{

   130

	struct e1000_phy_info *phy = &hw->phy;

   131

	s32 ret_val = 0;

   132

	u16 phy_id;

   133

	u16 retry_count = 0;

   134

   135

	if (!(phy->ops.read_reg))

   136

		goto out;

   137

   138

	while (retry_count < 2) {

   139

		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   140

		if (ret_val)

   141

			goto out;

   142

   143

		phy->id = (u32)(phy_id << 16);

   144

		udelay(20);

   145

		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   146

		if (ret_val)

   147

			goto out;

   148

   149

		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

   150

		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   151

   152

		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)

   153

			goto out;

   154

   155

		retry_count++;

   156

	}

   157

out:

   158

	return ret_val;

   159

}

   160

   161

/**

   162

 *  e1000e_phy_reset_dsp - Reset PHY DSP

   163

 *  @hw: pointer to the HW structure

   164

 *

   165

 *  Reset the digital signal processor.

   166

 **/

   167

s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)

   168

{

   169

	s32 ret_val;

   170

   171

	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

   172

	if (ret_val)

   173

		return ret_val;

   174

   175

	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);

   176

}

   177

   178

/**

   179

 *  e1000e_read_phy_reg_mdic - Read MDI control register

   180

 *  @hw: pointer to the HW structure

   181

 *  @offset: register offset to be read

   182

 *  @data: pointer to the read data

   183

 *

   184

 *  Reads the MDI control register in the PHY at offset and stores the

   185

 *  information read to data.

   186

 **/

   187

s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)

   188

{

   189

	struct e1000_phy_info *phy = &hw->phy;

   190

	u32 i, mdic = 0;

   191

   192

	if (offset > MAX_PHY_REG_ADDRESS) {

   193

		e_dbg("PHY Address %d is out of range\n", offset);

   194

		return -E1000_ERR_PARAM;

   195

	}

   196

   197

	/*

   198

	 * Set up Op-code, Phy Address, and register offset in the MDI

   199

	 * Control register.  The MAC will take care of interfacing with the

   200

	 * PHY to retrieve the desired data.

   201

	 */

   202

	mdic = ((offset << E1000_MDIC_REG_SHIFT) |

   203

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   204

		(E1000_MDIC_OP_READ));

   205

   206

	ew32(MDIC, mdic);

   207

   208

	/*

   209

	 * Poll the ready bit to see if the MDI read completed

   210

	 * Increasing the time out as testing showed failures with

   211

	 * the lower time out

   212

	 */

   213

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   214

		udelay(50);

   215

		mdic = er32(MDIC);

   216

		if (mdic & E1000_MDIC_READY)

   217

			break;

   218

	}

   219

	if (!(mdic & E1000_MDIC_READY)) {

   220

		e_dbg("MDI Read did not complete\n");

   221

		return -E1000_ERR_PHY;

   222

	}

   223

	if (mdic & E1000_MDIC_ERROR) {

   224

		e_dbg("MDI Error\n");

   225

		return -E1000_ERR_PHY;

   226

	}

   227

	*data = (u16) mdic;

   228

   229

	/*

   230

	 * Allow some time after each MDIC transaction to avoid

   231

	 * reading duplicate data in the next MDIC transaction.

   232

	 */

   233

	if (hw->mac.type == e1000_pch2lan)

   234

		udelay(100);

   235

   236

	return 0;

   237

}

   238

   239

/**

   240

 *  e1000e_write_phy_reg_mdic - Write MDI control register

   241

 *  @hw: pointer to the HW structure

   242

 *  @offset: register offset to write to

   243

 *  @data: data to write to register at offset

   244

 *

   245

 *  Writes data to MDI control register in the PHY at offset.

   246

 **/

   247

s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)

   248

{

   249

	struct e1000_phy_info *phy = &hw->phy;

   250

	u32 i, mdic = 0;

   251

   252

	if (offset > MAX_PHY_REG_ADDRESS) {

   253

		e_dbg("PHY Address %d is out of range\n", offset);

   254

		return -E1000_ERR_PARAM;

   255

	}

   256

   257

	/*

   258

	 * Set up Op-code, Phy Address, and register offset in the MDI

   259

	 * Control register.  The MAC will take care of interfacing with the

   260

	 * PHY to retrieve the desired data.

   261

	 */

   262

	mdic = (((u32)data) |

   263

		(offset << E1000_MDIC_REG_SHIFT) |

   264

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   265

		(E1000_MDIC_OP_WRITE));

   266

   267

	ew32(MDIC, mdic);

   268

   269

	/*

   270

	 * Poll the ready bit to see if the MDI read completed

   271

	 * Increasing the time out as testing showed failures with

   272

	 * the lower time out

   273

	 */

   274

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   275

		udelay(50);

   276

		mdic = er32(MDIC);

   277

		if (mdic & E1000_MDIC_READY)

   278

			break;

   279

	}

   280

	if (!(mdic & E1000_MDIC_READY)) {

   281

		e_dbg("MDI Write did not complete\n");

   282

		return -E1000_ERR_PHY;

   283

	}

   284

	if (mdic & E1000_MDIC_ERROR) {

   285

		e_dbg("MDI Error\n");

   286

		return -E1000_ERR_PHY;

   287

	}

   288

   289

	/*

   290

	 * Allow some time after each MDIC transaction to avoid

   291

	 * reading duplicate data in the next MDIC transaction.

   292

	 */

   293

	if (hw->mac.type == e1000_pch2lan)

   294

		udelay(100);

   295

   296

	return 0;

   297

}

   298

   299

/**

   300

 *  e1000e_read_phy_reg_m88 - Read m88 PHY register

   301

 *  @hw: pointer to the HW structure

   302

 *  @offset: register offset to be read

   303

 *  @data: pointer to the read data

   304

 *

   305

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   306

 *  and storing the retrieved information in data.  Release any acquired

   307

 *  semaphores before exiting.

   308

 **/

   309

s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)

   310

{

   311

	s32 ret_val;

   312

   313

	ret_val = hw->phy.ops.acquire(hw);

   314

	if (ret_val)

   315

		return ret_val;

   316

   317

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   318

					   data);

   319

   320

	hw->phy.ops.release(hw);

   321

   322

	return ret_val;

   323

}

   324

   325

/**

   326

 *  e1000e_write_phy_reg_m88 - Write m88 PHY register

   327

 *  @hw: pointer to the HW structure

   328

 *  @offset: register offset to write to

   329

 *  @data: data to write at register offset

   330

 *

   331

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   332

 *  at the offset.  Release any acquired semaphores before exiting.

   333

 **/

   334

s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)

   335

{

   336

	s32 ret_val;

   337

   338

	ret_val = hw->phy.ops.acquire(hw);

   339

	if (ret_val)

   340

		return ret_val;

   341

   342

	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   343

					    data);

   344

   345

	hw->phy.ops.release(hw);

   346

   347

	return ret_val;

   348

}

   349

   350

/**

   351

 *  e1000_set_page_igp - Set page as on IGP-like PHY(s)

   352

 *  @hw: pointer to the HW structure

   353

 *  @page: page to set (shifted left when necessary)

   354

 *

   355

 *  Sets PHY page required for PHY register access.  Assumes semaphore is

   356

 *  already acquired.  Note, this function sets phy.addr to 1 so the caller

   357

 *  must set it appropriately (if necessary) after this function returns.

   358

 **/

   359

s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)

   360

{

   361

	e_dbg("Setting page 0x%x\n", page);

   362

   363

	hw->phy.addr = 1;

   364

   365

	return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);

   366

}

   367

   368

/**

   369

 *  __e1000e_read_phy_reg_igp - Read igp PHY register

   370

 *  @hw: pointer to the HW structure

   371

 *  @offset: register offset to be read

   372

 *  @data: pointer to the read data

   373

 *  @locked: semaphore has already been acquired or not

   374

 *

   375

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   376

 *  and stores the retrieved information in data.  Release any acquired

   377

 *  semaphores before exiting.

   378

 **/

   379

static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,

   380

                                    bool locked)

   381

{

   382

	s32 ret_val = 0;

   383

   384

	if (!locked) {

   385

		if (!(hw->phy.ops.acquire))

   386

			goto out;

   387

   388

		ret_val = hw->phy.ops.acquire(hw);

   389

		if (ret_val)

   390

			goto out;

   391

	}

   392

   393

	if (offset > MAX_PHY_MULTI_PAGE_REG) {

   394

		ret_val = e1000e_write_phy_reg_mdic(hw,

   395

						    IGP01E1000_PHY_PAGE_SELECT,

   396

						    (u16)offset);

   397

		if (ret_val)

   398

			goto release;

   399

	}

   400

   401

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   402

	                                  data);

   403

   404

release:

   405

	if (!locked)

   406

		hw->phy.ops.release(hw);

   407

out:

   408

	return ret_val;

   409

}

   410

   411

/**

   412

 *  e1000e_read_phy_reg_igp - Read igp PHY register

   413

 *  @hw: pointer to the HW structure

   414

 *  @offset: register offset to be read

   415

 *  @data: pointer to the read data

   416

 *

   417

 *  Acquires semaphore then reads the PHY register at offset and stores the

   418

 *  retrieved information in data.

   419

 *  Release the acquired semaphore before exiting.

   420

 **/

   421

s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)

   422

{

   423

	return __e1000e_read_phy_reg_igp(hw, offset, data, false);

   424

}

   425

   426

/**

   427

 *  e1000e_read_phy_reg_igp_locked - Read igp PHY register

   428

 *  @hw: pointer to the HW structure

   429

 *  @offset: register offset to be read

   430

 *  @data: pointer to the read data

   431

 *

   432

 *  Reads the PHY register at offset and stores the retrieved information

   433

 *  in data.  Assumes semaphore already acquired.

   434

 **/

   435

s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)

   436

{

   437

	return __e1000e_read_phy_reg_igp(hw, offset, data, true);

   438

}

   439

   440

/**

   441

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   442

 *  @hw: pointer to the HW structure

   443

 *  @offset: register offset to write to

   444

 *  @data: data to write at register offset

   445

 *  @locked: semaphore has already been acquired or not

   446

 *

   447

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   448

 *  at the offset.  Release any acquired semaphores before exiting.

   449

 **/

   450

static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,

   451

                                     bool locked)

   452

{

   453

	s32 ret_val = 0;

   454

   455

	if (!locked) {

   456

		if (!(hw->phy.ops.acquire))

   457

			goto out;

   458

   459

		ret_val = hw->phy.ops.acquire(hw);

   460

		if (ret_val)

   461

			goto out;

   462

	}

   463

   464

	if (offset > MAX_PHY_MULTI_PAGE_REG) {

   465

		ret_val = e1000e_write_phy_reg_mdic(hw,

   466

						    IGP01E1000_PHY_PAGE_SELECT,

   467

						    (u16)offset);

   468

		if (ret_val)

   469

			goto release;

   470

	}

   471

   472

	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   473

					    data);

   474

   475

release:

   476

	if (!locked)

   477

		hw->phy.ops.release(hw);

   478

   479

out:

   480

	return ret_val;

   481

}

   482

   483

/**

   484

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   485

 *  @hw: pointer to the HW structure

   486

 *  @offset: register offset to write to

   487

 *  @data: data to write at register offset

   488

 *

   489

 *  Acquires semaphore then writes the data to PHY register

   490

 *  at the offset.  Release any acquired semaphores before exiting.

   491

 **/

   492

s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)

   493

{

   494

	return __e1000e_write_phy_reg_igp(hw, offset, data, false);

   495

}

   496

   497

/**

   498

 *  e1000e_write_phy_reg_igp_locked - Write igp PHY register

   499

 *  @hw: pointer to the HW structure

   500

 *  @offset: register offset to write to

   501

 *  @data: data to write at register offset

   502

 *

   503

 *  Writes the data to PHY register at the offset.

   504

 *  Assumes semaphore already acquired.

   505

 **/

   506

s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)

   507

{

   508

	return __e1000e_write_phy_reg_igp(hw, offset, data, true);

   509

}

   510

   511

/**

   512

 *  __e1000_read_kmrn_reg - Read kumeran register

   513

 *  @hw: pointer to the HW structure

   514

 *  @offset: register offset to be read

   515

 *  @data: pointer to the read data

   516

 *  @locked: semaphore has already been acquired or not

   517

 *

   518

 *  Acquires semaphore, if necessary.  Then reads the PHY register at offset

   519

 *  using the kumeran interface.  The information retrieved is stored in data.

   520

 *  Release any acquired semaphores before exiting.

   521

 **/

   522

static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,

   523

                                 bool locked)

   524

{

   525

	u32 kmrnctrlsta;

   526

	s32 ret_val = 0;

   527

   528

	if (!locked) {

   529

		if (!(hw->phy.ops.acquire))

   530