1

/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2007-2008  Florian Pose, Ingenieurgemeinschaft IgH

     6

 *

     7

 *  This file is part of the IgH EtherCAT Master.

     8

 *

     9

 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10

 *  modify it under the terms of the GNU General Public License version 2, as

    11

 *  published by the Free Software Foundation.

    12

 *

    13

 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16

 *  Public License for more details.

    17

 *

    18

 *  You should have received a copy of the GNU General Public License along

    19

 *  with the IgH EtherCAT Master; if not, write to the Free Software

    20

 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21

 *

    22

 *  Using the EtherCAT technology and brand is permitted in compliance with

    23

 *  the industrial property and similar rights of Beckhoff Automation GmbH.

    24

 *

    25

 *  vim: noexpandtab

    26

 *

    27

 *****************************************************************************/

    28

    29

/**

    30

   \file

    31

   EtherCAT driver for e100-compatible NICs.

    32

*/

    33

    34

/* Former documentation: */

    35

    36

/*******************************************************************************

    37

  Intel PRO/100 Linux driver

    38

  Copyright(c) 1999 - 2006 Intel Corporation.

    39

    40

  This program is free software; you can redistribute it and/or modify it

    41

  under the terms and conditions of the GNU General Public License,

    42

  version 2, as published by the Free Software Foundation.

    43

    44

  This program is distributed in the hope it will be useful, but WITHOUT

    45

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    46

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    47

  more details.

    48

    49

  You should have received a copy of the GNU General Public License along with

    50

  this program; if not, write to the Free Software Foundation, Inc.,

    51

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    52

    53

  The full GNU General Public License is included in this distribution in

    54

  the file called "COPYING".

    55

    56

  Contact Information:

    57

  Linux NICS <linux.nics@intel.com>

    58

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    59

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    60

    61

*******************************************************************************/

    62

    63

/*

    64

 *	e100.c: Intel(R) PRO/100 ethernet driver

    65

 *

    66

 *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

    67

 *	original e100 driver, but better described as a munging of

    68

 *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

    69

 *

    70

 *	References:

    71

 *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

    72

 *		Open Source Software Developers Manual,

    73

 *		http://sourceforge.net/projects/e1000

    74

 *

    75

 *

    76

 *	                      Theory of Operation

    77

 *

    78

 *	I.   General

    79

 *

    80

 *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

    81

 *	controller family, which includes the 82557, 82558, 82559, 82550,

    82

 *	82551, and 82562 devices.  82558 and greater controllers

    83

 *	integrate the Intel 82555 PHY.  The controllers are used in

    84

 *	server and client network interface cards, as well as in

    85

 *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

    86

 *	configurations.  8255x supports a 32-bit linear addressing

    87

 *	mode and operates at 33Mhz PCI clock rate.

    88

 *

    89

 *	II.  Driver Operation

    90

 *

    91

 *	Memory-mapped mode is used exclusively to access the device's

    92

 *	shared-memory structure, the Control/Status Registers (CSR). All

    93

 *	setup, configuration, and control of the device, including queuing

    94

 *	of Tx, Rx, and configuration commands is through the CSR.

    95

 *	cmd_lock serializes accesses to the CSR command register.  cb_lock

    96

 *	protects the shared Command Block List (CBL).

    97

 *

    98

 *	8255x is highly MII-compliant and all access to the PHY go

    99

 *	through the Management Data Interface (MDI).  Consequently, the

   100

 *	driver leverages the mii.c library shared with other MII-compliant

   101

 *	devices.

   102

 *

   103

 *	Big- and Little-Endian byte order as well as 32- and 64-bit

   104

 *	archs are supported.  Weak-ordered memory and non-cache-coherent

   105

 *	archs are supported.

   106

 *

   107

 *	III. Transmit

   108

 *

   109

 *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

   110

 *	together in a fixed-size ring (CBL) thus forming the flexible mode

   111

 *	memory structure.  A TCB marked with the suspend-bit indicates

   112

 *	the end of the ring.  The last TCB processed suspends the

   113

 *	controller, and the controller can be restarted by issue a CU

   114

 *	resume command to continue from the suspend point, or a CU start

   115

 *	command to start at a given position in the ring.

   116

 *

   117

 *	Non-Tx commands (config, multicast setup, etc) are linked

   118

 *	into the CBL ring along with Tx commands.  The common structure

   119

 *	used for both Tx and non-Tx commands is the Command Block (CB).

   120

 *

   121

 *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

   122

 *	is the next CB to check for completion; cb_to_send is the first

   123

 *	CB to start on in case of a previous failure to resume.  CB clean

   124

 *	up happens in interrupt context in response to a CU interrupt.

   125

 *	cbs_avail keeps track of number of free CB resources available.

   126

 *

   127

 * 	Hardware padding of short packets to minimum packet size is

   128

 * 	enabled.  82557 pads with 7Eh, while the later controllers pad

   129

 * 	with 00h.

   130

 *

   131

 *	IV.  Recieve

   132

 *

   133

 *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

   134

 *	Descriptors (RFD) + data buffer, thus forming the simplified mode

   135

 *	memory structure.  Rx skbs are allocated to contain both the RFD

   136

 *	and the data buffer, but the RFD is pulled off before the skb is

   137

 *	indicated.  The data buffer is aligned such that encapsulated

   138

 *	protocol headers are u32-aligned.  Since the RFD is part of the

   139

 *	mapped shared memory, and completion status is contained within

   140

 *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

   141

 *	view from software and hardware.

   142

 *

   143

 *	Under typical operation, the  receive unit (RU) is start once,

   144

 *	and the controller happily fills RFDs as frames arrive.  If

   145

 *	replacement RFDs cannot be allocated, or the RU goes non-active,

   146

 *	the RU must be restarted.  Frame arrival generates an interrupt,

   147

 *	and Rx indication and re-allocation happen in the same context,

   148

 *	therefore no locking is required.  A software-generated interrupt

   149

 *	is generated from the watchdog to recover from a failed allocation

   150

 *	senario where all Rx resources have been indicated and none re-

   151

 *	placed.

   152

 *

   153

 *	V.   Miscellaneous

   154

 *

   155

 * 	VLAN offloading of tagging, stripping and filtering is not

   156

 * 	supported, but driver will accommodate the extra 4-byte VLAN tag

   157

 * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

   158

 * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

   159

 * 	not supported (hardware limitation).

   160

 *

   161

 * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

   162

 *

   163

 * 	Thanks to JC (jchapman@katalix.com) for helping with

   164

 * 	testing/troubleshooting the development driver.

   165

 *

   166

 * 	TODO:

   167

 * 	o several entry points race with dev->close

   168

 * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

   169

 *

   170

 *	FIXES:

   171

 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

   172

 *	- Stratus87247: protect MDI control register manipulations

   173

 */

   174

   175

#include <linux/module.h>

   176

#include <linux/moduleparam.h>

   177

#include <linux/kernel.h>

   178

#include <linux/types.h>

   179

#include <linux/slab.h>

   180

#include <linux/delay.h>

   181

#include <linux/init.h>

   182

#include <linux/pci.h>

   183

#include <linux/dma-mapping.h>

   184

#include <linux/netdevice.h>

   185

#include <linux/etherdevice.h>

   186

#include <linux/mii.h>

   187

#include <linux/if_vlan.h>

   188

#include <linux/skbuff.h>

   189

#include <linux/ethtool.h>

   190

#include <linux/string.h>

   191

#include <asm/unaligned.h>

   192

   193

// EtherCAT includes

   194

#include "../globals.h"

   195

#include "ecdev.h"

   196

   197

#define DRV_NAME		"ec_e100"

   198

#define DRV_EXT			"-NAPI"

   199

#define DRV_VERSION		"3.5.17-k2"DRV_EXT

   200

#define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"

   201

#define DRV_COPYRIGHT		"Copyright(c) 1999-2006 Intel Corporation"

   202

#define PFX			DRV_NAME ": "

   203

   204

#define E100_WATCHDOG_PERIOD	(2 * HZ)

   205

#define E100_NAPI_WEIGHT	16

   206

   207

MODULE_DESCRIPTION(DRV_DESCRIPTION);

   208

MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   209

MODULE_LICENSE("GPL");

   210

MODULE_VERSION(DRV_VERSION ", master " EC_MASTER_VERSION);

   211

   212

void e100_ec_poll(struct net_device *);

   213

   214

static int debug = 3;

   215

static int eeprom_bad_csum_allow = 0;

   216

module_param(debug, int, 0);

   217

module_param(eeprom_bad_csum_allow, int, 0);

   218

MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

   219

MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

   220

#define DPRINTK(nlevel, klevel, fmt, args...) \

   221

	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

   222

	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

   223

		__FUNCTION__ , ## args))

   224

   225

#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

   226

	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

   227

	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

   228

static struct pci_device_id e100_id_table[] = {

   229

	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

   230

	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

   231

	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

   232

	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

   233

	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

   234

	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

   235

	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

   236

	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

   237

	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

   238

	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

   239

	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

   240

	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

   241

	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

   242

	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

   243

	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

   244

	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

   245

	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

   246

	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

   247

	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

   248

	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

   249

	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

   250

	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

   251

	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

   252

	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

   253

	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

   254

	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

   255

	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

   256

	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

   257

	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

   258

	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

   259

	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

   260

	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

   261

	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

   262

	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

   263

	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

   264

	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

   265

	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

   266

	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

   267

	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

   268

	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

   269

	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

   270

	{ 0, }

   271

};

   272

// prevent from being loaded automatically

   273

//MODULE_DEVICE_TABLE(pci, e100_id_table);

   274

   275

enum mac {

   276

	mac_82557_D100_A  = 0,

   277

	mac_82557_D100_B  = 1,

   278

	mac_82557_D100_C  = 2,

   279

	mac_82558_D101_A4 = 4,

   280

	mac_82558_D101_B0 = 5,

   281

	mac_82559_D101M   = 8,

   282

	mac_82559_D101S   = 9,

   283

	mac_82550_D102    = 12,

   284

	mac_82550_D102_C  = 13,

   285

	mac_82551_E       = 14,

   286

	mac_82551_F       = 15,

   287

	mac_82551_10      = 16,

   288

	mac_unknown       = 0xFF,

   289

};

   290

   291

enum phy {

   292

	phy_100a     = 0x000003E0,

   293

	phy_100c     = 0x035002A8,

   294

	phy_82555_tx = 0x015002A8,

   295

	phy_nsc_tx   = 0x5C002000,

   296

	phy_82562_et = 0x033002A8,

   297

	phy_82562_em = 0x032002A8,

   298

	phy_82562_ek = 0x031002A8,

   299

	phy_82562_eh = 0x017002A8,

   300

	phy_unknown  = 0xFFFFFFFF,

   301

};

   302

   303

/* CSR (Control/Status Registers) */

   304

struct csr {

   305

	struct {

   306

		u8 status;

   307

		u8 stat_ack;

   308

		u8 cmd_lo;

   309

		u8 cmd_hi;

   310

		u32 gen_ptr;

   311

	} scb;

   312

	u32 port;

   313

	u16 flash_ctrl;

   314

	u8 eeprom_ctrl_lo;

   315

	u8 eeprom_ctrl_hi;

   316

	u32 mdi_ctrl;

   317

	u32 rx_dma_count;

   318

};

   319

   320

enum scb_status {

   321

	rus_ready        = 0x10,

   322

	rus_mask         = 0x3C,

   323

};

   324

   325

enum ru_state  {

   326

	RU_SUSPENDED = 0,

   327

	RU_RUNNING	 = 1,

   328

	RU_UNINITIALIZED = -1,

   329

};

   330

   331

enum scb_stat_ack {

   332

	stat_ack_not_ours    = 0x00,

   333

	stat_ack_sw_gen      = 0x04,

   334

	stat_ack_rnr         = 0x10,

   335

	stat_ack_cu_idle     = 0x20,

   336

	stat_ack_frame_rx    = 0x40,

   337

	stat_ack_cu_cmd_done = 0x80,

   338

	stat_ack_not_present = 0xFF,

   339

	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

   340

	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

   341

};

   342

   343

enum scb_cmd_hi {

   344

	irq_mask_none = 0x00,

   345

	irq_mask_all  = 0x01,

   346

	irq_sw_gen    = 0x02,

   347

};

   348

   349

enum scb_cmd_lo {

   350

	cuc_nop        = 0x00,

   351

	ruc_start      = 0x01,

   352

	ruc_load_base  = 0x06,

   353

	cuc_start      = 0x10,

   354

	cuc_resume     = 0x20,

   355

	cuc_dump_addr  = 0x40,

   356

	cuc_dump_stats = 0x50,

   357

	cuc_load_base  = 0x60,

   358

	cuc_dump_reset = 0x70,

   359

};

   360

   361

enum cuc_dump {

   362

	cuc_dump_complete       = 0x0000A005,

   363

	cuc_dump_reset_complete = 0x0000A007,

   364

};

   365

   366

enum port {

   367

	software_reset  = 0x0000,

   368

	selftest        = 0x0001,

   369

	selective_reset = 0x0002,

   370

};

   371

   372

enum eeprom_ctrl_lo {

   373

	eesk = 0x01,

   374

	eecs = 0x02,

   375

	eedi = 0x04,

   376

	eedo = 0x08,

   377

};

   378

   379

enum mdi_ctrl {

   380

	mdi_write = 0x04000000,

   381

	mdi_read  = 0x08000000,

   382

	mdi_ready = 0x10000000,

   383

};

   384

   385

enum eeprom_op {

   386

	op_write = 0x05,

   387

	op_read  = 0x06,

   388

	op_ewds  = 0x10,

   389

	op_ewen  = 0x13,

   390

};

   391

   392

enum eeprom_offsets {

   393

	eeprom_cnfg_mdix  = 0x03,

   394

	eeprom_id         = 0x0A,

   395

	eeprom_config_asf = 0x0D,

   396

	eeprom_smbus_addr = 0x90,

   397

};

   398

   399

enum eeprom_cnfg_mdix {

   400

	eeprom_mdix_enabled = 0x0080,

   401

};

   402

   403

enum eeprom_id {

   404

	eeprom_id_wol = 0x0020,

   405

};

   406

   407

enum eeprom_config_asf {

   408

	eeprom_asf = 0x8000,

   409

	eeprom_gcl = 0x4000,

   410

};

   411

   412

enum cb_status {

   413

	cb_complete = 0x8000,

   414

	cb_ok       = 0x2000,

   415

};

   416

   417

enum cb_command {

   418

	cb_nop    = 0x0000,

   419

	cb_iaaddr = 0x0001,

   420

	cb_config = 0x0002,

   421

	cb_multi  = 0x0003,

   422

	cb_tx     = 0x0004,

   423

	cb_ucode  = 0x0005,

   424

	cb_dump   = 0x0006,

   425

	cb_tx_sf  = 0x0008,

   426

	cb_cid    = 0x1f00,

   427

	cb_i      = 0x2000,

   428

	cb_s      = 0x4000,

   429

	cb_el     = 0x8000,

   430

};

   431

   432

struct rfd {

   433

	u16 status;

   434

	u16 command;

   435

	u32 link;

   436

	u32 rbd;

   437

	u16 actual_size;

   438

	u16 size;

   439

};

   440

   441

struct rx {

   442

	struct rx *next, *prev;

   443

	struct sk_buff *skb;

   444

	dma_addr_t dma_addr;

   445

};

   446

   447

#if defined(__BIG_ENDIAN_BITFIELD)

   448

#define X(a,b)	b,a

   449

#else

   450

#define X(a,b)	a,b

   451

#endif

   452

struct config {

   453

/*0*/	u8 X(byte_count:6, pad0:2);

   454

/*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

   455

/*2*/	u8 adaptive_ifs;

   456

/*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

   457

	   term_write_cache_line:1), pad3:4);

   458

/*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   459

/*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   460

/*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   461

	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   462

	   rx_discard_overruns:1), rx_save_bad_frames:1);

   463

/*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   464

	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   465

	   tx_dynamic_tbd:1);

   466

/*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   467

/*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   468

	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   469

/*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   470

	   loopback:2);

   471

/*11*/	u8 X(linear_priority:3, pad11:5);

   472

/*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   473

/*13*/	u8 ip_addr_lo;

   474

/*14*/	u8 ip_addr_hi;

   475

/*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   476

	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   477

	   pad15_2:1), crs_or_cdt:1);

   478

/*16*/	u8 fc_delay_lo;

   479

/*17*/	u8 fc_delay_hi;

   480

/*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   481

	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   482

/*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   483

	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   484

	   full_duplex_force:1), full_duplex_pin:1);

   485

/*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   486

/*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   487

/*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   488

	u8 pad_d102[9];

   489

};

   490

   491

#define E100_MAX_MULTICAST_ADDRS	64

   492

struct multi {

   493

	u16 count;

   494

	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   495

};

   496

   497

/* Important: keep total struct u32-aligned */

   498

#define UCODE_SIZE			134

   499

struct cb {

   500

	u16 status;

   501

	u16 command;

   502

	u32 link;

   503

	union {

   504

		u8 iaaddr[ETH_ALEN];

   505

		u32 ucode[UCODE_SIZE];

   506

		struct config config;

   507

		struct multi multi;

   508

		struct {

   509

			u32 tbd_array;

   510

			u16 tcb_byte_count;

   511

			u8 threshold;

   512

			u8 tbd_count;

   513

			struct {

   514

				u32 buf_addr;

   515

				u16 size;

   516

				u16 eol;

   517

			} tbd;

   518

		} tcb;

   519

		u32 dump_buffer_addr;

   520

	} u;

   521

	struct cb *next, *prev;

   522

	dma_addr_t dma_addr;

   523

	struct sk_buff *skb;

   524

};

   525

   526

enum loopback {

   527

	lb_none = 0, lb_mac = 1, lb_phy = 3,

   528

};