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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2006 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

/* e1000_hw.h

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 * Structures, enums, and macros for the MAC

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 */

    32

    33

#ifndef _E1000_HW_H_

    34

#define _E1000_HW_H_

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    36

#include "e1000_osdep.h"

    37

    38

/* Forward declarations of structures used by the shared code */

    39

struct e1000_hw;

    40

struct e1000_hw_stats;

    41

    42

/* Enumerated types specific to the e1000 hardware */

    43

/* Media Access Controlers */

    44

typedef enum {

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	e1000_undefined = 0,

    46

	e1000_82542_rev2_0,

    47

	e1000_82542_rev2_1,

    48

	e1000_82543,

    49

	e1000_82544,

    50

	e1000_82540,

    51

	e1000_82545,

    52

	e1000_82545_rev_3,

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	e1000_82546,

    54

	e1000_82546_rev_3,

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	e1000_82541,

    56

	e1000_82541_rev_2,

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	e1000_82547,

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	e1000_82547_rev_2,

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	e1000_num_macs

    60

} e1000_mac_type;

    61

    62

typedef enum {

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	e1000_eeprom_uninitialized = 0,

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	e1000_eeprom_spi,

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	e1000_eeprom_microwire,

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	e1000_eeprom_flash,

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	e1000_eeprom_none,	/* No NVM support */

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	e1000_num_eeprom_types

    69

} e1000_eeprom_type;

    70

    71

/* Media Types */

    72

typedef enum {

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	e1000_media_type_copper = 0,

    74

	e1000_media_type_fiber = 1,

    75

	e1000_media_type_internal_serdes = 2,

    76

	e1000_num_media_types

    77

} e1000_media_type;

    78

    79

typedef enum {

    80

	e1000_10_half = 0,

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	e1000_10_full = 1,

    82

	e1000_100_half = 2,

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	e1000_100_full = 3

    84

} e1000_speed_duplex_type;

    85

    86

/* Flow Control Settings */

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typedef enum {

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	E1000_FC_NONE = 0,

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	E1000_FC_RX_PAUSE = 1,

    90

	E1000_FC_TX_PAUSE = 2,

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	E1000_FC_FULL = 3,

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	E1000_FC_DEFAULT = 0xFF

    93

} e1000_fc_type;

    94

    95

struct e1000_shadow_ram {

    96

	u16 eeprom_word;

    97

	bool modified;

    98

};

    99

   100

/* PCI bus types */

   101

typedef enum {

   102

	e1000_bus_type_unknown = 0,

   103

	e1000_bus_type_pci,

   104

	e1000_bus_type_pcix,

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	e1000_bus_type_reserved

   106

} e1000_bus_type;

   107

   108

/* PCI bus speeds */

   109

typedef enum {

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	e1000_bus_speed_unknown = 0,

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	e1000_bus_speed_33,

   112

	e1000_bus_speed_66,

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	e1000_bus_speed_100,

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	e1000_bus_speed_120,

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	e1000_bus_speed_133,

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	e1000_bus_speed_reserved

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} e1000_bus_speed;

   118

   119

/* PCI bus widths */

   120

typedef enum {

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	e1000_bus_width_unknown = 0,

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	e1000_bus_width_32,

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	e1000_bus_width_64,

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	e1000_bus_width_reserved

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} e1000_bus_width;

   126

   127

/* PHY status info structure and supporting enums */

   128

typedef enum {

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	e1000_cable_length_50 = 0,

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	e1000_cable_length_50_80,

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	e1000_cable_length_80_110,

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	e1000_cable_length_110_140,

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	e1000_cable_length_140,

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	e1000_cable_length_undefined = 0xFF

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} e1000_cable_length;

   136

   137

typedef enum {

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	e1000_gg_cable_length_60 = 0,

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	e1000_gg_cable_length_60_115 = 1,

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	e1000_gg_cable_length_115_150 = 2,

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	e1000_gg_cable_length_150 = 4

   142

} e1000_gg_cable_length;

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   144

typedef enum {

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	e1000_igp_cable_length_10 = 10,

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	e1000_igp_cable_length_20 = 20,

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	e1000_igp_cable_length_30 = 30,

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	e1000_igp_cable_length_40 = 40,

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	e1000_igp_cable_length_50 = 50,

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	e1000_igp_cable_length_60 = 60,

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	e1000_igp_cable_length_70 = 70,

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	e1000_igp_cable_length_80 = 80,

   153

	e1000_igp_cable_length_90 = 90,

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	e1000_igp_cable_length_100 = 100,

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	e1000_igp_cable_length_110 = 110,

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	e1000_igp_cable_length_115 = 115,

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	e1000_igp_cable_length_120 = 120,

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	e1000_igp_cable_length_130 = 130,

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	e1000_igp_cable_length_140 = 140,

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	e1000_igp_cable_length_150 = 150,

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	e1000_igp_cable_length_160 = 160,

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	e1000_igp_cable_length_170 = 170,

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	e1000_igp_cable_length_180 = 180

   164

} e1000_igp_cable_length;

   165

   166

typedef enum {

   167

	e1000_10bt_ext_dist_enable_normal = 0,

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	e1000_10bt_ext_dist_enable_lower,

   169

	e1000_10bt_ext_dist_enable_undefined = 0xFF

   170

} e1000_10bt_ext_dist_enable;

   171

   172

typedef enum {

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	e1000_rev_polarity_normal = 0,

   174

	e1000_rev_polarity_reversed,

   175

	e1000_rev_polarity_undefined = 0xFF

   176

} e1000_rev_polarity;

   177

   178

typedef enum {

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	e1000_downshift_normal = 0,

   180

	e1000_downshift_activated,

   181

	e1000_downshift_undefined = 0xFF

   182

} e1000_downshift;

   183

   184

typedef enum {

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	e1000_smart_speed_default = 0,

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	e1000_smart_speed_on,

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	e1000_smart_speed_off

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} e1000_smart_speed;

   189

   190

typedef enum {

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	e1000_polarity_reversal_enabled = 0,

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	e1000_polarity_reversal_disabled,

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	e1000_polarity_reversal_undefined = 0xFF

   194

} e1000_polarity_reversal;

   195

   196

typedef enum {

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	e1000_auto_x_mode_manual_mdi = 0,

   198

	e1000_auto_x_mode_manual_mdix,

   199

	e1000_auto_x_mode_auto1,

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	e1000_auto_x_mode_auto2,

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	e1000_auto_x_mode_undefined = 0xFF

   202

} e1000_auto_x_mode;

   203

   204

typedef enum {

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	e1000_1000t_rx_status_not_ok = 0,

   206

	e1000_1000t_rx_status_ok,

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	e1000_1000t_rx_status_undefined = 0xFF

   208

} e1000_1000t_rx_status;

   209

   210

typedef enum {

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    e1000_phy_m88 = 0,

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    e1000_phy_igp,

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    e1000_phy_undefined = 0xFF

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} e1000_phy_type;

   215

   216

typedef enum {

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	e1000_ms_hw_default = 0,

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	e1000_ms_force_master,

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	e1000_ms_force_slave,

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	e1000_ms_auto

   221

} e1000_ms_type;

   222

   223

typedef enum {

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	e1000_ffe_config_enabled = 0,

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	e1000_ffe_config_active,

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	e1000_ffe_config_blocked

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} e1000_ffe_config;

   228

   229

typedef enum {

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	e1000_dsp_config_disabled = 0,

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	e1000_dsp_config_enabled,

   232

	e1000_dsp_config_activated,

   233

	e1000_dsp_config_undefined = 0xFF

   234

} e1000_dsp_config;

   235

   236

struct e1000_phy_info {

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	e1000_cable_length cable_length;

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	e1000_10bt_ext_dist_enable extended_10bt_distance;

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	e1000_rev_polarity cable_polarity;

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	e1000_downshift downshift;

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	e1000_polarity_reversal polarity_correction;

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	e1000_auto_x_mode mdix_mode;

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	e1000_1000t_rx_status local_rx;

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	e1000_1000t_rx_status remote_rx;

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};

   246

   247

struct e1000_phy_stats {

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	u32 idle_errors;

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	u32 receive_errors;

   250

};

   251

   252

struct e1000_eeprom_info {

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	e1000_eeprom_type type;

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	u16 word_size;

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	u16 opcode_bits;

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	u16 address_bits;

   257

	u16 delay_usec;

   258

	u16 page_size;

   259

};

   260

   261

/* Flex ASF Information */

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#define E1000_HOST_IF_MAX_SIZE  2048

   263

   264

typedef enum {

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	e1000_byte_align = 0,

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	e1000_word_align = 1,

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	e1000_dword_align = 2

   268

} e1000_align_type;

   269

   270

/* Error Codes */

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#define E1000_SUCCESS      0

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#define E1000_ERR_EEPROM   1

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#define E1000_ERR_PHY      2

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#define E1000_ERR_CONFIG   3

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#define E1000_ERR_PARAM    4

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#define E1000_ERR_MAC_TYPE 5

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#define E1000_ERR_PHY_TYPE 6

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#define E1000_ERR_RESET   9

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#define E1000_ERR_MASTER_REQUESTS_PENDING 10

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#define E1000_ERR_HOST_INTERFACE_COMMAND 11

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#define E1000_BLK_PHY_RESET   12

   282

   283

#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \

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                                     (((_value) & 0xff00) >> 8))

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   286

/* Function prototypes */

   287

/* Initialization */

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s32 e1000_reset_hw(struct e1000_hw *hw);

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s32 e1000_init_hw(struct e1000_hw *hw);

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s32 e1000_set_mac_type(struct e1000_hw *hw);

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void e1000_set_media_type(struct e1000_hw *hw);

   292

   293

/* Link Configuration */

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s32 e1000_setup_link(struct e1000_hw *hw);

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s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);

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void e1000_config_collision_dist(struct e1000_hw *hw);

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s32 e1000_check_for_link(struct e1000_hw *hw);

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s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);

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s32 e1000_force_mac_fc(struct e1000_hw *hw);

   300

   301

/* PHY */

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s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);

   303

s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);

   304

s32 e1000_phy_hw_reset(struct e1000_hw *hw);

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s32 e1000_phy_reset(struct e1000_hw *hw);

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s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);

   307

s32 e1000_validate_mdi_setting(struct e1000_hw *hw);

   308

   309

/* EEPROM Functions */

   310

s32 e1000_init_eeprom_params(struct e1000_hw *hw);

   311

   312

/* MNG HOST IF functions */

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u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);

   314

   315

#define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64

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#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8	/* Host Interface data length */

   317

   318

#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10	/* Time in ms to process MNG command */

   319

#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0	/* Cookie offset */

   320

#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10	/* Cookie length */

   321

#define E1000_MNG_IAMT_MODE             0x3

   322

#define E1000_MNG_ICH_IAMT_MODE         0x2

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#define E1000_IAMT_SIGNATURE            0x544D4149	/* Intel(R) Active Management Technology signature */

   324

   325

#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1	/* DHCP parsing enabled */

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#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2	/* DHCP parsing enabled */

   327

#define E1000_VFTA_ENTRY_SHIFT                       0x5

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#define E1000_VFTA_ENTRY_MASK                        0x7F

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#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK              0x1F

   330

   331

struct e1000_host_mng_command_header {

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	u8 command_id;

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	u8 checksum;

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	u16 reserved1;

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	u16 reserved2;

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	u16 command_length;

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};

   338

   339

struct e1000_host_mng_command_info {

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	struct e1000_host_mng_command_header command_header;	/* Command Head/Command Result Head has 4 bytes */

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	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];	/* Command data can length 0..0x658 */

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};

   343

#ifdef __BIG_ENDIAN

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struct e1000_host_mng_dhcp_cookie {

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	u32 signature;

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	u16 vlan_id;

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	u8 reserved0;

   348

	u8 status;

   349

	u32 reserved1;

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	u8 checksum;

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	u8 reserved3;

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	u16 reserved2;

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};

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#else

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struct e1000_host_mng_dhcp_cookie {

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	u32 signature;

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	u8 status;

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	u8 reserved0;

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	u16 vlan_id;

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	u32 reserved1;

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	u16 reserved2;

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	u8 reserved3;

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	u8 checksum;

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};

   365

#endif

   366

   367

bool e1000_check_mng_mode(struct e1000_hw *hw);

   368

s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);

   369

s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);

   370

s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);

   371

s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);

   372

s32 e1000_read_mac_addr(struct e1000_hw *hw);

   373

   374

/* Filters (multicast, vlan, receive) */

   375

u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);

   376

void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);

   377

void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);

   378

void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);

   379

   380

/* LED functions */

   381

s32 e1000_setup_led(struct e1000_hw *hw);

   382

s32 e1000_cleanup_led(struct e1000_hw *hw);

   383

s32 e1000_led_on(struct e1000_hw *hw);

   384

s32 e1000_led_off(struct e1000_hw *hw);

   385

s32 e1000_blink_led_start(struct e1000_hw *hw);

   386

   387

/* Adaptive IFS Functions */

   388

   389

/* Everything else */

   390

void e1000_reset_adaptive(struct e1000_hw *hw);

   391

void e1000_update_adaptive(struct e1000_hw *hw);

   392

void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,

   393

			    u32 frame_len, u8 * mac_addr);

   394

void e1000_get_bus_info(struct e1000_hw *hw);

   395

void e1000_pci_set_mwi(struct e1000_hw *hw);

   396

void e1000_pci_clear_mwi(struct e1000_hw *hw);

   397

void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);

   398

int e1000_pcix_get_mmrbc(struct e1000_hw *hw);

   399

/* Port I/O is only supported on 82544 and newer */

   400

void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);

   401

   402

#define E1000_READ_REG_IO(a, reg) \

   403

    e1000_read_reg_io((a), E1000_##reg)

   404

#define E1000_WRITE_REG_IO(a, reg, val) \

   405

    e1000_write_reg_io((a), E1000_##reg, val)

   406

   407

/* PCI Device IDs */

   408

#define E1000_DEV_ID_82542               0x1000

   409

#define E1000_DEV_ID_82543GC_FIBER       0x1001

   410

#define E1000_DEV_ID_82543GC_COPPER      0x1004

   411

#define E1000_DEV_ID_82544EI_COPPER      0x1008

   412

#define E1000_DEV_ID_82544EI_FIBER       0x1009

   413

#define E1000_DEV_ID_82544GC_COPPER      0x100C

   414

#define E1000_DEV_ID_82544GC_LOM         0x100D

   415

#define E1000_DEV_ID_82540EM             0x100E

   416

#define E1000_DEV_ID_82540EM_LOM         0x1015

   417

#define E1000_DEV_ID_82540EP_LOM         0x1016

   418

#define E1000_DEV_ID_82540EP             0x1017

   419

#define E1000_DEV_ID_82540EP_LP          0x101E

   420

#define E1000_DEV_ID_82545EM_COPPER      0x100F

   421

#define E1000_DEV_ID_82545EM_FIBER       0x1011

   422

#define E1000_DEV_ID_82545GM_COPPER      0x1026

   423

#define E1000_DEV_ID_82545GM_FIBER       0x1027

   424

#define E1000_DEV_ID_82545GM_SERDES      0x1028

   425

#define E1000_DEV_ID_82546EB_COPPER      0x1010

   426

#define E1000_DEV_ID_82546EB_FIBER       0x1012

   427

#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D

   428

#define E1000_DEV_ID_82541EI             0x1013

   429

#define E1000_DEV_ID_82541EI_MOBILE      0x1018

   430

#define E1000_DEV_ID_82541ER_LOM         0x1014

   431

#define E1000_DEV_ID_82541ER             0x1078

   432

#define E1000_DEV_ID_82547GI             0x1075

   433

#define E1000_DEV_ID_82541GI             0x1076

   434

#define E1000_DEV_ID_82541GI_MOBILE      0x1077

   435

#define E1000_DEV_ID_82541GI_LF          0x107C

   436

#define E1000_DEV_ID_82546GB_COPPER      0x1079

   437

#define E1000_DEV_ID_82546GB_FIBER       0x107A

   438

#define E1000_DEV_ID_82546GB_SERDES      0x107B

   439

#define E1000_DEV_ID_82546GB_PCIE        0x108A

   440

#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099

   441

#define E1000_DEV_ID_82547EI             0x1019

   442

#define E1000_DEV_ID_82547EI_MOBILE      0x101A

   443

#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5

   444

   445

#define NODE_ADDRESS_SIZE 6

   446

#define ETH_LENGTH_OF_ADDRESS 6

   447

   448

/* MAC decode size is 128K - This is the size of BAR0 */

   449

#define MAC_DECODE_SIZE (128 * 1024)

   450

   451

#define E1000_82542_2_0_REV_ID 2

   452

#define E1000_82542_2_1_REV_ID 3

   453

#define E1000_REVISION_0       0

   454

#define E1000_REVISION_1       1

   455

#define E1000_REVISION_2       2

   456

#define E1000_REVISION_3       3

   457

   458

#define SPEED_10    10

   459

#define SPEED_100   100

   460

#define SPEED_1000  1000

   461

#define HALF_DUPLEX 1

   462

#define FULL_DUPLEX 2

   463

   464

/* The sizes (in bytes) of a ethernet packet */

   465

#define ENET_HEADER_SIZE             14

   466

#define MINIMUM_ETHERNET_FRAME_SIZE  64	/* With FCS */

   467

#define ETHERNET_FCS_SIZE            4

   468

#define MINIMUM_ETHERNET_PACKET_SIZE \

   469

    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)

   470

#define CRC_LENGTH                   ETHERNET_FCS_SIZE

   471

#define MAX_JUMBO_FRAME_SIZE         0x3F00

   472

   473

/* 802.1q VLAN Packet Sizes */

   474

#define VLAN_TAG_SIZE  4	/* 802.3ac tag (not DMAed) */

   475

   476

/* Ethertype field values */

   477

#define ETHERNET_IEEE_VLAN_TYPE 0x8100	/* 802.3ac packet */

   478

#define ETHERNET_IP_TYPE        0x0800	/* IP packets */

   479

#define ETHERNET_ARP_TYPE       0x0806	/* Address Resolution Protocol (ARP) */

   480

   481

/* Packet Header defines */

   482

#define IP_PROTOCOL_TCP    6

   483

#define IP_PROTOCOL_UDP    0x11

   484

   485

/* This defines the bits that are set in the Interrupt Mask

   486

 * Set/Read Register.  Each bit is documented below:

   487

 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)

   488

 *   o RXSEQ  = Receive Sequence Error

   489

 */

   490

#define POLL_IMS_ENABLE_MASK ( \

   491

    E1000_IMS_RXDMT0 |         \

   492

    E1000_IMS_RXSEQ)

   493

   494

/* This defines the bits that are set in the Interrupt Mask

   495

 * Set/Read Register.  Each bit is documented below:

   496

 *   o RXT0   = Receiver Timer Interrupt (ring 0)

   497

 *   o TXDW   = Transmit Descriptor Written Back

   498

 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)

   499

 *   o RXSEQ  = Receive Sequence Error

   500

 *   o LSC    = Link Status Change

   501

 */

   502

#define IMS_ENABLE_MASK ( \

   503

    E1000_IMS_RXT0   |    \

   504

    E1000_IMS_TXDW   |    \

   505

    E1000_IMS_RXDMT0 |    \

   506

    E1000_IMS_RXSEQ  |    \

   507

    E1000_IMS_LSC)

   508

   509

/* Number of high/low register pairs in the RAR. The RAR (Receive Address

   510

 * Registers) holds the directed and multicast addresses that we monitor. We

   511

 * reserve one of these spots for our directed address, allowing us room for

   512

 * E1000_RAR_ENTRIES - 1 multicast addresses.

   513

 */

   514

#define E1000_RAR_ENTRIES 15

   515

   516

#define MIN_NUMBER_OF_DESCRIPTORS  8

   517

#define MAX_NUMBER_OF_DESCRIPTORS  0xFFF8

   518

   519

/* Receive Descriptor */

   520

struct e1000_rx_desc {

   521

	__le64 buffer_addr;	/* Address of the descriptor's data buffer */

   522

	__le16 length;		/* Length of data DMAed into data buffer */

   523

	__le16 csum;		/* Packet checksum */

   524

	u8 status;		/* Descriptor status */

   525

	u8 errors;		/* Descriptor Errors */

   526

	__le16 special;

   527

};

   528

   529

/* Receive Descriptor - Extended */

   530