1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 */

    10

    11

#include <linux/module.h>

    12

#include <linux/moduleparam.h>

    13

#include <linux/pci.h>

    14

#include <linux/netdevice.h>

    15

#include <linux/etherdevice.h>

    16

#include <linux/delay.h>

    17

#include <linux/ethtool.h>

    18

#include <linux/mii.h>

    19

#include <linux/if_vlan.h>

    20

#include <linux/crc32.h>

    21

#include <linux/in.h>

    22

#include <linux/ip.h>

    23

#include <linux/tcp.h>

    24

#include <linux/init.h>

    25

#include <linux/interrupt.h>

    26

#include <linux/dma-mapping.h>

    27

#include <linux/pm_runtime.h>

    28

#include <linux/firmware.h>

    29

#include <linux/pci-aspm.h>

    30

#include <linux/prefetch.h>

    31

    32

#include <asm/io.h>

    33

#include <asm/irq.h>

    34

    35

#include "../globals.h"

    36

#include "ecdev.h"

    37

    38

#define RTL8169_VERSION "2.3LK-NAPI"

    39

#define MODULENAME "ec_r8169"

    40

#define PFX MODULENAME ": "

    41

    42

#define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"

    43

#define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"

    44

#define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"

    45

#define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"

    46

#define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"

    47

#define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"

    48

#define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"

    49

#define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"

    50

    51

#ifdef RTL8169_DEBUG

    52

#define assert(expr) \

    53

	if (!(expr)) {					\

    54

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    55

		#expr,__FILE__,__func__,__LINE__);		\

    56

	}

    57

#define dprintk(fmt, args...) \

    58

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    59

#else

    60

#define assert(expr) do {} while (0)

    61

#define dprintk(fmt, args...)	do {} while (0)

    62

#endif /* RTL8169_DEBUG */

    63

    64

#define R8169_MSG_DEFAULT \

    65

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    66

    67

#define TX_SLOTS_AVAIL(tp) \

    68

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)

    69

    70

/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */

    71

#define TX_FRAGS_READY_FOR(tp,nr_frags) \

    72

	(TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))

    73

    74

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    75

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    76

static const int multicast_filter_limit = 32;

    77

    78

#define MAX_READ_REQUEST_SHIFT	12

    79

#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */

    80

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    81

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    82

    83

#define R8169_REGS_SIZE		256

    84

#define R8169_NAPI_WEIGHT	64

    85

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    86

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    87

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    88

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    89

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    90

    91

#define RTL8169_TX_TIMEOUT	(6*HZ)

    92

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    93

    94

#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)

    95

#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)

    96

#define RTL_EEPROM_SIG_ADDR	0x0000

    97

    98

/* write/read MMIO register */

    99

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

   100

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

   101

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

   102

#define RTL_R8(reg)		readb (ioaddr + (reg))

   103

#define RTL_R16(reg)		readw (ioaddr + (reg))

   104

#define RTL_R32(reg)		readl (ioaddr + (reg))

   105

   106

enum mac_version {

   107

	RTL_GIGA_MAC_VER_01 = 0,

   108

	RTL_GIGA_MAC_VER_02,

   109

	RTL_GIGA_MAC_VER_03,

   110

	RTL_GIGA_MAC_VER_04,

   111

	RTL_GIGA_MAC_VER_05,

   112

	RTL_GIGA_MAC_VER_06,

   113

	RTL_GIGA_MAC_VER_07,

   114

	RTL_GIGA_MAC_VER_08,

   115

	RTL_GIGA_MAC_VER_09,

   116

	RTL_GIGA_MAC_VER_10,

   117

	RTL_GIGA_MAC_VER_11,

   118

	RTL_GIGA_MAC_VER_12,

   119

	RTL_GIGA_MAC_VER_13,

   120

	RTL_GIGA_MAC_VER_14,

   121

	RTL_GIGA_MAC_VER_15,

   122

	RTL_GIGA_MAC_VER_16,

   123

	RTL_GIGA_MAC_VER_17,

   124

	RTL_GIGA_MAC_VER_18,

   125

	RTL_GIGA_MAC_VER_19,

   126

	RTL_GIGA_MAC_VER_20,

   127

	RTL_GIGA_MAC_VER_21,

   128

	RTL_GIGA_MAC_VER_22,

   129

	RTL_GIGA_MAC_VER_23,

   130

	RTL_GIGA_MAC_VER_24,

   131

	RTL_GIGA_MAC_VER_25,

   132

	RTL_GIGA_MAC_VER_26,

   133

	RTL_GIGA_MAC_VER_27,

   134

	RTL_GIGA_MAC_VER_28,

   135

	RTL_GIGA_MAC_VER_29,

   136

	RTL_GIGA_MAC_VER_30,

   137

	RTL_GIGA_MAC_VER_31,

   138

	RTL_GIGA_MAC_VER_32,

   139

	RTL_GIGA_MAC_VER_33,

   140

	RTL_GIGA_MAC_VER_34,

   141

	RTL_GIGA_MAC_VER_35,

   142

	RTL_GIGA_MAC_VER_36,

   143

	RTL_GIGA_MAC_NONE   = 0xff,

   144

};

   145

   146

enum rtl_tx_desc_version {

   147

	RTL_TD_0	= 0,

   148

	RTL_TD_1	= 1,

   149

};

   150

   151

#define JUMBO_1K	ETH_DATA_LEN

   152

#define JUMBO_4K	(4*1024 - ETH_HLEN - 2)

   153

#define JUMBO_6K	(6*1024 - ETH_HLEN - 2)

   154

#define JUMBO_7K	(7*1024 - ETH_HLEN - 2)

   155

#define JUMBO_9K	(9*1024 - ETH_HLEN - 2)

   156

   157

#define _R(NAME,TD,FW,SZ,B) {	\

   158

	.name = NAME,		\

   159

	.txd_version = TD,	\

   160

	.fw_name = FW,		\

   161

	.jumbo_max = SZ,	\

   162

	.jumbo_tx_csum = B	\

   163

}

   164

   165

static const struct {

   166

	const char *name;

   167

	enum rtl_tx_desc_version txd_version;

   168

	const char *fw_name;

   169

	u16 jumbo_max;

   170

	bool jumbo_tx_csum;

   171

} rtl_chip_infos[] = {

   172

	/* PCI devices. */

   173

	[RTL_GIGA_MAC_VER_01] =

   174

		_R("RTL8169",		RTL_TD_0, NULL, JUMBO_7K, true),

   175

	[RTL_GIGA_MAC_VER_02] =

   176

		_R("RTL8169s",		RTL_TD_0, NULL, JUMBO_7K, true),

   177

	[RTL_GIGA_MAC_VER_03] =

   178

		_R("RTL8110s",		RTL_TD_0, NULL, JUMBO_7K, true),

   179

	[RTL_GIGA_MAC_VER_04] =

   180

		_R("RTL8169sb/8110sb",	RTL_TD_0, NULL, JUMBO_7K, true),

   181

	[RTL_GIGA_MAC_VER_05] =

   182

		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),

   183

	[RTL_GIGA_MAC_VER_06] =

   184

		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),

   185

	/* PCI-E devices. */

   186

	[RTL_GIGA_MAC_VER_07] =

   187

		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),

   188

	[RTL_GIGA_MAC_VER_08] =

   189

		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),

   190

	[RTL_GIGA_MAC_VER_09] =

   191

		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),

   192

	[RTL_GIGA_MAC_VER_10] =

   193

		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),

   194

	[RTL_GIGA_MAC_VER_11] =

   195

		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),

   196

	[RTL_GIGA_MAC_VER_12] =

   197

		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),

   198

	[RTL_GIGA_MAC_VER_13] =

   199

		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),

   200

	[RTL_GIGA_MAC_VER_14] =

   201

		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),

   202

	[RTL_GIGA_MAC_VER_15] =

   203

		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),

   204

	[RTL_GIGA_MAC_VER_16] =

   205

		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),

   206

	[RTL_GIGA_MAC_VER_17] =

   207

		_R("RTL8168b/8111b",	RTL_TD_1, NULL, JUMBO_4K, false),

   208

	[RTL_GIGA_MAC_VER_18] =

   209

		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),

   210

	[RTL_GIGA_MAC_VER_19] =

   211

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   212

	[RTL_GIGA_MAC_VER_20] =

   213

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   214

	[RTL_GIGA_MAC_VER_21] =

   215

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   216

	[RTL_GIGA_MAC_VER_22] =

   217

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   218

	[RTL_GIGA_MAC_VER_23] =

   219

		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),

   220

	[RTL_GIGA_MAC_VER_24] =

   221

		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),

   222

	[RTL_GIGA_MAC_VER_25] =

   223

		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_1,

   224

							JUMBO_9K, false),

   225

	[RTL_GIGA_MAC_VER_26] =

   226

		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_2,

   227

							JUMBO_9K, false),

   228

	[RTL_GIGA_MAC_VER_27] =

   229

		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),

   230

	[RTL_GIGA_MAC_VER_28] =

   231

		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),

   232

	[RTL_GIGA_MAC_VER_29] =

   233

		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,

   234

							JUMBO_1K, true),

   235

	[RTL_GIGA_MAC_VER_30] =

   236

		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,

   237

							JUMBO_1K, true),

   238

	[RTL_GIGA_MAC_VER_31] =

   239

		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),

   240

	[RTL_GIGA_MAC_VER_32] =

   241

		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_1,

   242

							JUMBO_9K, false),

   243

	[RTL_GIGA_MAC_VER_33] =

   244

		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_2,

   245

							JUMBO_9K, false),

   246

	[RTL_GIGA_MAC_VER_34] =

   247

		_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,

   248

							JUMBO_9K, false),

   249

	[RTL_GIGA_MAC_VER_35] =

   250

		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_1,

   251

							JUMBO_9K, false),

   252

	[RTL_GIGA_MAC_VER_36] =

   253

		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_2,

   254

							JUMBO_9K, false),

   255

};

   256

#undef _R

   257

   258

enum cfg_version {

   259

	RTL_CFG_0 = 0x00,

   260

	RTL_CFG_1,

   261

	RTL_CFG_2

   262

};

   263

   264

static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {

   265

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   266

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   267

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   268

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   269

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   270

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   271

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4302), 0, 0, RTL_CFG_0 },

   272

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   273

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   274

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   275

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   276

	{ 0x0001,				0x8168,

   277

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   278

	{0,},

   279

};

   280

   281

/* prevent driver from being loaded automatically */

   282

//MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   283

   284

static int rx_buf_sz = 16383;

   285

static int use_dac;

   286

static struct {

   287

	u32 msg_enable;

   288

} debug = { -1 };

   289

   290

enum rtl_registers {

   291

	MAC0		= 0,	/* Ethernet hardware address. */

   292

	MAC4		= 4,

   293

	MAR0		= 8,	/* Multicast filter. */

   294

	CounterAddrLow		= 0x10,

   295

	CounterAddrHigh		= 0x14,

   296

	TxDescStartAddrLow	= 0x20,

   297

	TxDescStartAddrHigh	= 0x24,

   298

	TxHDescStartAddrLow	= 0x28,

   299

	TxHDescStartAddrHigh	= 0x2c,

   300

	FLASH		= 0x30,

   301

	ERSR		= 0x36,

   302

	ChipCmd		= 0x37,

   303

	TxPoll		= 0x38,

   304

	IntrMask	= 0x3c,

   305

	IntrStatus	= 0x3e,

   306

   307

	TxConfig	= 0x40,

   308

#define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */

   309

#define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */

   310

   311

	RxConfig	= 0x44,

   312

#define	RX128_INT_EN			(1 << 15)	/* 8111c and later */

   313

#define	RX_MULTI_EN			(1 << 14)	/* 8111c only */

   314

#define	RXCFG_FIFO_SHIFT		13

   315

					/* No threshold before first PCI xfer */

   316

#define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)

   317

#define	RXCFG_DMA_SHIFT			8

   318

					/* Unlimited maximum PCI burst. */

   319

#define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)

   320

   321

	RxMissed	= 0x4c,

   322

	Cfg9346		= 0x50,

   323

	Config0		= 0x51,

   324

	Config1		= 0x52,

   325

	Config2		= 0x53,

   326

#define PME_SIGNAL			(1 << 5)	/* 8168c and later */

   327

   328

	Config3		= 0x54,

   329

	Config4		= 0x55,

   330

	Config5		= 0x56,

   331

	MultiIntr	= 0x5c,

   332

	PHYAR		= 0x60,

   333

	PHYstatus	= 0x6c,

   334

	RxMaxSize	= 0xda,

   335

	CPlusCmd	= 0xe0,

   336

	IntrMitigate	= 0xe2,

   337

	RxDescAddrLow	= 0xe4,

   338

	RxDescAddrHigh	= 0xe8,

   339

	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */

   340

   341

#define NoEarlyTx	0x3f	/* Max value : no early transmit. */

   342

   343

	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */

   344

   345

#define TxPacketMax	(8064 >> 7)

   346

#define EarlySize	0x27

   347

   348

	FuncEvent	= 0xf0,

   349

	FuncEventMask	= 0xf4,

   350

	FuncPresetState	= 0xf8,

   351

	FuncForceEvent	= 0xfc,

   352

};

   353

   354

enum rtl8110_registers {

   355

	TBICSR			= 0x64,

   356

	TBI_ANAR		= 0x68,

   357

	TBI_LPAR		= 0x6a,

   358

};

   359

   360

enum rtl8168_8101_registers {

   361

	CSIDR			= 0x64,

   362

	CSIAR			= 0x68,

   363

#define	CSIAR_FLAG			0x80000000

   364

#define	CSIAR_WRITE_CMD			0x80000000

   365

#define	CSIAR_BYTE_ENABLE		0x0f

   366

#define	CSIAR_BYTE_ENABLE_SHIFT		12

   367

#define	CSIAR_ADDR_MASK			0x0fff

   368

	PMCH			= 0x6f,

   369

	EPHYAR			= 0x80,

   370

#define	EPHYAR_FLAG			0x80000000

   371

#define	EPHYAR_WRITE_CMD		0x80000000

   372

#define	EPHYAR_REG_MASK			0x1f

   373

#define	EPHYAR_REG_SHIFT		16

   374

#define	EPHYAR_DATA_MASK		0xffff

   375

	DLLPR			= 0xd0,

   376

#define	PFM_EN				(1 << 6)

   377

	DBG_REG			= 0xd1,

   378

#define	FIX_NAK_1			(1 << 4)

   379

#define	FIX_NAK_2			(1 << 3)

   380

	TWSI			= 0xd2,

   381

	MCU			= 0xd3,

   382

#define	NOW_IS_OOB			(1 << 7)

   383

#define	EN_NDP				(1 << 3)

   384

#define	EN_OOB_RESET			(1 << 2)

   385

	EFUSEAR			= 0xdc,

   386

#define	EFUSEAR_FLAG			0x80000000

   387

#define	EFUSEAR_WRITE_CMD		0x80000000

   388

#define	EFUSEAR_READ_CMD		0x00000000

   389

#define	EFUSEAR_REG_MASK		0x03ff

   390

#define	EFUSEAR_REG_SHIFT		8

   391

#define	EFUSEAR_DATA_MASK		0xff

   392

};

   393

   394

enum rtl8168_registers {

   395

	LED_FREQ		= 0x1a,

   396

	EEE_LED			= 0x1b,

   397

	ERIDR			= 0x70,

   398

	ERIAR			= 0x74,

   399

#define ERIAR_FLAG			0x80000000

   400

#define ERIAR_WRITE_CMD			0x80000000

   401

#define ERIAR_READ_CMD			0x00000000

   402

#define ERIAR_ADDR_BYTE_ALIGN		4

   403

#define ERIAR_TYPE_SHIFT		16

   404

#define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)

   405

#define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)

   406

#define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)

   407

#define ERIAR_MASK_SHIFT		12

   408

#define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)

   409

#define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)

   410

#define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)

   411

	EPHY_RXER_NUM		= 0x7c,

   412

	OCPDR			= 0xb0,	/* OCP GPHY access */

   413

#define OCPDR_WRITE_CMD			0x80000000

   414

#define OCPDR_READ_CMD			0x00000000

   415

#define OCPDR_REG_MASK			0x7f

   416

#define OCPDR_GPHY_REG_SHIFT		16

   417

#define OCPDR_DATA_MASK			0xffff

   418

	OCPAR			= 0xb4,

   419

#define OCPAR_FLAG			0x80000000

   420

#define OCPAR_GPHY_WRITE_CMD		0x8000f060

   421

#define OCPAR_GPHY_READ_CMD		0x0000f060

   422

	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */

   423

	MISC			= 0xf0,	/* 8168e only. */

   424

#define TXPLA_RST			(1 << 29)

   425

#define PWM_EN				(1 << 22)

   426

};

   427

   428

enum rtl_register_content {

   429

	/* InterruptStatusBits */

   430

	SYSErr		= 0x8000,

   431

	PCSTimeout	= 0x4000,

   432

	SWInt		= 0x0100,

   433

	TxDescUnavail	= 0x0080,

   434

	RxFIFOOver	= 0x0040,

   435

	LinkChg		= 0x0020,

   436

	RxOverflow	= 0x0010,

   437

	TxErr		= 0x0008,

   438

	TxOK		= 0x0004,

   439

	RxErr		= 0x0002,

   440

	RxOK		= 0x0001,

   441

   442

	/* RxStatusDesc */

   443

	RxBOVF	= (1 << 24),

   444

	RxFOVF	= (1 << 23),

   445

	RxRWT	= (1 << 22),

   446

	RxRES	= (1 << 21),

   447

	RxRUNT	= (1 << 20),

   448

	RxCRC	= (1 << 19),

   449

   450

	/* ChipCmdBits */

   451

	StopReq		= 0x80,

   452

	CmdReset	= 0x10,

   453

	CmdRxEnb	= 0x08,

   454

	CmdTxEnb	= 0x04,

   455

	RxBufEmpty	= 0x01,

   456

   457

	/* TXPoll register p.5 */

   458

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   459

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   460

	FSWInt		= 0x01,		/* Forced software interrupt */

   461

   462

	/* Cfg9346Bits */

   463

	Cfg9346_Lock	= 0x00,

   464

	Cfg9346_Unlock	= 0xc0,

   465

   466

	/* rx_mode_bits */

   467

	AcceptErr	= 0x20,

   468

	AcceptRunt	= 0x10,

   469

	AcceptBroadcast	= 0x08,

   470

	AcceptMulticast	= 0x04,

   471

	AcceptMyPhys	= 0x02,

   472

	AcceptAllPhys	= 0x01,

   473

#define RX_CONFIG_ACCEPT_MASK		0x3f

   474

   475

	/* TxConfigBits */

   476

	TxInterFrameGapShift = 24,

   477

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   478

   479

	/* Config1 register p.24 */

   480

	LEDS1		= (1 << 7),

   481

	LEDS0		= (1 << 6),

   482

	Speed_down	= (1 << 4),

   483

	MEMMAP		= (1 << 3),

   484

	IOMAP		= (1 << 2),

   485

	VPD		= (1 << 1),

   486

	PMEnable	= (1 << 0),	/* Power Management Enable */

   487

   488

	/* Config2 register p. 25 */

   489

	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */

   490

	PCI_Clock_66MHz = 0x01,

   491

	PCI_Clock_33MHz = 0x00,

   492

   493

	/* Config3 register p.25 */

   494

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   495

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   496

	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */

   497

	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */

   498

   499

	/* Config4 register */

   500

	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */

   501

   502

	/* Config5 register p.27 */

   503

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   504

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   505

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   506

	Spi_en		= (1 << 3),

   507

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   508

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   509

   510

	/* TBICSR p.28 */

   511

	TBIReset	= 0x80000000,

   512

	TBILoopback	= 0x40000000,

   513

	TBINwEnable	= 0x20000000,

   514

	TBINwRestart	= 0x10000000,

   515

	TBILinkOk	= 0x02000000,

   516

	TBINwComplete	= 0x01000000,

   517

   518

	/* CPlusCmd p.31 */

   519

	EnableBist	= (1 << 15),	// 8168 8101

   520

	Mac_dbgo_oe	= (1 << 14),	// 8168 8101

   521

	Normal_mode	= (1 << 13),	// unused

   522

	Force_half_dup	= (1 << 12),	// 8168 8101

   523

	Force_rxflow_en	= (1 << 11),	// 8168 8101

   524

	Force_txflow_en	= (1 << 10),	// 8168 8101

   525

	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101

   526

	ASF		= (1 << 8),	// 8168 8101

   527

	PktCntrDisable	= (1 << 7),	// 8168 8101

   528

	Mac_dbgo_sel	= 0x001c,	// 8168

   529

	RxVlan		= (1 << 6),

   530

	RxChkSum	= (1 << 5),