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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2010 Intel Corporation.

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     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

    28

    29

#include "e1000-2.6.37-ethercat.h"

    30

    31

enum e1000_mng_mode {

    32

	e1000_mng_mode_none = 0,

    33

	e1000_mng_mode_asf,

    34

	e1000_mng_mode_pt,

    35

	e1000_mng_mode_ipmi,

    36

	e1000_mng_mode_host_if_only

    37

};

    38

    39

#define E1000_FACTPS_MNGCG		0x20000000

    40

    41

/* Intel(R) Active Management Technology signature */

    42

#define E1000_IAMT_SIGNATURE		0x544D4149

    43

    44

/**

    45

 *  e1000e_get_bus_info_pcie - Get PCIe bus information

    46

 *  @hw: pointer to the HW structure

    47

 *

    48

 *  Determines and stores the system bus information for a particular

    49

 *  network interface.  The following bus information is determined and stored:

    50

 *  bus speed, bus width, type (PCIe), and PCIe function.

    51

 **/

    52

s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)

    53

{

    54

	struct e1000_mac_info *mac = &hw->mac;

    55

	struct e1000_bus_info *bus = &hw->bus;

    56

	struct e1000_adapter *adapter = hw->adapter;

    57

	u16 pcie_link_status, cap_offset;

    58

    59

	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);

    60

	if (!cap_offset) {

    61

		bus->width = e1000_bus_width_unknown;

    62

	} else {

    63

		pci_read_config_word(adapter->pdev,

    64

				     cap_offset + PCIE_LINK_STATUS,

    65

				     &pcie_link_status);

    66

		bus->width = (enum e1000_bus_width)((pcie_link_status &

    67

						     PCIE_LINK_WIDTH_MASK) >>

    68

						    PCIE_LINK_WIDTH_SHIFT);

    69

	}

    70

    71

	mac->ops.set_lan_id(hw);

    72

    73

	return 0;

    74

}

    75

    76

/**

    77

 *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices

    78

 *

    79

 *  @hw: pointer to the HW structure

    80

 *

    81

 *  Determines the LAN function id by reading memory-mapped registers

    82

 *  and swaps the port value if requested.

    83

 **/

    84

void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)

    85

{

    86

	struct e1000_bus_info *bus = &hw->bus;

    87

	u32 reg;

    88

    89

	/*

    90

	 * The status register reports the correct function number

    91

	 * for the device regardless of function swap state.

    92

	 */

    93

	reg = er32(STATUS);

    94

	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

    95

}

    96

    97

/**

    98

 *  e1000_set_lan_id_single_port - Set LAN id for a single port device

    99

 *  @hw: pointer to the HW structure

   100

 *

   101

 *  Sets the LAN function id to zero for a single port device.

   102

 **/

   103

void e1000_set_lan_id_single_port(struct e1000_hw *hw)

   104

{

   105

	struct e1000_bus_info *bus = &hw->bus;

   106

   107

	bus->func = 0;

   108

}

   109

   110

/**

   111

 *  e1000_clear_vfta_generic - Clear VLAN filter table

   112

 *  @hw: pointer to the HW structure

   113

 *

   114

 *  Clears the register array which contains the VLAN filter table by

   115

 *  setting all the values to 0.

   116

 **/

   117

void e1000_clear_vfta_generic(struct e1000_hw *hw)

   118

{

   119

	u32 offset;

   120

   121

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

   122

		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);

   123

		e1e_flush();

   124

	}

   125

}

   126

   127

/**

   128

 *  e1000_write_vfta_generic - Write value to VLAN filter table

   129

 *  @hw: pointer to the HW structure

   130

 *  @offset: register offset in VLAN filter table

   131

 *  @value: register value written to VLAN filter table

   132

 *

   133

 *  Writes value at the given offset in the register array which stores

   134

 *  the VLAN filter table.

   135

 **/

   136

void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)

   137

{

   138

	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);

   139

	e1e_flush();

   140

}

   141

   142

/**

   143

 *  e1000e_init_rx_addrs - Initialize receive address's

   144

 *  @hw: pointer to the HW structure

   145

 *  @rar_count: receive address registers

   146

 *

   147

 *  Setups the receive address registers by setting the base receive address

   148

 *  register to the devices MAC address and clearing all the other receive

   149

 *  address registers to 0.

   150

 **/

   151

void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   152

{

   153

	u32 i;

   154

	u8 mac_addr[ETH_ALEN] = {0};

   155

   156

	/* Setup the receive address */

   157

	e_dbg("Programming MAC Address into RAR[0]\n");

   158

   159

	e1000e_rar_set(hw, hw->mac.addr, 0);

   160

   161

	/* Zero out the other (rar_entry_count - 1) receive addresses */

   162

	e_dbg("Clearing RAR[1-%u]\n", rar_count-1);

   163

	for (i = 1; i < rar_count; i++)

   164

		e1000e_rar_set(hw, mac_addr, i);

   165

}

   166

   167

/**

   168

 *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr

   169

 *  @hw: pointer to the HW structure

   170

 *

   171

 *  Checks the nvm for an alternate MAC address.  An alternate MAC address

   172

 *  can be setup by pre-boot software and must be treated like a permanent

   173

 *  address and must override the actual permanent MAC address. If an

   174

 *  alternate MAC address is found it is programmed into RAR0, replacing

   175

 *  the permanent address that was installed into RAR0 by the Si on reset.

   176

 *  This function will return SUCCESS unless it encounters an error while

   177

 *  reading the EEPROM.

   178

 **/

   179

s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)

   180

{

   181

	u32 i;

   182

	s32 ret_val = 0;

   183

	u16 offset, nvm_alt_mac_addr_offset, nvm_data;

   184

	u8 alt_mac_addr[ETH_ALEN];

   185

   186

	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);

   187

	if (ret_val)

   188

		goto out;

   189

   190

	/* Check for LOM (vs. NIC) or one of two valid mezzanine cards */

   191

	if (!((nvm_data & NVM_COMPAT_LOM) ||

   192

	      (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_DUAL) ||

   193

	      (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)))

   194

		goto out;

   195

   196

	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,

   197

	                         &nvm_alt_mac_addr_offset);

   198

	if (ret_val) {

   199

		e_dbg("NVM Read Error\n");

   200

		goto out;

   201

	}

   202

   203

	if (nvm_alt_mac_addr_offset == 0xFFFF) {

   204

		/* There is no Alternate MAC Address */

   205

		goto out;

   206

	}

   207

   208

	if (hw->bus.func == E1000_FUNC_1)

   209

		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;

   210

	for (i = 0; i < ETH_ALEN; i += 2) {

   211

		offset = nvm_alt_mac_addr_offset + (i >> 1);

   212

		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);

   213

		if (ret_val) {

   214

			e_dbg("NVM Read Error\n");

   215

			goto out;

   216

		}

   217

   218

		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);

   219

		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);

   220

	}

   221

   222

	/* if multicast bit is set, the alternate address will not be used */

   223

	if (alt_mac_addr[0] & 0x01) {

   224

		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");

   225

		goto out;

   226

	}

   227

   228

	/*

   229

	 * We have a valid alternate MAC address, and we want to treat it the

   230

	 * same as the normal permanent MAC address stored by the HW into the

   231

	 * RAR. Do this by mapping this address into RAR0.

   232

	 */

   233

	e1000e_rar_set(hw, alt_mac_addr, 0);

   234

   235

out:

   236

	return ret_val;

   237

}

   238

   239

/**

   240

 *  e1000e_rar_set - Set receive address register

   241

 *  @hw: pointer to the HW structure

   242

 *  @addr: pointer to the receive address

   243

 *  @index: receive address array register

   244

 *

   245

 *  Sets the receive address array register at index to the address passed

   246

 *  in by addr.

   247

 **/

   248

void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)

   249

{

   250

	u32 rar_low, rar_high;

   251

   252

	/*

   253

	 * HW expects these in little endian so we reverse the byte order

   254

	 * from network order (big endian) to little endian

   255

	 */

   256

	rar_low = ((u32) addr[0] |

   257

		   ((u32) addr[1] << 8) |

   258

		    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));

   259

   260

	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

   261

   262

	/* If MAC address zero, no need to set the AV bit */

   263

	if (rar_low || rar_high)

   264

		rar_high |= E1000_RAH_AV;

   265

   266

	/*

   267

	 * Some bridges will combine consecutive 32-bit writes into

   268

	 * a single burst write, which will malfunction on some parts.

   269

	 * The flushes avoid this.

   270

	 */

   271

	ew32(RAL(index), rar_low);

   272

	e1e_flush();

   273

	ew32(RAH(index), rar_high);

   274

	e1e_flush();

   275

}

   276

   277

/**

   278

 *  e1000_hash_mc_addr - Generate a multicast hash value

   279

 *  @hw: pointer to the HW structure

   280

 *  @mc_addr: pointer to a multicast address

   281

 *

   282

 *  Generates a multicast address hash value which is used to determine

   283

 *  the multicast filter table array address and new table value.  See

   284

 *  e1000_mta_set_generic()

   285

 **/

   286

static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   287

{

   288

	u32 hash_value, hash_mask;

   289

	u8 bit_shift = 0;

   290

   291

	/* Register count multiplied by bits per register */

   292

	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   293

   294

	/*

   295

	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts

   296

	 * where 0xFF would still fall within the hash mask.

   297

	 */

   298

	while (hash_mask >> bit_shift != 0xFF)

   299

		bit_shift++;

   300

   301

	/*

   302

	 * The portion of the address that is used for the hash table

   303

	 * is determined by the mc_filter_type setting.

   304

	 * The algorithm is such that there is a total of 8 bits of shifting.

   305

	 * The bit_shift for a mc_filter_type of 0 represents the number of

   306

	 * left-shifts where the MSB of mc_addr[5] would still fall within

   307

	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   308

	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   309

	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   310

	 * cases are a variation of this algorithm...essentially raising the

   311

	 * number of bits to shift mc_addr[5] left, while still keeping the

   312

	 * 8-bit shifting total.

   313

	 *

   314

	 * For example, given the following Destination MAC Address and an

   315

	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   316

	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   317

	 * values resulting from each mc_filter_type...

   318

	 * [0] [1] [2] [3] [4] [5]

   319

	 * 01  AA  00  12  34  56

   320

	 * LSB		 MSB

   321

	 *

   322

	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   323

	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   324

	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   325

	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   326

	 */

   327

	switch (hw->mac.mc_filter_type) {

   328

	default:

   329

	case 0:

   330

		break;

   331

	case 1:

   332

		bit_shift += 1;

   333

		break;

   334

	case 2:

   335

		bit_shift += 2;

   336

		break;

   337

	case 3:

   338

		bit_shift += 4;

   339

		break;

   340

	}

   341

   342

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   343

				  (((u16) mc_addr[5]) << bit_shift)));

   344

   345

	return hash_value;

   346

}

   347

   348

/**

   349

 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses

   350

 *  @hw: pointer to the HW structure

   351

 *  @mc_addr_list: array of multicast addresses to program

   352

 *  @mc_addr_count: number of multicast addresses to program

   353

 *

   354

 *  Updates entire Multicast Table Array.

   355

 *  The caller must have a packed mc_addr_list of multicast addresses.

   356

 **/

   357

void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,

   358

					u8 *mc_addr_list, u32 mc_addr_count)

   359

{

   360

	u32 hash_value, hash_bit, hash_reg;

   361

	int i;

   362

   363

	/* clear mta_shadow */

   364

	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

   365

   366

	/* update mta_shadow from mc_addr_list */

   367

	for (i = 0; (u32) i < mc_addr_count; i++) {

   368

		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);

   369

   370

		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   371

		hash_bit = hash_value & 0x1F;

   372

   373

		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);

   374

		mc_addr_list += (ETH_ALEN);

   375

	}

   376

   377

	/* replace the entire MTA table */

   378

	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)

   379

		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);

   380

	e1e_flush();

   381

}

   382

   383

/**

   384

 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters

   385

 *  @hw: pointer to the HW structure

   386

 *

   387

 *  Clears the base hardware counters by reading the counter registers.

   388

 **/

   389

void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)

   390

{

   391

	er32(CRCERRS);

   392

	er32(SYMERRS);

   393

	er32(MPC);

   394

	er32(SCC);

   395

	er32(ECOL);

   396

	er32(MCC);

   397

	er32(LATECOL);

   398

	er32(COLC);

   399

	er32(DC);

   400

	er32(SEC);

   401

	er32(RLEC);

   402

	er32(XONRXC);

   403

	er32(XONTXC);

   404

	er32(XOFFRXC);

   405

	er32(XOFFTXC);

   406

	er32(FCRUC);

   407

	er32(GPRC);

   408

	er32(BPRC);

   409

	er32(MPRC);

   410

	er32(GPTC);

   411

	er32(GORCL);

   412

	er32(GORCH);

   413

	er32(GOTCL);

   414

	er32(GOTCH);

   415

	er32(RNBC);

   416

	er32(RUC);

   417

	er32(RFC);

   418

	er32(ROC);

   419

	er32(RJC);

   420

	er32(TORL);

   421

	er32(TORH);

   422

	er32(TOTL);

   423

	er32(TOTH);

   424

	er32(TPR);

   425

	er32(TPT);

   426

	er32(MPTC);

   427

	er32(BPTC);

   428

}

   429

   430

/**

   431

 *  e1000e_check_for_copper_link - Check for link (Copper)

   432

 *  @hw: pointer to the HW structure

   433

 *

   434

 *  Checks to see of the link status of the hardware has changed.  If a

   435

 *  change in link status has been detected, then we read the PHY registers

   436

 *  to get the current speed/duplex if link exists.

   437

 **/

   438

s32 e1000e_check_for_copper_link(struct e1000_hw *hw)

   439

{

   440

	struct e1000_mac_info *mac = &hw->mac;

   441

	s32 ret_val;

   442

	bool link;

   443

   444

	/*

   445

	 * We only want to go out to the PHY registers to see if Auto-Neg

   446

	 * has completed and/or if our link status has changed.  The

   447

	 * get_link_status flag is set upon receiving a Link Status

   448

	 * Change or Rx Sequence Error interrupt.

   449

	 */

   450

	if (!mac->get_link_status)

   451

		return 0;

   452

   453

	/*

   454

	 * First we want to see if the MII Status Register reports

   455

	 * link.  If so, then we want to get the current speed/duplex

   456

	 * of the PHY.

   457

	 */

   458

	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   459

	if (ret_val)

   460

		return ret_val;

   461

   462

	if (!link)

   463

		return ret_val; /* No link detected */

   464

   465

	mac->get_link_status = false;

   466

   467

	/*

   468

	 * Check if there was DownShift, must be checked

   469

	 * immediately after link-up

   470

	 */

   471

	e1000e_check_downshift(hw);

   472

   473

	/*

   474

	 * If we are forcing speed/duplex, then we simply return since

   475

	 * we have already determined whether we have link or not.

   476

	 */

   477

	if (!mac->autoneg) {

   478

		ret_val = -E1000_ERR_CONFIG;

   479

		return ret_val;

   480

	}

   481

   482

	/*

   483

	 * Auto-Neg is enabled.  Auto Speed Detection takes care

   484

	 * of MAC speed/duplex configuration.  So we only need to

   485

	 * configure Collision Distance in the MAC.

   486

	 */

   487

	e1000e_config_collision_dist(hw);

   488

   489

	/*

   490

	 * Configure Flow Control now that Auto-Neg has completed.

   491

	 * First, we need to restore the desired flow control

   492

	 * settings because we may have had to re-autoneg with a

   493

	 * different link partner.

   494

	 */

   495

	ret_val = e1000e_config_fc_after_link_up(hw);

   496

	if (ret_val) {

   497

		e_dbg("Error configuring flow control\n");

   498

	}

   499

   500

	return ret_val;

   501

}

   502

   503

/**

   504

 *  e1000e_check_for_fiber_link - Check for link (Fiber)

   505

 *  @hw: pointer to the HW structure

   506

 *

   507

 *  Checks for link up on the hardware.  If link is not up and we have

   508

 *  a signal, then we need to force link up.

   509

 **/

   510

s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)

   511

{

   512

	struct e1000_mac_info *mac = &hw->mac;

   513

	u32 rxcw;

   514

	u32 ctrl;

   515

	u32 status;

   516

	s32 ret_val;

   517

   518

	ctrl = er32(CTRL);

   519

	status = er32(STATUS);

   520

	rxcw = er32(RXCW);

   521

   522

	/*

   523

	 * If we don't have link (auto-negotiation failed or link partner

   524

	 * cannot auto-negotiate), the cable is plugged in (we have signal),

   525

	 * and our link partner is not trying to auto-negotiate with us (we

   526

	 * are receiving idles or data), we need to force link up. We also

   527

	 * need to give auto-negotiation time to complete, in case the cable

   528

	 * was just plugged in. The autoneg_failed flag does this.

   529

	 */

   530

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */