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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2008 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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*******************************************************************************/

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    29

/*

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 * 82562G 10/100 Network Connection

    31

 * 82562G-2 10/100 Network Connection

    32

 * 82562GT 10/100 Network Connection

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 * 82562GT-2 10/100 Network Connection

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 * 82562V 10/100 Network Connection

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 * 82562V-2 10/100 Network Connection

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 * 82566DC-2 Gigabit Network Connection

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 * 82566DC Gigabit Network Connection

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 * 82566DM-2 Gigabit Network Connection

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 * 82566DM Gigabit Network Connection

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 * 82566MC Gigabit Network Connection

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 * 82566MM Gigabit Network Connection

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 * 82567LM Gigabit Network Connection

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 * 82567LF Gigabit Network Connection

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 * 82567V Gigabit Network Connection

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 * 82567LM-2 Gigabit Network Connection

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 * 82567LF-2 Gigabit Network Connection

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 * 82567V-2 Gigabit Network Connection

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 * 82567LF-3 Gigabit Network Connection

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 * 82567LM-3 Gigabit Network Connection

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 * 82567LM-4 Gigabit Network Connection

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 * 82577LM Gigabit Network Connection

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 * 82577LC Gigabit Network Connection

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 * 82578DM Gigabit Network Connection

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 * 82578DC Gigabit Network Connection

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 */

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#include <linux/netdevice.h>

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#include <linux/ethtool.h>

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#include <linux/delay.h>

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#include <linux/pci.h>

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#include "e1000.h"

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    64

#define ICH_FLASH_GFPREG		0x0000

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#define ICH_FLASH_HSFSTS		0x0004

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#define ICH_FLASH_HSFCTL		0x0006

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#define ICH_FLASH_FADDR			0x0008

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#define ICH_FLASH_FDATA0		0x0010

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#define ICH_FLASH_PR0			0x0074

    70

    71

#define ICH_FLASH_READ_COMMAND_TIMEOUT	500

    72

#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500

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#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000

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#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

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#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

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#define ICH_CYCLE_READ			0

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#define ICH_CYCLE_WRITE			2

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#define ICH_CYCLE_ERASE			3

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    81

#define FLASH_GFPREG_BASE_MASK		0x1FFF

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#define FLASH_SECTOR_ADDR_SHIFT		12

    83

    84

#define ICH_FLASH_SEG_SIZE_256		256

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#define ICH_FLASH_SEG_SIZE_4K		4096

    86

#define ICH_FLASH_SEG_SIZE_8K		8192

    87

#define ICH_FLASH_SEG_SIZE_64K		65536

    88

    89

    90

#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */

    91

    92

#define E1000_ICH_MNG_IAMT_MODE		0x2

    93

    94

#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \

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				 (ID_LED_DEF1_OFF2 <<  8) | \

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				 (ID_LED_DEF1_ON2  <<  4) | \

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				 (ID_LED_DEF1_DEF2))

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    99

#define E1000_ICH_NVM_SIG_WORD		0x13

   100

#define E1000_ICH_NVM_SIG_MASK		0xC000

   101

#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0

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#define E1000_ICH_NVM_SIG_VALUE         0x80

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   104

#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

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   106

#define E1000_FEXTNVM_SW_CONFIG		1

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#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

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   109

#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL

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   111

#define E1000_ICH_RAR_ENTRIES		7

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   113

#define PHY_PAGE_SHIFT 5

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#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

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			   ((reg) & MAX_PHY_REG_ADDRESS))

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#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */

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#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */

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   119

#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002

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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

   121

#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200

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   123

#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */

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   125

#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */

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   127

/* SMBus Address Phy Register */

   128

#define HV_SMB_ADDR            PHY_REG(768, 26)

   129

#define HV_SMB_ADDR_PEC_EN     0x0200

   130

#define HV_SMB_ADDR_VALID      0x0080

   131

   132

/* Strapping Option Register - RO */

   133

#define E1000_STRAP                     0x0000C

   134

#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

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#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

   136

   137

/* OEM Bits Phy Register */

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#define HV_OEM_BITS            PHY_REG(768, 25)

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#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */

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#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */

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#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */

   142

   143

#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */

   144

#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */

   145

   146

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

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/* Offset 04h HSFSTS */

   148

union ich8_hws_flash_status {

   149

	struct ich8_hsfsts {

   150

		u16 flcdone    :1; /* bit 0 Flash Cycle Done */

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		u16 flcerr     :1; /* bit 1 Flash Cycle Error */

   152

		u16 dael       :1; /* bit 2 Direct Access error Log */

   153

		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */

   154

		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */

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		u16 reserved1  :2; /* bit 13:6 Reserved */

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		u16 reserved2  :6; /* bit 13:6 Reserved */

   157

		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */

   158

		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */

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	} hsf_status;

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	u16 regval;

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};

   162

   163

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

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/* Offset 06h FLCTL */

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union ich8_hws_flash_ctrl {

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	struct ich8_hsflctl {

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		u16 flcgo      :1;   /* 0 Flash Cycle Go */

   168

		u16 flcycle    :2;   /* 2:1 Flash Cycle */

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		u16 reserved   :5;   /* 7:3 Reserved  */

   170

		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */

   171

		u16 flockdn    :6;   /* 15:10 Reserved */

   172

	} hsf_ctrl;

   173

	u16 regval;

   174

};

   175

   176

/* ICH Flash Region Access Permissions */

   177

union ich8_hws_flash_regacc {

   178

	struct ich8_flracc {

   179

		u32 grra      :8; /* 0:7 GbE region Read Access */

   180

		u32 grwa      :8; /* 8:15 GbE region Write Access */

   181

		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */

   182

		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */

   183

	} hsf_flregacc;

   184

	u16 regval;

   185

};

   186

   187

/* ICH Flash Protected Region */

   188

union ich8_flash_protected_range {

   189

	struct ich8_pr {

   190

		u32 base:13;     /* 0:12 Protected Range Base */

   191

		u32 reserved1:2; /* 13:14 Reserved */

   192

		u32 rpe:1;       /* 15 Read Protection Enable */

   193

		u32 limit:13;    /* 16:28 Protected Range Limit */

   194

		u32 reserved2:2; /* 29:30 Reserved */

   195

		u32 wpe:1;       /* 31 Write Protection Enable */

   196

	} range;

   197

	u32 regval;

   198

};

   199

   200

static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);

   201

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   202

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   203

static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);

   204

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   205

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

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						u32 offset, u8 byte);

   207

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   208

					 u8 *data);

   209

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u16 *data);

   211

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u8 size, u16 *data);

   213

static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

   214

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   215

static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);

   216

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

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static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

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static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

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static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

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static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

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static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

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static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

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static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   224

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   225

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   226

static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   227

static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);

   228

   229

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   230

{

   231

	return readw(hw->flash_address + reg);

   232

}

   233

   234

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   235

{

   236

	return readl(hw->flash_address + reg);

   237

}

   238

   239

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   240

{

   241

	writew(val, hw->flash_address + reg);

   242

}

   243

   244

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   245

{

   246

	writel(val, hw->flash_address + reg);

   247

}

   248

   249

#define er16flash(reg)		__er16flash(hw, (reg))

   250

#define er32flash(reg)		__er32flash(hw, (reg))

   251

#define ew16flash(reg,val)	__ew16flash(hw, (reg), (val))

   252

#define ew32flash(reg,val)	__ew32flash(hw, (reg), (val))

   253

   254

/**

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 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

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 *  @hw: pointer to the HW structure

   257

 *

   258

 *  Initialize family-specific PHY parameters and function pointers.

   259

 **/

   260

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   261

{

   262

	struct e1000_phy_info *phy = &hw->phy;

   263

	s32 ret_val = 0;

   264

   265

	phy->addr                     = 1;

   266

	phy->reset_delay_us           = 100;

   267

   268

	phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;

   269

	phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;

   270

	phy->ops.read_phy_reg_locked  = e1000_read_phy_reg_hv_locked;

   271

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   272

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   273

	phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;

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	phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;

   275

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   276

   277

	phy->id = e1000_phy_unknown;

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	e1000e_get_phy_id(hw);

   279

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   280

   281

	if (phy->type == e1000_phy_82577) {

   282

		phy->ops.check_polarity = e1000_check_polarity_82577;

   283

		phy->ops.force_speed_duplex =

   284

			e1000_phy_force_speed_duplex_82577;

   285

		phy->ops.get_cable_length   = e1000_get_cable_length_82577;

   286

		phy->ops.get_phy_info = e1000_get_phy_info_82577;

   287

		phy->ops.commit_phy = e1000e_phy_sw_reset;

   288

	}

   289

   290

	return ret_val;

   291

}

   292

   293

/**

   294

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   295

 *  @hw: pointer to the HW structure

   296

 *

   297

 *  Initialize family-specific PHY parameters and function pointers.

   298

 **/

   299

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   300

{

   301

	struct e1000_phy_info *phy = &hw->phy;

   302

	s32 ret_val;

   303

	u16 i = 0;

   304

   305

	phy->addr			= 1;

   306

	phy->reset_delay_us		= 100;

   307

   308

	/*

   309

	 * We may need to do this twice - once for IGP and if that fails,

   310

	 * we'll set BM func pointers and try again

   311

	 */

   312

	ret_val = e1000e_determine_phy_address(hw);

   313

	if (ret_val) {

   314

		hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;

   315

		hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;

   316

		ret_val = e1000e_determine_phy_address(hw);

   317

		if (ret_val)

   318

			return ret_val;

   319

	}

   320

   321

	phy->id = 0;

   322

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   323

	       (i++ < 100)) {

   324

		msleep(1);

   325

		ret_val = e1000e_get_phy_id(hw);

   326

		if (ret_val)

   327

			return ret_val;

   328

	}

   329

   330

	/* Verify phy id */

   331

	switch (phy->id) {

   332

	case IGP03E1000_E_PHY_ID:

   333

		phy->type = e1000_phy_igp_3;

   334

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   335

		phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;

   336

		phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;

   337

		break;

   338

	case IFE_E_PHY_ID:

   339

	case IFE_PLUS_E_PHY_ID:

   340

	case IFE_C_E_PHY_ID:

   341

		phy->type = e1000_phy_ife;

   342

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   343

		break;

   344

	case BME1000_E_PHY_ID:

   345

		phy->type = e1000_phy_bm;

   346

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   347

		hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;

   348

		hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;

   349

		hw->phy.ops.commit_phy = e1000e_phy_sw_reset;

   350

		break;

   351

	default:

   352

		return -E1000_ERR_PHY;

   353

		break;

   354

	}

   355

   356

	phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;

   357

   358

	return 0;

   359

}

   360

   361

/**

   362

 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   363

 *  @hw: pointer to the HW structure

   364

 *

   365

 *  Initialize family-specific NVM parameters and function

   366

 *  pointers.

   367

 **/

   368

static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   369

{

   370

	struct e1000_nvm_info *nvm = &hw->nvm;

   371

	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   372

	u32 gfpreg, sector_base_addr, sector_end_addr;

   373

	u16 i;

   374

   375

	/* Can't read flash registers if the register set isn't mapped. */

   376

	if (!hw->flash_address) {

   377

		hw_dbg(hw, "ERROR: Flash registers not mapped\n");

   378

		return -E1000_ERR_CONFIG;

   379

	}

   380

   381

	nvm->type = e1000_nvm_flash_sw;

   382

   383

	gfpreg = er32flash(ICH_FLASH_GFPREG);

   384

   385

	/*

   386

	 * sector_X_addr is a "sector"-aligned address (4096 bytes)

   387

	 * Add 1 to sector_end_addr since this sector is included in

   388

	 * the overall size.

   389

	 */

   390

	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   391

	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   392

   393

	/* flash_base_addr is byte-aligned */

   394

	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   395

   396

	/*

   397

	 * find total size of the NVM, then cut in half since the total

   398

	 * size represents two separate NVM banks.

   399

	 */

   400

	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)

   401

				<< FLASH_SECTOR_ADDR_SHIFT;

   402

	nvm->flash_bank_size /= 2;

   403

	/* Adjust to word count */

   404

	nvm->flash_bank_size /= sizeof(u16);

   405

   406

	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;

   407

   408

	/* Clear shadow ram */

   409

	for (i = 0; i < nvm->word_size; i++) {

   410

		dev_spec->shadow_ram[i].modified = 0;

   411

		dev_spec->shadow_ram[i].value    = 0xFFFF;

   412

	}

   413

   414

	return 0;

   415

}

   416

   417

/**

   418

 *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers

   419

 *  @hw: pointer to the HW structure

   420

 *

   421

 *  Initialize family-specific MAC parameters and function

   422

 *  pointers.

   423

 **/

   424

static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)

   425

{

   426

	struct e1000_hw *hw = &adapter->hw;

   427

	struct e1000_mac_info *mac = &hw->mac;

   428

   429

	/* Set media type function pointer */

   430

	hw->phy.media_type = e1000_media_type_copper;

   431

   432

	/* Set mta register count */

   433

	mac->mta_reg_count = 32;

   434

	/* Set rar entry count */

   435

	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;

   436

	if (mac->type == e1000_ich8lan)

   437

		mac->rar_entry_count--;

   438

	/* Set if manageability features are enabled. */

   439

	mac->arc_subsystem_valid = 1;

   440

   441

	/* LED operations */

   442

	switch (mac->type) {

   443

	case e1000_ich8lan:

   444

	case e1000_ich9lan:

   445

	case e1000_ich10lan:

   446

		/* ID LED init */

   447

		mac->ops.id_led_init = e1000e_id_led_init;

   448

		/* setup LED */

   449

		mac->ops.setup_led = e1000e_setup_led_generic;

   450

		/* cleanup LED */

   451

		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;

   452

		/* turn on/off LED */

   453

		mac->ops.led_on = e1000_led_on_ich8lan;

   454

		mac->ops.led_off = e1000_led_off_ich8lan;

   455

		break;

   456

	case e1000_pchlan:

   457

		/* ID LED init */

   458

		mac->ops.id_led_init = e1000_id_led_init_pchlan;

   459

		/* setup LED */

   460

		mac->ops.setup_led = e1000_setup_led_pchlan;

   461

		/* cleanup LED */

   462

		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;

   463

		/* turn on/off LED */

   464

		mac->ops.led_on = e1000_led_on_pchlan;

   465

		mac->ops.led_off = e1000_led_off_pchlan;

   466

		break;

   467

	default:

   468

		break;

   469

	}

   470

   471

	/* Enable PCS Lock-loss workaround for ICH8 */

   472

	if (mac->type == e1000_ich8lan)

   473

		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);

   474

   475

	return 0;

   476

}

   477

   478

/**

   479

 *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)

   480

 *  @hw: pointer to the HW structure

   481

 *

   482

 *  Checks to see of the link status of the hardware has changed.  If a

   483

 *  change in link status has been detected, then we read the PHY registers

   484

 *  to get the current speed/duplex if link exists.

   485

 **/

   486

static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)

   487

{

   488

	struct e1000_mac_info *mac = &hw->mac;

   489

	s32 ret_val;

   490

	bool link;

   491

   492

	/*

   493

	 * We only want to go out to the PHY registers to see if Auto-Neg

   494

	 * has completed and/or if our link status has changed.  The

   495

	 * get_link_status flag is set upon receiving a Link Status

   496

	 * Change or Rx Sequence Error interrupt.

   497

	 */

   498

	if (!mac->get_link_status) {

   499

		ret_val = 0;

   500

		goto out;

   501

	}

   502

   503

	/*

   504

	 * First we want to see if the MII Status Register reports

   505

	 * link.  If so, then we want to get the current speed/duplex

   506

	 * of the PHY.

   507

	 */

   508

	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   509

	if (ret_val)

   510

		goto out;

   511

   512

	if (hw->mac.type == e1000_pchlan) {

   513

		ret_val = e1000_k1_gig_workaround_hv(hw, link);

   514

		if (ret_val)

   515

			goto out;

   516

	}

   517

   518

	if (!link)

   519

		goto out; /* No link detected */

   520

   521

	mac->get_link_status = false;

   522

   523

	if (hw->phy.type == e1000_phy_82578) {

   524

		ret_val = e1000_link_stall_workaround_hv(hw);

   525

		if (ret_val)

   526

			goto out;

   527

	}

   528

   529

	/*

   530

	 * Check if there was DownShift, must be checked