1

/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2007-2008  Florian Pose, Ingenieurgemeinschaft IgH

     6

 *

     7

 *  This file is part of the IgH EtherCAT Master.

     8

 *

     9

 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10

 *  modify it under the terms of the GNU General Public License version 2, as

    11

 *  published by the Free Software Foundation.

    12

 *

    13

 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16

 *  Public License for more details.

    17

 *

    18

 *  You should have received a copy of the GNU General Public License along

    19

 *  with the IgH EtherCAT Master; if not, write to the Free Software

    20

 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21

 *

    22

 *  ---

    23

 *

    24

 *  The license mentioned above concerns the source code only. Using the

    25

 *  EtherCAT technology and brand is only permitted in compliance with the

    26

 *  industrial property and similar rights of Beckhoff Automation GmbH.

    27

 *

    28

 *  ---

    29

 *

    30

 *  vim: noexpandtab

    31

 *

    32

 *****************************************************************************/

    33

    34

/**

    35

   \file

    36

   EtherCAT driver for e100-compatible NICs.

    37

*/

    38

    39

/* Former documentation: */

    40

    41

/*******************************************************************************

    42

    43

  Intel PRO/100 Linux driver

    44

  Copyright(c) 1999 - 2006 Intel Corporation.

    45

    46

  This program is free software; you can redistribute it and/or modify it

    47

  under the terms and conditions of the GNU General Public License,

    48

  version 2, as published by the Free Software Foundation.

    49

    50

  This program is distributed in the hope it will be useful, but WITHOUT

    51

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    52

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    53

  more details.

    54

    55

  You should have received a copy of the GNU General Public License along with

    56

  this program; if not, write to the Free Software Foundation, Inc.,

    57

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    58

    59

  The full GNU General Public License is included in this distribution in

    60

  the file called "COPYING".

    61

    62

  Contact Information:

    63

  Linux NICS <linux.nics@intel.com>

    64

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    65

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    66

    67

*******************************************************************************/

    68

    69

/*

    70

 *	e100.c: Intel(R) PRO/100 ethernet driver

    71

 *

    72

 *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

    73

 *	original e100 driver, but better described as a munging of

    74

 *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

    75

 *

    76

 *	References:

    77

 *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

    78

 *		Open Source Software Developers Manual,

    79

 *		http://sourceforge.net/projects/e1000

    80

 *

    81

 *

    82

 *	                      Theory of Operation

    83

 *

    84

 *	I.   General

    85

 *

    86

 *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

    87

 *	controller family, which includes the 82557, 82558, 82559, 82550,

    88

 *	82551, and 82562 devices.  82558 and greater controllers

    89

 *	integrate the Intel 82555 PHY.  The controllers are used in

    90

 *	server and client network interface cards, as well as in

    91

 *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

    92

 *	configurations.  8255x supports a 32-bit linear addressing

    93

 *	mode and operates at 33Mhz PCI clock rate.

    94

 *

    95

 *	II.  Driver Operation

    96

 *

    97

 *	Memory-mapped mode is used exclusively to access the device's

    98

 *	shared-memory structure, the Control/Status Registers (CSR). All

    99

 *	setup, configuration, and control of the device, including queuing

   100

 *	of Tx, Rx, and configuration commands is through the CSR.

   101

 *	cmd_lock serializes accesses to the CSR command register.  cb_lock

   102

 *	protects the shared Command Block List (CBL).

   103

 *

   104

 *	8255x is highly MII-compliant and all access to the PHY go

   105

 *	through the Management Data Interface (MDI).  Consequently, the

   106

 *	driver leverages the mii.c library shared with other MII-compliant

   107

 *	devices.

   108

 *

   109

 *	Big- and Little-Endian byte order as well as 32- and 64-bit

   110

 *	archs are supported.  Weak-ordered memory and non-cache-coherent

   111

 *	archs are supported.

   112

 *

   113

 *	III. Transmit

   114

 *

   115

 *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

   116

 *	together in a fixed-size ring (CBL) thus forming the flexible mode

   117

 *	memory structure.  A TCB marked with the suspend-bit indicates

   118

 *	the end of the ring.  The last TCB processed suspends the

   119

 *	controller, and the controller can be restarted by issue a CU

   120

 *	resume command to continue from the suspend point, or a CU start

   121

 *	command to start at a given position in the ring.

   122

 *

   123

 *	Non-Tx commands (config, multicast setup, etc) are linked

   124

 *	into the CBL ring along with Tx commands.  The common structure

   125

 *	used for both Tx and non-Tx commands is the Command Block (CB).

   126

 *

   127

 *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

   128

 *	is the next CB to check for completion; cb_to_send is the first

   129

 *	CB to start on in case of a previous failure to resume.  CB clean

   130

 *	up happens in interrupt context in response to a CU interrupt.

   131

 *	cbs_avail keeps track of number of free CB resources available.

   132

 *

   133

 * 	Hardware padding of short packets to minimum packet size is

   134

 * 	enabled.  82557 pads with 7Eh, while the later controllers pad

   135

 * 	with 00h.

   136

 *

   137

 *	IV.  Receive

   138

 *

   139

 *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

   140

 *	Descriptors (RFD) + data buffer, thus forming the simplified mode

   141

 *	memory structure.  Rx skbs are allocated to contain both the RFD

   142

 *	and the data buffer, but the RFD is pulled off before the skb is

   143

 *	indicated.  The data buffer is aligned such that encapsulated

   144

 *	protocol headers are u32-aligned.  Since the RFD is part of the

   145

 *	mapped shared memory, and completion status is contained within

   146

 *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

   147

 *	view from software and hardware.

   148

 *

   149

 *	In order to keep updates to the RFD link field from colliding with

   150

 *	hardware writes to mark packets complete, we use the feature that

   151

 *	hardware will not write to a size 0 descriptor and mark the previous

   152

 *	packet as end-of-list (EL).   After updating the link, we remove EL

   153

 *	and only then restore the size such that hardware may use the

   154

 *	previous-to-end RFD.

   155

 *

   156

 *	Under typical operation, the  receive unit (RU) is start once,

   157

 *	and the controller happily fills RFDs as frames arrive.  If

   158

 *	replacement RFDs cannot be allocated, or the RU goes non-active,

   159

 *	the RU must be restarted.  Frame arrival generates an interrupt,

   160

 *	and Rx indication and re-allocation happen in the same context,

   161

 *	therefore no locking is required.  A software-generated interrupt

   162

 *	is generated from the watchdog to recover from a failed allocation

   163

 *	scenario where all Rx resources have been indicated and none re-

   164

 *	placed.

   165

 *

   166

 *	V.   Miscellaneous

   167

 *

   168

 * 	VLAN offloading of tagging, stripping and filtering is not

   169

 * 	supported, but driver will accommodate the extra 4-byte VLAN tag

   170

 * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

   171

 * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

   172

 * 	not supported (hardware limitation).

   173

 *

   174

 * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

   175

 *

   176

 * 	Thanks to JC (jchapman@katalix.com) for helping with

   177

 * 	testing/troubleshooting the development driver.

   178

 *

   179

 * 	TODO:

   180

 * 	o several entry points race with dev->close

   181

 * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

   182

 *

   183

 *	FIXES:

   184

 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

   185

 *	- Stratus87247: protect MDI control register manipulations

   186

 */

   187

   188

#include <linux/module.h>

   189

#include <linux/moduleparam.h>

   190

#include <linux/kernel.h>

   191

#include <linux/types.h>

   192

#include <linux/slab.h>

   193

#include <linux/delay.h>

   194

#include <linux/init.h>

   195

#include <linux/pci.h>

   196

#include <linux/dma-mapping.h>

   197

#include <linux/netdevice.h>

   198

#include <linux/etherdevice.h>

   199

#include <linux/mii.h>

   200

#include <linux/if_vlan.h>

   201

#include <linux/skbuff.h>

   202

#include <linux/ethtool.h>

   203

#include <linux/string.h>

   204

#include <linux/firmware.h>

   205

#include <asm/unaligned.h>

   206

   207

// EtherCAT includes

   208

#include "../globals.h"

   209

#include "ecdev.h"

   210

   211

#define DRV_NAME		"ec_e100"

   212

   213

#define DRV_EXT			"-NAPI"

   214

#define DRV_VERSION		"3.5.23-k6"DRV_EXT

   215

#define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"

   216

#define DRV_COPYRIGHT		"Copyright(c) 1999-2006 Intel Corporation"

   217

#define PFX			DRV_NAME ": "

   218

   219

#define E100_WATCHDOG_PERIOD	(2 * HZ)

   220

#define E100_NAPI_WEIGHT	16

   221

   222

#define FIRMWARE_D101M		"e100/d101m_ucode.bin"

   223

#define FIRMWARE_D101S		"e100/d101s_ucode.bin"

   224

#define FIRMWARE_D102E		"e100/d102e_ucode.bin"

   225

   226

MODULE_DESCRIPTION(DRV_DESCRIPTION);

   227

MODULE_AUTHOR(DRV_COPYRIGHT);

   228

MODULE_LICENSE("GPL");

   229

MODULE_VERSION(DRV_VERSION);

   230

MODULE_FIRMWARE(FIRMWARE_D101M);

   231

MODULE_FIRMWARE(FIRMWARE_D101S);

   232

MODULE_FIRMWARE(FIRMWARE_D102E);

   233

   234

MODULE_DESCRIPTION(DRV_DESCRIPTION);

   235

MODULE_AUTHOR("Mario Witkowski <mario.witkowski@w4systems.de>");

   236

MODULE_LICENSE("GPL");

   237

MODULE_VERSION(DRV_VERSION ", master " EC_MASTER_VERSION);

   238

   239

void e100_ec_poll(struct net_device *);

   240

   241

static int debug = 3;

   242

static int eeprom_bad_csum_allow = 0;

   243

static int use_io = 0;

   244

module_param(debug, int, 0);

   245

module_param(eeprom_bad_csum_allow, int, 0);

   246

module_param(use_io, int, 0);

   247

MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

   248

MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

   249

MODULE_PARM_DESC(use_io, "Force use of i/o access mode");

   250

#define DPRINTK(nlevel, klevel, fmt, args...) \

   251

	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

   252

	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

   253

		__func__ , ## args))

   254

   255

#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

   256

	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

   257

	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

   258

static struct pci_device_id e100_id_table[] = {

   259

	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

   260

	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

   261

	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

   262

	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

   263

	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

   264

	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

   265

	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

   266

	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

   267

	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

   268

	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

   269

	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

   270

	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

   271

	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

   272

	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

   273

	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

   274

	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

   275

	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

   276

	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

   277

	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

   278

	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

   279

	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

   280

	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

   281

	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

   282

	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

   283

	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

   284

	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

   285

	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

   286

	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

   287

	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

   288

	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

   289

	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

   290

	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

   291

	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

   292

	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

   293

	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

   294

	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

   295

	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

   296

	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

   297

	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

   298

	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

   299

	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

   300

	{ 0, }

   301

};

   302

   303

// prevent from being loaded automatically

   304

//MODULE_DEVICE_TABLE(pci, e100_id_table);

   305

   306

enum mac {

   307

	mac_82557_D100_A  = 0,

   308

	mac_82557_D100_B  = 1,

   309

	mac_82557_D100_C  = 2,

   310

	mac_82558_D101_A4 = 4,

   311

	mac_82558_D101_B0 = 5,

   312

	mac_82559_D101M   = 8,

   313

	mac_82559_D101S   = 9,

   314

	mac_82550_D102    = 12,

   315

	mac_82550_D102_C  = 13,

   316

	mac_82551_E       = 14,

   317

	mac_82551_F       = 15,

   318

	mac_82551_10      = 16,

   319

	mac_unknown       = 0xFF,

   320

};

   321

   322

enum phy {

   323

	phy_100a     = 0x000003E0,

   324

	phy_100c     = 0x035002A8,

   325

	phy_82555_tx = 0x015002A8,

   326

	phy_nsc_tx   = 0x5C002000,

   327

	phy_82562_et = 0x033002A8,

   328

	phy_82562_em = 0x032002A8,

   329

	phy_82562_ek = 0x031002A8,

   330

	phy_82562_eh = 0x017002A8,

   331

	phy_unknown  = 0xFFFFFFFF,

   332

};

   333

   334

/* CSR (Control/Status Registers) */

   335

struct csr {

   336

	struct {

   337

		u8 status;

   338

		u8 stat_ack;

   339

		u8 cmd_lo;

   340

		u8 cmd_hi;

   341

		u32 gen_ptr;

   342

	} scb;

   343

	u32 port;

   344

	u16 flash_ctrl;

   345

	u8 eeprom_ctrl_lo;

   346

	u8 eeprom_ctrl_hi;

   347

	u32 mdi_ctrl;

   348

	u32 rx_dma_count;

   349

};

   350

   351

enum scb_status {

   352

	rus_no_res       = 0x08,

   353

	rus_ready        = 0x10,

   354

	rus_mask         = 0x3C,

   355

};

   356

   357

enum ru_state  {

   358

	RU_SUSPENDED = 0,

   359

	RU_RUNNING	 = 1,

   360

	RU_UNINITIALIZED = -1,

   361

};

   362

   363

enum scb_stat_ack {

   364

	stat_ack_not_ours    = 0x00,

   365

	stat_ack_sw_gen      = 0x04,

   366

	stat_ack_rnr         = 0x10,

   367

	stat_ack_cu_idle     = 0x20,

   368

	stat_ack_frame_rx    = 0x40,

   369

	stat_ack_cu_cmd_done = 0x80,

   370

	stat_ack_not_present = 0xFF,

   371

	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

   372

	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

   373

};

   374

   375

enum scb_cmd_hi {

   376

	irq_mask_none = 0x00,

   377

	irq_mask_all  = 0x01,

   378

	irq_sw_gen    = 0x02,

   379

};

   380

   381

enum scb_cmd_lo {

   382

	cuc_nop        = 0x00,

   383

	ruc_start      = 0x01,

   384

	ruc_load_base  = 0x06,

   385

	cuc_start      = 0x10,

   386

	cuc_resume     = 0x20,

   387

	cuc_dump_addr  = 0x40,

   388

	cuc_dump_stats = 0x50,

   389

	cuc_load_base  = 0x60,

   390

	cuc_dump_reset = 0x70,

   391

};

   392

   393

enum cuc_dump {

   394

	cuc_dump_complete       = 0x0000A005,

   395

	cuc_dump_reset_complete = 0x0000A007,

   396

};

   397

   398

enum port {

   399

	software_reset  = 0x0000,

   400

	selftest        = 0x0001,

   401

	selective_reset = 0x0002,

   402

};

   403

   404

enum eeprom_ctrl_lo {

   405

	eesk = 0x01,

   406

	eecs = 0x02,

   407

	eedi = 0x04,

   408

	eedo = 0x08,

   409

};

   410

   411

enum mdi_ctrl {

   412

	mdi_write = 0x04000000,

   413

	mdi_read  = 0x08000000,

   414

	mdi_ready = 0x10000000,

   415

};

   416

   417

enum eeprom_op {

   418

	op_write = 0x05,

   419

	op_read  = 0x06,

   420

	op_ewds  = 0x10,

   421

	op_ewen  = 0x13,

   422

};

   423

   424

enum eeprom_offsets {

   425

	eeprom_cnfg_mdix  = 0x03,

   426

	eeprom_id         = 0x0A,

   427

	eeprom_config_asf = 0x0D,

   428

	eeprom_smbus_addr = 0x90,

   429

};

   430

   431

enum eeprom_cnfg_mdix {

   432

	eeprom_mdix_enabled = 0x0080,

   433

};

   434

   435

enum eeprom_id {

   436

	eeprom_id_wol = 0x0020,

   437

};

   438

   439

enum eeprom_config_asf {

   440

	eeprom_asf = 0x8000,

   441

	eeprom_gcl = 0x4000,

   442

};

   443

   444

enum cb_status {

   445

	cb_complete = 0x8000,

   446

	cb_ok       = 0x2000,

   447

};

   448

   449

enum cb_command {

   450

	cb_nop    = 0x0000,

   451

	cb_iaaddr = 0x0001,

   452

	cb_config = 0x0002,

   453

	cb_multi  = 0x0003,

   454

	cb_tx     = 0x0004,

   455

	cb_ucode  = 0x0005,

   456

	cb_dump   = 0x0006,

   457

	cb_tx_sf  = 0x0008,

   458

	cb_cid    = 0x1f00,

   459

	cb_i      = 0x2000,

   460

	cb_s      = 0x4000,

   461

	cb_el     = 0x8000,

   462

};

   463

   464

struct rfd {

   465

	__le16 status;

   466

	__le16 command;

   467

	__le32 link;

   468

	__le32 rbd;

   469

	__le16 actual_size;

   470

	__le16 size;

   471

};

   472

   473

struct rx {

   474

	struct rx *next, *prev;

   475

	struct sk_buff *skb;

   476

	dma_addr_t dma_addr;

   477

};

   478

   479

#if defined(__BIG_ENDIAN_BITFIELD)

   480

#define X(a,b)	b,a

   481

#else

   482

#define X(a,b)	a,b

   483

#endif

   484

struct config {

   485

/*0*/	u8 X(byte_count:6, pad0:2);

   486

/*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

   487

/*2*/	u8 adaptive_ifs;

   488

/*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

   489

	   term_write_cache_line:1), pad3:4);

   490

/*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   491

/*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   492

/*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   493

	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   494

	   rx_discard_overruns:1), rx_save_bad_frames:1);

   495

/*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   496

	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   497

	   tx_dynamic_tbd:1);

   498

/*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   499

/*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   500

	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   501

/*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   502

	   loopback:2);

   503

/*11*/	u8 X(linear_priority:3, pad11:5);

   504

/*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   505

/*13*/	u8 ip_addr_lo;

   506

/*14*/	u8 ip_addr_hi;

   507

/*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   508

	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   509

	   pad15_2:1), crs_or_cdt:1);

   510

/*16*/	u8 fc_delay_lo;

   511

/*17*/	u8 fc_delay_hi;

   512

/*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   513

	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   514

/*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   515

	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   516

	   full_duplex_force:1), full_duplex_pin:1);

   517

/*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   518

/*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   519

/*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   520

	u8 pad_d102[9];

   521

};

   522

   523

#define E100_MAX_MULTICAST_ADDRS	64

   524

struct multi {

   525

	__le16 count;

   526

	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   527

};

   528

   529

/* Important: keep total struct u32-aligned */

   530

#define UCODE_SIZE			134