1

/*

     2

     3

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

     4

     5

	Maintained by Jeff Garzik <jgarzik@pobox.com>

     6

	Copyright 2000-2002 Jeff Garzik

     7

     8

	Much code comes from Donald Becker's rtl8139.c driver,

     9

	versions 1.13 and older.  This driver was originally based

    10

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    11

    12

	-----<snip>-----

    13

    14

        	Written 1997-2001 by Donald Becker.

    15

		This software may be used and distributed according to the

    16

		terms of the GNU General Public License (GPL), incorporated

    17

		herein by reference.  Drivers based on or derived from this

    18

		code fall under the GPL and must retain the authorship,

    19

		copyright and license notice.  This file is not a complete

    20

		program and may only be used when the entire operating

    21

		system is licensed under the GPL.

    22

    23

		This driver is for boards based on the RTL8129 and RTL8139

    24

		PCI ethernet chips.

    25

    26

		The author may be reached as becker@scyld.com, or C/O Scyld

    27

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    28

		MD 21403

    29

    30

		Support and updates available at

    31

		http://www.scyld.com/network/rtl8139.html

    32

    33

		Twister-tuning table provided by Kinston

    34

		<shangh@realtek.com.tw>.

    35

    36

	-----<snip>-----

    37

    38

	This software may be used and distributed according to the terms

    39

	of the GNU General Public License, incorporated herein by reference.

    40

    41

	Contributors:

    42

    43

		Donald Becker - he wrote the original driver, kudos to him!

    44

		(but please don't e-mail him for support, this isn't his driver)

    45

    46

		Tigran Aivazian - bug fixes, skbuff free cleanup

    47

    48

		Martin Mares - suggestions for PCI cleanup

    49

    50

		David S. Miller - PCI DMA and softnet updates

    51

    52

		Ernst Gill - fixes ported from BSD driver

    53

    54

		Daniel Kobras - identified specific locations of

    55

			posted MMIO write bugginess

    56

    57

		Gerard Sharp - bug fix, testing and feedback

    58

    59

		David Ford - Rx ring wrap fix

    60

    61

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    62

		to find and fix a crucial bug on older chipsets.

    63

    64

		Donald Becker/Chris Butterworth/Marcus Westergren -

    65

		Noticed various Rx packet size-related buglets.

    66

    67

		Santiago Garcia Mantinan - testing and feedback

    68

    69

		Jens David - 2.2.x kernel backports

    70

    71

		Martin Dennett - incredibly helpful insight on undocumented

    72

		features of the 8139 chips

    73

    74

		Jean-Jacques Michel - bug fix

    75

    76

		Tobias Ringström - Rx interrupt status checking suggestion

    77

    78

		Andrew Morton - Clear blocked signals, avoid

    79

		buffer overrun setting current->comm.

    80

    81

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

    82

    83

		Robert Kuebel - Save kernel thread from dying on any signal.

    84

    85

	Submitting bug reports:

    86

    87

		"rtl8139-diag -mmmaaavvveefN" output

    88

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

    89

    90

*/

    91

    92

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

    93

    94

#define DRV_NAME	"8139too"

    95

#define DRV_VERSION	"0.9.28"

    96

    97

    98

#include <linux/module.h>

    99

#include <linux/kernel.h>

   100

#include <linux/compiler.h>

   101

#include <linux/pci.h>

   102

#include <linux/init.h>

   103

#include <linux/netdevice.h>

   104

#include <linux/etherdevice.h>

   105

#include <linux/rtnetlink.h>

   106

#include <linux/delay.h>

   107

#include <linux/ethtool.h>

   108

#include <linux/mii.h>

   109

#include <linux/completion.h>

   110

#include <linux/crc32.h>

   111

#include <linux/io.h>

   112

#include <linux/uaccess.h>

   113

#include <linux/gfp.h>

   114

#include <asm/irq.h>

   115

   116

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   117

   118

/* Default Message level */

   119

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   120

                                 NETIF_MSG_PROBE  | \

   121

                                 NETIF_MSG_LINK)

   122

   123

   124

/* define to 1, 2 or 3 to enable copious debugging info */

   125

#define RTL8139_DEBUG 0

   126

   127

/* define to 1 to disable lightweight runtime debugging checks */

   128

#undef RTL8139_NDEBUG

   129

   130

   131

#ifdef RTL8139_NDEBUG

   132

#  define assert(expr) do {} while (0)

   133

#else

   134

#  define assert(expr) \

   135

        if (unlikely(!(expr))) {				\

   136

		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   137

		       #expr, __FILE__, __func__, __LINE__);	\

   138

        }

   139

#endif

   140

   141

   142

/* A few user-configurable values. */

   143

/* media options */

   144

#define MAX_UNITS 8

   145

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   146

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   147

   148

/* Whether to use MMIO or PIO. Default to MMIO. */

   149

#ifdef CONFIG_8139TOO_PIO

   150

static int use_io = 1;

   151

#else

   152

static int use_io = 0;

   153

#endif

   154

   155

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   156

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   157

static int multicast_filter_limit = 32;

   158

   159

/* bitmapped message enable number */

   160

static int debug = -1;

   161

   162

/*

   163

 * Receive ring size

   164

 * Warning: 64K ring has hardware issues and may lock up.

   165

 */

   166

#if defined(CONFIG_SH_DREAMCAST)

   167

#define RX_BUF_IDX 0	/* 8K ring */

   168

#else

   169

#define RX_BUF_IDX	2	/* 32K ring */

   170

#endif

   171

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   172

#define RX_BUF_PAD	16

   173

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   174

   175

#if RX_BUF_LEN == 65536

   176

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   177

#else

   178

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   179

#endif

   180

   181

/* Number of Tx descriptor registers. */

   182

#define NUM_TX_DESC	4

   183

   184

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   185

#define MAX_ETH_FRAME_SIZE	1536

   186

   187

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   188

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   189

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   190

   191

/* PCI Tuning Parameters

   192

   Threshold is bytes transferred to chip before transmission starts. */

   193

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   194

   195

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   196

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   197

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   198

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   199

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   200

   201

/* Operational parameters that usually are not changed. */

   202

/* Time in jiffies before concluding the transmitter is hung. */

   203

#define TX_TIMEOUT  (6*HZ)

   204

   205

   206

enum {

   207

	HAS_MII_XCVR = 0x010000,

   208

	HAS_CHIP_XCVR = 0x020000,

   209

	HAS_LNK_CHNG = 0x040000,

   210

};

   211

   212

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   213

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   214

#define RTL_MIN_IO_SIZE 0x80

   215

#define RTL8139B_IO_SIZE 256

   216

   217

#define RTL8129_CAPS	HAS_MII_XCVR

   218

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   219

   220

typedef enum {

   221

	RTL8139 = 0,

   222

	RTL8129,

   223

} board_t;

   224

   225

   226

/* indexed by board_t, above */

   227

static const struct {

   228

	const char *name;

   229

	u32 hw_flags;

   230

} board_info[] __devinitdata = {

   231

	{ "RealTek RTL8139", RTL8139_CAPS },

   232

	{ "RealTek RTL8129", RTL8129_CAPS },

   233

};

   234

   235

   236

static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   237

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   238

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   239

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   240

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   241

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   242

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   243

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   244

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   245

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   246

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   247

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   248

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   249

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   250

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   251

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   252

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   253

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   254

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   256

   257

#ifdef CONFIG_SH_SECUREEDGE5410

   258

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   259

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   260

#endif

   261

#ifdef CONFIG_8139TOO_8129

   262

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   263

#endif

   264

   265

	/* some crazy cards report invalid vendor ids like

   266

	 * 0x0001 here.  The other ids are valid and constant,

   267

	 * so we simply don't match on the main vendor id.

   268

	 */

   269

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   270

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   271

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   272

   273

	{0,}

   274

};

   275

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   276

   277

static struct {

   278

	const char str[ETH_GSTRING_LEN];

   279

} ethtool_stats_keys[] = {

   280

	{ "early_rx" },

   281

	{ "tx_buf_mapped" },

   282

	{ "tx_timeouts" },

   283

	{ "rx_lost_in_ring" },

   284

};

   285

   286

/* The rest of these values should never change. */

   287

   288

/* Symbolic offsets to registers. */

   289

enum RTL8139_registers {

   290

	MAC0		= 0,	 /* Ethernet hardware address. */

   291

	MAR0		= 8,	 /* Multicast filter. */

   292

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   293

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   294

	RxBuf		= 0x30,

   295

	ChipCmd		= 0x37,

   296

	RxBufPtr	= 0x38,

   297

	RxBufAddr	= 0x3A,

   298

	IntrMask	= 0x3C,

   299

	IntrStatus	= 0x3E,

   300

	TxConfig	= 0x40,

   301

	RxConfig	= 0x44,

   302

	Timer		= 0x48,	 /* A general-purpose counter. */

   303

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   304

	Cfg9346		= 0x50,

   305

	Config0		= 0x51,

   306

	Config1		= 0x52,

   307

	TimerInt	= 0x54,

   308

	MediaStatus	= 0x58,

   309

	Config3		= 0x59,

   310

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   311

	HltClk		= 0x5B,

   312

	MultiIntr	= 0x5C,

   313

	TxSummary	= 0x60,

   314

	BasicModeCtrl	= 0x62,

   315

	BasicModeStatus	= 0x64,

   316

	NWayAdvert	= 0x66,

   317

	NWayLPAR	= 0x68,

   318

	NWayExpansion	= 0x6A,

   319

	/* Undocumented registers, but required for proper operation. */

   320

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   321

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   322

	PARA78		= 0x78,

   323

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   324

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   325

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   326

};

   327

   328

enum ClearBitMasks {

   329

	MultiIntrClear	= 0xF000,

   330

	ChipCmdClear	= 0xE2,

   331

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   332

};

   333

   334

enum ChipCmdBits {

   335

	CmdReset	= 0x10,

   336

	CmdRxEnb	= 0x08,

   337

	CmdTxEnb	= 0x04,

   338

	RxBufEmpty	= 0x01,

   339

};

   340

   341

/* Interrupt register bits, using my own meaningful names. */

   342

enum IntrStatusBits {

   343

	PCIErr		= 0x8000,

   344

	PCSTimeout	= 0x4000,

   345

	RxFIFOOver	= 0x40,

   346

	RxUnderrun	= 0x20,

   347

	RxOverflow	= 0x10,

   348

	TxErr		= 0x08,

   349

	TxOK		= 0x04,

   350

	RxErr		= 0x02,

   351

	RxOK		= 0x01,

   352

   353

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   354

};

   355

   356

enum TxStatusBits {

   357

	TxHostOwns	= 0x2000,

   358

	TxUnderrun	= 0x4000,

   359

	TxStatOK	= 0x8000,

   360

	TxOutOfWindow	= 0x20000000,

   361

	TxAborted	= 0x40000000,

   362

	TxCarrierLost	= 0x80000000,

   363

};

   364

enum RxStatusBits {

   365

	RxMulticast	= 0x8000,

   366

	RxPhysical	= 0x4000,

   367

	RxBroadcast	= 0x2000,

   368

	RxBadSymbol	= 0x0020,

   369

	RxRunt		= 0x0010,

   370

	RxTooLong	= 0x0008,

   371

	RxCRCErr	= 0x0004,

   372

	RxBadAlign	= 0x0002,

   373

	RxStatusOK	= 0x0001,

   374

};

   375

   376

/* Bits in RxConfig. */

   377

enum rx_mode_bits {

   378

	AcceptErr	= 0x20,

   379

	AcceptRunt	= 0x10,

   380

	AcceptBroadcast	= 0x08,

   381

	AcceptMulticast	= 0x04,

   382

	AcceptMyPhys	= 0x02,

   383

	AcceptAllPhys	= 0x01,

   384

};

   385

   386

/* Bits in TxConfig. */

   387

enum tx_config_bits {

   388

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   389

        TxIFGShift	= 24,

   390

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   391

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   392

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   393

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   394

   395

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   396

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   397

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   398

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   399

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   400

   401

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   402

};

   403

   404

/* Bits in Config1 */

   405

enum Config1Bits {

   406

	Cfg1_PM_Enable	= 0x01,

   407

	Cfg1_VPD_Enable	= 0x02,

   408

	Cfg1_PIO	= 0x04,

   409

	Cfg1_MMIO	= 0x08,

   410

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   411

	Cfg1_Driver_Load = 0x20,

   412

	Cfg1_LED0	= 0x40,

   413

	Cfg1_LED1	= 0x80,

   414

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   415

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   416

};

   417

   418

/* Bits in Config3 */

   419

enum Config3Bits {

   420

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   421

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   422

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   423

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   424

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   425

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   426

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   427

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   428

};

   429

   430

/* Bits in Config4 */

   431

enum Config4Bits {

   432

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   433

};

   434

   435

/* Bits in Config5 */

   436

enum Config5Bits {

   437

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   438

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   439

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   440

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   441

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   442

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   443

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   444

};

   445

   446

enum RxConfigBits {

   447

	/* rx fifo threshold */

   448

	RxCfgFIFOShift	= 13,

   449

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   450

   451

	/* Max DMA burst */

   452

	RxCfgDMAShift	= 8,

   453

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   454

   455

	/* rx ring buffer length */

   456

	RxCfgRcv8K	= 0,

   457

	RxCfgRcv16K	= (1 << 11),

   458

	RxCfgRcv32K	= (1 << 12),

   459

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   460

   461

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   462

	RxNoWrap	= (1 << 7),

   463

};

   464

   465

/* Twister tuning parameters from RealTek.

   466

   Completely undocumented, but required to tune bad links on some boards. */

   467

enum CSCRBits {

   468

	CSCR_LinkOKBit		= 0x0400,

   469

	CSCR_LinkChangeBit	= 0x0800,

   470

	CSCR_LinkStatusBits	= 0x0f000,

   471

	CSCR_LinkDownOffCmd	= 0x003c0,

   472

	CSCR_LinkDownCmd	= 0x0f3c0,

   473

};

   474

   475

enum Cfg9346Bits {

   476

	Cfg9346_Lock	= 0x00,

   477

	Cfg9346_Unlock	= 0xC0,

   478

};

   479

   480

typedef enum {

   481

	CH_8139	= 0,

   482

	CH_8139_K,

   483

	CH_8139A,

   484

	CH_8139A_G,

   485

	CH_8139B,

   486

	CH_8130,

   487

	CH_8139C,

   488

	CH_8100,

   489

	CH_8100B_8139D,

   490

	CH_8101,

   491

} chip_t;

   492

   493

enum chip_flags {

   494

	HasHltClk	= (1 << 0),

   495

	HasLWake	= (1 << 1),

   496

};

   497

   498

#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   499

	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   500

#define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   501

   502

/* directly indexed by chip_t, above */

   503

static const struct {

   504

	const char *name;

   505

	u32 version; /* from RTL8139C/RTL8139D docs */

   506

	u32 flags;

   507

} rtl_chip_info[] = {

   508

	{ "RTL-8139",

   509

	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   510

	  HasHltClk,

   511

	},

   512

   513

	{ "RTL-8139 rev K",

   514

	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   515

	  HasHltClk,

   516

	},

   517

   518

	{ "RTL-8139A",

   519

	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   520

	  HasHltClk, /* XXX undocumented? */

   521

	},

   522

   523

	{ "RTL-8139A rev G",

   524

	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   525

	  HasHltClk, /* XXX undocumented? */

   526

	},

   527

   528

	{ "RTL-8139B",

   529

	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   530

	  HasLWake,