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/******************************************************************************

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 *

     3

 *  $Id$

     4

 *

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 *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

    22

 *  ---

    23

 *

    24

 *  The license mentioned above concerns the source code only. Using the

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 *  EtherCAT technology and brand is only permitted in compliance with the

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 *  industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/**

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   \file

    32

   EtherCAT driver for RTL8139-compatible NICs.

    33

*/

    34

    35

/*****************************************************************************/

    36

    37

/*

    38

  Former documentation:

    39

    40

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41

    42

	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43

	Copyright 2000-2002 Jeff Garzik

    44

    45

	Much code comes from Donald Becker's rtl8139.c driver,

    46

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48

    49

	-----<snip>-----

    50

    51

        	Written 1997-2001 by Donald Becker.

    52

		This software may be used and distributed according to the

    53

		terms of the GNU General Public License (GPL), incorporated

    54

		herein by reference.  Drivers based on or derived from this

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		code fall under the GPL and must retain the authorship,

    56

		copyright and license notice.  This file is not a complete

    57

		program and may only be used when the entire operating

    58

		system is licensed under the GPL.

    59

    60

		This driver is for boards based on the RTL8129 and RTL8139

    61

		PCI ethernet chips.

    62

    63

		The author may be reached as becker@scyld.com, or C/O Scyld

    64

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65

		MD 21403

    66

    67

		Support and updates available at

    68

		http://www.scyld.com/network/rtl8139.html

    69

    70

		Twister-tuning table provided by Kinston

    71

		<shangh@realtek.com.tw>.

    72

    73

	-----<snip>-----

    74

    75

	This software may be used and distributed according to the terms

    76

	of the GNU General Public License, incorporated herein by reference.

    77

    78

	Contributors:

    79

    80

		Donald Becker - he wrote the original driver, kudos to him!

    81

		(but please don't e-mail him for support, this isn't his driver)

    82

    83

		Tigran Aivazian - bug fixes, skbuff free cleanup

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    85

		Martin Mares - suggestions for PCI cleanup

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		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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    91

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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    94

		Gerard Sharp - bug fix, testing and feedback

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    96

		David Ford - Rx ring wrap fix

    97

    98

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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   101

		Donald Becker/Chris Butterworth/Marcus Westergren -

   102

		Noticed various Rx packet size-related buglets.

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   104

		Santiago Garcia Mantinan - testing and feedback

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   106

		Jens David - 2.2.x kernel backports

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   108

		Martin Dennett - incredibly helpful insight on undocumented

   109

		features of the 8139 chips

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   111

		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

   121

   122

	Submitting bug reports:

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   124

		"rtl8139-diag -mmmaaavvveefN" output

   125

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

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   127

*/

   128

   129

#define DRV_NAME	"ec_8139too"

   130

#define DRV_VERSION	"0.9.28"

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   132

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

   137

#include <linux/init.h>

   138

#include <linux/netdevice.h>

   139

#include <linux/etherdevice.h>

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#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <linux/io.h>

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#include <linux/uaccess.h>

   148

#include <asm/irq.h>

   149

   150

#include "../globals.h"

   151

#include "ecdev.h"

   152

   153

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

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   157

#define PFX DRV_NAME ": "

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   159

/* Default Message level */

   160

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   161

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   163

   164

   165

/* define to 1, 2 or 3 to enable copious debugging info */

   166

#define RTL8139_DEBUG 0

   167

   168

/* define to 1 to disable lightweight runtime debugging checks */

   169

#undef RTL8139_NDEBUG

   170

   171

   172

#ifdef RTL8139_NDEBUG

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#  define assert(expr) do {} while (0)

   174

#else

   175

#  define assert(expr) \

   176

        if(unlikely(!(expr))) {				        \

   177

        pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   178

	#expr, __FILE__, __func__, __LINE__);			\

   179

        }

   180

#endif

   181

   182

   183

/* A few user-configurable values. */

   184

/* media options */

   185

#define MAX_UNITS 8

   186

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   187

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   188

   189

/* Whether to use MMIO or PIO. Default to MMIO. */

   190

#ifdef CONFIG_8139TOO_PIO

   191

static int use_io = 1;

   192

#else

   193

static int use_io = 0;

   194

#endif

   195

   196

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   197

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   198

static int multicast_filter_limit = 32;

   199

   200

/* bitmapped message enable number */

   201

static int debug = -1;

   202

   203

/*

   204

 * Receive ring size

   205

 * Warning: 64K ring has hardware issues and may lock up.

   206

 */

   207

#if defined(CONFIG_SH_DREAMCAST)

   208

#define RX_BUF_IDX 0	/* 8K ring */

   209

#else

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#define RX_BUF_IDX	2	/* 32K ring */

   211

#endif

   212

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   213

#define RX_BUF_PAD	16

   214

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

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   216

#if RX_BUF_LEN == 65536

   217

#define RX_BUF_TOT_LEN	RX_BUF_LEN

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#else

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#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   220

#endif

   221

   222

/* Number of Tx descriptor registers. */

   223

#define NUM_TX_DESC	4

   224

   225

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   226

#define MAX_ETH_FRAME_SIZE	1536

   227

   228

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   229

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   230

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   231

   232

/* PCI Tuning Parameters

   233

   Threshold is bytes transferred to chip before transmission starts. */

   234

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   235

   236

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   237

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   238

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   239

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   240

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   241

   242

/* Operational parameters that usually are not changed. */

   243

/* Time in jiffies before concluding the transmitter is hung. */

   244

#define TX_TIMEOUT  (6*HZ)

   245

   246

   247

enum {

   248

	HAS_MII_XCVR = 0x010000,

   249

	HAS_CHIP_XCVR = 0x020000,

   250

	HAS_LNK_CHNG = 0x040000,

   251

};

   252

   253

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   254

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   255

#define RTL_MIN_IO_SIZE 0x80

   256

#define RTL8139B_IO_SIZE 256

   257

   258

#define RTL8129_CAPS	HAS_MII_XCVR

   259

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   260

   261

typedef enum {

   262

	RTL8139 = 0,

   263

	RTL8129,

   264

} board_t;

   265

   266

   267

/* indexed by board_t, above */

   268

static const struct {

   269

	const char *name;

   270

	u32 hw_flags;

   271

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

   273

	{ "RealTek RTL8129", RTL8129_CAPS },

   274

};

   275

   276

   277

static struct pci_device_id rtl8139_pci_tbl[] = {

   278

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   282

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

   298

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   300

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   304

#endif

   305

   306

	/* some crazy cards report invalid vendor ids like

   307

	 * 0x0001 here.  The other ids are valid and constant,

   308

	 * so we simply don't match on the main vendor id.

   309

	 */

   310

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   312

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   313

   314

	{0,}

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};

   316

   317

/* prevent driver from being loaded automatically */

   318

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   319

   320

static struct {

   321

	const char str[ETH_GSTRING_LEN];

   322

} ethtool_stats_keys[] = {

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	{ "early_rx" },

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	{ "tx_buf_mapped" },

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	{ "tx_timeouts" },

   326

	{ "rx_lost_in_ring" },

   327

};

   328

   329

/* The rest of these values should never change. */

   330

   331

/* Symbolic offsets to registers. */

   332

enum RTL8139_registers {

   333

	MAC0		= 0,	 /* Ethernet hardware address. */

   334

	MAR0		= 8,	 /* Multicast filter. */

   335

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   336

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   337

	RxBuf		= 0x30,

   338

	ChipCmd		= 0x37,

   339

	RxBufPtr	= 0x38,

   340

	RxBufAddr	= 0x3A,

   341

	IntrMask	= 0x3C,

   342

	IntrStatus	= 0x3E,

   343

	TxConfig	= 0x40,

   344

	RxConfig	= 0x44,

   345

	Timer		= 0x48,	 /* A general-purpose counter. */

   346

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   347

	Cfg9346		= 0x50,

   348

	Config0		= 0x51,

   349

	Config1		= 0x52,

   350

	TimerInt	= 0x54,

   351

	MediaStatus	= 0x58,

   352

	Config3		= 0x59,

   353

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   354

	HltClk		= 0x5B,

   355

	MultiIntr	= 0x5C,

   356

	TxSummary	= 0x60,

   357

	BasicModeCtrl	= 0x62,

   358

	BasicModeStatus	= 0x64,

   359

	NWayAdvert	= 0x66,

   360

	NWayLPAR	= 0x68,

   361

	NWayExpansion	= 0x6A,

   362

	/* Undocumented registers, but required for proper operation. */

   363

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   364

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   365

	PARA78		= 0x78,

   366

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   367

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   368

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   369

};

   370

   371

enum ClearBitMasks {

   372

	MultiIntrClear	= 0xF000,

   373

	ChipCmdClear	= 0xE2,

   374

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

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};

   376

   377

enum ChipCmdBits {

   378

	CmdReset	= 0x10,

   379

	CmdRxEnb	= 0x08,

   380

	CmdTxEnb	= 0x04,

   381

	RxBufEmpty	= 0x01,

   382

};

   383

   384

/* Interrupt register bits, using my own meaningful names. */

   385

enum IntrStatusBits {

   386

	PCIErr		= 0x8000,

   387

	PCSTimeout	= 0x4000,

   388

	RxFIFOOver	= 0x40,

   389

	RxUnderrun	= 0x20,

   390

	RxOverflow	= 0x10,

   391

	TxErr		= 0x08,

   392

	TxOK		= 0x04,

   393

	RxErr		= 0x02,

   394

	RxOK		= 0x01,

   395

   396

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   397

};

   398

   399

enum TxStatusBits {

   400

	TxHostOwns	= 0x2000,

   401

	TxUnderrun	= 0x4000,

   402

	TxStatOK	= 0x8000,

   403

	TxOutOfWindow	= 0x20000000,

   404

	TxAborted	= 0x40000000,

   405

	TxCarrierLost	= 0x80000000,

   406

};

   407

enum RxStatusBits {

   408

	RxMulticast	= 0x8000,

   409

	RxPhysical	= 0x4000,

   410

	RxBroadcast	= 0x2000,

   411

	RxBadSymbol	= 0x0020,

   412

	RxRunt		= 0x0010,

   413

	RxTooLong	= 0x0008,

   414

	RxCRCErr	= 0x0004,

   415

	RxBadAlign	= 0x0002,

   416

	RxStatusOK	= 0x0001,

   417

};

   418

   419

/* Bits in RxConfig. */

   420

enum rx_mode_bits {

   421

	AcceptErr	= 0x20,

   422

	AcceptRunt	= 0x10,

   423

	AcceptBroadcast	= 0x08,

   424

	AcceptMulticast	= 0x04,

   425

	AcceptMyPhys	= 0x02,

   426

	AcceptAllPhys	= 0x01,

   427

};

   428

   429

/* Bits in TxConfig. */

   430

enum tx_config_bits {

   431

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   432

        TxIFGShift	= 24,

   433

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   434

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   435

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   436

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   437

   438

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   439

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   440

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   441

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   442

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   443

   444

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   445

};

   446

   447

/* Bits in Config1 */

   448

enum Config1Bits {

   449

	Cfg1_PM_Enable	= 0x01,

   450

	Cfg1_VPD_Enable	= 0x02,

   451

	Cfg1_PIO	= 0x04,

   452

	Cfg1_MMIO	= 0x08,

   453

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   454

	Cfg1_Driver_Load = 0x20,

   455

	Cfg1_LED0	= 0x40,

   456

	Cfg1_LED1	= 0x80,

   457

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   458

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   459

};

   460

   461

/* Bits in Config3 */

   462

enum Config3Bits {

   463

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   464

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   465

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   466

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   467

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   468

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   469

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   470

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   471

};

   472

   473

/* Bits in Config4 */

   474

enum Config4Bits {

   475

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   476

};

   477

   478

/* Bits in Config5 */

   479

enum Config5Bits {

   480

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   481

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   482

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   483

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   484

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   485

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   486

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   487

};

   488

   489

enum RxConfigBits {

   490

	/* rx fifo threshold */

   491

	RxCfgFIFOShift	= 13,

   492

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   493

   494

	/* Max DMA burst */

   495

	RxCfgDMAShift	= 8,

   496

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   497

   498

	/* rx ring buffer length */

   499

	RxCfgRcv8K	= 0,

   500

	RxCfgRcv16K	= (1 << 11),

   501

	RxCfgRcv32K	= (1 << 12),

   502

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   503

   504

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   505

	RxNoWrap	= (1 << 7),

   506

};

   507

   508

/* Twister tuning parameters from RealTek.

   509

   Completely undocumented, but required to tune bad links on some boards. */

   510

enum CSCRBits {

   511

	CSCR_LinkOKBit		= 0x0400,

   512

	CSCR_LinkChangeBit	= 0x0800,

   513

	CSCR_LinkStatusBits	= 0x0f000,

   514

	CSCR_LinkDownOffCmd	= 0x003c0,

   515

	CSCR_LinkDownCmd	= 0x0f3c0,

   516

};

   517

   518

enum Cfg9346Bits {

   519

	Cfg9346_Lock	= 0x00,

   520

	Cfg9346_Unlock	= 0xC0,

   521

};

   522

   523

typedef enum {

   524

	CH_8139	= 0,

   525

	CH_8139_K,

   526

	CH_8139A,

   527

	CH_8139A_G,

   528

	CH_8139B,

   529

	CH_8130,