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/******************************************************************************

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 *

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 *  $Id$

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 *

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 *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

    22

 *  ---

    23

 *

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 *  The license mentioned above concerns the source code only. Using the

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 *  EtherCAT technology and brand is only permitted in compliance with the

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 *  industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/**

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   \file

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   EtherCAT driver for RTL8139-compatible NICs.

    33

*/

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/*****************************************************************************/

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    37

/*

    38

  Former documentation:

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    40

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41

    42

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    44

    45

	Much code comes from Donald Becker's rtl8139.c driver,

    46

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48

    49

	-----<snip>-----

    50

    51

        	Written 1997-2001 by Donald Becker.

    52

		This software may be used and distributed according to the

    53

		terms of the GNU General Public License (GPL), incorporated

    54

		herein by reference.  Drivers based on or derived from this

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		code fall under the GPL and must retain the authorship,

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		copyright and license notice.  This file is not a complete

    57

		program and may only be used when the entire operating

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		system is licensed under the GPL.

    59

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		This driver is for boards based on the RTL8129 and RTL8139

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		PCI ethernet chips.

    62

    63

		The author may be reached as becker@scyld.com, or C/O Scyld

    64

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65

		MD 21403

    66

    67

		Support and updates available at

    68

		http://www.scyld.com/network/rtl8139.html

    69

    70

		Twister-tuning table provided by Kinston

    71

		<shangh@realtek.com.tw>.

    72

    73

	-----<snip>-----

    74

    75

	This software may be used and distributed according to the terms

    76

	of the GNU General Public License, incorporated herein by reference.

    77

    78

	Contributors:

    79

    80

		Donald Becker - he wrote the original driver, kudos to him!

    81

		(but please don't e-mail him for support, this isn't his driver)

    82

    83

		Tigran Aivazian - bug fixes, skbuff free cleanup

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		Martin Mares - suggestions for PCI cleanup

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		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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		Gerard Sharp - bug fix, testing and feedback

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    96

		David Ford - Rx ring wrap fix

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    98

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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		Donald Becker/Chris Butterworth/Marcus Westergren -

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		Noticed various Rx packet size-related buglets.

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   104

		Santiago Garcia Mantinan - testing and feedback

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		Jens David - 2.2.x kernel backports

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   108

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

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   111

		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

   121

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	Submitting bug reports:

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   124

		"rtl8139-diag -mmmaaavvveefN" output

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		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

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   127

*/

   128

   129

#define DRV_NAME	"ec_8139too"

   130

#define DRV_VERSION	"0.9.28"

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

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#include <linux/init.h>

   138

#include <linux/netdevice.h>

   139

#include <linux/etherdevice.h>

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#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <linux/io.h>

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#include <linux/uaccess.h>

   148

#include <asm/irq.h>

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   150

#include "../globals.h"

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#include "ecdev.h"

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   153

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

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   157

#define PFX DRV_NAME ": "

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   159

/* Default Message level */

   160

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   161

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   163

   164

   165

/* define to 1, 2 or 3 to enable copious debugging info */

   166

#define RTL8139_DEBUG 0

   167

   168

/* define to 1 to disable lightweight runtime debugging checks */

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#undef RTL8139_NDEBUG

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   171

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#if RTL8139_DEBUG

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/* note: prints function name for you */

   174

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)

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#else

   176

#  define DPRINTK(fmt, args...)

   177

#endif

   178

   179

#ifdef RTL8139_NDEBUG

   180

#  define assert(expr) do {} while (0)

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#else

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#  define assert(expr) \

   183

        if(unlikely(!(expr))) {				        \

   184

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   185

	#expr, __FILE__, __func__, __LINE__);			\

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        }

   187

#endif

   188

   189

   190

/* A few user-configurable values. */

   191

/* media options */

   192

#define MAX_UNITS 8

   193

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   194

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   195

   196

/* Whether to use MMIO or PIO. Default to MMIO. */

   197

#ifdef CONFIG_8139TOO_PIO

   198

static int use_io = 1;

   199

#else

   200

static int use_io = 0;

   201

#endif

   202

   203

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

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   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   205

static int multicast_filter_limit = 32;

   206

   207

/* bitmapped message enable number */

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static int debug = -1;

   209

   210

/*

   211

 * Receive ring size

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 * Warning: 64K ring has hardware issues and may lock up.

   213

 */

   214

#if defined(CONFIG_SH_DREAMCAST)

   215

#define RX_BUF_IDX 0	/* 8K ring */

   216

#else

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#define RX_BUF_IDX	2	/* 32K ring */

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#endif

   219

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   220

#define RX_BUF_PAD	16

   221

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   222

   223

#if RX_BUF_LEN == 65536

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#define RX_BUF_TOT_LEN	RX_BUF_LEN

   225

#else

   226

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   227

#endif

   228

   229

/* Number of Tx descriptor registers. */

   230

#define NUM_TX_DESC	4

   231

   232

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   233

#define MAX_ETH_FRAME_SIZE	1536

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   235

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   236

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   237

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   238

   239

/* PCI Tuning Parameters

   240

   Threshold is bytes transferred to chip before transmission starts. */

   241

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   242

   243

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   244

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   245

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   246

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   247

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   248

   249

/* Operational parameters that usually are not changed. */

   250

/* Time in jiffies before concluding the transmitter is hung. */

   251

#define TX_TIMEOUT  (6*HZ)

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   253

   254

enum {

   255

	HAS_MII_XCVR = 0x010000,

   256

	HAS_CHIP_XCVR = 0x020000,

   257

	HAS_LNK_CHNG = 0x040000,

   258

};

   259

   260

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   261

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   262

#define RTL_MIN_IO_SIZE 0x80

   263

#define RTL8139B_IO_SIZE 256

   264

   265

#define RTL8129_CAPS	HAS_MII_XCVR

   266

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   267

   268

typedef enum {

   269

	RTL8139 = 0,

   270

	RTL8129,

   271

} board_t;

   272

   273

   274

/* indexed by board_t, above */

   275

static const struct {

   276

	const char *name;

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	u32 hw_flags;

   278

} board_info[] __devinitdata = {

   279

	{ "RealTek RTL8139", RTL8139_CAPS },

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	{ "RealTek RTL8129", RTL8129_CAPS },

   281

};

   282

   283

   284

static struct pci_device_id rtl8139_pci_tbl[] = {

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	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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   305

#ifdef CONFIG_SH_SECUREEDGE5410

   306

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308

#endif

   309

#ifdef CONFIG_8139TOO_8129

   310

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   311

#endif

   312

   313

	/* some crazy cards report invalid vendor ids like

   314

	 * 0x0001 here.  The other ids are valid and constant,

   315

	 * so we simply don't match on the main vendor id.

   316

	 */

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	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   319

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   320

   321

	{0,}

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};

   323

   324

/* prevent driver from being loaded automatically */

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//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   326

   327

static struct {

   328

	const char str[ETH_GSTRING_LEN];

   329

} ethtool_stats_keys[] = {

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	{ "early_rx" },

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	{ "tx_buf_mapped" },

   332

	{ "tx_timeouts" },

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	{ "rx_lost_in_ring" },

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};

   335

   336

/* The rest of these values should never change. */

   337

   338

/* Symbolic offsets to registers. */

   339

enum RTL8139_registers {

   340

	MAC0		= 0,	 /* Ethernet hardware address. */

   341

	MAR0		= 8,	 /* Multicast filter. */

   342

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   343

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   344

	RxBuf		= 0x30,

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	ChipCmd		= 0x37,

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	RxBufPtr	= 0x38,

   347

	RxBufAddr	= 0x3A,

   348

	IntrMask	= 0x3C,

   349

	IntrStatus	= 0x3E,

   350

	TxConfig	= 0x40,

   351

	RxConfig	= 0x44,

   352

	Timer		= 0x48,	 /* A general-purpose counter. */

   353

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   354

	Cfg9346		= 0x50,

   355

	Config0		= 0x51,

   356

	Config1		= 0x52,

   357

	TimerInt	= 0x54,

   358

	MediaStatus	= 0x58,

   359

	Config3		= 0x59,

   360

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   361

	HltClk		= 0x5B,

   362

	MultiIntr	= 0x5C,

   363

	TxSummary	= 0x60,

   364

	BasicModeCtrl	= 0x62,

   365

	BasicModeStatus	= 0x64,

   366

	NWayAdvert	= 0x66,

   367

	NWayLPAR	= 0x68,

   368

	NWayExpansion	= 0x6A,

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	/* Undocumented registers, but required for proper operation. */

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	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   371

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   372

	PARA78		= 0x78,

   373

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   374

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   375

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   376

};

   377

   378

enum ClearBitMasks {

   379

	MultiIntrClear	= 0xF000,

   380

	ChipCmdClear	= 0xE2,

   381

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   382

};

   383

   384

enum ChipCmdBits {

   385

	CmdReset	= 0x10,

   386

	CmdRxEnb	= 0x08,

   387

	CmdTxEnb	= 0x04,

   388

	RxBufEmpty	= 0x01,

   389

};

   390

   391

/* Interrupt register bits, using my own meaningful names. */

   392

enum IntrStatusBits {

   393

	PCIErr		= 0x8000,

   394

	PCSTimeout	= 0x4000,

   395

	RxFIFOOver	= 0x40,

   396

	RxUnderrun	= 0x20,

   397

	RxOverflow	= 0x10,

   398

	TxErr		= 0x08,

   399

	TxOK		= 0x04,

   400

	RxErr		= 0x02,

   401

	RxOK		= 0x01,

   402

   403

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   404

};

   405

   406

enum TxStatusBits {

   407

	TxHostOwns	= 0x2000,

   408

	TxUnderrun	= 0x4000,

   409

	TxStatOK	= 0x8000,

   410

	TxOutOfWindow	= 0x20000000,

   411

	TxAborted	= 0x40000000,

   412

	TxCarrierLost	= 0x80000000,

   413

};

   414

enum RxStatusBits {

   415

	RxMulticast	= 0x8000,

   416

	RxPhysical	= 0x4000,

   417

	RxBroadcast	= 0x2000,

   418

	RxBadSymbol	= 0x0020,

   419

	RxRunt		= 0x0010,

   420

	RxTooLong	= 0x0008,

   421

	RxCRCErr	= 0x0004,

   422

	RxBadAlign	= 0x0002,

   423

	RxStatusOK	= 0x0001,

   424

};

   425

   426

/* Bits in RxConfig. */

   427

enum rx_mode_bits {

   428

	AcceptErr	= 0x20,

   429

	AcceptRunt	= 0x10,

   430

	AcceptBroadcast	= 0x08,

   431

	AcceptMulticast	= 0x04,

   432

	AcceptMyPhys	= 0x02,

   433

	AcceptAllPhys	= 0x01,

   434

};

   435

   436

/* Bits in TxConfig. */

   437

enum tx_config_bits {

   438

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   439

        TxIFGShift	= 24,

   440

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   441

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   442

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   443

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   444

   445

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   446

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   447

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   448

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   449

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   450

   451

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   452

};

   453

   454

/* Bits in Config1 */

   455

enum Config1Bits {

   456

	Cfg1_PM_Enable	= 0x01,

   457

	Cfg1_VPD_Enable	= 0x02,

   458

	Cfg1_PIO	= 0x04,

   459

	Cfg1_MMIO	= 0x08,

   460

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   461

	Cfg1_Driver_Load = 0x20,

   462

	Cfg1_LED0	= 0x40,

   463

	Cfg1_LED1	= 0x80,

   464

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   465

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   466

};

   467

   468

/* Bits in Config3 */

   469

enum Config3Bits {

   470

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   471

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   472

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   473

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   474

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   475

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   476

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   477

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   478

};

   479

   480

/* Bits in Config4 */

   481

enum Config4Bits {

   482

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   483

};

   484

   485

/* Bits in Config5 */

   486

enum Config5Bits {

   487

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   488

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   489

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   490

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   491

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   492

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   493

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   494

};

   495

   496

enum RxConfigBits {

   497

	/* rx fifo threshold */

   498

	RxCfgFIFOShift	= 13,

   499

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   500

   501

	/* Max DMA burst */

   502

	RxCfgDMAShift	= 8,

   503

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   504

   505

	/* rx ring buffer length */

   506

	RxCfgRcv8K	= 0,

   507

	RxCfgRcv16K	= (1 << 11),

   508

	RxCfgRcv32K	= (1 << 12),

   509

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   510

   511

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   512

	RxNoWrap	= (1 << 7),

   513

};

   514

   515

/* Twister tuning parameters from RealTek.

   516

   Completely undocumented, but required to tune bad links on some boards. */

   517

enum CSCRBits {

   518

	CSCR_LinkOKBit		= 0x0400,

   519

	CSCR_LinkChangeBit	= 0x0800,

   520

	CSCR_LinkStatusBits	= 0x0f000,

   521

	CSCR_LinkDownOffCmd	= 0x003c0,

   522

	CSCR_LinkDownCmd	= 0x0f3c0,

   523

};

   524

   525

enum Cfg9346Bits {

   526

	Cfg9346_Lock	= 0x00,

   527

	Cfg9346_Unlock	= 0xC0,

   528

};

   529