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/* Intel PRO/1000 Linux driver

     2

 * Copyright(c) 1999 - 2014 Intel Corporation.

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 *

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 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

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 * The full GNU General Public License is included in this distribution in

    14

 * the file called "COPYING".

    15

 *

    16

 * Contact Information:

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 * Linux NICS <linux.nics@intel.com>

    18

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    19

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    20

 */

    21

    22

#ifndef _E1000_HW_H_

    23

#define _E1000_HW_H_

    24

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#include "regs.h"

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#include "defines.h"

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    28

struct e1000_hw;

    29

    30

#define E1000_DEV_ID_82571EB_COPPER		0x105E

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#define E1000_DEV_ID_82571EB_FIBER		0x105F

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#define E1000_DEV_ID_82571EB_SERDES		0x1060

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#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4

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#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5

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#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5

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#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC

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#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9

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#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA

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#define E1000_DEV_ID_82572EI_COPPER		0x107D

    40

#define E1000_DEV_ID_82572EI_FIBER		0x107E

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#define E1000_DEV_ID_82572EI_SERDES		0x107F

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#define E1000_DEV_ID_82572EI			0x10B9

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#define E1000_DEV_ID_82573E			0x108B

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#define E1000_DEV_ID_82573E_IAMT		0x108C

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#define E1000_DEV_ID_82573L			0x109A

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#define E1000_DEV_ID_82574L			0x10D3

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#define E1000_DEV_ID_82574LA			0x10F6

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#define E1000_DEV_ID_82583V			0x150C

    49

#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096

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#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098

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#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA

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#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB

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#define E1000_DEV_ID_ICH8_82567V_3		0x1501

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#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049

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#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A

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#define E1000_DEV_ID_ICH8_IGP_C			0x104B

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#define E1000_DEV_ID_ICH8_IFE			0x104C

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#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4

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#define E1000_DEV_ID_ICH8_IFE_G			0x10C5

    60

#define E1000_DEV_ID_ICH8_IGP_M			0x104D

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#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD

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#define E1000_DEV_ID_ICH9_BM			0x10E5

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#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5

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#define E1000_DEV_ID_ICH9_IGP_M			0x10BF

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#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB

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#define E1000_DEV_ID_ICH9_IGP_C			0x294C

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#define E1000_DEV_ID_ICH9_IFE			0x10C0

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#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3

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#define E1000_DEV_ID_ICH9_IFE_G			0x10C2

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#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC

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#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD

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#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE

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#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE

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#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF

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#define E1000_DEV_ID_ICH10_D_BM_V		0x1525

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#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA

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#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB

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#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF

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#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0

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#define E1000_DEV_ID_PCH2_LV_LM			0x1502

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#define E1000_DEV_ID_PCH2_LV_V			0x1503

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#define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A

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#define E1000_DEV_ID_PCH_LPT_I217_V		0x153B

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#define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A

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#define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559

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#define E1000_DEV_ID_PCH_I218_LM2		0x15A0

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#define E1000_DEV_ID_PCH_I218_V2		0x15A1

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#define E1000_DEV_ID_PCH_I218_LM3		0x15A2	/* Wildcat Point PCH */

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#define E1000_DEV_ID_PCH_I218_V3		0x15A3	/* Wildcat Point PCH */

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    91

#define E1000_REVISION_4	4

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    93

#define E1000_FUNC_1		1

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    95

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0

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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3

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    98

enum e1000_mac_type {

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	e1000_82571,

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	e1000_82572,

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	e1000_82573,

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	e1000_82574,

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	e1000_82583,

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	e1000_80003es2lan,

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	e1000_ich8lan,

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	e1000_ich9lan,

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	e1000_ich10lan,

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	e1000_pchlan,

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	e1000_pch2lan,

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	e1000_pch_lpt,

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};

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   113

enum e1000_media_type {

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	e1000_media_type_unknown = 0,

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	e1000_media_type_copper = 1,

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	e1000_media_type_fiber = 2,

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	e1000_media_type_internal_serdes = 3,

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	e1000_num_media_types

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};

   120

   121

enum e1000_nvm_type {

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	e1000_nvm_unknown = 0,

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	e1000_nvm_none,

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	e1000_nvm_eeprom_spi,

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	e1000_nvm_flash_hw,

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	e1000_nvm_flash_sw

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};

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   129

enum e1000_nvm_override {

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	e1000_nvm_override_none = 0,

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	e1000_nvm_override_spi_small,

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	e1000_nvm_override_spi_large

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};

   134

   135

enum e1000_phy_type {

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	e1000_phy_unknown = 0,

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	e1000_phy_none,

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	e1000_phy_m88,

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	e1000_phy_igp,

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	e1000_phy_igp_2,

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	e1000_phy_gg82563,

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	e1000_phy_igp_3,

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	e1000_phy_ife,

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	e1000_phy_bm,

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	e1000_phy_82578,

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	e1000_phy_82577,

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	e1000_phy_82579,

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	e1000_phy_i217,

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};

   150

   151

enum e1000_bus_width {

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	e1000_bus_width_unknown = 0,

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	e1000_bus_width_pcie_x1,

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	e1000_bus_width_pcie_x2,

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	e1000_bus_width_pcie_x4 = 4,

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	e1000_bus_width_32,

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	e1000_bus_width_64,

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	e1000_bus_width_reserved

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};

   160

   161

enum e1000_1000t_rx_status {

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	e1000_1000t_rx_status_not_ok = 0,

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	e1000_1000t_rx_status_ok,

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	e1000_1000t_rx_status_undefined = 0xFF

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};

   166

   167

enum e1000_rev_polarity {

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	e1000_rev_polarity_normal = 0,

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	e1000_rev_polarity_reversed,

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	e1000_rev_polarity_undefined = 0xFF

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};

   172

   173

enum e1000_fc_mode {

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	e1000_fc_none = 0,

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	e1000_fc_rx_pause,

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	e1000_fc_tx_pause,

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	e1000_fc_full,

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	e1000_fc_default = 0xFF

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};

   180

   181

enum e1000_ms_type {

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	e1000_ms_hw_default = 0,

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	e1000_ms_force_master,

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	e1000_ms_force_slave,

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	e1000_ms_auto

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};

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enum e1000_smart_speed {

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	e1000_smart_speed_default = 0,

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	e1000_smart_speed_on,

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	e1000_smart_speed_off

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};

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enum e1000_serdes_link_state {

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	e1000_serdes_link_down = 0,

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	e1000_serdes_link_autoneg_progress,

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	e1000_serdes_link_autoneg_complete,

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	e1000_serdes_link_forced_up

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};

   200

   201

/* Receive Descriptor - Extended */

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union e1000_rx_desc_extended {

   203

	struct {

   204

		__le64 buffer_addr;

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		__le64 reserved;

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	} read;

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	struct {

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		struct {

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			__le32 mrq;	      /* Multiple Rx Queues */

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			union {

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				__le32 rss;	    /* RSS Hash */

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				struct {

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					__le16 ip_id;  /* IP id */

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					__le16 csum;   /* Packet Checksum */

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				} csum_ip;

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			} hi_dword;

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		} lower;

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		struct {

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			__le32 status_error;     /* ext status/error */

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			__le16 length;

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			__le16 vlan;	     /* VLAN tag */

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		} upper;

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	} wb;  /* writeback */

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};

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   226

#define MAX_PS_BUFFERS 4

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   228

/* Number of packet split data buffers (not including the header buffer) */

   229

#define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)

   230

   231

/* Receive Descriptor - Packet Split */

   232

union e1000_rx_desc_packet_split {

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	struct {

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		/* one buffer for protocol header(s), three data buffers */

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		__le64 buffer_addr[MAX_PS_BUFFERS];

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	} read;

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	struct {

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		struct {

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			__le32 mrq;	      /* Multiple Rx Queues */

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			union {

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				__le32 rss;	      /* RSS Hash */

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				struct {

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					__le16 ip_id;    /* IP id */

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					__le16 csum;     /* Packet Checksum */

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				} csum_ip;

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			} hi_dword;

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		} lower;

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		struct {

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			__le32 status_error;     /* ext status/error */

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			__le16 length0;	  /* length of buffer 0 */

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			__le16 vlan;	     /* VLAN tag */

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		} middle;

   253

		struct {

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			__le16 header_status;

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			/* length of buffers 1-3 */

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			__le16 length[PS_PAGE_BUFFERS];

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		} upper;

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		__le64 reserved;

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	} wb; /* writeback */

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};

   261

   262

/* Transmit Descriptor */

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struct e1000_tx_desc {

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	__le64 buffer_addr;      /* Address of the descriptor's data buffer */

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	union {

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		__le32 data;

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		struct {

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			__le16 length;    /* Data buffer length */

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			u8 cso;	/* Checksum offset */

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			u8 cmd;	/* Descriptor control */

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		} flags;

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	} lower;

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	union {

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		__le32 data;

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		struct {

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			u8 status;     /* Descriptor status */

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			u8 css;	/* Checksum start */

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			__le16 special;

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		} fields;

   280

	} upper;

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};

   282

   283

/* Offload Context Descriptor */

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struct e1000_context_desc {

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	union {

   286

		__le32 ip_config;

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		struct {

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			u8 ipcss;      /* IP checksum start */

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			u8 ipcso;      /* IP checksum offset */

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			__le16 ipcse;     /* IP checksum end */

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		} ip_fields;

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	} lower_setup;

   293

	union {

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		__le32 tcp_config;

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		struct {

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			u8 tucss;      /* TCP checksum start */

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			u8 tucso;      /* TCP checksum offset */

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			__le16 tucse;     /* TCP checksum end */

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		} tcp_fields;

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	} upper_setup;

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	__le32 cmd_and_length;

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	union {

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		__le32 data;

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		struct {

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			u8 status;     /* Descriptor status */

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			u8 hdr_len;    /* Header length */

   307

			__le16 mss;       /* Maximum segment size */

   308

		} fields;

   309

	} tcp_seg_setup;

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};

   311

   312

/* Offload data descriptor */

   313

struct e1000_data_desc {

   314

	__le64 buffer_addr;   /* Address of the descriptor's buffer address */

   315

	union {

   316

		__le32 data;

   317

		struct {

   318

			__le16 length;    /* Data buffer length */

   319

			u8 typ_len_ext;

   320

			u8 cmd;

   321

		} flags;

   322

	} lower;

   323

	union {

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		__le32 data;

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		struct {

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			u8 status;     /* Descriptor status */

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			u8 popts;      /* Packet Options */

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			__le16 special;

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		} fields;

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	} upper;

   331

};

   332

   333

/* Statistics counters collected by the MAC */

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struct e1000_hw_stats {

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	u64 crcerrs;

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	u64 algnerrc;

   337

	u64 symerrs;

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	u64 rxerrc;

   339

	u64 mpc;

   340

	u64 scc;

   341

	u64 ecol;

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	u64 mcc;

   343

	u64 latecol;

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	u64 colc;

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	u64 dc;

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	u64 tncrs;

   347

	u64 sec;

   348

	u64 cexterr;

   349

	u64 rlec;

   350

	u64 xonrxc;

   351

	u64 xontxc;

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	u64 xoffrxc;

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	u64 xofftxc;

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	u64 fcruc;

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	u64 prc64;

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	u64 prc127;

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	u64 prc255;

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	u64 prc511;

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	u64 prc1023;

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	u64 prc1522;

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	u64 gprc;

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	u64 bprc;

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	u64 mprc;

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	u64 gptc;

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	u64 gorc;

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	u64 gotc;

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	u64 rnbc;

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	u64 ruc;

   369

	u64 rfc;

   370

	u64 roc;

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	u64 rjc;

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	u64 mgprc;

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	u64 mgpdc;

   374

	u64 mgptc;

   375

	u64 tor;

   376

	u64 tot;

   377

	u64 tpr;

   378

	u64 tpt;

   379

	u64 ptc64;

   380

	u64 ptc127;

   381

	u64 ptc255;

   382

	u64 ptc511;

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	u64 ptc1023;

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	u64 ptc1522;

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	u64 mptc;

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	u64 bptc;

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	u64 tsctc;

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	u64 tsctfc;

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	u64 iac;

   390

	u64 icrxptc;

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	u64 icrxatc;

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	u64 ictxptc;

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	u64 ictxatc;

   394

	u64 ictxqec;

   395

	u64 ictxqmtc;

   396

	u64 icrxdmtc;

   397

	u64 icrxoc;

   398

};

   399

   400

struct e1000_phy_stats {

   401

	u32 idle_errors;

   402

	u32 receive_errors;

   403

};

   404

   405

struct e1000_host_mng_dhcp_cookie {

   406

	u32 signature;

   407

	u8 status;

   408

	u8 reserved0;

   409

	u16 vlan_id;

   410

	u32 reserved1;

   411

	u16 reserved2;

   412

	u8 reserved3;

   413

	u8 checksum;

   414

};

   415

   416

/* Host Interface "Rev 1" */

   417

struct e1000_host_command_header {

   418

	u8 command_id;

   419

	u8 command_length;

   420

	u8 command_options;

   421

	u8 checksum;

   422

};

   423

   424

#define E1000_HI_MAX_DATA_LENGTH	252

   425

struct e1000_host_command_info {

   426

	struct e1000_host_command_header command_header;

   427

	u8 command_data[E1000_HI_MAX_DATA_LENGTH];

   428

};

   429

   430

/* Host Interface "Rev 2" */

   431

struct e1000_host_mng_command_header {

   432

	u8 command_id;

   433

	u8 checksum;

   434

	u16 reserved1;

   435

	u16 reserved2;

   436

	u16 command_length;

   437

};

   438

   439

#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8

   440

struct e1000_host_mng_command_info {

   441

	struct e1000_host_mng_command_header command_header;

   442

	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];

   443

};

   444

   445

#include "mac.h"

   446

#include "phy.h"

   447

#include "nvm.h"

   448

#include "manage.h"

   449

   450

/* Function pointers for the MAC. */

   451

struct e1000_mac_operations {

   452

	s32  (*id_led_init)(struct e1000_hw *);

   453

	s32  (*blink_led)(struct e1000_hw *);

   454

	bool (*check_mng_mode)(struct e1000_hw *);

   455

	s32  (*check_for_link)(struct e1000_hw *);

   456

	s32  (*cleanup_led)(struct e1000_hw *);

   457

	void (*clear_hw_cntrs)(struct e1000_hw *);

   458

	void (*clear_vfta)(struct e1000_hw *);

   459

	s32  (*get_bus_info)(struct e1000_hw *);

   460

	void (*set_lan_id)(struct e1000_hw *);

   461

	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);

   462

	s32  (*led_on)(struct e1000_hw *);

   463

	s32  (*led_off)(struct e1000_hw *);

   464

	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);

   465

	s32  (*reset_hw)(struct e1000_hw *);

   466

	s32  (*init_hw)(struct e1000_hw *);

   467

	s32  (*setup_link)(struct e1000_hw *);

   468

	s32  (*setup_physical_interface)(struct e1000_hw *);

   469

	s32  (*setup_led)(struct e1000_hw *);

   470

	void (*write_vfta)(struct e1000_hw *, u32, u32);

   471

	void (*config_collision_dist)(struct e1000_hw *);

   472

	int  (*rar_set)(struct e1000_hw *, u8 *, u32);

   473

	s32  (*read_mac_addr)(struct e1000_hw *);

   474

	u32  (*rar_get_count)(struct e1000_hw *);

   475

};

   476

   477

/* When to use various PHY register access functions:

   478

 *

   479

 *                 Func   Caller

   480

 *   Function      Does   Does    When to use

   481

 *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   482

 *   X_reg         L,P,A  n/a     for simple PHY reg accesses

   483

 *   X_reg_locked  P,A    L       for multiple accesses of different regs

   484

 *                                on different pages

   485

 *   X_reg_page    A      L,P     for multiple accesses of different regs

   486

 *                                on the same page

   487

 *

   488

 * Where X=[read|write], L=locking, P=sets page, A=register access

   489

 *

   490

 */

   491

struct e1000_phy_operations {

   492

	s32  (*acquire)(struct e1000_hw *);

   493

	s32  (*cfg_on_link_up)(struct e1000_hw *);

   494

	s32  (*check_polarity)(struct e1000_hw *);

   495

	s32  (*check_reset_block)(struct e1000_hw *);

   496

	s32  (*commit)(struct e1000_hw *);

   497

	s32  (*force_speed_duplex)(struct e1000_hw *);

   498

	s32  (*get_cfg_done)(struct e1000_hw *hw);

   499

	s32  (*get_cable_length)(struct e1000_hw *);

   500

	s32  (*get_info)(struct e1000_hw *);

   501

	s32  (*set_page)(struct e1000_hw *, u16);

   502

	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);

   503

	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);

   504

	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);

   505

	void (*release)(struct e1000_hw *);

   506

	s32  (*reset)(struct e1000_hw *);

   507

	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);

   508

	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);

   509

	s32  (*write_reg)(struct e1000_hw *, u32, u16);

   510

	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);

   511

	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);

   512

	void (*power_up)(struct e1000_hw *);

   513

	void (*power_down)(struct e1000_hw *);

   514

};

   515

   516

/* Function pointers for the NVM. */

   517

struct e1000_nvm_operations {

   518

	s32  (*acquire)(struct e1000_hw *);

   519

	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);

   520

	void (*release)(struct e1000_hw *);

   521

	void (*reload)(struct e1000_hw *);

   522

	s32  (*update)(struct e1000_hw *);

   523

	s32  (*valid_led_default)(struct e1000_hw *, u16 *);

   524

	s32  (*validate)(struct e1000_hw *);

   525

	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);

   526

};

   527

   528

struct e1000_mac_info {

   529

	struct e1000_mac_operations ops;

   530

	u8 addr[ETH_ALEN];