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/* Intel PRO/1000 Linux driver

     2

 * Copyright(c) 1999 - 2014 Intel Corporation.

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 *

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 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

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 * The full GNU General Public License is included in this distribution in

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 * the file called "COPYING".

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 *

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 * Contact Information:

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 * Linux NICS <linux.nics@intel.com>

    18

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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 */

    21

    22

/* Linux PRO/1000 Ethernet Driver main header file */

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    24

#ifndef _E1000_H_

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#define _E1000_H_

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    27

#include <linux/bitops.h>

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#include <linux/types.h>

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#include <linux/timer.h>

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#include <linux/workqueue.h>

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#include <linux/io.h>

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#include <linux/netdevice.h>

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#include <linux/pci.h>

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#include <linux/pci-aspm.h>

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#include <linux/crc32.h>

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#include <linux/if_vlan.h>

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#include <linux/clocksource.h>

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#include <linux/net_tstamp.h>

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#include <linux/ptp_clock_kernel.h>

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#include <linux/ptp_classify.h>

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#include <linux/mii.h>

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#include <linux/mdio.h>

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#include "hw.h"

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    45

struct e1000_info;

    46

    47

#define e_dbg(format, arg...) \

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	netdev_dbg(hw->adapter->netdev, format, ## arg)

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#define e_err(format, arg...) \

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	netdev_err(adapter->netdev, format, ## arg)

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#define e_info(format, arg...) \

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	netdev_info(adapter->netdev, format, ## arg)

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#define e_warn(format, arg...) \

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	netdev_warn(adapter->netdev, format, ## arg)

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#define e_notice(format, arg...) \

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	netdev_notice(adapter->netdev, format, ## arg)

    57

    58

/* Interrupt modes, as used by the IntMode parameter */

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#define E1000E_INT_MODE_LEGACY		0

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#define E1000E_INT_MODE_MSI		1

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#define E1000E_INT_MODE_MSIX		2

    62

    63

/* Tx/Rx descriptor defines */

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#define E1000_DEFAULT_TXD		256

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#define E1000_MAX_TXD			4096

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#define E1000_MIN_TXD			64

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    68

#define E1000_DEFAULT_RXD		256

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#define E1000_MAX_RXD			4096

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#define E1000_MIN_RXD			64

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    72

#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */

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#define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */

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    75

#define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */

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/* How many Tx Descriptors do we need to call netif_wake_queue ? */

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/* How many Rx Buffers do we bundle into one write to the hardware ? */

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#define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */

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    81

#define AUTO_ALL_MODES			0

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#define E1000_EEPROM_APME		0x0400

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    84

#define E1000_MNG_VLAN_NONE		(-1)

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    86

#define DEFAULT_JUMBO			9234

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    88

/* Time to wait before putting the device into D3 if there's no link (in ms). */

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#define LINK_TIMEOUT		100

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    91

/* Count for polling __E1000_RESET condition every 10-20msec.

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 * Experimentation has shown the reset can take approximately 210msec.

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 */

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#define E1000_CHECK_RESET_COUNT		25

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#define DEFAULT_RDTR			0

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#define DEFAULT_RADV			8

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#define BURST_RDTR			0x20

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#define BURST_RADV			0x20

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   101

/* in the case of WTHRESH, it appears at least the 82571/2 hardware

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 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when

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 * WTHRESH=4, so a setting of 5 gives the most efficient bus

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 * utilization but to avoid possible Tx stalls, set it to 1

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 */

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#define E1000_TXDCTL_DMA_BURST_ENABLE                          \

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	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \

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	 E1000_TXDCTL_COUNT_DESC |                             \

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	 (1 << 16) | /* wthresh must be +1 more than desired */\

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	 (1 << 8)  | /* hthresh */                             \

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	 0x1f)       /* pthresh */

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#define E1000_RXDCTL_DMA_BURST_ENABLE                          \

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	(0x01000000 | /* set descriptor granularity */         \

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	 (4 << 16)  | /* set writeback threshold    */         \

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	 (4 << 8)   | /* set prefetch threshold     */         \

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	 0x20)        /* set hthresh                */

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   119

#define E1000_TIDV_FPD (1 << 31)

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#define E1000_RDTR_FPD (1 << 31)

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   122

enum e1000_boards {

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	board_82571,

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	board_82572,

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	board_82573,

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	board_82574,

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	board_82583,

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	board_80003es2lan,

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	board_ich8lan,

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	board_ich9lan,

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	board_ich10lan,

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	board_pchlan,

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	board_pch2lan,

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	board_pch_lpt,

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};

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   137

struct e1000_ps_page {

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	struct page *page;

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	u64 dma; /* must be u64 - written to hw */

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};

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/* wrappers around a pointer to a socket buffer,

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 * so a DMA handle can be stored along with the buffer

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 */

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struct e1000_buffer {

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	dma_addr_t dma;

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	struct sk_buff *skb;

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	union {

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		/* Tx */

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		struct {

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			unsigned long time_stamp;

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			u16 length;

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			u16 next_to_watch;

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			unsigned int segs;

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			unsigned int bytecount;

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			u16 mapped_as_page;

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		};

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		/* Rx */

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		struct {

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			/* arrays of page information for packet split */

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			struct e1000_ps_page *ps_pages;

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			struct page *page;

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		};

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	};

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};

   166

   167

struct e1000_ring {

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	struct e1000_adapter *adapter;	/* back pointer to adapter */

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	void *desc;			/* pointer to ring memory  */

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	dma_addr_t dma;			/* phys address of ring    */

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	unsigned int size;		/* length of ring in bytes */

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	unsigned int count;		/* number of desc. in ring */

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	u16 next_to_use;

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	u16 next_to_clean;

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	void __iomem *head;

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	void __iomem *tail;

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	/* array of buffer information structs */

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	struct e1000_buffer *buffer_info;

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   183

	char name[IFNAMSIZ + 5];

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	u32 ims_val;

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	u32 itr_val;

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	void __iomem *itr_register;

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	int set_itr;

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	struct sk_buff *rx_skb_top;

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};

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   192

/* PHY register snapshot values */

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struct e1000_phy_regs {

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	u16 bmcr;		/* basic mode control register    */

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	u16 bmsr;		/* basic mode status register     */

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	u16 advertise;		/* auto-negotiation advertisement */

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	u16 lpa;		/* link partner ability register  */

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	u16 expansion;		/* auto-negotiation expansion reg */

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	u16 ctrl1000;		/* 1000BASE-T control register    */

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	u16 stat1000;		/* 1000BASE-T status register     */

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	u16 estatus;		/* extended status register       */

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};

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   204

/* board specific private data structure */

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struct e1000_adapter {

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	struct timer_list watchdog_timer;

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	struct timer_list phy_info_timer;

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	struct timer_list blink_timer;

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	struct work_struct reset_task;

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	struct work_struct watchdog_task;

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   213

	const struct e1000_info *ei;

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	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

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	u32 bd_number;

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	u32 rx_buffer_len;

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	u16 mng_vlan_id;

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	u16 link_speed;

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	u16 link_duplex;

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	u16 eeprom_vers;

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   223

	/* track device up/down/testing state */

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	unsigned long state;

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	/* Interrupt Throttle Rate */

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	u32 itr;

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	u32 itr_setting;

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	u16 tx_itr;

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	u16 rx_itr;

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	/* Tx - one ring per active queue */

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	struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;

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	u32 tx_fifo_limit;

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	struct napi_struct napi;

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	unsigned int uncorr_errors;	/* uncorrectable ECC errors */

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	unsigned int corr_errors;	/* correctable ECC errors */

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	unsigned int restart_queue;

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	u32 txd_cmd;

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	bool detect_tx_hung;

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	bool tx_hang_recheck;

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	u8 tx_timeout_factor;

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	u32 tx_int_delay;

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	u32 tx_abs_int_delay;

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   250

	unsigned int total_tx_bytes;

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	unsigned int total_tx_packets;

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	unsigned int total_rx_bytes;

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	unsigned int total_rx_packets;

   254

   255

	/* Tx stats */

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	u64 tpt_old;

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	u64 colc_old;

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	u32 gotc;

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	u64 gotc_old;

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	u32 tx_timeout_count;

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	u32 tx_fifo_head;

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	u32 tx_head_addr;

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	u32 tx_fifo_size;

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	u32 tx_dma_failed;

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	u32 tx_hwtstamp_timeouts;

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   267

	/* Rx */

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	bool (*clean_rx)(struct e1000_ring *ring, int *work_done,

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			 int work_to_do) ____cacheline_aligned_in_smp;

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	void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,

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			     gfp_t gfp);

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	struct e1000_ring *rx_ring;

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	u32 rx_int_delay;

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	u32 rx_abs_int_delay;

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	/* Rx stats */

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	u64 hw_csum_err;

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	u64 hw_csum_good;

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	u64 rx_hdr_split;

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	u32 gorc;

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	u64 gorc_old;

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	u32 alloc_rx_buff_failed;

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	u32 rx_dma_failed;

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	u32 rx_hwtstamp_cleared;

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	unsigned int rx_ps_pages;

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	u16 rx_ps_bsize0;

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	u32 max_frame_size;

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	u32 min_frame_size;

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	/* OS defined structs */

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	struct net_device *netdev;

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	struct pci_dev *pdev;

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	/* structs defined in e1000_hw.h */

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	struct e1000_hw hw;

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	spinlock_t stats64_lock;	/* protects statistics counters */

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	struct e1000_hw_stats stats;

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	struct e1000_phy_info phy_info;

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	struct e1000_phy_stats phy_stats;

   303

   304

	/* Snapshot of PHY registers */

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	struct e1000_phy_regs phy_regs;

   306

   307

	struct e1000_ring test_tx_ring;

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	struct e1000_ring test_rx_ring;

   309

	u32 test_icr;

   310

   311

	u32 msg_enable;

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	unsigned int num_vectors;

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	struct msix_entry *msix_entries;

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	int int_mode;

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	u32 eiac_mask;

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	u32 eeprom_wol;

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	u32 wol;

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	u32 pba;

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	u32 max_hw_frame_size;

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	bool fc_autoneg;

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	unsigned int flags;

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	unsigned int flags2;

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	struct work_struct downshift_task;

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	struct work_struct update_phy_task;

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	struct work_struct print_hang_task;

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   330

	int phy_hang_count;

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   332

	u16 tx_ring_count;

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	u16 rx_ring_count;

   334

   335

	struct hwtstamp_config hwtstamp_config;

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	struct delayed_work systim_overflow_work;

   337

	struct sk_buff *tx_hwtstamp_skb;

   338

	unsigned long tx_hwtstamp_start;

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	struct work_struct tx_hwtstamp_work;

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	spinlock_t systim_lock;	/* protects SYSTIML/H regsters */

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	struct cyclecounter cc;

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	struct timecounter tc;

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	struct ptp_clock *ptp_clock;

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	struct ptp_clock_info ptp_clock_info;

   345

   346

	u16 eee_advert;

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};

   348

   349

struct e1000_info {

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	enum e1000_mac_type	mac;

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	unsigned int		flags;

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	unsigned int		flags2;

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	u32			pba;

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	u32			max_hw_frame_size;

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	s32			(*get_variants)(struct e1000_adapter *);

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	const struct e1000_mac_operations *mac_ops;

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	const struct e1000_phy_operations *phy_ops;

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	const struct e1000_nvm_operations *nvm_ops;

   359

};

   360

   361

s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);

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   363

/* The system time is maintained by a 64-bit counter comprised of the 32-bit

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 * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore

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 * its resolution) is based on the contents of the TIMINCA register - it

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 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).

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 * For the best accuracy, the incperiod should be as small as possible.  The

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 * incvalue is scaled by a factor as large as possible (while still fitting

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 * in bits 23:0) so that relatively small clock corrections can be made.

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 *

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 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of

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 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)

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 * bits to count nanoseconds leaving the rest for fractional nonseconds.

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 */

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#define INCVALUE_96MHz		125

   376

#define INCVALUE_SHIFT_96MHz	17

   377

#define INCPERIOD_SHIFT_96MHz	2

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#define INCPERIOD_96MHz		(12 >> INCPERIOD_SHIFT_96MHz)

   379

   380

#define INCVALUE_25MHz		40

   381

#define INCVALUE_SHIFT_25MHz	18

   382

#define INCPERIOD_25MHz		1

   383

   384

/* Another drawback of scaling the incvalue by a large factor is the

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 * 64-bit SYSTIM register overflows more quickly.  This is dealt with

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 * by simply reading the clock before it overflows.

   387

 *

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 * Clock	ns bits	Overflows after

   389

 * ~~~~~~	~~~~~~~	~~~~~~~~~~~~~~~

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 * 96MHz	47-bit	2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs

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 * 25MHz	46-bit	2^46 / 10^9 / 3600 = 19.55 hours

   392

 */

   393

#define E1000_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 60 * 4)

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#define E1000_MAX_82574_SYSTIM_REREADS	50

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#define E1000_82574_SYSTIM_EPSILON	(1ULL << 35ULL)

   396

   397

/* hardware capability, feature, and workaround flags */

   398

#define FLAG_HAS_AMT                      (1 << 0)

   399

#define FLAG_HAS_FLASH                    (1 << 1)

   400

#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)

   401

#define FLAG_HAS_WOL                      (1 << 3)

   402

/* reserved bit4 */

   403

#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)

   404

#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)

   405

#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)

   406

#define FLAG_READ_ONLY_NVM                (1 << 8)

   407

#define FLAG_IS_ICH                       (1 << 9)

   408

#define FLAG_HAS_MSIX                     (1 << 10)

   409

#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)

   410

#define FLAG_IS_QUAD_PORT_A               (1 << 12)

   411

#define FLAG_IS_QUAD_PORT                 (1 << 13)

   412

#define FLAG_HAS_HW_TIMESTAMP             (1 << 14)

   413

#define FLAG_APME_IN_WUC                  (1 << 15)

   414

#define FLAG_APME_IN_CTRL3                (1 << 16)

   415

#define FLAG_APME_CHECK_PORT_B            (1 << 17)

   416

#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)

   417

#define FLAG_NO_WAKE_UCAST                (1 << 19)

   418

#define FLAG_MNG_PT_ENABLED               (1 << 20)

   419

#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)

   420

#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)

   421

#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)

   422

#define FLAG_RX_NEEDS_RESTART             (1 << 24)

   423

#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)

   424

#define FLAG_SMART_POWER_DOWN             (1 << 26)

   425

#define FLAG_MSI_ENABLED                  (1 << 27)

   426

/* reserved (1 << 28) */

   427

#define FLAG_TSO_FORCE                    (1 << 29)

   428

#define FLAG_RESTART_NOW                  (1 << 30)

   429

#define FLAG_MSI_TEST_FAILED              (1 << 31)

   430

   431

#define FLAG2_CRC_STRIPPING               (1 << 0)

   432

#define FLAG2_HAS_PHY_WAKEUP              (1 << 1)

   433

#define FLAG2_IS_DISCARDING               (1 << 2)

   434

#define FLAG2_DISABLE_ASPM_L1             (1 << 3)

   435

#define FLAG2_HAS_PHY_STATS               (1 << 4)

   436

#define FLAG2_HAS_EEE                     (1 << 5)

   437

#define FLAG2_DMA_BURST                   (1 << 6)

   438

#define FLAG2_DISABLE_ASPM_L0S            (1 << 7)

   439

#define FLAG2_DISABLE_AIM                 (1 << 8)

   440

#define FLAG2_CHECK_PHY_HANG              (1 << 9)

   441

#define FLAG2_NO_DISABLE_RX               (1 << 10)

   442

#define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)

   443

#define FLAG2_DFLT_CRC_STRIPPING          (1 << 12)

   444

#define FLAG2_CHECK_RX_HWTSTAMP           (1 << 13)

   445

   446

#define E1000_RX_DESC_PS(R, i)	    \

   447

	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))

   448

#define E1000_RX_DESC_EXT(R, i)	    \

   449

	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))

   450

#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))

   451

#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)

   452

#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)

   453

   454

enum e1000_state_t {

   455

	__E1000_TESTING,

   456

	__E1000_RESETTING,

   457

	__E1000_ACCESS_SHARED_RESOURCE,

   458

	__E1000_DOWN

   459

};

   460

   461

enum latency_range {

   462

	lowest_latency = 0,

   463

	low_latency = 1,

   464

	bulk_latency = 2,

   465

	latency_invalid = 255

   466

};

   467

   468

extern char e1000e_driver_name[];

   469

extern const char e1000e_driver_version[];

   470

   471

void e1000e_check_options(struct e1000_adapter *adapter);

   472

void e1000e_set_ethtool_ops(struct net_device *netdev);

   473

   474

int e1000e_up(struct e1000_adapter *adapter);

   475

void e1000e_down(struct e1000_adapter *adapter, bool reset);

   476

void e1000e_reinit_locked(struct e1000_adapter *adapter);

   477

void e1000e_reset(struct e1000_adapter *adapter);

   478

void e1000e_power_up_phy(struct e1000_adapter *adapter);

   479

int e1000e_setup_rx_resources(struct e1000_ring *ring);

   480

int e1000e_setup_tx_resources(struct e1000_ring *ring);

   481

void e1000e_free_rx_resources(struct e1000_ring *ring);

   482

void e1000e_free_tx_resources(struct e1000_ring *ring);

   483

struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,

   484

					     struct rtnl_link_stats64 *stats);

   485

void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);

   486

void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);

   487

void e1000e_get_hw_control(struct e1000_adapter *adapter);

   488

void e1000e_release_hw_control(struct e1000_adapter *adapter);

   489

void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);

   490

   491

extern unsigned int copybreak;

   492

   493

extern const struct e1000_info e1000_82571_info;

   494

extern const struct e1000_info e1000_82572_info;

   495

extern const struct e1000_info e1000_82573_info;

   496

extern const struct e1000_info e1000_82574_info;

   497

extern const struct e1000_info e1000_82583_info;

   498

extern const struct e1000_info e1000_ich8_info;

   499

extern const struct e1000_info e1000_ich9_info;

   500

extern const struct e1000_info e1000_ich10_info;

   501

extern const struct e1000_info e1000_pch_info;

   502

extern const struct e1000_info e1000_pch2_info;

   503

extern const struct e1000_info e1000_pch_lpt_info;

   504

extern const struct e1000_info e1000_es2_info;

   505

   506

void e1000e_ptp_init(struct e1000_adapter *adapter);

   507

void e1000e_ptp_remove(struct e1000_adapter *adapter);

   508

   509

static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)

   510

{

   511

	return hw->phy.ops.reset(hw);

   512

}

   513

   514

static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)

   515

{

   516

	return hw->phy.ops.read_reg(hw, offset, data);

   517

}

   518

   519

static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)

   520

{

   521

	return hw->phy.ops.read_reg_locked(hw, offset, data);

   522

}

   523

   524

static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)

   525

{

   526

	return hw->phy.ops.write_reg(hw, offset, data);

   527

}

   528

   529

static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)

   530

{