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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2009 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

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  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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*******************************************************************************/

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#ifndef _E1000_DEFINES_H_

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#define _E1000_DEFINES_H_

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#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */

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#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */

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#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */

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#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

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#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */

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#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */

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#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */

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#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

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#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */

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#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */

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#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */

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#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */

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#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */

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#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */

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#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */

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#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */

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#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */

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#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */

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    51

/* Number of Transmit and Receive Descriptors must be a multiple of 8 */

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#define REQ_TX_DESCRIPTOR_MULTIPLE  8

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#define REQ_RX_DESCRIPTOR_MULTIPLE  8

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    55

/* Definitions for power management and wakeup registers */

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/* Wake Up Control */

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#define E1000_WUC_APME       0x00000001 /* APM Enable */

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#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */

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#define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */

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    61

/* Wake Up Filter Control */

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#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */

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#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */

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#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */

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#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */

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#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */

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#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */

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    69

/* Wake Up Status */

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#define E1000_WUS_LNKC         E1000_WUFC_LNKC

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#define E1000_WUS_MAG          E1000_WUFC_MAG

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#define E1000_WUS_EX           E1000_WUFC_EX

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#define E1000_WUS_MC           E1000_WUFC_MC

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#define E1000_WUS_BC           E1000_WUFC_BC

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    76

/* Extended Device Control */

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#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */

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#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */

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#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */

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#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */

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#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */

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#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000

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#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000

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#define E1000_CTRL_EXT_EIAME          0x01000000

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#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */

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#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */

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#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers after IMS clear */

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#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */

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#define E1000_CTRL_EXT_PHYPDEN        0x00100000

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    91

/* Receive Descriptor bit definitions */

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#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */

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#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */

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#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */

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#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */

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#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */

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#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */

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#define E1000_RXD_ERR_CE        0x01    /* CRC Error */

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#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */

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#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */

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#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */

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#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */

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#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */

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#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */

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#define E1000_RXDEXT_STATERR_CE    0x01000000

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#define E1000_RXDEXT_STATERR_SE    0x02000000

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#define E1000_RXDEXT_STATERR_SEQ   0x04000000

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#define E1000_RXDEXT_STATERR_CXE   0x10000000

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#define E1000_RXDEXT_STATERR_RXE   0x80000000

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/* mask to determine if packets should be dropped due to frame errors */

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#define E1000_RXD_ERR_FRAME_ERR_MASK ( \

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    E1000_RXD_ERR_CE  |                \

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    E1000_RXD_ERR_SE  |                \

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    E1000_RXD_ERR_SEQ |                \

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    E1000_RXD_ERR_CXE |                \

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    E1000_RXD_ERR_RXE)

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/* Same mask, but for extended and packet split descriptors */

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#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \

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    E1000_RXDEXT_STATERR_CE  |            \

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    E1000_RXDEXT_STATERR_SE  |            \

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    E1000_RXDEXT_STATERR_SEQ |            \

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    E1000_RXDEXT_STATERR_CXE |            \

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    E1000_RXDEXT_STATERR_RXE)

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#define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000

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   130

/* Management Control */

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#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */

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#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */

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#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */

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#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */

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#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */

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/* Enable MAC address filtering */

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#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000

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/* Enable MNG packets to host memory */

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#define E1000_MANC_EN_MNG2HOST   0x00200000

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#define E1000_MANC2H_PORT_623    0x00000020 /* Port 0x26f */

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#define E1000_MANC2H_PORT_664    0x00000040 /* Port 0x298 */

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#define E1000_MDEF_PORT_623      0x00000800 /* Port 0x26f */

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#define E1000_MDEF_PORT_664      0x00000400 /* Port 0x298 */

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   146

/* Receive Control */

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#define E1000_RCTL_EN             0x00000002    /* enable */

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#define E1000_RCTL_SBP            0x00000004    /* store bad packet */

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#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */

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#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */

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#define E1000_RCTL_LPE            0x00000020    /* long packet enable */

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#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */

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#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */

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#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */

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#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */

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#define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min threshold size */

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#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */

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#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */

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#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */

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/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */

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#define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */

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#define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */

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#define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */

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#define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */

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/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */

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#define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */

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#define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */

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#define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */

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#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */

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#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */

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#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */

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#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */

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#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */

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#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */

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/*

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 * Use byte values for the following shift parameters

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 * Usage:

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 *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &

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 *                  E1000_PSRCTL_BSIZE0_MASK) |

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 *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &

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 *                  E1000_PSRCTL_BSIZE1_MASK) |

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 *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &

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 *                  E1000_PSRCTL_BSIZE2_MASK) |

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 *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;

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 *                  E1000_PSRCTL_BSIZE3_MASK))

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 * where value0 = [128..16256],  default=256

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 *       value1 = [1024..64512], default=4096

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 *       value2 = [0..64512],    default=4096

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 *       value3 = [0..64512],    default=0

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 */

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#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F

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#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00

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#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000

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#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000

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#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */

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#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */

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#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */

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#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */

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   203

/* SWFW_SYNC Definitions */

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#define E1000_SWFW_EEP_SM   0x1

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#define E1000_SWFW_PHY0_SM  0x2

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#define E1000_SWFW_PHY1_SM  0x4

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#define E1000_SWFW_CSR_SM   0x8

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   209

/* Device Control */

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#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */

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#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */

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#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */

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#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */

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#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */

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#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */

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#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */

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#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */

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#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */

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#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */

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#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */

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#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */

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#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */

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#define E1000_CTRL_LANPHYPC_VALUE    0x00020000 /* SW value of LANPHYPC */

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#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */

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#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */

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#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */

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#define E1000_CTRL_RST      0x04000000  /* Global reset */

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#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */

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#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */

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#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */

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#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */

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/*

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 * Bit definitions for the Management Data IO (MDIO) and Management Data

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 * Clock (MDC) pins in the Device Control Register.

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 */

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/* Device Status */

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#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */

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#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */

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#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */

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#define E1000_STATUS_FUNC_SHIFT 2

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#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */

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#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */

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#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */

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#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */

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#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */

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#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM */

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#define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */

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#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */

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   252

/* Constants used to interpret the masked PCI-X bus speed. */

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#define HALF_DUPLEX 1

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#define FULL_DUPLEX 2

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#define ADVERTISE_10_HALF                 0x0001

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#define ADVERTISE_10_FULL                 0x0002

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#define ADVERTISE_100_HALF                0x0004

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#define ADVERTISE_100_FULL                0x0008

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#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */

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#define ADVERTISE_1000_FULL               0x0020

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/* 1000/H is not supported, nor spec-compliant. */

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#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \

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				ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \

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						     ADVERTISE_1000_FULL)

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#define E1000_ALL_NOT_GIG      ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \

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				ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

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#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

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#define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)

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#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)

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#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX

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   277

/* LED Control */

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#define E1000_PHY_LED0_MODE_MASK          0x00000007

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#define E1000_PHY_LED0_IVRT               0x00000008

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#define E1000_PHY_LED0_MASK               0x0000001F

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#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F

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#define E1000_LEDCTL_LED0_MODE_SHIFT      0

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#define E1000_LEDCTL_LED0_IVRT            0x00000040

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#define E1000_LEDCTL_LED0_BLINK           0x00000080

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#define E1000_LEDCTL_MODE_LINK_UP       0x2

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#define E1000_LEDCTL_MODE_LED_ON        0xE

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#define E1000_LEDCTL_MODE_LED_OFF       0xF

   290

   291

/* Transmit Descriptor bit definitions */

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#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */

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#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */

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#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */

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#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */

   296

#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

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#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */

   298

#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */

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#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */

   300

#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

   301

#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */

   302

#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */

   303

#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */

   304

#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */

   305

#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */

   306

#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */

   307

#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */

   308

#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */

   309

#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */

   310

#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */

   311

   312

/* Transmit Control */

   313

#define E1000_TCTL_EN     0x00000002    /* enable Tx */

   314

#define E1000_TCTL_PSP    0x00000008    /* pad short packets */

   315

#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */

   316

#define E1000_TCTL_COLD   0x003ff000    /* collision distance */

   317

#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */

   318

#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */

   319

   320

/* Transmit Arbitration Count */

   321

   322

/* SerDes Control */

   323

#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400

   324

   325

/* Receive Checksum Control */

   326

#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */

   327

#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */

   328

   329

/* Header split receive */

   330

#define E1000_RFCTL_NFSW_DIS            0x00000040

   331

#define E1000_RFCTL_NFSR_DIS            0x00000080

   332

#define E1000_RFCTL_ACK_DIS             0x00001000

   333

#define E1000_RFCTL_EXTEN               0x00008000

   334

#define E1000_RFCTL_IPV6_EX_DIS         0x00010000

   335

#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000

   336

   337

/* Collision related configuration parameters */

   338

#define E1000_COLLISION_THRESHOLD       15

   339

#define E1000_CT_SHIFT                  4

   340

#define E1000_COLLISION_DISTANCE        63

   341

#define E1000_COLD_SHIFT                12

   342

   343

/* Default values for the transmit IPG register */

   344

#define DEFAULT_82543_TIPG_IPGT_COPPER 8

   345

   346

#define E1000_TIPG_IPGT_MASK  0x000003FF

   347

   348

#define DEFAULT_82543_TIPG_IPGR1 8

   349

#define E1000_TIPG_IPGR1_SHIFT  10

   350

   351

#define DEFAULT_82543_TIPG_IPGR2 6

   352

#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7

   353

#define E1000_TIPG_IPGR2_SHIFT  20

   354

   355

#define MAX_JUMBO_FRAME_SIZE    0x3F00

   356

   357

/* Extended Configuration Control and Size */

   358

#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020

   359

#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001

   360

#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008

   361

#define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020

   362

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000

   363

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16

   364

#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000

   365

#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16

   366

   367

#define E1000_PHY_CTRL_D0A_LPLU           0x00000002

   368

#define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004

   369

#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008

   370

#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040

   371

   372

#define E1000_KABGTXD_BGSQLBIAS           0x00050000

   373

   374

/* PBA constants */

   375

#define E1000_PBA_8K  0x0008    /* 8KB */

   376

#define E1000_PBA_16K 0x0010    /* 16KB */

   377

   378

#define E1000_PBS_16K E1000_PBA_16K

   379

   380

#define IFS_MAX       80

   381

#define IFS_MIN       40

   382

#define IFS_RATIO     4

   383

#define IFS_STEP      10

   384

#define MIN_NUM_XMITS 1000

   385

   386

/* SW Semaphore Register */

   387

#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */

   388

#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */

   389

#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */

   390

   391

#define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */

   392

   393

/* Interrupt Cause Read */

   394

#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */

   395

#define E1000_ICR_LSC           0x00000004 /* Link Status Change */

   396

#define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */

   397

#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */

   398

#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */

   399

#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */

   400

#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */

   401

#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */

   402

#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */

   403

#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */

   404

#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */

   405

   406

/* PBA ECC Register */

   407

#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */

   408

#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */

   409

#define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */

   410

#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */

   411

#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */

   412

   413

/*

   414

 * This defines the bits that are set in the Interrupt Mask

   415

 * Set/Read Register.  Each bit is documented below:

   416

 *   o RXT0   = Receiver Timer Interrupt (ring 0)

   417

 *   o TXDW   = Transmit Descriptor Written Back

   418

 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)

   419

 *   o RXSEQ  = Receive Sequence Error

   420

 *   o LSC    = Link Status Change

   421

 */

   422

#define IMS_ENABLE_MASK ( \

   423

    E1000_IMS_RXT0   |    \

   424

    E1000_IMS_TXDW   |    \

   425

    E1000_IMS_RXDMT0 |    \

   426

    E1000_IMS_RXSEQ  |    \

   427

    E1000_IMS_LSC)

   428

   429

/* Interrupt Mask Set */

   430

#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */

   431

#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */

   432

#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */

   433

#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */

   434

#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */

   435

#define E1000_IMS_RXQ0      E1000_ICR_RXQ0      /* Rx Queue 0 Interrupt */

   436

#define E1000_IMS_RXQ1      E1000_ICR_RXQ1      /* Rx Queue 1 Interrupt */

   437

#define E1000_IMS_TXQ0      E1000_ICR_TXQ0      /* Tx Queue 0 Interrupt */

   438

#define E1000_IMS_TXQ1      E1000_ICR_TXQ1      /* Tx Queue 1 Interrupt */

   439

#define E1000_IMS_OTHER     E1000_ICR_OTHER     /* Other Interrupts */

   440

   441

/* Interrupt Cause Set */

   442

#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */

   443

#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */

   444

#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */

   445

   446

/* Transmit Descriptor Control */

   447

#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */

   448

#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */

   449

#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */

   450

#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */

   451

/* Enable the counting of desc. still to be processed. */

   452

#define E1000_TXDCTL_COUNT_DESC 0x00400000

   453

   454

/* Flow Control Constants */

   455

#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001

   456

#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100

   457

#define FLOW_CONTROL_TYPE         0x8808

   458

   459

/* 802.1q VLAN Packet Size */

   460

#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */

   461

   462

/* Receive Address */

   463

/*

   464

 * Number of high/low register pairs in the RAR. The RAR (Receive Address

   465

 * Registers) holds the directed and multicast addresses that we monitor.

   466

 * Technically, we have 16 spots.  However, we reserve one of these spots

   467

 * (RAR[15]) for our directed address used by controllers with

   468

 * manageability enabled, allowing us room for 15 multicast addresses.

   469

 */

   470

#define E1000_RAR_ENTRIES     15

   471

#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */

   472

#define E1000_RAL_MAC_ADDR_LEN 4

   473

#define E1000_RAH_MAC_ADDR_LEN 2

   474

   475

/* Error Codes */

   476

#define E1000_ERR_NVM      1

   477

#define E1000_ERR_PHY      2

   478

#define E1000_ERR_CONFIG   3

   479

#define E1000_ERR_PARAM    4

   480

#define E1000_ERR_MAC_INIT 5

   481

#define E1000_ERR_PHY_TYPE 6

   482

#define E1000_ERR_RESET   9

   483

#define E1000_ERR_MASTER_REQUESTS_PENDING 10

   484

#define E1000_ERR_HOST_INTERFACE_COMMAND 11

   485

#define E1000_BLK_PHY_RESET   12

   486

#define E1000_ERR_SWFW_SYNC 13

   487

#define E1000_NOT_IMPLEMENTED 14

   488

   489

/* Loop limit on how long we wait for auto-negotiation to complete */

   490

#define FIBER_LINK_UP_LIMIT               50

   491

#define COPPER_LINK_UP_LIMIT              10

   492

#define PHY_AUTO_NEG_LIMIT                45

   493

#define PHY_FORCE_LIMIT                   20

   494

/* Number of 100 microseconds we wait for PCI Express master disable */

   495

#define MASTER_DISABLE_TIMEOUT      800

   496

/* Number of milliseconds we wait for PHY configuration done after MAC reset */

   497

#define PHY_CFG_TIMEOUT             100

   498

/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */

   499

#define MDIO_OWNERSHIP_TIMEOUT      10

   500

/* Number of milliseconds for NVM auto read done after MAC reset. */

   501

#define AUTO_READ_DONE_TIMEOUT      10

   502

   503

/* Flow Control */

   504

#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */

   505

#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */

   506

#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */

   507

   508

/* Transmit Configuration Word */

   509

#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */

   510

#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */

   511

#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */

   512

#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */

   513

#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */

   514

   515

/* Receive Configuration Word */

   516

#define E1000_RXCW_IV         0x08000000        /* Receive config invalid */

   517

#define E1000_RXCW_C          0x20000000        /* Receive config */

   518

#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */

   519

   520

/* PCI Express Control */

   521

#define E1000_GCR_RXD_NO_SNOOP          0x00000001

   522

#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002

   523

#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004

   524

#define E1000_GCR_TXD_NO_SNOOP          0x00000008

   525

#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010

   526

#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020

   527

   528

#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \

   529

			   E1000_GCR_RXDSCW_NO_SNOOP      | \

   530

			   E1000_GCR_RXDSCR_NO_SNOOP      | \