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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2012 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

    28

    29

/*

    30

 * 80003ES2LAN Gigabit Ethernet Controller (Copper)

    31

 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    32

 */

    33

    34

#include "e1000.h"

    35

    36

#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00

    37

#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02

    38

#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10

    39

#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F

    40

    41

#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008

    42

#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800

    43

#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010

    44

    45

#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

    46

#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000

    47

#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000

    48

    49

#define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C

    50

#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004

    51

    52

#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

    53

#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000

    54

    55

#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8

    56

#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9

    57

    58

/* GG82563 PHY Specific Status Register (Page 0, Register 16 */

    59

#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */

    60

#define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060

    61

#define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */

    62

#define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */

    63

#define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */

    64

    65

/* PHY Specific Control Register 2 (Page 0, Register 26) */

    66

#define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000

    67

						/* 1=Reverse Auto-Negotiation */

    68

    69

/* MAC Specific Control Register (Page 2, Register 21) */

    70

/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

    71

#define GG82563_MSCR_TX_CLK_MASK		 0x0007

    72

#define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004

    73

#define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005

    74

#define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007

    75

    76

#define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */

    77

    78

/* DSP Distance Register (Page 5, Register 26) */

    79

#define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M

    80

							   1 = 50-80M

    81

							   2 = 80-110M

    82

							   3 = 110-140M

    83

							   4 = >140M */

    84

    85

/* Kumeran Mode Control Register (Page 193, Register 16) */

    86

#define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800

    87

    88

/* Max number of times Kumeran read/write should be validated */

    89

#define GG82563_MAX_KMRN_RETRY  0x5

    90

    91

/* Power Management Control Register (Page 193, Register 20) */

    92

#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001

    93

					   /* 1=Enable SERDES Electrical Idle */

    94

    95

/* In-Band Control Register (Page 194, Register 18) */

    96

#define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */

    97

    98

/*

    99

 * A table for the GG82563 cable length where the range is defined

   100

 * with a lower bound at "index" and the upper bound at

   101

 * "index + 5".

   102

 */

   103

static const u16 e1000_gg82563_cable_length_table[] = {

   104

	 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };

   105

#define GG82563_CABLE_LENGTH_TABLE_SIZE \

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		ARRAY_SIZE(e1000_gg82563_cable_length_table)

   107

   108

static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

   109

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   110

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   111

static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

   112

static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

   113

static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

   114

static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

   115

static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);

   116

static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   117

                                            u16 *data);

   118

static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   119

                                             u16 data);

   120

static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);

   121

   122

/**

   123

 *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

   124

 *  @hw: pointer to the HW structure

   125

 **/

   126

static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

   127

{

   128

	struct e1000_phy_info *phy = &hw->phy;

   129

	s32 ret_val;

   130

   131

	if (hw->phy.media_type != e1000_media_type_copper) {

   132

		phy->type	= e1000_phy_none;

   133

		return 0;

   134

	} else {

   135

		phy->ops.power_up = e1000_power_up_phy_copper;

   136

		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

   137

	}

   138

   139

	phy->addr		= 1;

   140

	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

   141

	phy->reset_delay_us      = 100;

   142

	phy->type		= e1000_phy_gg82563;

   143

   144

	/* This can only be done after all function pointers are setup. */

   145

	ret_val = e1000e_get_phy_id(hw);

   146

   147

	/* Verify phy id */

   148

	if (phy->id != GG82563_E_PHY_ID)

   149

		return -E1000_ERR_PHY;

   150

   151

	return ret_val;

   152

}

   153

   154

/**

   155

 *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

   156

 *  @hw: pointer to the HW structure

   157

 **/

   158

static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

   159

{

   160

	struct e1000_nvm_info *nvm = &hw->nvm;

   161

	u32 eecd = er32(EECD);

   162

	u16 size;

   163

   164

	nvm->opcode_bits	= 8;

   165

	nvm->delay_usec	 = 1;

   166

	switch (nvm->override) {

   167

	case e1000_nvm_override_spi_large:

   168

		nvm->page_size    = 32;

   169

		nvm->address_bits = 16;

   170

		break;

   171

	case e1000_nvm_override_spi_small:

   172

		nvm->page_size    = 8;

   173

		nvm->address_bits = 8;

   174

		break;

   175

	default:

   176

		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   177

		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   178

		break;

   179

	}

   180

   181

	nvm->type = e1000_nvm_eeprom_spi;

   182

   183

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   184

			  E1000_EECD_SIZE_EX_SHIFT);

   185

   186

	/*

   187

	 * Added to a constant, "size" becomes the left-shift value

   188

	 * for setting word_size.

   189

	 */

   190

	size += NVM_WORD_SIZE_BASE_SHIFT;

   191

   192

	/* EEPROM access above 16k is unsupported */

   193

	if (size > 14)

   194

		size = 14;

   195

	nvm->word_size	= 1 << size;

   196

   197

	return 0;

   198

}

   199

   200

/**

   201

 *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   202

 *  @hw: pointer to the HW structure

   203

 **/

   204

static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)

   205

{

   206

	struct e1000_mac_info *mac = &hw->mac;

   207

   208

	/* Set media type and media-dependent function pointers */

   209

	switch (hw->adapter->pdev->device) {

   210

	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   211

		hw->phy.media_type = e1000_media_type_internal_serdes;

   212

		mac->ops.check_for_link = e1000e_check_for_serdes_link;

   213

		mac->ops.setup_physical_interface =

   214

		    e1000e_setup_fiber_serdes_link;

   215

		break;

   216

	default:

   217

		hw->phy.media_type = e1000_media_type_copper;

   218

		mac->ops.check_for_link = e1000e_check_for_copper_link;

   219

		mac->ops.setup_physical_interface =

   220

		    e1000_setup_copper_link_80003es2lan;

   221

		break;

   222

	}

   223

   224

	/* Set mta register count */

   225

	mac->mta_reg_count = 128;

   226

	/* Set rar entry count */

   227

	mac->rar_entry_count = E1000_RAR_ENTRIES;

   228

	/* FWSM register */

   229

	mac->has_fwsm = true;

   230

	/* ARC supported; valid only if manageability features are enabled. */

   231

	mac->arc_subsystem_valid =

   232

	        (er32(FWSM) & E1000_FWSM_MODE_MASK)

   233

	                ? true : false;

   234

	/* Adaptive IFS not supported */

   235

	mac->adaptive_ifs = false;

   236

   237

	/* set lan id for port to determine which phy lock to use */

   238

	hw->mac.ops.set_lan_id(hw);

   239

   240

	return 0;

   241

}

   242

   243

static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   244

{

   245

	struct e1000_hw *hw = &adapter->hw;

   246

	s32 rc;

   247

   248

	rc = e1000_init_mac_params_80003es2lan(hw);

   249

	if (rc)

   250

		return rc;

   251

   252

	rc = e1000_init_nvm_params_80003es2lan(hw);

   253

	if (rc)

   254

		return rc;

   255

   256

	rc = e1000_init_phy_params_80003es2lan(hw);

   257

	if (rc)

   258

		return rc;

   259

   260

	return 0;

   261

}

   262

   263

/**

   264

 *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   265

 *  @hw: pointer to the HW structure

   266

 *

   267

 *  A wrapper to acquire access rights to the correct PHY.

   268

 **/

   269

static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   270

{

   271

	u16 mask;

   272

   273

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   274

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   275

}

   276

   277

/**

   278

 *  e1000_release_phy_80003es2lan - Release rights to access PHY

   279

 *  @hw: pointer to the HW structure

   280

 *

   281

 *  A wrapper to release access rights to the correct PHY.

   282

 **/

   283

static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   284

{

   285

	u16 mask;

   286

   287

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   288

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   289

}

   290

   291

/**

   292

 *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register

   293

 *  @hw: pointer to the HW structure

   294

 *

   295

 *  Acquire the semaphore to access the Kumeran interface.

   296

 *

   297

 **/

   298

static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   299

{

   300

	u16 mask;

   301

   302

	mask = E1000_SWFW_CSR_SM;

   303

   304

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   305

}

   306

   307

/**

   308

 *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register

   309

 *  @hw: pointer to the HW structure

   310

 *

   311

 *  Release the semaphore used to access the Kumeran interface

   312

 **/

   313

static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   314

{

   315

	u16 mask;

   316

   317

	mask = E1000_SWFW_CSR_SM;

   318

   319

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   320

}

   321

   322

/**

   323

 *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   324

 *  @hw: pointer to the HW structure

   325

 *

   326

 *  Acquire the semaphore to access the EEPROM.

   327

 **/

   328

static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   329

{

   330

	s32 ret_val;

   331

   332

	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   333

	if (ret_val)

   334

		return ret_val;

   335

   336

	ret_val = e1000e_acquire_nvm(hw);

   337

   338

	if (ret_val)

   339

		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   340

   341

	return ret_val;

   342

}

   343

   344

/**

   345

 *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   346

 *  @hw: pointer to the HW structure

   347

 *

   348

 *  Release the semaphore used to access the EEPROM.

   349

 **/

   350

static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   351

{

   352

	e1000e_release_nvm(hw);

   353

	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   354

}

   355

   356

/**

   357

 *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   358

 *  @hw: pointer to the HW structure

   359

 *  @mask: specifies which semaphore to acquire

   360

 *

   361

 *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   362

 *  will also specify which port we're acquiring the lock for.

   363

 **/

   364

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   365

{

   366

	u32 swfw_sync;

   367

	u32 swmask = mask;

   368

	u32 fwmask = mask << 16;

   369

	s32 i = 0;

   370

	s32 timeout = 50;

   371

   372

	while (i < timeout) {

   373

		if (e1000e_get_hw_semaphore(hw))

   374

			return -E1000_ERR_SWFW_SYNC;

   375

   376

		swfw_sync = er32(SW_FW_SYNC);

   377

		if (!(swfw_sync & (fwmask | swmask)))

   378

			break;

   379

   380

		/*

   381

		 * Firmware currently using resource (fwmask)

   382

		 * or other software thread using resource (swmask)

   383

		 */

   384

		e1000e_put_hw_semaphore(hw);

   385

		mdelay(5);

   386

		i++;

   387

	}

   388

   389

	if (i == timeout) {

   390

		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");

   391

		return -E1000_ERR_SWFW_SYNC;

   392

	}

   393

   394

	swfw_sync |= swmask;

   395

	ew32(SW_FW_SYNC, swfw_sync);

   396

   397

	e1000e_put_hw_semaphore(hw);

   398

   399

	return 0;

   400

}

   401

   402

/**

   403

 *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   404

 *  @hw: pointer to the HW structure

   405

 *  @mask: specifies which semaphore to acquire

   406

 *

   407

 *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   408

 *  will also specify which port we're releasing the lock for.

   409

 **/

   410

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   411

{

   412

	u32 swfw_sync;

   413

   414

	while (e1000e_get_hw_semaphore(hw) != 0)

   415

		; /* Empty */

   416

   417

	swfw_sync = er32(SW_FW_SYNC);

   418

	swfw_sync &= ~mask;

   419

	ew32(SW_FW_SYNC, swfw_sync);

   420

   421

	e1000e_put_hw_semaphore(hw);

   422

}

   423

   424

/**

   425

 *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   426

 *  @hw: pointer to the HW structure

   427

 *  @offset: offset of the register to read

   428

 *  @data: pointer to the data returned from the operation

   429

 *

   430

 *  Read the GG82563 PHY register.

   431

 **/

   432

static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   433

						  u32 offset, u16 *data)

   434

{

   435

	s32 ret_val;

   436

	u32 page_select;

   437

	u16 temp;

   438

   439

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   440

	if (ret_val)

   441

		return ret_val;

   442

   443

	/* Select Configuration Page */

   444

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   445

		page_select = GG82563_PHY_PAGE_SELECT;

   446

	} else {

   447

		/*

   448

		 * Use Alternative Page Select register to access

   449

		 * registers 30 and 31

   450

		 */

   451

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   452

	}

   453

   454

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   455

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   456

	if (ret_val) {

   457

		e1000_release_phy_80003es2lan(hw);

   458

		return ret_val;

   459

	}

   460

   461

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   462

		/*

   463

		 * The "ready" bit in the MDIC register may be incorrectly set

   464

		 * before the device has completed the "Page Select" MDI

   465

		 * transaction.  So we wait 200us after each MDI command...

   466

		 */

   467

		udelay(200);

   468

   469

		/* ...and verify the command was successful. */

   470

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   471

   472

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   473

			e1000_release_phy_80003es2lan(hw);

   474

			return -E1000_ERR_PHY;

   475

		}

   476

   477

		udelay(200);

   478

   479

		ret_val = e1000e_read_phy_reg_mdic(hw,

   480

		                                  MAX_PHY_REG_ADDRESS & offset,

   481

		                                  data);

   482

   483

		udelay(200);

   484

	} else {

   485

		ret_val = e1000e_read_phy_reg_mdic(hw,

   486

		                                  MAX_PHY_REG_ADDRESS & offset,

   487

		                                  data);

   488

	}

   489

   490

	e1000_release_phy_80003es2lan(hw);

   491

   492

	return ret_val;

   493

}

   494

   495

/**

   496

 *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   497

 *  @hw: pointer to the HW structure

   498

 *  @offset: offset of the register to read

   499

 *  @data: value to write to the register

   500

 *

   501

 *  Write to the GG82563 PHY register.

   502

 **/

   503

static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   504

						   u32 offset, u16 data)

   505

{

   506

	s32 ret_val;

   507

	u32 page_select;

   508

	u16 temp;

   509

   510

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   511

	if (ret_val)

   512

		return ret_val;

   513

   514

	/* Select Configuration Page */

   515

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   516

		page_select = GG82563_PHY_PAGE_SELECT;

   517

	} else {

   518

		/*

   519

		 * Use Alternative Page Select register to access

   520

		 * registers 30 and 31

   521

		 */

   522

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   523

	}

   524

   525

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   526

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   527

	if (ret_val) {

   528

		e1000_release_phy_80003es2lan(hw);

   529

		return ret_val;

   530

	}