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/******************************************************************************

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 *

     3

 *  $Id$

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 *

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 *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

    22

 *  ---

    23

 *

    24

 *  The license mentioned above concerns the source code only. Using the

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 *  EtherCAT technology and brand is only permitted in compliance with the

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 *  industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/**

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   \file

    32

   EtherCAT driver for RTL8139-compatible NICs.

    33

*/

    34

    35

/*****************************************************************************/

    36

    37

/*

    38

  Former documentation:

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    40

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41

    42

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    44

    45

	Much code comes from Donald Becker's rtl8139.c driver,

    46

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48

    49

	-----<snip>-----

    50

    51

        	Written 1997-2001 by Donald Becker.

    52

		This software may be used and distributed according to the

    53

		terms of the GNU General Public License (GPL), incorporated

    54

		herein by reference.  Drivers based on or derived from this

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		code fall under the GPL and must retain the authorship,

    56

		copyright and license notice.  This file is not a complete

    57

		program and may only be used when the entire operating

    58

		system is licensed under the GPL.

    59

    60

		This driver is for boards based on the RTL8129 and RTL8139

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		PCI ethernet chips.

    62

    63

		The author may be reached as becker@scyld.com, or C/O Scyld

    64

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65

		MD 21403

    66

    67

		Support and updates available at

    68

		http://www.scyld.com/network/rtl8139.html

    69

    70

		Twister-tuning table provided by Kinston

    71

		<shangh@realtek.com.tw>.

    72

    73

	-----<snip>-----

    74

    75

	This software may be used and distributed according to the terms

    76

	of the GNU General Public License, incorporated herein by reference.

    77

    78

	Contributors:

    79

    80

		Donald Becker - he wrote the original driver, kudos to him!

    81

		(but please don't e-mail him for support, this isn't his driver)

    82

    83

		Tigran Aivazian - bug fixes, skbuff free cleanup

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    85

		Martin Mares - suggestions for PCI cleanup

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		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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    91

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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    94

		Gerard Sharp - bug fix, testing and feedback

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    96

		David Ford - Rx ring wrap fix

    97

    98

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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   101

		Donald Becker/Chris Butterworth/Marcus Westergren -

   102

		Noticed various Rx packet size-related buglets.

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   104

		Santiago Garcia Mantinan - testing and feedback

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		Jens David - 2.2.x kernel backports

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   108

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

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   111

		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   124

		"rtl8139-diag -mmmaaavvveefN" output

   125

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

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   127

*/

   128

   129

#define DRV_NAME	"ec_8139too"

   130

#define DRV_VERSION	"0.9.28"

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

   137

#include <linux/init.h>

   138

#include <linux/netdevice.h>

   139

#include <linux/etherdevice.h>

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#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <linux/io.h>

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#include <linux/uaccess.h>

   148

#include <linux/gfp.h>

   149

#include <asm/irq.h>

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   151

#include "../globals.h"

   152

#include "ecdev.h"

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   154

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

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   158

#define PFX DRV_NAME ": "

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   160

/* Default Message level */

   161

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   162

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   164

   165

   166

/* define to 1, 2 or 3 to enable copious debugging info */

   167

#define RTL8139_DEBUG 0

   168

   169

/* define to 1 to disable lightweight runtime debugging checks */

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#undef RTL8139_NDEBUG

   171

   172

   173

#ifdef RTL8139_NDEBUG

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#  define assert(expr) do {} while (0)

   175

#else

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#  define assert(expr) \

   177

        if(unlikely(!(expr))) {				        \

   178

        pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   179

	#expr, __FILE__, __func__, __LINE__);			\

   180

        }

   181

#endif

   182

   183

   184

/* A few user-configurable values. */

   185

/* media options */

   186

#define MAX_UNITS 8

   187

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   188

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   189

   190

/* Whether to use MMIO or PIO. Default to MMIO. */

   191

#ifdef CONFIG_8139TOO_PIO

   192

static int use_io = 1;

   193

#else

   194

static int use_io = 0;

   195

#endif

   196

   197

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   198

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   199

static int multicast_filter_limit = 32;

   200

   201

/* bitmapped message enable number */

   202

static int debug = -1;

   203

   204

/*

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 * Receive ring size

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 * Warning: 64K ring has hardware issues and may lock up.

   207

 */

   208

#if defined(CONFIG_SH_DREAMCAST)

   209

#define RX_BUF_IDX 0	/* 8K ring */

   210

#else

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#define RX_BUF_IDX	2	/* 32K ring */

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#endif

   213

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   214

#define RX_BUF_PAD	16

   215

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

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   217

#if RX_BUF_LEN == 65536

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#define RX_BUF_TOT_LEN	RX_BUF_LEN

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#else

   220

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   221

#endif

   222

   223

/* Number of Tx descriptor registers. */

   224

#define NUM_TX_DESC	4

   225

   226

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   227

#define MAX_ETH_FRAME_SIZE	1536

   228

   229

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   230

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   231

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   232

   233

/* PCI Tuning Parameters

   234

   Threshold is bytes transferred to chip before transmission starts. */

   235

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   236

   237

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   238

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   239

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   240

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   241

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   242

   243

/* Operational parameters that usually are not changed. */

   244

/* Time in jiffies before concluding the transmitter is hung. */

   245

#define TX_TIMEOUT  (6*HZ)

   246

   247

   248

enum {

   249

	HAS_MII_XCVR = 0x010000,

   250

	HAS_CHIP_XCVR = 0x020000,

   251

	HAS_LNK_CHNG = 0x040000,

   252

};

   253

   254

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   255

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   256

#define RTL_MIN_IO_SIZE 0x80

   257

#define RTL8139B_IO_SIZE 256

   258

   259

#define RTL8129_CAPS	HAS_MII_XCVR

   260

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   261

   262

typedef enum {

   263

	RTL8139 = 0,

   264

	RTL8129,

   265

} board_t;

   266

   267

   268

/* indexed by board_t, above */

   269

static const struct {

   270

	const char *name;

   271

	u32 hw_flags;

   272

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

   274

	{ "RealTek RTL8129", RTL8129_CAPS },

   275

};

   276

   277

   278

static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   279

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298

   299

#ifdef CONFIG_SH_SECUREEDGE5410

   300

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   305

#endif

   306

   307

	/* some crazy cards report invalid vendor ids like

   308

	 * 0x0001 here.  The other ids are valid and constant,

   309

	 * so we simply don't match on the main vendor id.

   310

	 */

   311

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   313

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   314

   315

	{0,}

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};

   317

   318

/* prevent driver from being loaded automatically */

   319

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   320

   321

static struct {

   322

	const char str[ETH_GSTRING_LEN];

   323

} ethtool_stats_keys[] = {

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	{ "early_rx" },

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	{ "tx_buf_mapped" },

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	{ "tx_timeouts" },

   327

	{ "rx_lost_in_ring" },

   328

};

   329

   330

/* The rest of these values should never change. */

   331

   332

/* Symbolic offsets to registers. */

   333

enum RTL8139_registers {

   334

	MAC0		= 0,	 /* Ethernet hardware address. */

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	MAR0		= 8,	 /* Multicast filter. */

   336

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   337

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   338

	RxBuf		= 0x30,

   339

	ChipCmd		= 0x37,

   340

	RxBufPtr	= 0x38,

   341

	RxBufAddr	= 0x3A,

   342

	IntrMask	= 0x3C,

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	IntrStatus	= 0x3E,

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	TxConfig	= 0x40,

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	RxConfig	= 0x44,

   346

	Timer		= 0x48,	 /* A general-purpose counter. */

   347

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   348

	Cfg9346		= 0x50,

   349

	Config0		= 0x51,

   350

	Config1		= 0x52,

   351

	TimerInt	= 0x54,

   352

	MediaStatus	= 0x58,

   353

	Config3		= 0x59,

   354

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   355

	HltClk		= 0x5B,

   356

	MultiIntr	= 0x5C,

   357

	TxSummary	= 0x60,

   358

	BasicModeCtrl	= 0x62,

   359

	BasicModeStatus	= 0x64,

   360

	NWayAdvert	= 0x66,

   361

	NWayLPAR	= 0x68,

   362

	NWayExpansion	= 0x6A,

   363

	/* Undocumented registers, but required for proper operation. */

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	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   365

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   366

	PARA78		= 0x78,

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	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   368

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   369

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   370

};

   371

   372

enum ClearBitMasks {

   373

	MultiIntrClear	= 0xF000,

   374

	ChipCmdClear	= 0xE2,

   375

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

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};

   377

   378

enum ChipCmdBits {

   379

	CmdReset	= 0x10,

   380

	CmdRxEnb	= 0x08,

   381

	CmdTxEnb	= 0x04,

   382

	RxBufEmpty	= 0x01,

   383

};

   384

   385

/* Interrupt register bits, using my own meaningful names. */

   386

enum IntrStatusBits {

   387

	PCIErr		= 0x8000,

   388

	PCSTimeout	= 0x4000,

   389

	RxFIFOOver	= 0x40,

   390

	RxUnderrun	= 0x20,

   391

	RxOverflow	= 0x10,

   392

	TxErr		= 0x08,

   393

	TxOK		= 0x04,

   394

	RxErr		= 0x02,

   395

	RxOK		= 0x01,

   396

   397

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   398

};

   399

   400

enum TxStatusBits {

   401

	TxHostOwns	= 0x2000,

   402

	TxUnderrun	= 0x4000,

   403

	TxStatOK	= 0x8000,

   404

	TxOutOfWindow	= 0x20000000,

   405

	TxAborted	= 0x40000000,

   406

	TxCarrierLost	= 0x80000000,

   407

};

   408

enum RxStatusBits {

   409

	RxMulticast	= 0x8000,

   410

	RxPhysical	= 0x4000,

   411

	RxBroadcast	= 0x2000,

   412

	RxBadSymbol	= 0x0020,

   413

	RxRunt		= 0x0010,

   414

	RxTooLong	= 0x0008,

   415

	RxCRCErr	= 0x0004,

   416

	RxBadAlign	= 0x0002,

   417

	RxStatusOK	= 0x0001,

   418

};

   419

   420

/* Bits in RxConfig. */

   421

enum rx_mode_bits {

   422

	AcceptErr	= 0x20,

   423

	AcceptRunt	= 0x10,

   424

	AcceptBroadcast	= 0x08,

   425

	AcceptMulticast	= 0x04,

   426

	AcceptMyPhys	= 0x02,

   427

	AcceptAllPhys	= 0x01,

   428

};

   429

   430

/* Bits in TxConfig. */

   431

enum tx_config_bits {

   432

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   433

        TxIFGShift	= 24,

   434

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   435

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   436

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   437

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   438

   439

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   440

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   441

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   442

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   443

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   444

   445

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   446

};

   447

   448

/* Bits in Config1 */

   449

enum Config1Bits {

   450

	Cfg1_PM_Enable	= 0x01,

   451

	Cfg1_VPD_Enable	= 0x02,

   452

	Cfg1_PIO	= 0x04,

   453

	Cfg1_MMIO	= 0x08,

   454

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   455

	Cfg1_Driver_Load = 0x20,

   456

	Cfg1_LED0	= 0x40,

   457

	Cfg1_LED1	= 0x80,

   458

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   459

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   460

};

   461

   462

/* Bits in Config3 */

   463

enum Config3Bits {

   464

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   465

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   466

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   467

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   468

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   469

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   470

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   471

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   472

};

   473

   474

/* Bits in Config4 */

   475

enum Config4Bits {

   476

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   477

};

   478

   479

/* Bits in Config5 */

   480

enum Config5Bits {

   481

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   482

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   483

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   484

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   485

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   486

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   487

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   488

};

   489

   490

enum RxConfigBits {

   491

	/* rx fifo threshold */

   492

	RxCfgFIFOShift	= 13,

   493

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   494

   495

	/* Max DMA burst */

   496

	RxCfgDMAShift	= 8,

   497

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   498

   499

	/* rx ring buffer length */

   500

	RxCfgRcv8K	= 0,

   501

	RxCfgRcv16K	= (1 << 11),

   502

	RxCfgRcv32K	= (1 << 12),

   503

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   504

   505

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   506

	RxNoWrap	= (1 << 7),

   507

};

   508

   509

/* Twister tuning parameters from RealTek.

   510

   Completely undocumented, but required to tune bad links on some boards. */

   511

enum CSCRBits {

   512

	CSCR_LinkOKBit		= 0x0400,

   513

	CSCR_LinkChangeBit	= 0x0800,

   514

	CSCR_LinkStatusBits	= 0x0f000,

   515

	CSCR_LinkDownOffCmd	= 0x003c0,

   516

	CSCR_LinkDownCmd	= 0x0f3c0,

   517

};

   518

   519

enum Cfg9346Bits {

   520

	Cfg9346_Lock	= 0x00,

   521

	Cfg9346_Unlock	= 0xC0,

   522

};

   523

   524

typedef enum {

   525

	CH_8139	= 0,

   526

	CH_8139_K,

   527

	CH_8139A,

   528

	CH_8139A_G,

   529

	CH_8139B,

   530

	CH_8130,