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/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006-2008  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  Using the EtherCAT technology and brand is permitted in compliance with

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 *  the industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/**

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   \file

    29

   EtherCAT driver for RTL8139-compatible NICs.

    30

*/

    31

    32

/*****************************************************************************/

    33

    34

/*

    35

  Former documentation:

    36

    37

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    38

    39

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    41

    42

	Much code comes from Donald Becker's rtl8139.c driver,

    43

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    45

    46

	-----<snip>-----

    47

    48

        	Written 1997-2001 by Donald Becker.

    49

		This software may be used and distributed according to the

    50

		terms of the GNU General Public License (GPL), incorporated

    51

		herein by reference.  Drivers based on or derived from this

    52

		code fall under the GPL and must retain the authorship,

    53

		copyright and license notice.  This file is not a complete

    54

		program and may only be used when the entire operating

    55

		system is licensed under the GPL.

    56

    57

		This driver is for boards based on the RTL8129 and RTL8139

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		PCI ethernet chips.

    59

    60

		The author may be reached as becker@scyld.com, or C/O Scyld

    61

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    62

		MD 21403

    63

    64

		Support and updates available at

    65

		http://www.scyld.com/network/rtl8139.html

    66

    67

		Twister-tuning table provided by Kinston

    68

		<shangh@realtek.com.tw>.

    69

    70

	-----<snip>-----

    71

    72

	This software may be used and distributed according to the terms

    73

	of the GNU General Public License, incorporated herein by reference.

    74

    75

	Contributors:

    76

    77

		Donald Becker - he wrote the original driver, kudos to him!

    78

		(but please don't e-mail him for support, this isn't his driver)

    79

    80

		Tigran Aivazian - bug fixes, skbuff free cleanup

    81

    82

		Martin Mares - suggestions for PCI cleanup

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    84

		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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    91

		Gerard Sharp - bug fix, testing and feedback

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    93

		David Ford - Rx ring wrap fix

    94

    95

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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    98

		Donald Becker/Chris Butterworth/Marcus Westergren -

    99

		Noticed various Rx packet size-related buglets.

   100

   101

		Santiago Garcia Mantinan - testing and feedback

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   103

		Jens David - 2.2.x kernel backports

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   105

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

   107

   108

		Jean-Jacques Michel - bug fix

   109

   110

		Tobias Ringström - Rx interrupt status checking suggestion

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   112

		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   121

		"rtl8139-diag -mmmaaavvveefN" output

   122

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   123

   124

*/

   125

   126

#define DRV_NAME	"ec_8139too"

   127

#define DRV_VERSION	"0.9.27"

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#include <linux/config.h>

   131

#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

   135

#include <linux/init.h>

   136

#include <linux/ioport.h>

   137

#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

   139

#include <linux/rtnetlink.h>

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#include <linux/delay.h>

   141

#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

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#include <asm/uaccess.h>

   147

#include <asm/irq.h>

   148

   149

#include "../globals.h"

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#include "ecdev.h"

   151

   152

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

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   156

#define PFX DRV_NAME ": "

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   158

/* Default Message level */

   159

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   160

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

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   163

   164

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   165

#ifdef CONFIG_8139TOO_PIO

   166

#define USE_IO_OPS 1

   167

#endif

   168

   169

/* define to 1, 2 or 3 to enable copious debugging info */

   170

#define RTL8139_DEBUG 0

   171

   172

/* define to 1 to disable lightweight runtime debugging checks */

   173

#undef RTL8139_NDEBUG

   174

   175

   176

#if RTL8139_DEBUG

   177

/* note: prints function name for you */

   178

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

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#else

   180

#  define DPRINTK(fmt, args...)

   181

#endif

   182

   183

#ifdef RTL8139_NDEBUG

   184

#  define assert(expr) do {} while (0)

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#else

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#  define assert(expr) \

   187

        if(unlikely(!(expr))) {				        \

   188

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   189

        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   190

        }

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#endif

   192

   193

   194

/* A few user-configurable values. */

   195

/* media options */

   196

#define MAX_UNITS 8

   197

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   198

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   199

   200

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   201

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   202

static int multicast_filter_limit = 32;

   203

   204

/* bitmapped message enable number */

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static int debug = -1;

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   207

/*

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 * Receive ring size 

   209

 * Warning: 64K ring has hardware issues and may lock up.

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 */

   211

#if defined(CONFIG_SH_DREAMCAST)

   212

#define RX_BUF_IDX	1	/* 16K ring */

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#else

   214

#define RX_BUF_IDX	2	/* 32K ring */

   215

#endif

   216

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   217

#define RX_BUF_PAD	16

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#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   219

   220

#if RX_BUF_LEN == 65536

   221

#define RX_BUF_TOT_LEN	RX_BUF_LEN

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#else

   223

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   224

#endif

   225

   226

/* Number of Tx descriptor registers. */

   227

#define NUM_TX_DESC	4

   228

   229

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   230

#define MAX_ETH_FRAME_SIZE	1536

   231

   232

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   233

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   234

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   235

   236

/* PCI Tuning Parameters

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   Threshold is bytes transferred to chip before transmission starts. */

   238

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   239

   240

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   241

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   242

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   243

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   244

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   245

   246

/* Operational parameters that usually are not changed. */

   247

/* Time in jiffies before concluding the transmitter is hung. */

   248

#define TX_TIMEOUT  (6*HZ)

   249

   250

   251

enum {

   252

	HAS_MII_XCVR = 0x010000,

   253

	HAS_CHIP_XCVR = 0x020000,

   254

	HAS_LNK_CHNG = 0x040000,

   255

};

   256

   257

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   258

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   259

#define RTL_MIN_IO_SIZE 0x80

   260

#define RTL8139B_IO_SIZE 256

   261

   262

#define RTL8129_CAPS	HAS_MII_XCVR

   263

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   264

   265

typedef enum {

   266

	RTL8139 = 0,

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	RTL8129,

   268

} board_t;

   269

   270

   271

/* indexed by board_t, above */

   272

static const struct {

   273

	const char *name;

   274

	u32 hw_flags;

   275

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

   277

	{ "RealTek RTL8129", RTL8129_CAPS },

   278

};

   279

   280

   281

static struct pci_device_id rtl8139_pci_tbl[] = {

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	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   301

   302

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

   306

#ifdef CONFIG_8139TOO_8129

   307

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   308

#endif

   309

   310

	/* some crazy cards report invalid vendor ids like

   311

	 * 0x0001 here.  The other ids are valid and constant,

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	 * so we simply don't match on the main vendor id.

   313

	 */

   314

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   316

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   317

   318

	{0,}

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};

   320

   321

/* prevent driver from being loaded automatically */

   322

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   323

   324

static struct {

   325

	const char str[ETH_GSTRING_LEN];

   326

} ethtool_stats_keys[] = {

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	{ "early_rx" },

   328

	{ "tx_buf_mapped" },

   329

	{ "tx_timeouts" },

   330

	{ "rx_lost_in_ring" },

   331

};

   332

   333

/* The rest of these values should never change. */

   334

   335

/* Symbolic offsets to registers. */

   336

enum RTL8139_registers {

   337

	MAC0 = 0,		/* Ethernet hardware address. */

   338

	MAR0 = 8,		/* Multicast filter. */

   339

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   340

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   341

	RxBuf = 0x30,

   342

	ChipCmd = 0x37,

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	RxBufPtr = 0x38,

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	RxBufAddr = 0x3A,

   345

	IntrMask = 0x3C,

   346

	IntrStatus = 0x3E,

   347

	TxConfig = 0x40,

   348

	RxConfig = 0x44,

   349

	Timer = 0x48,		/* A general-purpose counter. */

   350

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   351

	Cfg9346 = 0x50,

   352

	Config0 = 0x51,

   353

	Config1 = 0x52,

   354

	FlashReg = 0x54,

   355

	MediaStatus = 0x58,

   356

	Config3 = 0x59,

   357

	Config4 = 0x5A,		/* absent on RTL-8139A */

   358

	HltClk = 0x5B,

   359

	MultiIntr = 0x5C,

   360

	TxSummary = 0x60,

   361

	BasicModeCtrl = 0x62,

   362

	BasicModeStatus = 0x64,

   363

	NWayAdvert = 0x66,

   364

	NWayLPAR = 0x68,

   365

	NWayExpansion = 0x6A,

   366

	/* Undocumented registers, but required for proper operation. */

   367

	FIFOTMS = 0x70,		/* FIFO Control and test. */

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	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   369

	PARA78 = 0x78,

   370

	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   371

	Config5 = 0xD8,		/* absent on RTL-8139A */

   372

};

   373

   374

enum ClearBitMasks {

   375

	MultiIntrClear = 0xF000,

   376

	ChipCmdClear = 0xE2,

   377

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   378

};

   379

   380

enum ChipCmdBits {

   381

	CmdReset = 0x10,

   382

	CmdRxEnb = 0x08,

   383

	CmdTxEnb = 0x04,

   384

	RxBufEmpty = 0x01,

   385

};

   386

   387

/* Interrupt register bits, using my own meaningful names. */

   388

enum IntrStatusBits {

   389

	PCIErr = 0x8000,

   390

	PCSTimeout = 0x4000,

   391

	RxFIFOOver = 0x40,

   392

	RxUnderrun = 0x20,

   393

	RxOverflow = 0x10,

   394

	TxErr = 0x08,

   395

	TxOK = 0x04,

   396

	RxErr = 0x02,

   397

	RxOK = 0x01,

   398

   399

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   400

};

   401

   402

enum TxStatusBits {

   403

	TxHostOwns = 0x2000,

   404

	TxUnderrun = 0x4000,

   405

	TxStatOK = 0x8000,

   406

	TxOutOfWindow = 0x20000000,

   407

	TxAborted = 0x40000000,

   408

	TxCarrierLost = 0x80000000,

   409

};

   410

enum RxStatusBits {

   411

	RxMulticast = 0x8000,

   412

	RxPhysical = 0x4000,

   413

	RxBroadcast = 0x2000,

   414

	RxBadSymbol = 0x0020,

   415

	RxRunt = 0x0010,

   416

	RxTooLong = 0x0008,

   417

	RxCRCErr = 0x0004,

   418

	RxBadAlign = 0x0002,

   419

	RxStatusOK = 0x0001,

   420

};

   421

   422

/* Bits in RxConfig. */

   423

enum rx_mode_bits {

   424

	AcceptErr = 0x20,

   425

	AcceptRunt = 0x10,

   426

	AcceptBroadcast = 0x08,

   427

	AcceptMulticast = 0x04,

   428

	AcceptMyPhys = 0x02,

   429

	AcceptAllPhys = 0x01,

   430

};

   431

   432

/* Bits in TxConfig. */

   433

enum tx_config_bits {

   434

   435

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   436

        TxIFGShift = 24,

   437

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   438

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   439

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   440

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   441

   442

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   443

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   444

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   445

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   446

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   447

   448

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   449

};

   450

   451

/* Bits in Config1 */

   452

enum Config1Bits {

   453

	Cfg1_PM_Enable = 0x01,

   454

	Cfg1_VPD_Enable = 0x02,

   455

	Cfg1_PIO = 0x04,

   456

	Cfg1_MMIO = 0x08,

   457

	LWAKE = 0x10,		/* not on 8139, 8139A */

   458

	Cfg1_Driver_Load = 0x20,

   459

	Cfg1_LED0 = 0x40,

   460

	Cfg1_LED1 = 0x80,

   461

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   462

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   463

};

   464

   465

/* Bits in Config3 */

   466

enum Config3Bits {

   467

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   468

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   469

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   470

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   471

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   472

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   473

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   474

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   475

};

   476

   477

/* Bits in Config4 */

   478

enum Config4Bits {

   479

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   480

};

   481

   482

/* Bits in Config5 */

   483

enum Config5Bits {

   484

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   485

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   486

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   487

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   488

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   489

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   490

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   491

};

   492

   493

enum RxConfigBits {

   494

	/* rx fifo threshold */

   495

	RxCfgFIFOShift = 13,

   496

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   497

   498

	/* Max DMA burst */

   499

	RxCfgDMAShift = 8,

   500

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   501

   502

	/* rx ring buffer length */

   503

	RxCfgRcv8K = 0,

   504

	RxCfgRcv16K = (1 << 11),

   505

	RxCfgRcv32K = (1 << 12),

   506

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   507

   508

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   509

	RxNoWrap = (1 << 7),

   510

};

   511

   512

/* Twister tuning parameters from RealTek.

   513

   Completely undocumented, but required to tune bad links on some boards. */

   514

enum CSCRBits {

   515

	CSCR_LinkOKBit = 0x0400,

   516

	CSCR_LinkChangeBit = 0x0800,

   517

	CSCR_LinkStatusBits = 0x0f000,

   518

	CSCR_LinkDownOffCmd = 0x003c0,

   519

	CSCR_LinkDownCmd = 0x0f3c0,

   520

};

   521

   522

enum Cfg9346Bits {

   523

	Cfg9346_Lock = 0x00,

   524

	Cfg9346_Unlock = 0xC0,

   525

};

   526

   527

typedef enum {

   528

	CH_8139 = 0,