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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2006 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

/* e1000_hw.h

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 * Structures, enums, and macros for the MAC

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 */

    32

    33

#ifndef _E1000_HW_H_

    34

#define _E1000_HW_H_

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    36

#include "e1000_osdep.h"

    37

    38

    39

/* Forward declarations of structures used by the shared code */

    40

struct e1000_hw;

    41

struct e1000_hw_stats;

    42

    43

/* Enumerated types specific to the e1000 hardware */

    44

/* Media Access Controlers */

    45

typedef enum {

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    e1000_undefined = 0,

    47

    e1000_82542_rev2_0,

    48

    e1000_82542_rev2_1,

    49

    e1000_82543,

    50

    e1000_82544,

    51

    e1000_82540,

    52

    e1000_82545,

    53

    e1000_82545_rev_3,

    54

    e1000_82546,

    55

    e1000_82546_rev_3,

    56

    e1000_82541,

    57

    e1000_82541_rev_2,

    58

    e1000_82547,

    59

    e1000_82547_rev_2,

    60

    e1000_82571,

    61

    e1000_82572,

    62

    e1000_82573,

    63

    e1000_80003es2lan,

    64

    e1000_ich8lan,

    65

    e1000_num_macs

    66

} e1000_mac_type;

    67

    68

typedef enum {

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    e1000_eeprom_uninitialized = 0,

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    e1000_eeprom_spi,

    71

    e1000_eeprom_microwire,

    72

    e1000_eeprom_flash,

    73

    e1000_eeprom_ich8,

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    e1000_eeprom_none, /* No NVM support */

    75

    e1000_num_eeprom_types

    76

} e1000_eeprom_type;

    77

    78

/* Media Types */

    79

typedef enum {

    80

    e1000_media_type_copper = 0,

    81

    e1000_media_type_fiber = 1,

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    e1000_media_type_internal_serdes = 2,

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    e1000_num_media_types

    84

} e1000_media_type;

    85

    86

typedef enum {

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    e1000_10_half = 0,

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    e1000_10_full = 1,

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    e1000_100_half = 2,

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    e1000_100_full = 3

    91

} e1000_speed_duplex_type;

    92

    93

/* Flow Control Settings */

    94

typedef enum {

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    E1000_FC_NONE = 0,

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    E1000_FC_RX_PAUSE = 1,

    97

    E1000_FC_TX_PAUSE = 2,

    98

    E1000_FC_FULL = 3,

    99

    E1000_FC_DEFAULT = 0xFF

   100

} e1000_fc_type;

   101

   102

struct e1000_shadow_ram {

   103

    uint16_t    eeprom_word;

   104

    boolean_t   modified;

   105

};

   106

   107

/* PCI bus types */

   108

typedef enum {

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    e1000_bus_type_unknown = 0,

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    e1000_bus_type_pci,

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    e1000_bus_type_pcix,

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    e1000_bus_type_pci_express,

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    e1000_bus_type_reserved

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} e1000_bus_type;

   115

   116

/* PCI bus speeds */

   117

typedef enum {

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    e1000_bus_speed_unknown = 0,

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    e1000_bus_speed_33,

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    e1000_bus_speed_66,

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    e1000_bus_speed_100,

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    e1000_bus_speed_120,

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    e1000_bus_speed_133,

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    e1000_bus_speed_2500,

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    e1000_bus_speed_reserved

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} e1000_bus_speed;

   127

   128

/* PCI bus widths */

   129

typedef enum {

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    e1000_bus_width_unknown = 0,

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    /* These PCIe values should literally match the possible return values

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     * from config space */

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    e1000_bus_width_pciex_1 = 1,

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    e1000_bus_width_pciex_2 = 2,

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    e1000_bus_width_pciex_4 = 4,

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    e1000_bus_width_32,

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    e1000_bus_width_64,

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    e1000_bus_width_reserved

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} e1000_bus_width;

   140

   141

/* PHY status info structure and supporting enums */

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typedef enum {

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    e1000_cable_length_50 = 0,

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    e1000_cable_length_50_80,

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    e1000_cable_length_80_110,

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    e1000_cable_length_110_140,

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    e1000_cable_length_140,

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    e1000_cable_length_undefined = 0xFF

   149

} e1000_cable_length;

   150

   151

typedef enum {

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    e1000_gg_cable_length_60 = 0,

   153

    e1000_gg_cable_length_60_115 = 1,

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    e1000_gg_cable_length_115_150 = 2,

   155

    e1000_gg_cable_length_150 = 4

   156

} e1000_gg_cable_length;

   157

   158

typedef enum {

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    e1000_igp_cable_length_10  = 10,

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    e1000_igp_cable_length_20  = 20,

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    e1000_igp_cable_length_30  = 30,

   162

    e1000_igp_cable_length_40  = 40,

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    e1000_igp_cable_length_50  = 50,

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    e1000_igp_cable_length_60  = 60,

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    e1000_igp_cable_length_70  = 70,

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    e1000_igp_cable_length_80  = 80,

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    e1000_igp_cable_length_90  = 90,

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    e1000_igp_cable_length_100 = 100,

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    e1000_igp_cable_length_110 = 110,

   170

    e1000_igp_cable_length_115 = 115,

   171

    e1000_igp_cable_length_120 = 120,

   172

    e1000_igp_cable_length_130 = 130,

   173

    e1000_igp_cable_length_140 = 140,

   174

    e1000_igp_cable_length_150 = 150,

   175

    e1000_igp_cable_length_160 = 160,

   176

    e1000_igp_cable_length_170 = 170,

   177

    e1000_igp_cable_length_180 = 180

   178

} e1000_igp_cable_length;

   179

   180

typedef enum {

   181

    e1000_10bt_ext_dist_enable_normal = 0,

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    e1000_10bt_ext_dist_enable_lower,

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    e1000_10bt_ext_dist_enable_undefined = 0xFF

   184

} e1000_10bt_ext_dist_enable;

   185

   186

typedef enum {

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    e1000_rev_polarity_normal = 0,

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    e1000_rev_polarity_reversed,

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    e1000_rev_polarity_undefined = 0xFF

   190

} e1000_rev_polarity;

   191

   192

typedef enum {

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    e1000_downshift_normal = 0,

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    e1000_downshift_activated,

   195

    e1000_downshift_undefined = 0xFF

   196

} e1000_downshift;

   197

   198

typedef enum {

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    e1000_smart_speed_default = 0,

   200

    e1000_smart_speed_on,

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    e1000_smart_speed_off

   202

} e1000_smart_speed;

   203

   204

typedef enum {

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    e1000_polarity_reversal_enabled = 0,

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    e1000_polarity_reversal_disabled,

   207

    e1000_polarity_reversal_undefined = 0xFF

   208

} e1000_polarity_reversal;

   209

   210

typedef enum {

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    e1000_auto_x_mode_manual_mdi = 0,

   212

    e1000_auto_x_mode_manual_mdix,

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    e1000_auto_x_mode_auto1,

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    e1000_auto_x_mode_auto2,

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    e1000_auto_x_mode_undefined = 0xFF

   216

} e1000_auto_x_mode;

   217

   218

typedef enum {

   219

    e1000_1000t_rx_status_not_ok = 0,

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    e1000_1000t_rx_status_ok,

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    e1000_1000t_rx_status_undefined = 0xFF

   222

} e1000_1000t_rx_status;

   223

   224

typedef enum {

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    e1000_phy_m88 = 0,

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    e1000_phy_igp,

   227

    e1000_phy_igp_2,

   228

    e1000_phy_gg82563,

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    e1000_phy_igp_3,

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    e1000_phy_ife,

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    e1000_phy_undefined = 0xFF

   232

} e1000_phy_type;

   233

   234

typedef enum {

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    e1000_ms_hw_default = 0,

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    e1000_ms_force_master,

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    e1000_ms_force_slave,

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    e1000_ms_auto

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} e1000_ms_type;

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   241

typedef enum {

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    e1000_ffe_config_enabled = 0,

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    e1000_ffe_config_active,

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    e1000_ffe_config_blocked

   245

} e1000_ffe_config;

   246

   247

typedef enum {

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    e1000_dsp_config_disabled = 0,

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    e1000_dsp_config_enabled,

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    e1000_dsp_config_activated,

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    e1000_dsp_config_undefined = 0xFF

   252

} e1000_dsp_config;

   253

   254

struct e1000_phy_info {

   255

    e1000_cable_length cable_length;

   256

    e1000_10bt_ext_dist_enable extended_10bt_distance;

   257

    e1000_rev_polarity cable_polarity;

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    e1000_downshift downshift;

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    e1000_polarity_reversal polarity_correction;

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    e1000_auto_x_mode mdix_mode;

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    e1000_1000t_rx_status local_rx;

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    e1000_1000t_rx_status remote_rx;

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};

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   265

struct e1000_phy_stats {

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    uint32_t idle_errors;

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    uint32_t receive_errors;

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};

   269

   270

struct e1000_eeprom_info {

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    e1000_eeprom_type type;

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    uint16_t word_size;

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    uint16_t opcode_bits;

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    uint16_t address_bits;

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    uint16_t delay_usec;

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    uint16_t page_size;

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    boolean_t use_eerd;

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    boolean_t use_eewr;

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};

   280

   281

/* Flex ASF Information */

   282

#define E1000_HOST_IF_MAX_SIZE  2048

   283

   284

typedef enum {

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    e1000_byte_align = 0,

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    e1000_word_align = 1,

   287

    e1000_dword_align = 2

   288

} e1000_align_type;

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   290

   291

   292

/* Error Codes */

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#define E1000_SUCCESS      0

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#define E1000_ERR_EEPROM   1

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#define E1000_ERR_PHY      2

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#define E1000_ERR_CONFIG   3

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#define E1000_ERR_PARAM    4

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#define E1000_ERR_MAC_TYPE 5

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#define E1000_ERR_PHY_TYPE 6

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#define E1000_ERR_RESET   9

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#define E1000_ERR_MASTER_REQUESTS_PENDING 10

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#define E1000_ERR_HOST_INTERFACE_COMMAND 11

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#define E1000_BLK_PHY_RESET   12

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#define E1000_ERR_SWFW_SYNC 13

   305

   306

#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \

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                                     (((_value) & 0xff00) >> 8))

   308

   309

/* Function prototypes */

   310

/* Initialization */

   311

int32_t e1000_reset_hw(struct e1000_hw *hw);

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int32_t e1000_init_hw(struct e1000_hw *hw);

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int32_t e1000_set_mac_type(struct e1000_hw *hw);

   314

void e1000_set_media_type(struct e1000_hw *hw);

   315

   316

/* Link Configuration */

   317

int32_t e1000_setup_link(struct e1000_hw *hw);

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int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);

   319

void e1000_config_collision_dist(struct e1000_hw *hw);

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int32_t e1000_check_for_link(struct e1000_hw *hw);

   321

int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);

   322

int32_t e1000_force_mac_fc(struct e1000_hw *hw);

   323

   324

/* PHY */

   325

int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);

   326

int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);

   327

int32_t e1000_phy_hw_reset(struct e1000_hw *hw);

   328

int32_t e1000_phy_reset(struct e1000_hw *hw);

   329

int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);

   330

int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);

   331

   332

void e1000_phy_powerdown_workaround(struct e1000_hw *hw);

   333

   334

/* EEPROM Functions */

   335

int32_t e1000_init_eeprom_params(struct e1000_hw *hw);

   336

   337

/* MNG HOST IF functions */

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uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);

   339

   340

#define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64

   341

#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8   /* Host Interface data length */

   342

   343

#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10      /* Time in ms to process MNG command */

   344

#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0   /* Cookie offset */

   345

#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10    /* Cookie length */

   346

#define E1000_MNG_IAMT_MODE             0x3

   347

#define E1000_MNG_ICH_IAMT_MODE         0x2

   348

#define E1000_IAMT_SIGNATURE            0x544D4149 /* Intel(R) Active Management Technology signature */

   349

   350

#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */

   351

#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2 /* DHCP parsing enabled */

   352

#define E1000_VFTA_ENTRY_SHIFT                       0x5

   353

#define E1000_VFTA_ENTRY_MASK                        0x7F

   354

#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK              0x1F

   355

   356

struct e1000_host_mng_command_header {

   357

    uint8_t command_id;

   358

    uint8_t checksum;

   359

    uint16_t reserved1;

   360

    uint16_t reserved2;

   361

    uint16_t command_length;

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};

   363

   364

struct e1000_host_mng_command_info {

   365

    struct e1000_host_mng_command_header command_header;  /* Command Head/Command Result Head has 4 bytes */

   366

    uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH];   /* Command data can length 0..0x658*/

   367

};

   368

#ifdef __BIG_ENDIAN

   369

struct e1000_host_mng_dhcp_cookie{

   370

    uint32_t signature;

   371

    uint16_t vlan_id;

   372

    uint8_t reserved0;

   373

    uint8_t status;

   374

    uint32_t reserved1;

   375

    uint8_t checksum;

   376

    uint8_t reserved3;

   377

    uint16_t reserved2;

   378

};

   379

#else

   380

struct e1000_host_mng_dhcp_cookie{

   381

    uint32_t signature;

   382

    uint8_t status;

   383

    uint8_t reserved0;

   384

    uint16_t vlan_id;

   385

    uint32_t reserved1;

   386

    uint16_t reserved2;

   387

    uint8_t reserved3;

   388

    uint8_t checksum;

   389

};

   390

#endif

   391

   392

int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,

   393

                                  uint16_t length);

   394

boolean_t e1000_check_mng_mode(struct e1000_hw *hw);

   395

boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);

   396

int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);

   397

int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);

   398

int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);

   399

int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);

   400

int32_t e1000_read_mac_addr(struct e1000_hw * hw);

   401

   402

/* Filters (multicast, vlan, receive) */

   403

uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);

   404

void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);

   405

void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);

   406

void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);

   407

   408

/* LED functions */

   409

int32_t e1000_setup_led(struct e1000_hw *hw);

   410

int32_t e1000_cleanup_led(struct e1000_hw *hw);

   411

int32_t e1000_led_on(struct e1000_hw *hw);

   412

int32_t e1000_led_off(struct e1000_hw *hw);

   413

int32_t e1000_blink_led_start(struct e1000_hw *hw);

   414

   415

/* Adaptive IFS Functions */

   416

   417

/* Everything else */

   418

void e1000_reset_adaptive(struct e1000_hw *hw);

   419

void e1000_update_adaptive(struct e1000_hw *hw);

   420

void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);

   421

void e1000_get_bus_info(struct e1000_hw *hw);

   422

void e1000_pci_set_mwi(struct e1000_hw *hw);

   423

void e1000_pci_clear_mwi(struct e1000_hw *hw);

   424

void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);

   425

void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);

   426

int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value);

   427

/* Port I/O is only supported on 82544 and newer */

   428

void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);

   429

int32_t e1000_disable_pciex_master(struct e1000_hw *hw);

   430

int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);

   431

   432

   433

#define E1000_READ_REG_IO(a, reg) \

   434

    e1000_read_reg_io((a), E1000_##reg)

   435

#define E1000_WRITE_REG_IO(a, reg, val) \

   436

    e1000_write_reg_io((a), E1000_##reg, val)

   437

   438

/* PCI Device IDs */

   439

#define E1000_DEV_ID_82542               0x1000

   440

#define E1000_DEV_ID_82543GC_FIBER       0x1001

   441

#define E1000_DEV_ID_82543GC_COPPER      0x1004

   442

#define E1000_DEV_ID_82544EI_COPPER      0x1008

   443

#define E1000_DEV_ID_82544EI_FIBER       0x1009

   444

#define E1000_DEV_ID_82544GC_COPPER      0x100C

   445

#define E1000_DEV_ID_82544GC_LOM         0x100D

   446

#define E1000_DEV_ID_82540EM             0x100E

   447

#define E1000_DEV_ID_82540EM_LOM         0x1015

   448

#define E1000_DEV_ID_82540EP_LOM         0x1016

   449

#define E1000_DEV_ID_82540EP             0x1017

   450

#define E1000_DEV_ID_82540EP_LP          0x101E

   451

#define E1000_DEV_ID_82545EM_COPPER      0x100F

   452

#define E1000_DEV_ID_82545EM_FIBER       0x1011

   453

#define E1000_DEV_ID_82545GM_COPPER      0x1026

   454

#define E1000_DEV_ID_82545GM_FIBER       0x1027

   455

#define E1000_DEV_ID_82545GM_SERDES      0x1028

   456

#define E1000_DEV_ID_82546EB_COPPER      0x1010

   457

#define E1000_DEV_ID_82546EB_FIBER       0x1012

   458

#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D

   459

#define E1000_DEV_ID_82541EI             0x1013

   460

#define E1000_DEV_ID_82541EI_MOBILE      0x1018

   461

#define E1000_DEV_ID_82541ER_LOM         0x1014

   462

#define E1000_DEV_ID_82541ER             0x1078

   463

#define E1000_DEV_ID_82547GI             0x1075

   464

#define E1000_DEV_ID_82541GI             0x1076

   465

#define E1000_DEV_ID_82541GI_MOBILE      0x1077

   466

#define E1000_DEV_ID_82541GI_LF          0x107C

   467

#define E1000_DEV_ID_82546GB_COPPER      0x1079

   468

#define E1000_DEV_ID_82546GB_FIBER       0x107A

   469

#define E1000_DEV_ID_82546GB_SERDES      0x107B

   470

#define E1000_DEV_ID_82546GB_PCIE        0x108A

   471

#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099

   472

#define E1000_DEV_ID_82547EI             0x1019

   473

#define E1000_DEV_ID_82547EI_MOBILE      0x101A

   474

#define E1000_DEV_ID_82571EB_COPPER      0x105E

   475

#define E1000_DEV_ID_82571EB_FIBER       0x105F

   476

#define E1000_DEV_ID_82571EB_SERDES      0x1060

   477

#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4

   478

#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE  0x10BC

   479

#define E1000_DEV_ID_82572EI_COPPER      0x107D

   480

#define E1000_DEV_ID_82572EI_FIBER       0x107E

   481

#define E1000_DEV_ID_82572EI_SERDES      0x107F

   482

#define E1000_DEV_ID_82572EI             0x10B9

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#define E1000_DEV_ID_82573E              0x108B

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#define E1000_DEV_ID_82573E_IAMT         0x108C

   485

#define E1000_DEV_ID_82573L              0x109A

   486

#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5

   487

#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096

   488

#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098

   489

#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA

   490

#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB

   491

   492

#define E1000_DEV_ID_ICH8_IGP_M_AMT      0x1049

   493

#define E1000_DEV_ID_ICH8_IGP_AMT        0x104A

   494

#define E1000_DEV_ID_ICH8_IGP_C          0x104B

   495

#define E1000_DEV_ID_ICH8_IFE            0x104C

   496

#define E1000_DEV_ID_ICH8_IFE_GT         0x10C4

   497

#define E1000_DEV_ID_ICH8_IFE_G          0x10C5

   498

#define E1000_DEV_ID_ICH8_IGP_M          0x104D

   499

   500

   501

#define NODE_ADDRESS_SIZE 6

   502

#define ETH_LENGTH_OF_ADDRESS 6

   503

   504

/* MAC decode size is 128K - This is the size of BAR0 */

   505

#define MAC_DECODE_SIZE (128 * 1024)

   506

   507

#define E1000_82542_2_0_REV_ID 2

   508

#define E1000_82542_2_1_REV_ID 3

   509

#define E1000_REVISION_0       0

   510

#define E1000_REVISION_1       1

   511

#define E1000_REVISION_2       2

   512

#define E1000_REVISION_3       3

   513

   514

#define SPEED_10    10

   515

#define SPEED_100   100

   516

#define SPEED_1000  1000

   517

#define HALF_DUPLEX 1

   518

#define FULL_DUPLEX 2

   519

   520

/* The sizes (in bytes) of a ethernet packet */

   521

#define ENET_HEADER_SIZE             14

   522

#define MAXIMUM_ETHERNET_FRAME_SIZE  1518 /* With FCS */

   523

#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */

   524

#define ETHERNET_FCS_SIZE            4

   525

#define MAXIMUM_ETHERNET_PACKET_SIZE \

   526

    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)

   527

#define MINIMUM_ETHERNET_PACKET_SIZE \

   528

    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)

   529

#define CRC_LENGTH                   ETHERNET_FCS_SIZE

   530