1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 *

    10

 * vim: noexpandtab

    11

 */

    12

    13

#include <linux/module.h>

    14

#include <linux/moduleparam.h>

    15

#include <linux/pci.h>

    16

#include <linux/netdevice.h>

    17

#include <linux/etherdevice.h>

    18

#include <linux/delay.h>

    19

#include <linux/ethtool.h>

    20

#include <linux/mii.h>

    21

#include <linux/if_vlan.h>

    22

#include <linux/crc32.h>

    23

#include <linux/in.h>

    24

#include <linux/ip.h>

    25

#include <linux/tcp.h>

    26

#include <linux/init.h>

    27

#include <linux/dma-mapping.h>

    28

    29

#include <asm/system.h>

    30

#include <asm/io.h>

    31

#include <asm/irq.h>

    32

    33

#include "../globals.h"

    34

#include "ecdev.h"

    35

    36

#define RTL8169_VERSION "2.3LK-NAPI"

    37

#define MODULENAME "ec_r8169"

    38

#define PFX MODULENAME ": "

    39

    40

#ifdef RTL8169_DEBUG

    41

#define assert(expr) \

    42

	if (!(expr)) {					\

    43

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    44

		#expr,__FILE__,__func__,__LINE__);		\

    45

	}

    46

#define dprintk(fmt, args...) \

    47

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    48

#else

    49

#define assert(expr) do {} while (0)

    50

#define dprintk(fmt, args...)	do {} while (0)

    51

#endif /* RTL8169_DEBUG */

    52

    53

#define R8169_MSG_DEFAULT \

    54

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    55

    56

#define TX_BUFFS_AVAIL(tp) \

    57

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    58

    59

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

    60

static const int max_interrupt_work = 20;

    61

    62

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    63

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    64

static const int multicast_filter_limit = 32;

    65

    66

/* MAC address length */

    67

#define MAC_ADDR_LEN	6

    68

    69

#define MAX_READ_REQUEST_SHIFT	12

    70

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

    71

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    72

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    73

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

    74

#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */

    75

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    76

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    77

    78

#define R8169_REGS_SIZE		256

    79

#define R8169_NAPI_WEIGHT	64

    80

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    81

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    82

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    83

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    84

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    85

    86

#define RTL8169_TX_TIMEOUT	(6*HZ)

    87

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    88

    89

#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)

    90

#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)

    91

#define RTL_EEPROM_SIG_ADDR	0x0000

    92

    93

/* write/read MMIO register */

    94

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

    95

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

    96

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

    97

#define RTL_R8(reg)		readb (ioaddr + (reg))

    98

#define RTL_R16(reg)		readw (ioaddr + (reg))

    99

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

   100

   101

enum mac_version {

   102

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

   103

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

   104

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

   105

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

   106

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

   107

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

   108

	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e

   109

	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e

   110

	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e

   111

	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e

   112

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   113

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be

   114

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb

   115

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?

   116

	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?

   117

	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec

   118

	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf

   119

	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP

   120

	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C

   121

	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C

   122

	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C

   123

	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C

   124

	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP

   125

	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP

   126

	RTL_GIGA_MAC_VER_25 = 0x19  // 8168D

   127

};

   128

   129

#define _R(NAME,MAC,MASK) \

   130

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   131

   132

static const struct {

   133

	const char *name;

   134

	u8 mac_version;

   135

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   136

} rtl_chip_info[] = {

   137

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   138

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   139

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   140

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   141

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   142

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   143

	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E

   144

	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E

   145

	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E

   146

	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E

   147

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   148

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   149

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   150

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   151

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139

   152

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E

   153

	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E

   154

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E

   155

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E

   156

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E

   157

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E

   158

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E

   159

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E

   160

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E

   161

	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E

   162

};

   163

#undef _R

   164

   165

enum cfg_version {

   166

	RTL_CFG_0 = 0x00,

   167

	RTL_CFG_1,

   168

	RTL_CFG_2

   169

};

   170

   171

static void rtl_hw_start_8169(struct net_device *);

   172

static void rtl_hw_start_8168(struct net_device *);

   173

static void rtl_hw_start_8101(struct net_device *);

   174

   175

static struct pci_device_id rtl8169_pci_tbl[] = {

   176

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   177

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   178

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   179

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   180

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   181

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   182

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   183

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   184

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   185

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   186

	{ 0x0001,				0x8168,

   187

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   188

	{0,},

   189

};

   190

   191

/* prevent driver from being loaded automatically */

   192

//MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   193

   194

static int rx_copybreak = 200;

   195

static int use_dac;

   196

static struct {

   197

	u32 msg_enable;

   198

} debug = { -1 };

   199

   200

enum rtl_registers {

   201

	MAC0		= 0,	/* Ethernet hardware address. */

   202

	MAC4		= 4,

   203

	MAR0		= 8,	/* Multicast filter. */

   204

	CounterAddrLow		= 0x10,

   205

	CounterAddrHigh		= 0x14,

   206

	TxDescStartAddrLow	= 0x20,

   207

	TxDescStartAddrHigh	= 0x24,

   208

	TxHDescStartAddrLow	= 0x28,

   209

	TxHDescStartAddrHigh	= 0x2c,

   210

	FLASH		= 0x30,

   211

	ERSR		= 0x36,

   212

	ChipCmd		= 0x37,

   213

	TxPoll		= 0x38,

   214

	IntrMask	= 0x3c,

   215

	IntrStatus	= 0x3e,

   216

	TxConfig	= 0x40,

   217

	RxConfig	= 0x44,

   218

	RxMissed	= 0x4c,

   219

	Cfg9346		= 0x50,

   220

	Config0		= 0x51,

   221

	Config1		= 0x52,

   222

	Config2		= 0x53,

   223

	Config3		= 0x54,

   224

	Config4		= 0x55,

   225

	Config5		= 0x56,

   226

	MultiIntr	= 0x5c,

   227

	PHYAR		= 0x60,

   228

	PHYstatus	= 0x6c,

   229

	RxMaxSize	= 0xda,

   230

	CPlusCmd	= 0xe0,

   231

	IntrMitigate	= 0xe2,

   232

	RxDescAddrLow	= 0xe4,

   233

	RxDescAddrHigh	= 0xe8,

   234

	EarlyTxThres	= 0xec,

   235

	FuncEvent	= 0xf0,

   236

	FuncEventMask	= 0xf4,

   237

	FuncPresetState	= 0xf8,

   238

	FuncForceEvent	= 0xfc,

   239

};

   240

   241

enum rtl8110_registers {

   242

	TBICSR			= 0x64,

   243

	TBI_ANAR		= 0x68,

   244

	TBI_LPAR		= 0x6a,

   245

};

   246

   247

enum rtl8168_8101_registers {

   248

	CSIDR			= 0x64,

   249

	CSIAR			= 0x68,

   250

#define	CSIAR_FLAG			0x80000000

   251

#define	CSIAR_WRITE_CMD			0x80000000

   252

#define	CSIAR_BYTE_ENABLE		0x0f

   253

#define	CSIAR_BYTE_ENABLE_SHIFT		12

   254

#define	CSIAR_ADDR_MASK			0x0fff

   255

   256

	EPHYAR			= 0x80,

   257

#define	EPHYAR_FLAG			0x80000000

   258

#define	EPHYAR_WRITE_CMD		0x80000000

   259

#define	EPHYAR_REG_MASK			0x1f

   260

#define	EPHYAR_REG_SHIFT		16

   261

#define	EPHYAR_DATA_MASK		0xffff

   262

	DBG_REG			= 0xd1,

   263

#define	FIX_NAK_1			(1 << 4)

   264

#define	FIX_NAK_2			(1 << 3)

   265

};

   266

   267

enum rtl_register_content {

   268

	/* InterruptStatusBits */

   269

	SYSErr		= 0x8000,

   270

	PCSTimeout	= 0x4000,

   271

	SWInt		= 0x0100,

   272

	TxDescUnavail	= 0x0080,

   273

	RxFIFOOver	= 0x0040,

   274

	LinkChg		= 0x0020,

   275

	RxOverflow	= 0x0010,

   276

	TxErr		= 0x0008,

   277

	TxOK		= 0x0004,

   278

	RxErr		= 0x0002,

   279

	RxOK		= 0x0001,

   280

   281

	/* RxStatusDesc */

   282

	RxFOVF	= (1 << 23),

   283

	RxRWT	= (1 << 22),

   284

	RxRES	= (1 << 21),

   285

	RxRUNT	= (1 << 20),

   286

	RxCRC	= (1 << 19),

   287

   288

	/* ChipCmdBits */

   289

	CmdReset	= 0x10,

   290

	CmdRxEnb	= 0x08,

   291

	CmdTxEnb	= 0x04,

   292

	RxBufEmpty	= 0x01,

   293

   294

	/* TXPoll register p.5 */

   295

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   296

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   297

	FSWInt		= 0x01,		/* Forced software interrupt */

   298

   299

	/* Cfg9346Bits */

   300

	Cfg9346_Lock	= 0x00,

   301

	Cfg9346_Unlock	= 0xc0,

   302

   303

	/* rx_mode_bits */

   304

	AcceptErr	= 0x20,

   305

	AcceptRunt	= 0x10,

   306

	AcceptBroadcast	= 0x08,

   307

	AcceptMulticast	= 0x04,

   308

	AcceptMyPhys	= 0x02,

   309

	AcceptAllPhys	= 0x01,

   310

   311

	/* RxConfigBits */

   312

	RxCfgFIFOShift	= 13,

   313

	RxCfgDMAShift	=  8,

   314

   315

	/* TxConfigBits */

   316

	TxInterFrameGapShift = 24,

   317

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   318

   319

	/* Config1 register p.24 */

   320

	LEDS1		= (1 << 7),

   321

	LEDS0		= (1 << 6),

   322

	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */

   323

	Speed_down	= (1 << 4),

   324

	MEMMAP		= (1 << 3),

   325

	IOMAP		= (1 << 2),

   326

	VPD		= (1 << 1),

   327

	PMEnable	= (1 << 0),	/* Power Management Enable */

   328

   329

	/* Config2 register p. 25 */

   330

	PCI_Clock_66MHz = 0x01,

   331

	PCI_Clock_33MHz = 0x00,

   332

   333

	/* Config3 register p.25 */

   334

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   335

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   336

	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */

   337

   338

	/* Config5 register p.27 */

   339

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   340

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   341

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   342

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   343

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   344

   345

	/* TBICSR p.28 */

   346

	TBIReset	= 0x80000000,

   347

	TBILoopback	= 0x40000000,

   348

	TBINwEnable	= 0x20000000,

   349

	TBINwRestart	= 0x10000000,

   350

	TBILinkOk	= 0x02000000,

   351

	TBINwComplete	= 0x01000000,

   352

   353

	/* CPlusCmd p.31 */

   354

	EnableBist	= (1 << 15),	// 8168 8101

   355

	Mac_dbgo_oe	= (1 << 14),	// 8168 8101

   356

	Normal_mode	= (1 << 13),	// unused

   357

	Force_half_dup	= (1 << 12),	// 8168 8101

   358

	Force_rxflow_en	= (1 << 11),	// 8168 8101

   359

	Force_txflow_en	= (1 << 10),	// 8168 8101

   360

	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101

   361

	ASF		= (1 << 8),	// 8168 8101

   362

	PktCntrDisable	= (1 << 7),	// 8168 8101

   363

	Mac_dbgo_sel	= 0x001c,	// 8168

   364

	RxVlan		= (1 << 6),

   365

	RxChkSum	= (1 << 5),

   366

	PCIDAC		= (1 << 4),

   367

	PCIMulRW	= (1 << 3),

   368

	INTT_0		= 0x0000,	// 8168

   369

	INTT_1		= 0x0001,	// 8168

   370

	INTT_2		= 0x0002,	// 8168

   371

	INTT_3		= 0x0003,	// 8168

   372

   373

	/* rtl8169_PHYstatus */

   374

	TBI_Enable	= 0x80,

   375

	TxFlowCtrl	= 0x40,

   376

	RxFlowCtrl	= 0x20,

   377

	_1000bpsF	= 0x10,

   378

	_100bps		= 0x08,

   379

	_10bps		= 0x04,

   380

	LinkStatus	= 0x02,

   381

	FullDup		= 0x01,

   382

   383

	/* _TBICSRBit */

   384

	TBILinkOK	= 0x02000000,

   385

   386

	/* DumpCounterCommand */

   387

	CounterDump	= 0x8,

   388

};

   389

   390

enum desc_status_bit {

   391

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   392

	RingEnd		= (1 << 30), /* End of descriptor ring */

   393

	FirstFrag	= (1 << 29), /* First segment of a packet */

   394

	LastFrag	= (1 << 28), /* Final segment of a packet */

   395

   396

	/* Tx private */

   397

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   398

	MSSShift	= 16,        /* MSS value position */

   399

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   400

	IPCS		= (1 << 18), /* Calculate IP checksum */

   401

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   402

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   403

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   404

   405

	/* Rx private */

   406

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   407

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   408

   409

#define RxProtoUDP	(PID1)

   410

#define RxProtoTCP	(PID0)

   411

#define RxProtoIP	(PID1 | PID0)

   412

#define RxProtoMask	RxProtoIP

   413

   414

	IPFail		= (1 << 16), /* IP checksum failed */

   415

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   416

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   417

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   418

};

   419

   420

#define RsvdMask	0x3fffc000

   421

   422

struct TxDesc {

   423

	__le32 opts1;

   424

	__le32 opts2;

   425

	__le64 addr;

   426

};

   427

   428

struct RxDesc {

   429

	__le32 opts1;

   430

	__le32 opts2;

   431

	__le64 addr;

   432

};

   433

   434

struct ring_info {

   435

	struct sk_buff	*skb;

   436

	u32		len;

   437

	u8		__pad[sizeof(void *) - sizeof(u32)];

   438

};

   439

   440

enum features {

   441

	RTL_FEATURE_WOL		= (1 << 0),

   442

	RTL_FEATURE_MSI		= (1 << 1),

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	RTL_FEATURE_GMII	= (1 << 2),

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};

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   446

struct rtl8169_private {

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	void __iomem *mmio_addr;	/* memory map physical address */

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	struct pci_dev *pci_dev;	/* Index of PCI device */

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	struct net_device *dev;

   450

	struct napi_struct napi;

   451

	spinlock_t lock;		/* spin lock flag */

   452

	u32 msg_enable;

   453

	int chipset;

   454

	int mac_version;

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	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   456

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   457

	u32 dirty_rx;

   458

	u32 dirty_tx;

   459

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   460

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   461

	dma_addr_t TxPhyAddr;

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	dma_addr_t RxPhyAddr;

   463

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   464

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

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	unsigned align;

   466

	unsigned rx_buf_sz;

   467

	struct timer_list timer;

   468

	u16 cp_cmd;

   469

	u16 intr_event;

   470

	u16 napi_event;

   471

	u16 intr_mask;

   472

	int phy_auto_nego_reg;

   473

	int phy_1000_ctrl_reg;

   474

#ifdef CONFIG_R8169_VLAN

   475

	struct vlan_group *vlgrp;

   476

#endif

   477

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   478

	int (*get_settings)(struct net_device *, struct ethtool_cmd *);

   479

	void (*phy_reset_enable)(void __iomem *);

   480

	void (*hw_start)(struct net_device *);

   481

	unsigned int (*phy_reset_pending)(void __iomem *);

   482

	unsigned int (*link_ok)(void __iomem *);

   483

	int pcie_cap;

   484

	struct delayed_work task;

   485

	unsigned features;

   486

   487

	struct mii_if_info mii;

   488

   489

	ec_device_t *ecdev;

   490

	unsigned long ec_watchdog_jiffies;

   491

};

   492

   493

MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

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MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver");

   495

module_param(rx_copybreak, int, 0);

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MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

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module_param(use_dac, int, 0);

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MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

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module_param_named(debug, debug.msg_enable, int, 0);

   500

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   501

MODULE_LICENSE("GPL");

   502

MODULE_VERSION(EC_MASTER_VERSION);

   503

   504

static int rtl8169_open(struct net_device *dev);

   505

static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);

   506

static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);

   507

static int rtl8169_init_ring(struct net_device *dev);

   508

static void rtl_hw_start(struct net_device *dev);

   509

static int rtl8169_close(struct net_device *dev);

   510

static void rtl_set_rx_mode(struct net_device *dev);

   511

static void rtl8169_tx_timeout(struct net_device *dev);

   512

static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);

   513

static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,

   514

				void __iomem *, u32 budget);

   515

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);

   516

static void rtl8169_down(struct net_device *dev);

   517

static void rtl8169_rx_clear(struct rtl8169_private *tp);

   518

static void ec_poll(struct net_device *dev);

   519

static int rtl8169_poll(struct napi_struct *napi, int budget);

   520

   521

static const unsigned int rtl8169_rx_config =

   522

	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);

   523

   524

static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)

   525

{

   526

	int i;

   527

   528

	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));

   529