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/*

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 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.

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 *

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 * Note: This driver is a cleanroom reimplementation based on reverse

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 *      engineered documentation written by Carl-Daniel Hailfinger

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 *      and Andrew de Quincey. It's neither supported nor endorsed

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 *      by NVIDIA Corp. Use at your own risk.

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 *

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 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered

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 * trademarks of NVIDIA Corporation in the United States and other

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 * countries.

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 *

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 * Copyright (C) 2003,4,5 Manfred Spraul

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 * Copyright (C) 2004 Andrew de Quincey (wol support)

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 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane

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 *		IRQ rate fixes, bigendian fixes, cleanups, verification)

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 * Copyright (c) 2004 NVIDIA Corporation

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License as published by

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 * the Free Software Foundation; either version 2 of the License, or

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 * (at your option) any later version.

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 *

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 * This program is distributed in the hope that it will be useful,

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 * but WITHOUT ANY WARRANTY; without even the implied warranty of

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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 * GNU General Public License for more details.

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 *

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 * You should have received a copy of the GNU General Public License

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 * along with this program; if not, write to the Free Software

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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

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 *

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 * Changelog:

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 * 	0.01: 05 Oct 2003: First release that compiles without warnings.

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 * 	0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.

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 * 			   Check all PCI BARs for the register window.

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 * 			   udelay added to mii_rw.

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 * 	0.03: 06 Oct 2003: Initialize dev->irq.

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 * 	0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.

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 * 	0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.

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 * 	0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,

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 * 			   irq mask updated

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 * 	0.07: 14 Oct 2003: Further irq mask updates.

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 * 	0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill

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 * 			   added into irq handler, NULL check for drain_ring.

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 * 	0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the

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 * 			   requested interrupt sources.

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 * 	0.10: 20 Oct 2003: First cleanup for release.

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 * 	0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.

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 * 			   MAC Address init fix, set_multicast cleanup.

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 * 	0.12: 23 Oct 2003: Cleanups for release.

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 * 	0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.

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 * 			   Set link speed correctly. start rx before starting

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 * 			   tx (nv_start_rx sets the link speed).

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 * 	0.14: 25 Oct 2003: Nic dependant irq mask.

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 * 	0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during

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 * 			   open.

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 * 	0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size

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 * 			   increased to 1628 bytes.

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 * 	0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from

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 * 			   the tx length.

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 * 	0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats

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 * 	0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac

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 * 			   addresses, really stop rx if already running

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 * 			   in nv_start_rx, clean up a bit.

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 * 	0.20: 07 Dec 2003: alloc fixes

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 * 	0.21: 12 Jan 2004: additional alloc fix, nic polling fix.

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 *	0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup

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 *			   on close.

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 *	0.23: 26 Jan 2004: various small cleanups

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 *	0.24: 27 Feb 2004: make driver even less anonymous in backtraces

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 *	0.25: 09 Mar 2004: wol support

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 *	0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes

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 *	0.27: 19 Jun 2004: Gigabit support, new descriptor rings,

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 *			   added CK804/MCP04 device IDs, code fixes

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 *			   for registers, link status and other minor fixes.

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 *	0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe

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 *	0.29: 31 Aug 2004: Add backup timer for link change notification.

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 *	0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset

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 *			   into nv_close, otherwise reenabling for wol can

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 *			   cause DMA to kfree'd memory.

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 *	0.31: 14 Nov 2004: ethtool support for getting/setting link

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 *			   capabilities.

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 *	0.32: 16 Apr 2005: RX_ERROR4 handling added.

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 *	0.33: 16 May 2005: Support for MCP51 added.

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 *	0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.

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 *	0.35: 26 Jun 2005: Support for MCP55 added.

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 *	0.36: 28 Jun 2005: Add jumbo frame support.

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 *	0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list

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 *	0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of

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 *			   per-packet flags.

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 *	0.39: 18 Jul 2005: Add 64bit descriptor support.

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 *	0.40: 19 Jul 2005: Add support for mac address change.

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 *	0.41: 30 Jul 2005: Write back original MAC in nv_close instead

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 *			   of nv_remove

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 *	0.42: 06 Aug 2005: Fix lack of link speed initialization

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 *			   in the second (and later) nv_open call

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 *	0.43: 10 Aug 2005: Add support for tx checksum.

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 *	0.44: 20 Aug 2005: Add support for scatter gather and segmentation.

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 *	0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check

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 *	0.46: 20 Oct 2005: Add irq optimization modes.

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 *	0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.

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 *	0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single

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 *	0.49: 10 Dec 2005: Fix tso for large buffers.

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 *	0.50: 20 Jan 2006: Add 8021pq tagging support.

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 *	0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.

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 *	0.52: 20 Jan 2006: Add MSI/MSIX support.

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 *	0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.

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 *	0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.

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 *	0.55: 22 Mar 2006: Add flow control (pause frame).

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 *	0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.

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 *	0.57: 14 May 2006: Mac address set in probe/remove and order corrections.

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 *

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 * Known bugs:

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 * We suspect that on some hardware no TX done interrupts are generated.

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 * This means recovery from netif_stop_queue only happens if the hw timer

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 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)

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 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.

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 * If your hardware reliably generates tx done interrupts, then you can remove

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 * DEV_NEED_TIMERIRQ from the driver_data flags.

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 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few

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 * superfluous timer interrupts from the nic.

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 */

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#ifdef CONFIG_FORCEDETH_NAPI

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#define DRIVERNAPI "-NAPI"

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#else

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#define DRIVERNAPI

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#endif

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#define FORCEDETH_VERSION		"0.57"

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#define DRV_NAME			"forcedeth"

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#include <linux/module.h>

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#include <linux/types.h>

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#include <linux/pci.h>

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#include <linux/interrupt.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/delay.h>

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#include <linux/spinlock.h>

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#include <linux/ethtool.h>

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#include <linux/timer.h>

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#include <linux/skbuff.h>

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#include <linux/mii.h>

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#include <linux/random.h>

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#include <linux/init.h>

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#include <linux/if_vlan.h>

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#include <linux/dma-mapping.h>

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#include <asm/irq.h>

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#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/system.h>

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#include "../globals.h"

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#include "ecdev.h"

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#if 0

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#define dprintk			printk

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#else

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#define dprintk(x...)		do { } while (0)

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#endif

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   163

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/*

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 * Hardware access:

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 */

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#define DEV_NEED_TIMERIRQ	0x0001  /* set the timer irq flag in the irq mask */

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#define DEV_NEED_LINKTIMER	0x0002	/* poll link settings. Relies on the timer irq */

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#define DEV_HAS_LARGEDESC	0x0004	/* device supports jumbo frames and needs packet format 2 */

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#define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */

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#define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */

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#define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */

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#define DEV_HAS_MSI             0x0040  /* device supports MSI */

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#define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */

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#define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */

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#define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */

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#define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */

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#define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */

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enum {

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	NvRegIrqStatus = 0x000,

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#define NVREG_IRQSTAT_MIIEVENT	0x040

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#define NVREG_IRQSTAT_MASK		0x1ff

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	NvRegIrqMask = 0x004,

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#define NVREG_IRQ_RX_ERROR		0x0001

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#define NVREG_IRQ_RX			0x0002

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#define NVREG_IRQ_RX_NOBUF		0x0004

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#define NVREG_IRQ_TX_ERR		0x0008

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#define NVREG_IRQ_TX_OK			0x0010

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#define NVREG_IRQ_TIMER			0x0020

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#define NVREG_IRQ_LINK			0x0040

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#define NVREG_IRQ_RX_FORCED		0x0080

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#define NVREG_IRQ_TX_FORCED		0x0100

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#define NVREG_IRQMASK_THROUGHPUT	0x00df

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#define NVREG_IRQMASK_CPU		0x0040

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#define NVREG_IRQ_TX_ALL		(NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)

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#define NVREG_IRQ_RX_ALL		(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)

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#define NVREG_IRQ_OTHER			(NVREG_IRQ_TIMER|NVREG_IRQ_LINK)

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#define NVREG_IRQ_UNKNOWN	(~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \

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					NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \

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					NVREG_IRQ_TX_FORCED))

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	NvRegUnknownSetupReg6 = 0x008,

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#define NVREG_UNKSETUP6_VAL		3

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/*

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 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic

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 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms

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 */

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	NvRegPollingInterval = 0x00c,

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#define NVREG_POLL_DEFAULT_THROUGHPUT	970

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#define NVREG_POLL_DEFAULT_CPU	13

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	NvRegMSIMap0 = 0x020,

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	NvRegMSIMap1 = 0x024,

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	NvRegMSIIrqMask = 0x030,

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#define NVREG_MSI_VECTOR_0_ENABLED 0x01

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	NvRegMisc1 = 0x080,

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#define NVREG_MISC1_PAUSE_TX	0x01

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#define NVREG_MISC1_HD		0x02

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#define NVREG_MISC1_FORCE	0x3b0f3c

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	NvRegMacReset = 0x3c,

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#define NVREG_MAC_RESET_ASSERT	0x0F3

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	NvRegTransmitterControl = 0x084,

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#define NVREG_XMITCTL_START	0x01

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	NvRegTransmitterStatus = 0x088,

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#define NVREG_XMITSTAT_BUSY	0x01

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	NvRegPacketFilterFlags = 0x8c,

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#define NVREG_PFF_PAUSE_RX	0x08

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#define NVREG_PFF_ALWAYS	0x7F0000

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#define NVREG_PFF_PROMISC	0x80

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#define NVREG_PFF_MYADDR	0x20

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#define NVREG_PFF_LOOPBACK	0x10

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	NvRegOffloadConfig = 0x90,

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#define NVREG_OFFLOAD_HOMEPHY	0x601

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#define NVREG_OFFLOAD_NORMAL	RX_NIC_BUFSIZE

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	NvRegReceiverControl = 0x094,

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#define NVREG_RCVCTL_START	0x01

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	NvRegReceiverStatus = 0x98,

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#define NVREG_RCVSTAT_BUSY	0x01

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	NvRegRandomSeed = 0x9c,

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#define NVREG_RNDSEED_MASK	0x00ff

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#define NVREG_RNDSEED_FORCE	0x7f00

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#define NVREG_RNDSEED_FORCE2	0x2d00

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#define NVREG_RNDSEED_FORCE3	0x7400

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	NvRegTxDeferral = 0xA0,

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#define NVREG_TX_DEFERRAL_DEFAULT	0x15050f

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#define NVREG_TX_DEFERRAL_RGMII_10_100	0x16070f

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#define NVREG_TX_DEFERRAL_RGMII_1000	0x14050f

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	NvRegRxDeferral = 0xA4,

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#define NVREG_RX_DEFERRAL_DEFAULT	0x16

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	NvRegMacAddrA = 0xA8,

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	NvRegMacAddrB = 0xAC,

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	NvRegMulticastAddrA = 0xB0,

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#define NVREG_MCASTADDRA_FORCE	0x01

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	NvRegMulticastAddrB = 0xB4,

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	NvRegMulticastMaskA = 0xB8,

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	NvRegMulticastMaskB = 0xBC,

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	NvRegPhyInterface = 0xC0,

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#define PHY_RGMII		0x10000000

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	NvRegTxRingPhysAddr = 0x100,

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	NvRegRxRingPhysAddr = 0x104,

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	NvRegRingSizes = 0x108,

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#define NVREG_RINGSZ_TXSHIFT 0

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#define NVREG_RINGSZ_RXSHIFT 16

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	NvRegTransmitPoll = 0x10c,

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#define NVREG_TRANSMITPOLL_MAC_ADDR_REV	0x00008000

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	NvRegLinkSpeed = 0x110,

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#define NVREG_LINKSPEED_FORCE 0x10000

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#define NVREG_LINKSPEED_10	1000

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#define NVREG_LINKSPEED_100	100

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#define NVREG_LINKSPEED_1000	50

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#define NVREG_LINKSPEED_MASK	(0xFFF)

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	NvRegUnknownSetupReg5 = 0x130,

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#define NVREG_UNKSETUP5_BIT31	(1<<31)

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	NvRegTxWatermark = 0x13c,

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#define NVREG_TX_WM_DESC1_DEFAULT	0x0200010

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#define NVREG_TX_WM_DESC2_3_DEFAULT	0x1e08000

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#define NVREG_TX_WM_DESC2_3_1000	0xfe08000

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	NvRegTxRxControl = 0x144,

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#define NVREG_TXRXCTL_KICK	0x0001

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#define NVREG_TXRXCTL_BIT1	0x0002

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#define NVREG_TXRXCTL_BIT2	0x0004

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#define NVREG_TXRXCTL_IDLE	0x0008

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#define NVREG_TXRXCTL_RESET	0x0010

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#define NVREG_TXRXCTL_RXCHECK	0x0400

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#define NVREG_TXRXCTL_DESC_1	0

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#define NVREG_TXRXCTL_DESC_2	0x02100

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#define NVREG_TXRXCTL_DESC_3	0x02200

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#define NVREG_TXRXCTL_VLANSTRIP 0x00040

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#define NVREG_TXRXCTL_VLANINS	0x00080

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	NvRegTxRingPhysAddrHigh = 0x148,

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	NvRegRxRingPhysAddrHigh = 0x14C,

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	NvRegTxPauseFrame = 0x170,

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#define NVREG_TX_PAUSEFRAME_DISABLE	0x1ff0080

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#define NVREG_TX_PAUSEFRAME_ENABLE	0x0c00030

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	NvRegMIIStatus = 0x180,

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#define NVREG_MIISTAT_ERROR		0x0001

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#define NVREG_MIISTAT_LINKCHANGE	0x0008

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#define NVREG_MIISTAT_MASK		0x000f

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#define NVREG_MIISTAT_MASK2		0x000f

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	NvRegUnknownSetupReg4 = 0x184,

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#define NVREG_UNKSETUP4_VAL	8

   312

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	NvRegAdapterControl = 0x188,

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#define NVREG_ADAPTCTL_START	0x02

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#define NVREG_ADAPTCTL_LINKUP	0x04

   316

#define NVREG_ADAPTCTL_PHYVALID	0x40000

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#define NVREG_ADAPTCTL_RUNNING	0x100000

   318

#define NVREG_ADAPTCTL_PHYSHIFT	24

   319

	NvRegMIISpeed = 0x18c,

   320

#define NVREG_MIISPEED_BIT8	(1<<8)

   321

#define NVREG_MIIDELAY	5

   322

	NvRegMIIControl = 0x190,

   323

#define NVREG_MIICTL_INUSE	0x08000

   324

#define NVREG_MIICTL_WRITE	0x00400

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#define NVREG_MIICTL_ADDRSHIFT	5

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	NvRegMIIData = 0x194,

   327

	NvRegWakeUpFlags = 0x200,

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#define NVREG_WAKEUPFLAGS_VAL		0x7770

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#define NVREG_WAKEUPFLAGS_BUSYSHIFT	24

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#define NVREG_WAKEUPFLAGS_ENABLESHIFT	16

   331

#define NVREG_WAKEUPFLAGS_D3SHIFT	12

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#define NVREG_WAKEUPFLAGS_D2SHIFT	8

   333

#define NVREG_WAKEUPFLAGS_D1SHIFT	4

   334

#define NVREG_WAKEUPFLAGS_D0SHIFT	0

   335

#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT		0x01

   336

#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT	0x02

   337

#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE	0x04

   338

#define NVREG_WAKEUPFLAGS_ENABLE	0x1111

   339

   340

	NvRegPatternCRC = 0x204,

   341

	NvRegPatternMask = 0x208,

   342

	NvRegPowerCap = 0x268,

   343

#define NVREG_POWERCAP_D3SUPP	(1<<30)

   344

#define NVREG_POWERCAP_D2SUPP	(1<<26)

   345

#define NVREG_POWERCAP_D1SUPP	(1<<25)

   346

	NvRegPowerState = 0x26c,

   347

#define NVREG_POWERSTATE_POWEREDUP	0x8000

   348

#define NVREG_POWERSTATE_VALID		0x0100

   349

#define NVREG_POWERSTATE_MASK		0x0003

   350

#define NVREG_POWERSTATE_D0		0x0000

   351

#define NVREG_POWERSTATE_D1		0x0001

   352

#define NVREG_POWERSTATE_D2		0x0002

   353

#define NVREG_POWERSTATE_D3		0x0003

   354

	NvRegTxCnt = 0x280,

   355

	NvRegTxZeroReXmt = 0x284,

   356

	NvRegTxOneReXmt = 0x288,

   357

	NvRegTxManyReXmt = 0x28c,

   358

	NvRegTxLateCol = 0x290,

   359

	NvRegTxUnderflow = 0x294,

   360

	NvRegTxLossCarrier = 0x298,

   361

	NvRegTxExcessDef = 0x29c,

   362

	NvRegTxRetryErr = 0x2a0,

   363

	NvRegRxFrameErr = 0x2a4,

   364

	NvRegRxExtraByte = 0x2a8,

   365

	NvRegRxLateCol = 0x2ac,

   366

	NvRegRxRunt = 0x2b0,

   367

	NvRegRxFrameTooLong = 0x2b4,

   368

	NvRegRxOverflow = 0x2b8,

   369

	NvRegRxFCSErr = 0x2bc,

   370

	NvRegRxFrameAlignErr = 0x2c0,

   371

	NvRegRxLenErr = 0x2c4,

   372

	NvRegRxUnicast = 0x2c8,

   373

	NvRegRxMulticast = 0x2cc,

   374

	NvRegRxBroadcast = 0x2d0,

   375

	NvRegTxDef = 0x2d4,

   376

	NvRegTxFrame = 0x2d8,

   377

	NvRegRxCnt = 0x2dc,

   378

	NvRegTxPause = 0x2e0,

   379

	NvRegRxPause = 0x2e4,

   380

	NvRegRxDropFrame = 0x2e8,

   381

	NvRegVlanControl = 0x300,

   382

#define NVREG_VLANCONTROL_ENABLE	0x2000

   383

	NvRegMSIXMap0 = 0x3e0,

   384

	NvRegMSIXMap1 = 0x3e4,

   385

	NvRegMSIXIrqStatus = 0x3f0,

   386

   387

	NvRegPowerState2 = 0x600,

   388

#define NVREG_POWERSTATE2_POWERUP_MASK		0x0F11

   389

#define NVREG_POWERSTATE2_POWERUP_REV_A3	0x0001

   390

};

   391

   392

/* Big endian: should work, but is untested */

   393

struct ring_desc {

   394

	__le32 buf;

   395

	__le32 flaglen;

   396

};

   397

   398

struct ring_desc_ex {

   399

	__le32 bufhigh;

   400

	__le32 buflow;

   401

	__le32 txvlan;

   402

	__le32 flaglen;

   403

};

   404

   405

union ring_type {

   406

	struct ring_desc* orig;

   407

	struct ring_desc_ex* ex;

   408

};

   409

   410

#define FLAG_MASK_V1 0xffff0000

   411

#define FLAG_MASK_V2 0xffffc000

   412

#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)

   413

#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)

   414

   415

#define NV_TX_LASTPACKET	(1<<16)

   416

#define NV_TX_RETRYERROR	(1<<19)

   417

#define NV_TX_FORCED_INTERRUPT	(1<<24)

   418

#define NV_TX_DEFERRED		(1<<26)

   419

#define NV_TX_CARRIERLOST	(1<<27)

   420

#define NV_TX_LATECOLLISION	(1<<28)

   421

#define NV_TX_UNDERFLOW		(1<<29)

   422

#define NV_TX_ERROR		(1<<30)

   423

#define NV_TX_VALID		(1<<31)

   424

   425

#define NV_TX2_LASTPACKET	(1<<29)

   426

#define NV_TX2_RETRYERROR	(1<<18)

   427

#define NV_TX2_FORCED_INTERRUPT	(1<<30)

   428

#define NV_TX2_DEFERRED		(1<<25)

   429

#define NV_TX2_CARRIERLOST	(1<<26)

   430

#define NV_TX2_LATECOLLISION	(1<<27)

   431

#define NV_TX2_UNDERFLOW	(1<<28)

   432

/* error and valid are the same for both */

   433

#define NV_TX2_ERROR		(1<<30)

   434

#define NV_TX2_VALID		(1<<31)

   435

#define NV_TX2_TSO		(1<<28)

   436

#define NV_TX2_TSO_SHIFT	14

   437

#define NV_TX2_TSO_MAX_SHIFT	14

   438

#define NV_TX2_TSO_MAX_SIZE	(1<<NV_TX2_TSO_MAX_SHIFT)

   439

#define NV_TX2_CHECKSUM_L3	(1<<27)

   440

#define NV_TX2_CHECKSUM_L4	(1<<26)

   441

   442

#define NV_TX3_VLAN_TAG_PRESENT (1<<18)

   443

   444

#define NV_RX_DESCRIPTORVALID	(1<<16)

   445

#define NV_RX_MISSEDFRAME	(1<<17)

   446

#define NV_RX_SUBSTRACT1	(1<<18)

   447

#define NV_RX_ERROR1		(1<<23)

   448

#define NV_RX_ERROR2		(1<<24)

   449

#define NV_RX_ERROR3		(1<<25)

   450

#define NV_RX_ERROR4		(1<<26)

   451

#define NV_RX_CRCERR		(1<<27)

   452

#define NV_RX_OVERFLOW		(1<<28)

   453

#define NV_RX_FRAMINGERR	(1<<29)

   454

#define NV_RX_ERROR		(1<<30)

   455

#define NV_RX_AVAIL		(1<<31)

   456

   457

#define NV_RX2_CHECKSUMMASK	(0x1C000000)

   458

#define NV_RX2_CHECKSUMOK1	(0x10000000)

   459

#define NV_RX2_CHECKSUMOK2	(0x14000000)

   460

#define NV_RX2_CHECKSUMOK3	(0x18000000)

   461

#define NV_RX2_DESCRIPTORVALID	(1<<29)

   462

#define NV_RX2_SUBSTRACT1	(1<<25)

   463

#define NV_RX2_ERROR1		(1<<18)

   464

#define NV_RX2_ERROR2		(1<<19)

   465

#define NV_RX2_ERROR3		(1<<20)

   466

#define NV_RX2_ERROR4		(1<<21)

   467

#define NV_RX2_CRCERR		(1<<22)

   468

#define NV_RX2_OVERFLOW		(1<<23)

   469

#define NV_RX2_FRAMINGERR	(1<<24)

   470

/* error and avail are the same for both */

   471

#define NV_RX2_ERROR		(1<<30)

   472

#define NV_RX2_AVAIL		(1<<31)

   473

   474

#define NV_RX3_VLAN_TAG_PRESENT (1<<16)

   475

#define NV_RX3_VLAN_TAG_MASK	(0x0000FFFF)

   476

   477

/* Miscelaneous hardware related defines: */

   478

#define NV_PCI_REGSZ_VER1      	0x270

   479

#define NV_PCI_REGSZ_VER2      	0x604

   480

   481

/* various timeout delays: all in usec */

   482

#define NV_TXRX_RESET_DELAY	4

   483

#define NV_TXSTOP_DELAY1	10

   484

#define NV_TXSTOP_DELAY1MAX	500000

   485

#define NV_TXSTOP_DELAY2	100

   486

#define NV_RXSTOP_DELAY1	10

   487

#define NV_RXSTOP_DELAY1MAX	500000

   488

#define NV_RXSTOP_DELAY2	100

   489

#define NV_SETUP5_DELAY		5

   490

#define NV_SETUP5_DELAYMAX	50000

   491

#define NV_POWERUP_DELAY	5

   492

#define NV_POWERUP_DELAYMAX	5000

   493

#define NV_MIIBUSY_DELAY	50

   494

#define NV_MIIPHY_DELAY	10

   495

#define NV_MIIPHY_DELAYMAX	10000

   496

#define NV_MAC_RESET_DELAY	64

   497

   498

#define NV_WAKEUPPATTERNS	5

   499

#define NV_WAKEUPMASKENTRIES	4

   500

   501

/* General driver defaults */

   502

#define NV_WATCHDOG_TIMEO	(5*HZ)

   503

   504

#define RX_RING_DEFAULT		128

   505

#define TX_RING_DEFAULT		256

   506

#define RX_RING_MIN		128

   507

#define TX_RING_MIN		64

   508

#define RING_MAX_DESC_VER_1	1024

   509

#define RING_MAX_DESC_VER_2_3	16384

   510

/*

   511

 * Difference between the get and put pointers for the tx ring.

   512

 * This is used to throttle the amount of data outstanding in the

   513

 * tx ring.

   514

 */

   515

#define TX_LIMIT_DIFFERENCE	1

   516

   517

/* rx/tx mac addr + type + vlan + align + slack*/

   518

#define NV_RX_HEADERS		(64)

   519

/* even more slack. */

   520

#define NV_RX_ALLOC_PAD		(64)

   521

   522

/* maximum mtu size */

   523

#define NV_PKTLIMIT_1	ETH_DATA_LEN	/* hard limit not known */

   524

#define NV_PKTLIMIT_2	9100	/* Actual limit according to NVidia: 9202 */

   525

   526

#define OOM_REFILL	(1+HZ/20)

   527

#define POLL_WAIT	(1+HZ/100)

   528

#define LINK_TIMEOUT	(3*HZ)

   529

#define STATS_INTERVAL	(10*HZ)

   530