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/*******************************************************************************

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  Intel PRO/100 Linux driver

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  Copyright(c) 1999 - 2006 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

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    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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*******************************************************************************/

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/*

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 *	e100.c: Intel(R) PRO/100 ethernet driver

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 *

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 *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

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 *	original e100 driver, but better described as a munging of

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 *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

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 *

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 *	References:

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 *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

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 *		Open Source Software Developers Manual,

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 *		http://sourceforge.net/projects/e1000

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 *

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 *

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 *	                      Theory of Operation

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 *

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 *	I.   General

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 *

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 *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

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 *	controller family, which includes the 82557, 82558, 82559, 82550,

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 *	82551, and 82562 devices.  82558 and greater controllers

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 *	integrate the Intel 82555 PHY.  The controllers are used in

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 *	server and client network interface cards, as well as in

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 *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

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 *	configurations.  8255x supports a 32-bit linear addressing

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 *	mode and operates at 33Mhz PCI clock rate.

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 *

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 *	II.  Driver Operation

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 *

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 *	Memory-mapped mode is used exclusively to access the device's

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 *	shared-memory structure, the Control/Status Registers (CSR). All

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 *	setup, configuration, and control of the device, including queuing

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 *	of Tx, Rx, and configuration commands is through the CSR.

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 *	cmd_lock serializes accesses to the CSR command register.  cb_lock

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 *	protects the shared Command Block List (CBL).

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 *

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 *	8255x is highly MII-compliant and all access to the PHY go

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 *	through the Management Data Interface (MDI).  Consequently, the

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 *	driver leverages the mii.c library shared with other MII-compliant

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 *	devices.

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 *

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 *	Big- and Little-Endian byte order as well as 32- and 64-bit

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 *	archs are supported.  Weak-ordered memory and non-cache-coherent

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 *	archs are supported.

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 *

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 *	III. Transmit

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 *

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 *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

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 *	together in a fixed-size ring (CBL) thus forming the flexible mode

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 *	memory structure.  A TCB marked with the suspend-bit indicates

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 *	the end of the ring.  The last TCB processed suspends the

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 *	controller, and the controller can be restarted by issue a CU

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 *	resume command to continue from the suspend point, or a CU start

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 *	command to start at a given position in the ring.

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 *

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 *	Non-Tx commands (config, multicast setup, etc) are linked

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 *	into the CBL ring along with Tx commands.  The common structure

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 *	used for both Tx and non-Tx commands is the Command Block (CB).

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 *

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 *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

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 *	is the next CB to check for completion; cb_to_send is the first

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 *	CB to start on in case of a previous failure to resume.  CB clean

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 *	up happens in interrupt context in response to a CU interrupt.

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 *	cbs_avail keeps track of number of free CB resources available.

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 *

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 * 	Hardware padding of short packets to minimum packet size is

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 * 	enabled.  82557 pads with 7Eh, while the later controllers pad

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 * 	with 00h.

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 *

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 *	IV.  Recieve

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 *

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 *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

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 *	Descriptors (RFD) + data buffer, thus forming the simplified mode

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 *	memory structure.  Rx skbs are allocated to contain both the RFD

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 *	and the data buffer, but the RFD is pulled off before the skb is

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 *	indicated.  The data buffer is aligned such that encapsulated

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 *	protocol headers are u32-aligned.  Since the RFD is part of the

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 *	mapped shared memory, and completion status is contained within

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 *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

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 *	view from software and hardware.

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 *

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 *	Under typical operation, the  receive unit (RU) is start once,

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 *	and the controller happily fills RFDs as frames arrive.  If

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 *	replacement RFDs cannot be allocated, or the RU goes non-active,

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 *	the RU must be restarted.  Frame arrival generates an interrupt,

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 *	and Rx indication and re-allocation happen in the same context,

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 *	therefore no locking is required.  A software-generated interrupt

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 *	is generated from the watchdog to recover from a failed allocation

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 *	senario where all Rx resources have been indicated and none re-

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 *	placed.

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 *

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 *	V.   Miscellaneous

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 *

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 * 	VLAN offloading of tagging, stripping and filtering is not

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 * 	supported, but driver will accommodate the extra 4-byte VLAN tag

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 * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

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 * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

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 * 	not supported (hardware limitation).

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 *

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 * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

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 *

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 * 	Thanks to JC (jchapman@katalix.com) for helping with

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 * 	testing/troubleshooting the development driver.

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 *

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 * 	TODO:

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 * 	o several entry points race with dev->close

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 * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

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 *

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 *	FIXES:

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 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

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 *	- Stratus87247: protect MDI control register manipulations

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 */

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#include <linux/module.h>

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#include <linux/moduleparam.h>

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#include <linux/kernel.h>

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#include <linux/types.h>

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#include <linux/slab.h>

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#include <linux/delay.h>

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#include <linux/init.h>

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#include <linux/pci.h>

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#include <linux/dma-mapping.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/mii.h>

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#include <linux/if_vlan.h>

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#include <linux/skbuff.h>

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#include <linux/ethtool.h>

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#include <linux/string.h>

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#include <asm/unaligned.h>

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#define DRV_NAME		"e100"

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#define DRV_EXT			"-NAPI"

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#define DRV_VERSION		"3.5.23-k4"DRV_EXT

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#define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"

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#define DRV_COPYRIGHT		"Copyright(c) 1999-2006 Intel Corporation"

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#define PFX			DRV_NAME ": "

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#define E100_WATCHDOG_PERIOD	(2 * HZ)

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#define E100_NAPI_WEIGHT	16

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MODULE_DESCRIPTION(DRV_DESCRIPTION);

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MODULE_AUTHOR(DRV_COPYRIGHT);

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MODULE_LICENSE("GPL");

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MODULE_VERSION(DRV_VERSION);

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static int debug = 3;

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static int eeprom_bad_csum_allow = 0;

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static int use_io = 0;

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module_param(debug, int, 0);

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module_param(eeprom_bad_csum_allow, int, 0);

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module_param(use_io, int, 0);

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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

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MODULE_PARM_DESC(use_io, "Force use of i/o access mode");

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#define DPRINTK(nlevel, klevel, fmt, args...) \

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	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

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	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

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		__FUNCTION__ , ## args))

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#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

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	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

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	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

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static struct pci_device_id e100_id_table[] = {

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	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

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	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

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	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

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	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

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	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

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	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

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	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

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	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

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	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

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	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

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	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

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	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

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	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

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	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

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	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

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	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

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	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

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	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

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	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

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	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

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	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

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	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

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	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

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	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

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	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

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	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

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	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

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	{ 0, }

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};

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MODULE_DEVICE_TABLE(pci, e100_id_table);

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enum mac {

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	mac_82557_D100_A  = 0,

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	mac_82557_D100_B  = 1,

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	mac_82557_D100_C  = 2,

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	mac_82558_D101_A4 = 4,

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	mac_82558_D101_B0 = 5,

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	mac_82559_D101M   = 8,

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	mac_82559_D101S   = 9,

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	mac_82550_D102    = 12,

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	mac_82550_D102_C  = 13,

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	mac_82551_E       = 14,

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	mac_82551_F       = 15,

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	mac_82551_10      = 16,

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	mac_unknown       = 0xFF,

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};

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enum phy {

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	phy_100a     = 0x000003E0,

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	phy_100c     = 0x035002A8,

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	phy_82555_tx = 0x015002A8,

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	phy_nsc_tx   = 0x5C002000,

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	phy_82562_et = 0x033002A8,

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	phy_82562_em = 0x032002A8,

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	phy_82562_ek = 0x031002A8,

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	phy_82562_eh = 0x017002A8,

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	phy_unknown  = 0xFFFFFFFF,

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};

   265

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/* CSR (Control/Status Registers) */

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struct csr {

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	struct {

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		u8 status;

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		u8 stat_ack;

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		u8 cmd_lo;

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		u8 cmd_hi;

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		u32 gen_ptr;

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	} scb;

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	u32 port;

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	u16 flash_ctrl;

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	u8 eeprom_ctrl_lo;

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	u8 eeprom_ctrl_hi;

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	u32 mdi_ctrl;

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	u32 rx_dma_count;

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};

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enum scb_status {

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	rus_ready        = 0x10,

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	rus_mask         = 0x3C,

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};

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enum ru_state  {

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	RU_SUSPENDED = 0,

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	RU_RUNNING	 = 1,

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	RU_UNINITIALIZED = -1,

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};

   293

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enum scb_stat_ack {

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	stat_ack_not_ours    = 0x00,

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	stat_ack_sw_gen      = 0x04,

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	stat_ack_rnr         = 0x10,

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	stat_ack_cu_idle     = 0x20,

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	stat_ack_frame_rx    = 0x40,

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	stat_ack_cu_cmd_done = 0x80,

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	stat_ack_not_present = 0xFF,

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	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

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	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

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};

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enum scb_cmd_hi {

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	irq_mask_none = 0x00,

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	irq_mask_all  = 0x01,

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	irq_sw_gen    = 0x02,

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};

   311

   312

enum scb_cmd_lo {

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	cuc_nop        = 0x00,

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	ruc_start      = 0x01,

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	ruc_load_base  = 0x06,

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	cuc_start      = 0x10,

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	cuc_resume     = 0x20,

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	cuc_dump_addr  = 0x40,

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	cuc_dump_stats = 0x50,

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	cuc_load_base  = 0x60,

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	cuc_dump_reset = 0x70,

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};

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enum cuc_dump {

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	cuc_dump_complete       = 0x0000A005,

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	cuc_dump_reset_complete = 0x0000A007,

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};

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enum port {

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	software_reset  = 0x0000,

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	selftest        = 0x0001,

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	selective_reset = 0x0002,

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};

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enum eeprom_ctrl_lo {

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	eesk = 0x01,

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	eecs = 0x02,

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	eedi = 0x04,

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	eedo = 0x08,

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};

   341

   342

enum mdi_ctrl {

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	mdi_write = 0x04000000,

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	mdi_read  = 0x08000000,

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	mdi_ready = 0x10000000,

   346

};

   347

   348

enum eeprom_op {

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	op_write = 0x05,

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	op_read  = 0x06,

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	op_ewds  = 0x10,

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	op_ewen  = 0x13,

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};

   354

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enum eeprom_offsets {

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	eeprom_cnfg_mdix  = 0x03,

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	eeprom_id         = 0x0A,

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	eeprom_config_asf = 0x0D,

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	eeprom_smbus_addr = 0x90,

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};

   361

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enum eeprom_cnfg_mdix {

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	eeprom_mdix_enabled = 0x0080,

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};

   365

   366

enum eeprom_id {

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	eeprom_id_wol = 0x0020,

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};

   369

   370

enum eeprom_config_asf {

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	eeprom_asf = 0x8000,

   372

	eeprom_gcl = 0x4000,

   373

};

   374

   375

enum cb_status {

   376

	cb_complete = 0x8000,

   377

	cb_ok       = 0x2000,

   378

};

   379

   380

enum cb_command {

   381

	cb_nop    = 0x0000,

   382

	cb_iaaddr = 0x0001,

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	cb_config = 0x0002,

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	cb_multi  = 0x0003,

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	cb_tx     = 0x0004,

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	cb_ucode  = 0x0005,

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	cb_dump   = 0x0006,

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	cb_tx_sf  = 0x0008,

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	cb_cid    = 0x1f00,

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	cb_i      = 0x2000,

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	cb_s      = 0x4000,

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	cb_el     = 0x8000,

   393

};

   394

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struct rfd {

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	u16 status;

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	u16 command;

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	u32 link;

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	u32 rbd;

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	u16 actual_size;

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	u16 size;

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};

   403

   404

struct rx {

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	struct rx *next, *prev;

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	struct sk_buff *skb;

   407

	dma_addr_t dma_addr;

   408

};

   409

   410

#if defined(__BIG_ENDIAN_BITFIELD)

   411

#define X(a,b)	b,a

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#else

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#define X(a,b)	a,b

   414

#endif

   415

struct config {

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/*0*/	u8 X(byte_count:6, pad0:2);

   417

/*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

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/*2*/	u8 adaptive_ifs;

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/*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

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	   term_write_cache_line:1), pad3:4);

   421

/*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   422

/*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   423

/*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   424

	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   425

	   rx_discard_overruns:1), rx_save_bad_frames:1);

   426

/*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   427

	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   428

	   tx_dynamic_tbd:1);

   429

/*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   430

/*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   431

	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   432

/*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   433

	   loopback:2);

   434

/*11*/	u8 X(linear_priority:3, pad11:5);

   435

/*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   436

/*13*/	u8 ip_addr_lo;

   437

/*14*/	u8 ip_addr_hi;

   438

/*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   439

	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   440

	   pad15_2:1), crs_or_cdt:1);

   441

/*16*/	u8 fc_delay_lo;

   442

/*17*/	u8 fc_delay_hi;

   443

/*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   444

	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   445

/*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   446

	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   447

	   full_duplex_force:1), full_duplex_pin:1);

   448

/*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   449

/*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   450

/*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   451

	u8 pad_d102[9];

   452

};

   453

   454

#define E100_MAX_MULTICAST_ADDRS	64

   455

struct multi {

   456

	u16 count;

   457

	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   458

};

   459

   460

/* Important: keep total struct u32-aligned */

   461

#define UCODE_SIZE			134

   462

struct cb {

   463

	u16 status;

   464

	u16 command;

   465

	u32 link;

   466

	union {

   467

		u8 iaaddr[ETH_ALEN];

   468

		u32 ucode[UCODE_SIZE];

   469

		struct config config;

   470

		struct multi multi;

   471

		struct {

   472

			u32 tbd_array;

   473

			u16 tcb_byte_count;

   474

			u8 threshold;

   475

			u8 tbd_count;

   476

			struct {

   477

				u32 buf_addr;

   478

				u16 size;

   479

				u16 eol;

   480

			} tbd;

   481

		} tcb;

   482

		u32 dump_buffer_addr;

   483

	} u;

   484

	struct cb *next, *prev;

   485

	dma_addr_t dma_addr;

   486

	struct sk_buff *skb;

   487

};

   488

   489

enum loopback {

   490

	lb_none = 0, lb_mac = 1, lb_phy = 3,

   491

};

   492

   493

struct stats {

   494

	u32 tx_good_frames, tx_max_collisions, tx_late_collisions,

   495

		tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,

   496

		tx_multiple_collisions, tx_total_collisions;

   497

	u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,

   498

		rx_resource_errors, rx_overrun_errors, rx_cdt_errors,

   499

		rx_short_frame_errors;

   500

	u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;

   501

	u16 xmt_tco_frames, rcv_tco_frames;

   502

	u32 complete;

   503

};

   504

   505

struct mem {

   506

	struct {

   507

		u32 signature;

   508

		u32 result;

   509

	} selftest;

   510

	struct stats stats;

   511

	u8 dump_buf[596];

   512

};

   513

   514

struct param_range {

   515

	u32 min;

   516

	u32 max;

   517

	u32 count;

   518

};

   519

   520

struct params {

   521

	struct param_range rfds;

   522

	struct param_range cbs;

   523

};

   524

   525

struct nic {

   526

	/* Begin: frequently used values: keep adjacent for cache effect */

   527

	u32 msg_enable				____cacheline_aligned;

   528

	struct net_device *netdev;

   529

	struct pci_dev *pdev;

   530