|
433
|
1 |
/******************************************************************************
|
|
|
2 |
*
|
|
|
3 |
* $Id$
|
|
|
4 |
*
|
|
|
5 |
* Copyright (C) 2006 Florian Pose, Ingenieurgemeinschaft IgH
|
|
|
6 |
*
|
|
|
7 |
* This file is part of the IgH EtherCAT Master.
|
|
|
8 |
*
|
|
|
9 |
* The IgH EtherCAT Master is free software; you can redistribute it
|
|
|
10 |
* and/or modify it under the terms of the GNU General Public License
|
|
|
11 |
* as published by the Free Software Foundation; either version 2 of the
|
|
|
12 |
* License, or (at your option) any later version.
|
|
|
13 |
*
|
|
|
14 |
* The IgH EtherCAT Master is distributed in the hope that it will be
|
|
|
15 |
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
16 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
17 |
* GNU General Public License for more details.
|
|
|
18 |
*
|
|
|
19 |
* You should have received a copy of the GNU General Public License
|
|
|
20 |
* along with the IgH EtherCAT Master; if not, write to the Free Software
|
|
|
21 |
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
|
22 |
*
|
|
|
23 |
* The right to use EtherCAT Technology is granted and comes free of
|
|
|
24 |
* charge under condition of compatibility of product made by
|
|
|
25 |
* Licensee. People intending to distribute/sell products based on the
|
|
|
26 |
* code, have to sign an agreement to guarantee that products using
|
|
|
27 |
* software based on IgH EtherCAT master stay compatible with the actual
|
|
|
28 |
* EtherCAT specification (which are released themselves as an open
|
|
|
29 |
* standard) as the (only) precondition to have the right to use EtherCAT
|
|
|
30 |
* Technology, IP and trade marks.
|
|
|
31 |
*
|
|
|
32 |
*****************************************************************************/
|
|
|
33 |
|
|
|
34 |
/**
|
|
|
35 |
\file
|
|
|
36 |
EtherCAT slave information interface FSM.
|
|
|
37 |
*/
|
|
|
38 |
|
|
|
39 |
/*****************************************************************************/
|
|
|
40 |
|
|
|
41 |
#include "globals.h"
|
|
|
42 |
#include "mailbox.h"
|
|
|
43 |
#include "master.h"
|
|
|
44 |
#include "fsm_sii.h"
|
|
|
45 |
|
|
|
46 |
/*****************************************************************************/
|
|
|
47 |
|
|
|
48 |
void ec_fsm_sii_start_reading(ec_fsm_sii_t *);
|
|
|
49 |
void ec_fsm_sii_read_check(ec_fsm_sii_t *);
|
|
|
50 |
void ec_fsm_sii_read_fetch(ec_fsm_sii_t *);
|
|
|
51 |
void ec_fsm_sii_start_writing(ec_fsm_sii_t *);
|
|
|
52 |
void ec_fsm_sii_write_check(ec_fsm_sii_t *);
|
|
|
53 |
void ec_fsm_sii_write_check2(ec_fsm_sii_t *);
|
|
|
54 |
void ec_fsm_sii_end(ec_fsm_sii_t *);
|
|
|
55 |
void ec_fsm_sii_error(ec_fsm_sii_t *);
|
|
|
56 |
|
|
|
57 |
/*****************************************************************************/
|
|
|
58 |
|
|
|
59 |
/**
|
|
|
60 |
Constructor.
|
|
|
61 |
*/
|
|
|
62 |
|
|
|
63 |
void ec_fsm_sii_init(ec_fsm_sii_t *fsm, /**< finite state machine */
|
|
|
64 |
ec_datagram_t *datagram /**< datagram structure to use */
|
|
|
65 |
)
|
|
|
66 |
{
|
|
|
67 |
fsm->state = NULL;
|
|
|
68 |
fsm->datagram = datagram;
|
|
|
69 |
}
|
|
|
70 |
|
|
|
71 |
/*****************************************************************************/
|
|
|
72 |
|
|
|
73 |
/**
|
|
|
74 |
Destructor.
|
|
|
75 |
*/
|
|
|
76 |
|
|
|
77 |
void ec_fsm_sii_clear(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
78 |
{
|
|
|
79 |
}
|
|
|
80 |
|
|
|
81 |
/*****************************************************************************/
|
|
|
82 |
|
|
|
83 |
/**
|
|
|
84 |
Initializes the SII read state machine.
|
|
|
85 |
*/
|
|
|
86 |
|
|
|
87 |
void ec_fsm_sii_read(ec_fsm_sii_t *fsm, /**< finite state machine */
|
|
|
88 |
ec_slave_t *slave, /**< slave to read from */
|
|
|
89 |
uint16_t offset, /**< offset to read from */
|
|
|
90 |
ec_fsm_sii_addressing_t mode /**< addressing scheme */
|
|
|
91 |
)
|
|
|
92 |
{
|
|
|
93 |
fsm->state = ec_fsm_sii_start_reading;
|
|
|
94 |
fsm->slave = slave;
|
|
|
95 |
fsm->offset = offset;
|
|
|
96 |
fsm->mode = mode;
|
|
|
97 |
}
|
|
|
98 |
|
|
|
99 |
/*****************************************************************************/
|
|
|
100 |
|
|
|
101 |
/**
|
|
|
102 |
Initializes the SII write state machine.
|
|
|
103 |
*/
|
|
|
104 |
|
|
|
105 |
void ec_fsm_sii_write(ec_fsm_sii_t *fsm, /**< finite state machine */
|
|
|
106 |
ec_slave_t *slave, /**< slave to read from */
|
|
|
107 |
uint16_t offset, /**< offset to read from */
|
|
|
108 |
uint16_t *value, /**< pointer to 2 bytes of data */
|
|
|
109 |
ec_fsm_sii_addressing_t mode /**< addressing scheme */
|
|
|
110 |
)
|
|
|
111 |
{
|
|
|
112 |
fsm->state = ec_fsm_sii_start_writing;
|
|
|
113 |
fsm->slave = slave;
|
|
|
114 |
fsm->offset = offset;
|
|
|
115 |
fsm->mode = mode;
|
|
|
116 |
memcpy(fsm->value, value, 2);
|
|
|
117 |
}
|
|
|
118 |
|
|
|
119 |
/*****************************************************************************/
|
|
|
120 |
|
|
|
121 |
/**
|
|
|
122 |
Executes the SII state machine.
|
|
|
123 |
*/
|
|
|
124 |
|
|
|
125 |
void ec_fsm_sii_exec(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
126 |
{
|
|
|
127 |
fsm->state(fsm);
|
|
|
128 |
}
|
|
|
129 |
|
|
|
130 |
/*****************************************************************************/
|
|
|
131 |
|
|
|
132 |
/**
|
|
|
133 |
Returns the running state of the master startup state machine.
|
|
|
134 |
\return non-zero if not terminated yet.
|
|
|
135 |
*/
|
|
|
136 |
|
|
|
137 |
int ec_fsm_sii_running(ec_fsm_sii_t *fsm /**< Finite state machine */)
|
|
|
138 |
{
|
|
|
139 |
return fsm->state != ec_fsm_sii_end && fsm->state != ec_fsm_sii_error;
|
|
|
140 |
}
|
|
|
141 |
|
|
|
142 |
/*****************************************************************************/
|
|
|
143 |
|
|
|
144 |
/**
|
|
|
145 |
Returns, if the master startup state machine terminated with success.
|
|
|
146 |
\return non-zero if successful.
|
|
|
147 |
*/
|
|
|
148 |
|
|
|
149 |
int ec_fsm_sii_success(ec_fsm_sii_t *fsm /**< Finite state machine */)
|
|
|
150 |
{
|
|
|
151 |
return fsm->state == ec_fsm_sii_end;
|
|
|
152 |
}
|
|
|
153 |
|
|
|
154 |
/******************************************************************************
|
|
|
155 |
* SII state machine
|
|
|
156 |
*****************************************************************************/
|
|
|
157 |
|
|
|
158 |
/**
|
|
|
159 |
SII state: START READING.
|
|
|
160 |
Starts reading the slave information interface.
|
|
|
161 |
*/
|
|
|
162 |
|
|
|
163 |
void ec_fsm_sii_start_reading(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
164 |
{
|
|
|
165 |
ec_datagram_t *datagram = fsm->datagram;
|
|
|
166 |
|
|
|
167 |
// initiate read operation
|
|
|
168 |
switch (fsm->mode) {
|
|
|
169 |
case EC_FSM_SII_POSITION:
|
|
|
170 |
ec_datagram_apwr(datagram, fsm->slave->ring_position, 0x502, 4);
|
|
|
171 |
break;
|
|
|
172 |
case EC_FSM_SII_NODE:
|
|
|
173 |
ec_datagram_npwr(datagram, fsm->slave->station_address, 0x502, 4);
|
|
|
174 |
break;
|
|
|
175 |
}
|
|
|
176 |
|
|
|
177 |
EC_WRITE_U8 (datagram->data, 0x00); // read-only access
|
|
|
178 |
EC_WRITE_U8 (datagram->data + 1, 0x01); // request read operation
|
|
|
179 |
EC_WRITE_U16(datagram->data + 2, fsm->offset);
|
|
|
180 |
ec_master_queue_datagram(fsm->slave->master, datagram);
|
|
|
181 |
fsm->state = ec_fsm_sii_read_check;
|
|
|
182 |
}
|
|
|
183 |
|
|
|
184 |
/*****************************************************************************/
|
|
|
185 |
|
|
|
186 |
/**
|
|
|
187 |
SII state: READ CHECK.
|
|
|
188 |
Checks, if the SII-read-datagram has been sent and issues a fetch datagram.
|
|
|
189 |
*/
|
|
|
190 |
|
|
|
191 |
void ec_fsm_sii_read_check(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
192 |
{
|
|
|
193 |
ec_datagram_t *datagram = fsm->datagram;
|
|
|
194 |
|
|
|
195 |
if (datagram->state != EC_DATAGRAM_RECEIVED
|
|
|
196 |
|| datagram->working_counter != 1) {
|
|
|
197 |
EC_ERR("SII: Reception of read datagram failed.\n");
|
|
|
198 |
fsm->state = ec_fsm_sii_error;
|
|
|
199 |
return;
|
|
|
200 |
}
|
|
|
201 |
|
|
|
202 |
fsm->cycles_start = datagram->cycles_sent;
|
|
|
203 |
fsm->check_once_more = 1;
|
|
|
204 |
|
|
|
205 |
// issue check/fetch datagram
|
|
|
206 |
switch (fsm->mode) {
|
|
|
207 |
case EC_FSM_SII_POSITION:
|
|
|
208 |
ec_datagram_aprd(datagram, fsm->slave->ring_position, 0x502, 10);
|
|
|
209 |
break;
|
|
|
210 |
case EC_FSM_SII_NODE:
|
|
|
211 |
ec_datagram_nprd(datagram, fsm->slave->station_address, 0x502, 10);
|
|
|
212 |
break;
|
|
|
213 |
}
|
|
|
214 |
ec_master_queue_datagram(fsm->slave->master, datagram);
|
|
|
215 |
fsm->state = ec_fsm_sii_read_fetch;
|
|
|
216 |
}
|
|
|
217 |
|
|
|
218 |
/*****************************************************************************/
|
|
|
219 |
|
|
|
220 |
/**
|
|
|
221 |
SII state: READ FETCH.
|
|
|
222 |
Fetches the result of an SII-read datagram.
|
|
|
223 |
*/
|
|
|
224 |
|
|
|
225 |
void ec_fsm_sii_read_fetch(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
226 |
{
|
|
|
227 |
ec_datagram_t *datagram = fsm->datagram;
|
|
|
228 |
|
|
|
229 |
if (datagram->state != EC_DATAGRAM_RECEIVED
|
|
|
230 |
|| datagram->working_counter != 1) {
|
|
|
231 |
EC_ERR("SII: Reception of check/fetch datagram failed.\n");
|
|
|
232 |
fsm->state = ec_fsm_sii_error;
|
|
|
233 |
return;
|
|
|
234 |
}
|
|
|
235 |
|
|
|
236 |
// check "busy bit"
|
|
|
237 |
if (EC_READ_U8(datagram->data + 1) & 0x81) {
|
|
|
238 |
// still busy... timeout?
|
|
|
239 |
if (datagram->cycles_received
|
|
|
240 |
- fsm->cycles_start >= (cycles_t) 10 * cpu_khz) {
|
|
|
241 |
if (!fsm->check_once_more) {
|
|
|
242 |
EC_ERR("SII: Read timeout.\n");
|
|
|
243 |
fsm->state = ec_fsm_sii_error;
|
|
|
244 |
#if 0
|
|
|
245 |
EC_DBG("SII busy: %02X %02X %02X %02X\n",
|
|
|
246 |
EC_READ_U8(datagram->data + 0),
|
|
|
247 |
EC_READ_U8(datagram->data + 1),
|
|
|
248 |
EC_READ_U8(datagram->data + 2),
|
|
|
249 |
EC_READ_U8(datagram->data + 3));
|
|
|
250 |
#endif
|
|
|
251 |
return;
|
|
|
252 |
}
|
|
|
253 |
fsm->check_once_more = 0;
|
|
|
254 |
}
|
|
|
255 |
|
|
|
256 |
// issue check/fetch datagram again
|
|
|
257 |
switch (fsm->mode) {
|
|
|
258 |
case EC_FSM_SII_POSITION:
|
|
|
259 |
ec_datagram_aprd(datagram, fsm->slave->ring_position, 0x502, 10);
|
|
|
260 |
break;
|
|
|
261 |
case EC_FSM_SII_NODE:
|
|
|
262 |
ec_datagram_nprd(datagram, fsm->slave->station_address, 0x502, 10);
|
|
|
263 |
break;
|
|
|
264 |
}
|
|
|
265 |
ec_master_queue_datagram(fsm->slave->master, datagram);
|
|
|
266 |
return;
|
|
|
267 |
}
|
|
|
268 |
|
|
|
269 |
#if 0
|
|
|
270 |
EC_DBG("SII rec: %02X %02X %02X %02X - %02X %02X %02X %02X\n",
|
|
|
271 |
EC_READ_U8(datagram->data + 0), EC_READ_U8(datagram->data + 1),
|
|
|
272 |
EC_READ_U8(datagram->data + 2), EC_READ_U8(datagram->data + 3),
|
|
|
273 |
EC_READ_U8(datagram->data + 6), EC_READ_U8(datagram->data + 7),
|
|
|
274 |
EC_READ_U8(datagram->data + 8), EC_READ_U8(datagram->data + 9));
|
|
|
275 |
#endif
|
|
|
276 |
|
|
|
277 |
// SII value received.
|
|
|
278 |
memcpy(fsm->value, datagram->data + 6, 4);
|
|
|
279 |
fsm->state = ec_fsm_sii_end;
|
|
|
280 |
}
|
|
|
281 |
|
|
|
282 |
/*****************************************************************************/
|
|
|
283 |
|
|
|
284 |
/**
|
|
|
285 |
SII state: START WRITING.
|
|
|
286 |
Starts reading the slave information interface.
|
|
|
287 |
*/
|
|
|
288 |
|
|
|
289 |
void ec_fsm_sii_start_writing(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
290 |
{
|
|
|
291 |
ec_datagram_t *datagram = fsm->datagram;
|
|
|
292 |
|
|
|
293 |
// initiate write operation
|
|
|
294 |
ec_datagram_npwr(datagram, fsm->slave->station_address, 0x502, 8);
|
|
|
295 |
EC_WRITE_U8 (datagram->data, 0x01); // enable write access
|
|
|
296 |
EC_WRITE_U8 (datagram->data + 1, 0x02); // request write operation
|
|
|
297 |
EC_WRITE_U32(datagram->data + 2, fsm->offset);
|
|
|
298 |
memcpy(datagram->data + 6, fsm->value, 2);
|
|
|
299 |
ec_master_queue_datagram(fsm->slave->master, datagram);
|
|
|
300 |
fsm->state = ec_fsm_sii_write_check;
|
|
|
301 |
}
|
|
|
302 |
|
|
|
303 |
/*****************************************************************************/
|
|
|
304 |
|
|
|
305 |
/**
|
|
|
306 |
SII state: WRITE CHECK.
|
|
|
307 |
*/
|
|
|
308 |
|
|
|
309 |
void ec_fsm_sii_write_check(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
310 |
{
|
|
|
311 |
ec_datagram_t *datagram = fsm->datagram;
|
|
|
312 |
|
|
|
313 |
if (datagram->state != EC_DATAGRAM_RECEIVED
|
|
|
314 |
|| datagram->working_counter != 1) {
|
|
|
315 |
EC_ERR("SII: Reception of write datagram failed.\n");
|
|
|
316 |
fsm->state = ec_fsm_sii_error;
|
|
|
317 |
return;
|
|
|
318 |
}
|
|
|
319 |
|
|
|
320 |
fsm->cycles_start = datagram->cycles_sent;
|
|
|
321 |
fsm->check_once_more = 1;
|
|
|
322 |
|
|
|
323 |
// issue check/fetch datagram
|
|
|
324 |
ec_datagram_nprd(datagram, fsm->slave->station_address, 0x502, 2);
|
|
|
325 |
ec_master_queue_datagram(fsm->slave->master, datagram);
|
|
|
326 |
fsm->state = ec_fsm_sii_write_check2;
|
|
|
327 |
}
|
|
|
328 |
|
|
|
329 |
/*****************************************************************************/
|
|
|
330 |
|
|
|
331 |
/**
|
|
|
332 |
SII state: WRITE CHECK 2.
|
|
|
333 |
*/
|
|
|
334 |
|
|
|
335 |
void ec_fsm_sii_write_check2(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
336 |
{
|
|
|
337 |
ec_datagram_t *datagram = fsm->datagram;
|
|
|
338 |
|
|
|
339 |
if (datagram->state != EC_DATAGRAM_RECEIVED
|
|
|
340 |
|| datagram->working_counter != 1) {
|
|
|
341 |
EC_ERR("SII: Reception of write check datagram failed.\n");
|
|
|
342 |
fsm->state = ec_fsm_sii_error;
|
|
|
343 |
return;
|
|
|
344 |
}
|
|
|
345 |
|
|
|
346 |
if (EC_READ_U8(datagram->data + 1) & 0x82) {
|
|
|
347 |
// still busy... timeout?
|
|
|
348 |
if (datagram->cycles_received
|
|
|
349 |
- fsm->cycles_start >= (cycles_t) 10 * cpu_khz) {
|
|
|
350 |
if (!fsm->check_once_more) {
|
|
|
351 |
EC_ERR("SII: Write timeout.\n");
|
|
|
352 |
fsm->state = ec_fsm_sii_error;
|
|
|
353 |
return;
|
|
|
354 |
}
|
|
|
355 |
fsm->check_once_more = 0;
|
|
|
356 |
}
|
|
|
357 |
|
|
|
358 |
// issue check/fetch datagram again
|
|
|
359 |
ec_master_queue_datagram(fsm->slave->master, datagram);
|
|
|
360 |
return;
|
|
|
361 |
}
|
|
|
362 |
|
|
|
363 |
if (EC_READ_U8(datagram->data + 1) & 0x40) {
|
|
|
364 |
EC_ERR("SII: Write operation failed!\n");
|
|
|
365 |
fsm->state = ec_fsm_sii_error;
|
|
|
366 |
return;
|
|
|
367 |
}
|
|
|
368 |
|
|
|
369 |
// success
|
|
|
370 |
fsm->state = ec_fsm_sii_end;
|
|
|
371 |
}
|
|
|
372 |
|
|
|
373 |
/*****************************************************************************/
|
|
|
374 |
|
|
|
375 |
/**
|
|
|
376 |
State: ERROR.
|
|
|
377 |
*/
|
|
|
378 |
|
|
|
379 |
void ec_fsm_sii_error(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
380 |
{
|
|
|
381 |
}
|
|
|
382 |
|
|
|
383 |
/*****************************************************************************/
|
|
|
384 |
|
|
|
385 |
/**
|
|
|
386 |
State: END.
|
|
|
387 |
*/
|
|
|
388 |
|
|
|
389 |
void ec_fsm_sii_end(ec_fsm_sii_t *fsm /**< finite state machine */)
|
|
|
390 |
{
|
|
|
391 |
}
|
|
|
392 |
|
|
|
393 |
/*****************************************************************************/
|