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AnnexF/integral_st.txt
author etisserant
Fri, 05 Oct 2007 10:24:39 +0200
changeset 64 ab704568fa25
parent 0 fb772792efd1
permissions -rwxr-xr-x
Fixed Bitwise negation in ST
0
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
etisserant
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 FUNCTION_BLOCK INTEGRAL
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   VAR_INPUT
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     RUN : BOOL ;       (* 1 = integrate, 0 = hold *)
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
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     R1 : BOOL ;        (* Overriding reset        *)
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
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     XIN : REAL ;       (* Input variable          *)
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
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     X0  : REAL ;       (* Initial value           *)
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
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     CYCLE : TIME ;     (* Sampling period         *)
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
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   END_VAR
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   VAR_OUTPUT
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     Q : BOOL ;         (* NOT R1                  *)
fb772792efd1 Initial commit. Last MatPLC CVS with some makefile inclusion removed in order to compile fine out of MatPLC.
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     XOUT : REAL ;      (* Integrated output       *)
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   END_VAR
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   Q := NOT R1 ;
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   IF R1 THEN XOUT := X0 ;
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   ELSIF RUN THEN XOUT := XOUT + XIN * TIME_TO_REAL(CYCLE);
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   END_IF ;
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 END_FUNCTION_BLOCK
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