# HG changeset patch # User Florian Pose # Date 1142612702 0 # Node ID d6679c77ad3f8c6f9f5befb53a1805a4babf5246 # Parent fad6709a526f8f28bd3bc258ac57e1def2c77dc5 ecrt_master_prepare_async_io() hinzugef?gt. diff -r fad6709a526f -r d6679c77ad3f include/ecrt.h --- a/include/ecrt.h Fri Mar 17 15:18:13 2006 +0000 +++ b/include/ecrt.h Fri Mar 17 16:25:02 2006 +0000 @@ -49,6 +49,7 @@ void ecrt_master_sync_io(ec_master_t *master); void ecrt_master_async_send(ec_master_t *master); void ecrt_master_async_receive(ec_master_t *master); +void ecrt_master_prepare_async_io(ec_master_t *master); void ecrt_master_debug(ec_master_t *master, int level); void ecrt_master_print(const ec_master_t *master); int ecrt_master_sdo_write(ec_master_t *master, diff -r fad6709a526f -r d6679c77ad3f master/master.c --- a/master/master.c Fri Mar 17 15:18:13 2006 +0000 +++ b/master/master.c Fri Mar 17 16:25:02 2006 +0000 @@ -100,6 +100,7 @@ master->command_index = 0; master->debug_level = 0; + master->timeout = 100; // us master->stats.timeouts = 0; master->stats.delayed = 0; master->stats.corrupted = 0; @@ -857,7 +858,7 @@ ec_master_send_commands(master); t_start = get_cycles(); // Sendezeit nehmen - t_timeout = 100 * cpu_khz / 1000; // 100us + t_timeout = master->timeout * cpu_khz / 1000; do { ec_device_call_isr(master->device); @@ -960,6 +961,37 @@ /*****************************************************************************/ /** + Bereitet Synchronen Datenverkehr vor. + + Fürgt einmal die Kommandos aller Domains zur Warteschlange hinzu, sendet + diese ab und wartet so lange, bis diese anschließend problemlos empfangen + werden können. +*/ + +void ecrt_master_prepare_async_io(ec_master_t *master) +{ + ec_domain_t *domain; + cycles_t t_start, t_end, t_timeout; + + // Alle empfangenen Kommandos aus der Liste entfernen + list_for_each_entry(domain, &master->domains, list) + ecrt_domain_queue(domain); + + ecrt_master_async_send(master); + + t_start = get_cycles(); // Sendezeit nehmen + t_timeout = master->timeout * cpu_khz / 1000; + + // Aktiv warten! + do { + t_end = get_cycles(); + } + while (t_end - t_start < t_timeout); +} + +/*****************************************************************************/ + +/** Setzt die Debug-Ebene des Masters. Folgende Debug-Level sind definiert: diff -r fad6709a526f -r d6679c77ad3f master/master.h --- a/master/master.h Fri Mar 17 15:18:13 2006 +0000 +++ b/master/master.h Fri Mar 17 16:25:02 2006 +0000 @@ -52,6 +52,7 @@ struct list_head domains; /**< Liste der Prozessdatendomänen */ int debug_level; /**< Debug-Level im Master-Code */ ec_stats_t stats; /**< Rahmen-Statistiken */ + unsigned int timeout; /**< Timeout für synchronen Datenaustausch */ }; /*****************************************************************************/ diff -r fad6709a526f -r d6679c77ad3f mini/mini.c --- a/mini/mini.c Fri Mar 17 15:18:13 2006 +0000 +++ b/mini/mini.c Fri Mar 17 16:25:02 2006 +0000 @@ -14,7 +14,7 @@ #include "../include/ecrt.h" // Echtzeitschnittstelle -//#define ASYNC +#define ASYNC /*****************************************************************************/ @@ -115,9 +115,8 @@ } #ifdef ASYNC - ecrt_domain_queue(domain1); - ecrt_master_async_send(master); - udelay(100); + // Einmal senden und warten... + ecrt_master_prepare_async_io(master); #endif printk("Starting cyclic sample thread.\n"); diff -r fad6709a526f -r d6679c77ad3f rt/msr_module.c --- a/rt/msr_module.c Fri Mar 17 15:18:13 2006 +0000 +++ b/rt/msr_module.c Fri Mar 17 16:25:02 2006 +0000 @@ -37,7 +37,7 @@ // EtherCAT #include "../include/ecrt.h" -//#define ASYNC +#define ASYNC // Defines/Makros #define HZREDUCTION (MSR_ABTASTFREQUENZ / HZ) @@ -229,10 +229,8 @@ #endif #ifdef ASYNC - ecrt_domain_queue(domain1); - ecrt_domain_queue(domain2); - ecrt_master_async_send(master); - udelay(100); + // Einmal senden und warten... + ecrt_master_prepare_async_io(master); #endif ipipe_init_attr(&attr);