diff -r 5a8959f77854 -r d4e0380d63b3 master/fsm_sii.c
--- a/master/fsm_sii.c	Mon Mar 17 09:06:21 2008 +0000
+++ b/master/fsm_sii.c	Mon Mar 17 09:38:48 2008 +0000
@@ -46,12 +46,12 @@
 /**
  * Read/Write timeout. [ms]
  */
-#define EEPROM_TIMEOUT 10
+#define SII_TIMEOUT 10
 
 /**
  * Time before evaluating answer at writing. [ms]
  */
-#define EEPROM_INHIBIT  5
+#define SII_INHIBIT  5
 
 //#define SII_DEBUG
 
@@ -290,7 +290,7 @@
 												 // read operation busy
         // still busy... timeout?
         if (datagram->cycles_received
-            - fsm->cycles_start >= (cycles_t) EEPROM_TIMEOUT * cpu_khz) {
+            - fsm->cycles_start >= (cycles_t) SII_TIMEOUT * cpu_khz) {
             if (fsm->check_once_more) {
 				fsm->check_once_more = 0;
 			} else {
@@ -426,7 +426,7 @@
 	/* FIXME: some slaves never answer with the busy flag set...
 	 * wait a few ms for the write operation to complete. */
 	if (datagram->cycles_received - fsm->cycles_start
-			< (cycles_t) EEPROM_INHIBIT * cpu_khz) {
+			< (cycles_t) SII_INHIBIT * cpu_khz) {
 #ifdef SII_DEBUG
 		EC_DBG("too early.\n");
 #endif
@@ -439,7 +439,7 @@
 												 // write operation busy bit
         // still busy... timeout?
         if (datagram->cycles_received
-            - fsm->cycles_start >= (cycles_t) EEPROM_TIMEOUT * cpu_khz) {
+            - fsm->cycles_start >= (cycles_t) SII_TIMEOUT * cpu_khz) {
             if (fsm->check_once_more) {
 				fsm->check_once_more = 0;
 			} else {