fp@583: /*
fp@583: * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
fp@583: *
fp@583: * Note: This driver is a cleanroom reimplementation based on reverse
fp@583: * engineered documentation written by Carl-Daniel Hailfinger
fp@583: * and Andrew de Quincey. It's neither supported nor endorsed
fp@583: * by NVIDIA Corp. Use at your own risk.
fp@583: *
fp@583: * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
fp@583: * trademarks of NVIDIA Corporation in the United States and other
fp@583: * countries.
fp@583: *
fp@583: * Copyright (C) 2003,4,5 Manfred Spraul
fp@583: * Copyright (C) 2004 Andrew de Quincey (wol support)
fp@583: * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
fp@583: * IRQ rate fixes, bigendian fixes, cleanups, verification)
fp@583: * Copyright (c) 2004 NVIDIA Corporation
fp@583: *
fp@583: * This program is free software; you can redistribute it and/or modify
fp@583: * it under the terms of the GNU General Public License as published by
fp@583: * the Free Software Foundation; either version 2 of the License, or
fp@583: * (at your option) any later version.
fp@583: *
fp@583: * This program is distributed in the hope that it will be useful,
fp@583: * but WITHOUT ANY WARRANTY; without even the implied warranty of
fp@583: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
fp@583: * GNU General Public License for more details.
fp@583: *
fp@583: * You should have received a copy of the GNU General Public License
fp@583: * along with this program; if not, write to the Free Software
fp@583: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
fp@583: *
fp@583: * Changelog:
fp@583: * 0.01: 05 Oct 2003: First release that compiles without warnings.
fp@583: * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
fp@583: * Check all PCI BARs for the register window.
fp@583: * udelay added to mii_rw.
fp@583: * 0.03: 06 Oct 2003: Initialize dev->irq.
fp@583: * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
fp@583: * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
fp@583: * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
fp@583: * irq mask updated
fp@583: * 0.07: 14 Oct 2003: Further irq mask updates.
fp@583: * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
fp@583: * added into irq handler, NULL check for drain_ring.
fp@583: * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
fp@583: * requested interrupt sources.
fp@583: * 0.10: 20 Oct 2003: First cleanup for release.
fp@583: * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
fp@583: * MAC Address init fix, set_multicast cleanup.
fp@583: * 0.12: 23 Oct 2003: Cleanups for release.
fp@583: * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
fp@583: * Set link speed correctly. start rx before starting
fp@583: * tx (nv_start_rx sets the link speed).
fp@583: * 0.14: 25 Oct 2003: Nic dependant irq mask.
fp@583: * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
fp@583: * open.
fp@583: * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
fp@583: * increased to 1628 bytes.
fp@583: * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
fp@583: * the tx length.
fp@583: * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
fp@583: * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
fp@583: * addresses, really stop rx if already running
fp@583: * in nv_start_rx, clean up a bit.
fp@583: * 0.20: 07 Dec 2003: alloc fixes
fp@583: * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
fp@583: * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
fp@583: * on close.
fp@583: * 0.23: 26 Jan 2004: various small cleanups
fp@583: * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
fp@583: * 0.25: 09 Mar 2004: wol support
fp@583: * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
fp@583: * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
fp@583: * added CK804/MCP04 device IDs, code fixes
fp@583: * for registers, link status and other minor fixes.
fp@583: * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
fp@583: * 0.29: 31 Aug 2004: Add backup timer for link change notification.
fp@583: * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
fp@583: * into nv_close, otherwise reenabling for wol can
fp@583: * cause DMA to kfree'd memory.
fp@583: * 0.31: 14 Nov 2004: ethtool support for getting/setting link
fp@583: * capabilities.
fp@583: * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
fp@583: * 0.33: 16 May 2005: Support for MCP51 added.
fp@583: * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
fp@583: * 0.35: 26 Jun 2005: Support for MCP55 added.
fp@583: * 0.36: 28 Jun 2005: Add jumbo frame support.
fp@583: * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
fp@583: * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
fp@583: * per-packet flags.
fp@583: * 0.39: 18 Jul 2005: Add 64bit descriptor support.
fp@583: * 0.40: 19 Jul 2005: Add support for mac address change.
fp@583: * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
fp@583: * of nv_remove
fp@583: * 0.42: 06 Aug 2005: Fix lack of link speed initialization
fp@583: * in the second (and later) nv_open call
fp@583: * 0.43: 10 Aug 2005: Add support for tx checksum.
fp@583: * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
fp@583: * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
fp@583: * 0.46: 20 Oct 2005: Add irq optimization modes.
fp@583: * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
fp@583: * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
fp@583: * 0.49: 10 Dec 2005: Fix tso for large buffers.
fp@583: * 0.50: 20 Jan 2006: Add 8021pq tagging support.
fp@583: * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
fp@583: * 0.52: 20 Jan 2006: Add MSI/MSIX support.
fp@583: * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
fp@583: * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
fp@583: * 0.55: 22 Mar 2006: Add flow control (pause frame).
fp@583: * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
fp@583: * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
fp@583: *
fp@583: * Known bugs:
fp@583: * We suspect that on some hardware no TX done interrupts are generated.
fp@583: * This means recovery from netif_stop_queue only happens if the hw timer
fp@583: * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
fp@583: * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
fp@583: * If your hardware reliably generates tx done interrupts, then you can remove
fp@583: * DEV_NEED_TIMERIRQ from the driver_data flags.
fp@583: * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
fp@583: * superfluous timer interrupts from the nic.
fp@583: */
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: #define DRIVERNAPI "-NAPI"
fp@583: #else
fp@583: #define DRIVERNAPI
fp@583: #endif
fp@583: #define FORCEDETH_VERSION "0.57"
fp@583: #define DRV_NAME "forcedeth"
fp@583:
fp@583: #include <linux/module.h>
fp@583: #include <linux/types.h>
fp@583: #include <linux/pci.h>
fp@583: #include <linux/interrupt.h>
fp@583: #include <linux/netdevice.h>
fp@583: #include <linux/etherdevice.h>
fp@583: #include <linux/delay.h>
fp@583: #include <linux/spinlock.h>
fp@583: #include <linux/ethtool.h>
fp@583: #include <linux/timer.h>
fp@583: #include <linux/skbuff.h>
fp@583: #include <linux/mii.h>
fp@583: #include <linux/random.h>
fp@583: #include <linux/init.h>
fp@583: #include <linux/if_vlan.h>
fp@583: #include <linux/dma-mapping.h>
fp@583:
fp@583: #include <asm/irq.h>
fp@583: #include <asm/io.h>
fp@583: #include <asm/uaccess.h>
fp@583: #include <asm/system.h>
fp@583:
fp@583: #include "../globals.h"
fp@583: #include "ecdev.h"
fp@583:
fp@583: #if 0
fp@583: #define dprintk printk
fp@583: #else
fp@583: #define dprintk(x...) do { } while (0)
fp@583: #endif
fp@583:
fp@583:
fp@583: /*
fp@583: * Hardware access:
fp@583: */
fp@583:
fp@583: #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
fp@583: #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
fp@583: #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
fp@583: #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
fp@583: #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
fp@583: #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
fp@583: #define DEV_HAS_MSI 0x0040 /* device supports MSI */
fp@583: #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
fp@583: #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
fp@583: #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
fp@583: #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
fp@583: #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
fp@583:
fp@583: enum {
fp@583: NvRegIrqStatus = 0x000,
fp@583: #define NVREG_IRQSTAT_MIIEVENT 0x040
fp@583: #define NVREG_IRQSTAT_MASK 0x1ff
fp@583: NvRegIrqMask = 0x004,
fp@583: #define NVREG_IRQ_RX_ERROR 0x0001
fp@583: #define NVREG_IRQ_RX 0x0002
fp@583: #define NVREG_IRQ_RX_NOBUF 0x0004
fp@583: #define NVREG_IRQ_TX_ERR 0x0008
fp@583: #define NVREG_IRQ_TX_OK 0x0010
fp@583: #define NVREG_IRQ_TIMER 0x0020
fp@583: #define NVREG_IRQ_LINK 0x0040
fp@583: #define NVREG_IRQ_RX_FORCED 0x0080
fp@583: #define NVREG_IRQ_TX_FORCED 0x0100
fp@583: #define NVREG_IRQMASK_THROUGHPUT 0x00df
fp@583: #define NVREG_IRQMASK_CPU 0x0040
fp@583: #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
fp@583: #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
fp@583: #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
fp@583:
fp@583: #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
fp@583: NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
fp@583: NVREG_IRQ_TX_FORCED))
fp@583:
fp@583: NvRegUnknownSetupReg6 = 0x008,
fp@583: #define NVREG_UNKSETUP6_VAL 3
fp@583:
fp@583: /*
fp@583: * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
fp@583: * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
fp@583: */
fp@583: NvRegPollingInterval = 0x00c,
fp@583: #define NVREG_POLL_DEFAULT_THROUGHPUT 970
fp@583: #define NVREG_POLL_DEFAULT_CPU 13
fp@583: NvRegMSIMap0 = 0x020,
fp@583: NvRegMSIMap1 = 0x024,
fp@583: NvRegMSIIrqMask = 0x030,
fp@583: #define NVREG_MSI_VECTOR_0_ENABLED 0x01
fp@583: NvRegMisc1 = 0x080,
fp@583: #define NVREG_MISC1_PAUSE_TX 0x01
fp@583: #define NVREG_MISC1_HD 0x02
fp@583: #define NVREG_MISC1_FORCE 0x3b0f3c
fp@583:
fp@583: NvRegMacReset = 0x3c,
fp@583: #define NVREG_MAC_RESET_ASSERT 0x0F3
fp@583: NvRegTransmitterControl = 0x084,
fp@583: #define NVREG_XMITCTL_START 0x01
fp@583: NvRegTransmitterStatus = 0x088,
fp@583: #define NVREG_XMITSTAT_BUSY 0x01
fp@583:
fp@583: NvRegPacketFilterFlags = 0x8c,
fp@583: #define NVREG_PFF_PAUSE_RX 0x08
fp@583: #define NVREG_PFF_ALWAYS 0x7F0000
fp@583: #define NVREG_PFF_PROMISC 0x80
fp@583: #define NVREG_PFF_MYADDR 0x20
fp@583: #define NVREG_PFF_LOOPBACK 0x10
fp@583:
fp@583: NvRegOffloadConfig = 0x90,
fp@583: #define NVREG_OFFLOAD_HOMEPHY 0x601
fp@583: #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
fp@583: NvRegReceiverControl = 0x094,
fp@583: #define NVREG_RCVCTL_START 0x01
fp@583: NvRegReceiverStatus = 0x98,
fp@583: #define NVREG_RCVSTAT_BUSY 0x01
fp@583:
fp@583: NvRegRandomSeed = 0x9c,
fp@583: #define NVREG_RNDSEED_MASK 0x00ff
fp@583: #define NVREG_RNDSEED_FORCE 0x7f00
fp@583: #define NVREG_RNDSEED_FORCE2 0x2d00
fp@583: #define NVREG_RNDSEED_FORCE3 0x7400
fp@583:
fp@583: NvRegTxDeferral = 0xA0,
fp@583: #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
fp@583: #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
fp@583: #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
fp@583: NvRegRxDeferral = 0xA4,
fp@583: #define NVREG_RX_DEFERRAL_DEFAULT 0x16
fp@583: NvRegMacAddrA = 0xA8,
fp@583: NvRegMacAddrB = 0xAC,
fp@583: NvRegMulticastAddrA = 0xB0,
fp@583: #define NVREG_MCASTADDRA_FORCE 0x01
fp@583: NvRegMulticastAddrB = 0xB4,
fp@583: NvRegMulticastMaskA = 0xB8,
fp@583: NvRegMulticastMaskB = 0xBC,
fp@583:
fp@583: NvRegPhyInterface = 0xC0,
fp@583: #define PHY_RGMII 0x10000000
fp@583:
fp@583: NvRegTxRingPhysAddr = 0x100,
fp@583: NvRegRxRingPhysAddr = 0x104,
fp@583: NvRegRingSizes = 0x108,
fp@583: #define NVREG_RINGSZ_TXSHIFT 0
fp@583: #define NVREG_RINGSZ_RXSHIFT 16
fp@583: NvRegTransmitPoll = 0x10c,
fp@583: #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
fp@583: NvRegLinkSpeed = 0x110,
fp@583: #define NVREG_LINKSPEED_FORCE 0x10000
fp@583: #define NVREG_LINKSPEED_10 1000
fp@583: #define NVREG_LINKSPEED_100 100
fp@583: #define NVREG_LINKSPEED_1000 50
fp@583: #define NVREG_LINKSPEED_MASK (0xFFF)
fp@583: NvRegUnknownSetupReg5 = 0x130,
fp@583: #define NVREG_UNKSETUP5_BIT31 (1<<31)
fp@583: NvRegTxWatermark = 0x13c,
fp@583: #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
fp@583: #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
fp@583: #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
fp@583: NvRegTxRxControl = 0x144,
fp@583: #define NVREG_TXRXCTL_KICK 0x0001
fp@583: #define NVREG_TXRXCTL_BIT1 0x0002
fp@583: #define NVREG_TXRXCTL_BIT2 0x0004
fp@583: #define NVREG_TXRXCTL_IDLE 0x0008
fp@583: #define NVREG_TXRXCTL_RESET 0x0010
fp@583: #define NVREG_TXRXCTL_RXCHECK 0x0400
fp@583: #define NVREG_TXRXCTL_DESC_1 0
fp@583: #define NVREG_TXRXCTL_DESC_2 0x02100
fp@583: #define NVREG_TXRXCTL_DESC_3 0x02200
fp@583: #define NVREG_TXRXCTL_VLANSTRIP 0x00040
fp@583: #define NVREG_TXRXCTL_VLANINS 0x00080
fp@583: NvRegTxRingPhysAddrHigh = 0x148,
fp@583: NvRegRxRingPhysAddrHigh = 0x14C,
fp@583: NvRegTxPauseFrame = 0x170,
fp@583: #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
fp@583: #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
fp@583: NvRegMIIStatus = 0x180,
fp@583: #define NVREG_MIISTAT_ERROR 0x0001
fp@583: #define NVREG_MIISTAT_LINKCHANGE 0x0008
fp@583: #define NVREG_MIISTAT_MASK 0x000f
fp@583: #define NVREG_MIISTAT_MASK2 0x000f
fp@583: NvRegUnknownSetupReg4 = 0x184,
fp@583: #define NVREG_UNKSETUP4_VAL 8
fp@583:
fp@583: NvRegAdapterControl = 0x188,
fp@583: #define NVREG_ADAPTCTL_START 0x02
fp@583: #define NVREG_ADAPTCTL_LINKUP 0x04
fp@583: #define NVREG_ADAPTCTL_PHYVALID 0x40000
fp@583: #define NVREG_ADAPTCTL_RUNNING 0x100000
fp@583: #define NVREG_ADAPTCTL_PHYSHIFT 24
fp@583: NvRegMIISpeed = 0x18c,
fp@583: #define NVREG_MIISPEED_BIT8 (1<<8)
fp@583: #define NVREG_MIIDELAY 5
fp@583: NvRegMIIControl = 0x190,
fp@583: #define NVREG_MIICTL_INUSE 0x08000
fp@583: #define NVREG_MIICTL_WRITE 0x00400
fp@583: #define NVREG_MIICTL_ADDRSHIFT 5
fp@583: NvRegMIIData = 0x194,
fp@583: NvRegWakeUpFlags = 0x200,
fp@583: #define NVREG_WAKEUPFLAGS_VAL 0x7770
fp@583: #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
fp@583: #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
fp@583: #define NVREG_WAKEUPFLAGS_D3SHIFT 12
fp@583: #define NVREG_WAKEUPFLAGS_D2SHIFT 8
fp@583: #define NVREG_WAKEUPFLAGS_D1SHIFT 4
fp@583: #define NVREG_WAKEUPFLAGS_D0SHIFT 0
fp@583: #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
fp@583: #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
fp@583: #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
fp@583: #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
fp@583:
fp@583: NvRegPatternCRC = 0x204,
fp@583: NvRegPatternMask = 0x208,
fp@583: NvRegPowerCap = 0x268,
fp@583: #define NVREG_POWERCAP_D3SUPP (1<<30)
fp@583: #define NVREG_POWERCAP_D2SUPP (1<<26)
fp@583: #define NVREG_POWERCAP_D1SUPP (1<<25)
fp@583: NvRegPowerState = 0x26c,
fp@583: #define NVREG_POWERSTATE_POWEREDUP 0x8000
fp@583: #define NVREG_POWERSTATE_VALID 0x0100
fp@583: #define NVREG_POWERSTATE_MASK 0x0003
fp@583: #define NVREG_POWERSTATE_D0 0x0000
fp@583: #define NVREG_POWERSTATE_D1 0x0001
fp@583: #define NVREG_POWERSTATE_D2 0x0002
fp@583: #define NVREG_POWERSTATE_D3 0x0003
fp@583: NvRegTxCnt = 0x280,
fp@583: NvRegTxZeroReXmt = 0x284,
fp@583: NvRegTxOneReXmt = 0x288,
fp@583: NvRegTxManyReXmt = 0x28c,
fp@583: NvRegTxLateCol = 0x290,
fp@583: NvRegTxUnderflow = 0x294,
fp@583: NvRegTxLossCarrier = 0x298,
fp@583: NvRegTxExcessDef = 0x29c,
fp@583: NvRegTxRetryErr = 0x2a0,
fp@583: NvRegRxFrameErr = 0x2a4,
fp@583: NvRegRxExtraByte = 0x2a8,
fp@583: NvRegRxLateCol = 0x2ac,
fp@583: NvRegRxRunt = 0x2b0,
fp@583: NvRegRxFrameTooLong = 0x2b4,
fp@583: NvRegRxOverflow = 0x2b8,
fp@583: NvRegRxFCSErr = 0x2bc,
fp@583: NvRegRxFrameAlignErr = 0x2c0,
fp@583: NvRegRxLenErr = 0x2c4,
fp@583: NvRegRxUnicast = 0x2c8,
fp@583: NvRegRxMulticast = 0x2cc,
fp@583: NvRegRxBroadcast = 0x2d0,
fp@583: NvRegTxDef = 0x2d4,
fp@583: NvRegTxFrame = 0x2d8,
fp@583: NvRegRxCnt = 0x2dc,
fp@583: NvRegTxPause = 0x2e0,
fp@583: NvRegRxPause = 0x2e4,
fp@583: NvRegRxDropFrame = 0x2e8,
fp@583: NvRegVlanControl = 0x300,
fp@583: #define NVREG_VLANCONTROL_ENABLE 0x2000
fp@583: NvRegMSIXMap0 = 0x3e0,
fp@583: NvRegMSIXMap1 = 0x3e4,
fp@583: NvRegMSIXIrqStatus = 0x3f0,
fp@583:
fp@583: NvRegPowerState2 = 0x600,
fp@583: #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
fp@583: #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
fp@583: };
fp@583:
fp@583: /* Big endian: should work, but is untested */
fp@583: struct ring_desc {
fp@583: __le32 buf;
fp@583: __le32 flaglen;
fp@583: };
fp@583:
fp@583: struct ring_desc_ex {
fp@583: __le32 bufhigh;
fp@583: __le32 buflow;
fp@583: __le32 txvlan;
fp@583: __le32 flaglen;
fp@583: };
fp@583:
fp@583: union ring_type {
fp@583: struct ring_desc* orig;
fp@583: struct ring_desc_ex* ex;
fp@583: };
fp@583:
fp@583: #define FLAG_MASK_V1 0xffff0000
fp@583: #define FLAG_MASK_V2 0xffffc000
fp@583: #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
fp@583: #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
fp@583:
fp@583: #define NV_TX_LASTPACKET (1<<16)
fp@583: #define NV_TX_RETRYERROR (1<<19)
fp@583: #define NV_TX_FORCED_INTERRUPT (1<<24)
fp@583: #define NV_TX_DEFERRED (1<<26)
fp@583: #define NV_TX_CARRIERLOST (1<<27)
fp@583: #define NV_TX_LATECOLLISION (1<<28)
fp@583: #define NV_TX_UNDERFLOW (1<<29)
fp@583: #define NV_TX_ERROR (1<<30)
fp@583: #define NV_TX_VALID (1<<31)
fp@583:
fp@583: #define NV_TX2_LASTPACKET (1<<29)
fp@583: #define NV_TX2_RETRYERROR (1<<18)
fp@583: #define NV_TX2_FORCED_INTERRUPT (1<<30)
fp@583: #define NV_TX2_DEFERRED (1<<25)
fp@583: #define NV_TX2_CARRIERLOST (1<<26)
fp@583: #define NV_TX2_LATECOLLISION (1<<27)
fp@583: #define NV_TX2_UNDERFLOW (1<<28)
fp@583: /* error and valid are the same for both */
fp@583: #define NV_TX2_ERROR (1<<30)
fp@583: #define NV_TX2_VALID (1<<31)
fp@583: #define NV_TX2_TSO (1<<28)
fp@583: #define NV_TX2_TSO_SHIFT 14
fp@583: #define NV_TX2_TSO_MAX_SHIFT 14
fp@583: #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
fp@583: #define NV_TX2_CHECKSUM_L3 (1<<27)
fp@583: #define NV_TX2_CHECKSUM_L4 (1<<26)
fp@583:
fp@583: #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
fp@583:
fp@583: #define NV_RX_DESCRIPTORVALID (1<<16)
fp@583: #define NV_RX_MISSEDFRAME (1<<17)
fp@583: #define NV_RX_SUBSTRACT1 (1<<18)
fp@583: #define NV_RX_ERROR1 (1<<23)
fp@583: #define NV_RX_ERROR2 (1<<24)
fp@583: #define NV_RX_ERROR3 (1<<25)
fp@583: #define NV_RX_ERROR4 (1<<26)
fp@583: #define NV_RX_CRCERR (1<<27)
fp@583: #define NV_RX_OVERFLOW (1<<28)
fp@583: #define NV_RX_FRAMINGERR (1<<29)
fp@583: #define NV_RX_ERROR (1<<30)
fp@583: #define NV_RX_AVAIL (1<<31)
fp@583:
fp@583: #define NV_RX2_CHECKSUMMASK (0x1C000000)
fp@583: #define NV_RX2_CHECKSUMOK1 (0x10000000)
fp@583: #define NV_RX2_CHECKSUMOK2 (0x14000000)
fp@583: #define NV_RX2_CHECKSUMOK3 (0x18000000)
fp@583: #define NV_RX2_DESCRIPTORVALID (1<<29)
fp@583: #define NV_RX2_SUBSTRACT1 (1<<25)
fp@583: #define NV_RX2_ERROR1 (1<<18)
fp@583: #define NV_RX2_ERROR2 (1<<19)
fp@583: #define NV_RX2_ERROR3 (1<<20)
fp@583: #define NV_RX2_ERROR4 (1<<21)
fp@583: #define NV_RX2_CRCERR (1<<22)
fp@583: #define NV_RX2_OVERFLOW (1<<23)
fp@583: #define NV_RX2_FRAMINGERR (1<<24)
fp@583: /* error and avail are the same for both */
fp@583: #define NV_RX2_ERROR (1<<30)
fp@583: #define NV_RX2_AVAIL (1<<31)
fp@583:
fp@583: #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
fp@583: #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
fp@583:
fp@583: /* Miscelaneous hardware related defines: */
fp@583: #define NV_PCI_REGSZ_VER1 0x270
fp@583: #define NV_PCI_REGSZ_VER2 0x604
fp@583:
fp@583: /* various timeout delays: all in usec */
fp@583: #define NV_TXRX_RESET_DELAY 4
fp@583: #define NV_TXSTOP_DELAY1 10
fp@583: #define NV_TXSTOP_DELAY1MAX 500000
fp@583: #define NV_TXSTOP_DELAY2 100
fp@583: #define NV_RXSTOP_DELAY1 10
fp@583: #define NV_RXSTOP_DELAY1MAX 500000
fp@583: #define NV_RXSTOP_DELAY2 100
fp@583: #define NV_SETUP5_DELAY 5
fp@583: #define NV_SETUP5_DELAYMAX 50000
fp@583: #define NV_POWERUP_DELAY 5
fp@583: #define NV_POWERUP_DELAYMAX 5000
fp@583: #define NV_MIIBUSY_DELAY 50
fp@583: #define NV_MIIPHY_DELAY 10
fp@583: #define NV_MIIPHY_DELAYMAX 10000
fp@583: #define NV_MAC_RESET_DELAY 64
fp@583:
fp@583: #define NV_WAKEUPPATTERNS 5
fp@583: #define NV_WAKEUPMASKENTRIES 4
fp@583:
fp@583: /* General driver defaults */
fp@583: #define NV_WATCHDOG_TIMEO (5*HZ)
fp@583:
fp@583: #define RX_RING_DEFAULT 128
fp@583: #define TX_RING_DEFAULT 256
fp@583: #define RX_RING_MIN 128
fp@583: #define TX_RING_MIN 64
fp@583: #define RING_MAX_DESC_VER_1 1024
fp@583: #define RING_MAX_DESC_VER_2_3 16384
fp@583: /*
fp@583: * Difference between the get and put pointers for the tx ring.
fp@583: * This is used to throttle the amount of data outstanding in the
fp@583: * tx ring.
fp@583: */
fp@583: #define TX_LIMIT_DIFFERENCE 1
fp@583:
fp@583: /* rx/tx mac addr + type + vlan + align + slack*/
fp@583: #define NV_RX_HEADERS (64)
fp@583: /* even more slack. */
fp@583: #define NV_RX_ALLOC_PAD (64)
fp@583:
fp@583: /* maximum mtu size */
fp@583: #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
fp@583: #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
fp@583:
fp@583: #define OOM_REFILL (1+HZ/20)
fp@583: #define POLL_WAIT (1+HZ/100)
fp@583: #define LINK_TIMEOUT (3*HZ)
fp@583: #define STATS_INTERVAL (10*HZ)
fp@583:
fp@583: /*
fp@583: * desc_ver values:
fp@583: * The nic supports three different descriptor types:
fp@583: * - DESC_VER_1: Original
fp@583: * - DESC_VER_2: support for jumbo frames.
fp@583: * - DESC_VER_3: 64-bit format.
fp@583: */
fp@583: #define DESC_VER_1 1
fp@583: #define DESC_VER_2 2
fp@583: #define DESC_VER_3 3
fp@583:
fp@583: /* PHY defines */
fp@583: #define PHY_OUI_MARVELL 0x5043
fp@583: #define PHY_OUI_CICADA 0x03f1
fp@583: #define PHYID1_OUI_MASK 0x03ff
fp@583: #define PHYID1_OUI_SHFT 6
fp@583: #define PHYID2_OUI_MASK 0xfc00
fp@583: #define PHYID2_OUI_SHFT 10
fp@583: #define PHYID2_MODEL_MASK 0x03f0
fp@583: #define PHY_MODEL_MARVELL_E3016 0x220
fp@583: #define PHY_MARVELL_E3016_INITMASK 0x0300
fp@583: #define PHY_INIT1 0x0f000
fp@583: #define PHY_INIT2 0x0e00
fp@583: #define PHY_INIT3 0x01000
fp@583: #define PHY_INIT4 0x0200
fp@583: #define PHY_INIT5 0x0004
fp@583: #define PHY_INIT6 0x02000
fp@583: #define PHY_GIGABIT 0x0100
fp@583:
fp@583: #define PHY_TIMEOUT 0x1
fp@583: #define PHY_ERROR 0x2
fp@583:
fp@583: #define PHY_100 0x1
fp@583: #define PHY_1000 0x2
fp@583: #define PHY_HALF 0x100
fp@583:
fp@583: #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
fp@583: #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
fp@583: #define NV_PAUSEFRAME_RX_ENABLE 0x0004
fp@583: #define NV_PAUSEFRAME_TX_ENABLE 0x0008
fp@583: #define NV_PAUSEFRAME_RX_REQ 0x0010
fp@583: #define NV_PAUSEFRAME_TX_REQ 0x0020
fp@583: #define NV_PAUSEFRAME_AUTONEG 0x0040
fp@583:
fp@583: /* MSI/MSI-X defines */
fp@583: #define NV_MSI_X_MAX_VECTORS 8
fp@583: #define NV_MSI_X_VECTORS_MASK 0x000f
fp@583: #define NV_MSI_CAPABLE 0x0010
fp@583: #define NV_MSI_X_CAPABLE 0x0020
fp@583: #define NV_MSI_ENABLED 0x0040
fp@583: #define NV_MSI_X_ENABLED 0x0080
fp@583:
fp@583: #define NV_MSI_X_VECTOR_ALL 0x0
fp@583: #define NV_MSI_X_VECTOR_RX 0x0
fp@583: #define NV_MSI_X_VECTOR_TX 0x1
fp@583: #define NV_MSI_X_VECTOR_OTHER 0x2
fp@583:
fp@583: /* statistics */
fp@583: struct nv_ethtool_str {
fp@583: char name[ETH_GSTRING_LEN];
fp@583: };
fp@583:
fp@583: static const struct nv_ethtool_str nv_estats_str[] = {
fp@583: { "tx_bytes" },
fp@583: { "tx_zero_rexmt" },
fp@583: { "tx_one_rexmt" },
fp@583: { "tx_many_rexmt" },
fp@583: { "tx_late_collision" },
fp@583: { "tx_fifo_errors" },
fp@583: { "tx_carrier_errors" },
fp@583: { "tx_excess_deferral" },
fp@583: { "tx_retry_error" },
fp@583: { "tx_deferral" },
fp@583: { "tx_packets" },
fp@583: { "tx_pause" },
fp@583: { "rx_frame_error" },
fp@583: { "rx_extra_byte" },
fp@583: { "rx_late_collision" },
fp@583: { "rx_runt" },
fp@583: { "rx_frame_too_long" },
fp@583: { "rx_over_errors" },
fp@583: { "rx_crc_errors" },
fp@583: { "rx_frame_align_error" },
fp@583: { "rx_length_error" },
fp@583: { "rx_unicast" },
fp@583: { "rx_multicast" },
fp@583: { "rx_broadcast" },
fp@583: { "rx_bytes" },
fp@583: { "rx_pause" },
fp@583: { "rx_drop_frame" },
fp@583: { "rx_packets" },
fp@583: { "rx_errors_total" }
fp@583: };
fp@583:
fp@583: struct nv_ethtool_stats {
fp@583: u64 tx_bytes;
fp@583: u64 tx_zero_rexmt;
fp@583: u64 tx_one_rexmt;
fp@583: u64 tx_many_rexmt;
fp@583: u64 tx_late_collision;
fp@583: u64 tx_fifo_errors;
fp@583: u64 tx_carrier_errors;
fp@583: u64 tx_excess_deferral;
fp@583: u64 tx_retry_error;
fp@583: u64 tx_deferral;
fp@583: u64 tx_packets;
fp@583: u64 tx_pause;
fp@583: u64 rx_frame_error;
fp@583: u64 rx_extra_byte;
fp@583: u64 rx_late_collision;
fp@583: u64 rx_runt;
fp@583: u64 rx_frame_too_long;
fp@583: u64 rx_over_errors;
fp@583: u64 rx_crc_errors;
fp@583: u64 rx_frame_align_error;
fp@583: u64 rx_length_error;
fp@583: u64 rx_unicast;
fp@583: u64 rx_multicast;
fp@583: u64 rx_broadcast;
fp@583: u64 rx_bytes;
fp@583: u64 rx_pause;
fp@583: u64 rx_drop_frame;
fp@583: u64 rx_packets;
fp@583: u64 rx_errors_total;
fp@583: };
fp@583:
fp@583: /* diagnostics */
fp@583: #define NV_TEST_COUNT_BASE 3
fp@583: #define NV_TEST_COUNT_EXTENDED 4
fp@583:
fp@583: static const struct nv_ethtool_str nv_etests_str[] = {
fp@583: { "link (online/offline)" },
fp@583: { "register (offline) " },
fp@583: { "interrupt (offline) " },
fp@583: { "loopback (offline) " }
fp@583: };
fp@583:
fp@583: struct register_test {
fp@583: __le32 reg;
fp@583: __le32 mask;
fp@583: };
fp@583:
fp@583: static const struct register_test nv_registers_test[] = {
fp@583: { NvRegUnknownSetupReg6, 0x01 },
fp@583: { NvRegMisc1, 0x03c },
fp@583: { NvRegOffloadConfig, 0x03ff },
fp@583: { NvRegMulticastAddrA, 0xffffffff },
fp@583: { NvRegTxWatermark, 0x0ff },
fp@583: { NvRegWakeUpFlags, 0x07777 },
fp@583: { 0,0 }
fp@583: };
fp@583:
fp@583: /*
fp@583: * SMP locking:
fp@583: * All hardware access under dev->priv->lock, except the performance
fp@583: * critical parts:
fp@583: * - rx is (pseudo-) lockless: it relies on the single-threading provided
fp@583: * by the arch code for interrupts.
fp@583: * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
fp@583: * needs dev->priv->lock :-(
fp@583: * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
fp@583: */
fp@583:
fp@583: /* in dev: base, irq */
fp@583: struct fe_priv {
fp@583: spinlock_t lock;
fp@583:
fp@583: /* General data:
fp@583: * Locking: spin_lock(&np->lock); */
fp@583: struct net_device_stats stats;
fp@583: struct nv_ethtool_stats estats;
fp@583: int in_shutdown;
fp@583: u32 linkspeed;
fp@583: int duplex;
fp@583: int autoneg;
fp@583: int fixed_mode;
fp@583: int phyaddr;
fp@583: int wolenabled;
fp@583: unsigned int phy_oui;
fp@583: unsigned int phy_model;
fp@583: u16 gigabit;
fp@583: int intr_test;
fp@583:
fp@583: /* General data: RO fields */
fp@583: dma_addr_t ring_addr;
fp@583: struct pci_dev *pci_dev;
fp@583: u32 orig_mac[2];
fp@583: u32 irqmask;
fp@583: u32 desc_ver;
fp@583: u32 txrxctl_bits;
fp@583: u32 vlanctl_bits;
fp@583: u32 driver_data;
fp@583: u32 register_size;
fp@583: int rx_csum;
fp@583:
fp@583: void __iomem *base;
fp@583:
fp@583: /* rx specific fields.
fp@583: * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
fp@583: */
fp@583: union ring_type rx_ring;
fp@583: unsigned int cur_rx, refill_rx;
fp@583: struct sk_buff **rx_skbuff;
fp@583: dma_addr_t *rx_dma;
fp@583: unsigned int rx_buf_sz;
fp@583: unsigned int pkt_limit;
fp@583: struct timer_list oom_kick;
fp@583: struct timer_list nic_poll;
fp@583: struct timer_list stats_poll;
fp@583: u32 nic_poll_irq;
fp@583: int rx_ring_size;
fp@583:
fp@583: /* media detection workaround.
fp@583: * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
fp@583: */
fp@583: int need_linktimer;
fp@583: unsigned long link_timeout;
fp@583: /*
fp@583: * tx specific fields.
fp@583: */
fp@583: union ring_type tx_ring;
fp@583: unsigned int next_tx, nic_tx;
fp@583: struct sk_buff **tx_skbuff;
fp@583: dma_addr_t *tx_dma;
fp@583: unsigned int *tx_dma_len;
fp@583: u32 tx_flags;
fp@583: int tx_ring_size;
fp@583: int tx_limit_start;
fp@583: int tx_limit_stop;
fp@583:
fp@583: /* vlan fields */
fp@583: struct vlan_group *vlangrp;
fp@583:
fp@583: /* msi/msi-x fields */
fp@583: u32 msi_flags;
fp@583: struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
fp@583:
fp@583: /* flow control */
fp@583: u32 pause_flags;
fp@583:
fp@583: ec_device_t *ecdev;
fp@583: };
fp@583:
fp@583: /*
fp@583: * Maximum number of loops until we assume that a bit in the irq mask
fp@583: * is stuck. Overridable with module param.
fp@583: */
fp@583: static int max_interrupt_work = 5;
fp@583:
fp@583: /*
fp@583: * Optimization can be either throuput mode or cpu mode
fp@583: *
fp@583: * Throughput Mode: Every tx and rx packet will generate an interrupt.
fp@583: * CPU Mode: Interrupts are controlled by a timer.
fp@583: */
fp@583: enum {
fp@583: NV_OPTIMIZATION_MODE_THROUGHPUT,
fp@583: NV_OPTIMIZATION_MODE_CPU
fp@583: };
fp@583: static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
fp@583:
fp@583: /*
fp@583: * Poll interval for timer irq
fp@583: *
fp@583: * This interval determines how frequent an interrupt is generated.
fp@583: * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
fp@583: * Min = 0, and Max = 65535
fp@583: */
fp@583: static int poll_interval = -1;
fp@583:
fp@583: /*
fp@583: * MSI interrupts
fp@583: */
fp@583: enum {
fp@583: NV_MSI_INT_DISABLED,
fp@583: NV_MSI_INT_ENABLED
fp@583: };
fp@583: static int msi = NV_MSI_INT_ENABLED;
fp@583:
fp@583: /*
fp@583: * MSIX interrupts
fp@583: */
fp@583: enum {
fp@583: NV_MSIX_INT_DISABLED,
fp@583: NV_MSIX_INT_ENABLED
fp@583: };
fp@583: static int msix = NV_MSIX_INT_ENABLED;
fp@583:
fp@583: /*
fp@583: * DMA 64bit
fp@583: */
fp@583: enum {
fp@583: NV_DMA_64BIT_DISABLED,
fp@583: NV_DMA_64BIT_ENABLED
fp@583: };
fp@583: static int dma_64bit = NV_DMA_64BIT_ENABLED;
fp@583:
fp@583: static int board_idx = -1;
fp@583:
fp@583: static inline struct fe_priv *get_nvpriv(struct net_device *dev)
fp@583: {
fp@583: return netdev_priv(dev);
fp@583: }
fp@583:
fp@583: static inline u8 __iomem *get_hwbase(struct net_device *dev)
fp@583: {
fp@583: return ((struct fe_priv *)netdev_priv(dev))->base;
fp@583: }
fp@583:
fp@583: static inline void pci_push(u8 __iomem *base)
fp@583: {
fp@583: /* force out pending posted writes */
fp@583: readl(base);
fp@583: }
fp@583:
fp@583: static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
fp@583: {
fp@583: return le32_to_cpu(prd->flaglen)
fp@583: & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
fp@583: }
fp@583:
fp@583: static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
fp@583: {
fp@583: return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
fp@583: }
fp@583:
fp@583: static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
fp@583: int delay, int delaymax, const char *msg)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: pci_push(base);
fp@583: do {
fp@583: udelay(delay);
fp@583: delaymax -= delay;
fp@583: if (delaymax < 0) {
fp@583: if (msg)
fp@583: printk(msg);
fp@583: return 1;
fp@583: }
fp@583: } while ((readl(base + offset) & mask) != target);
fp@583: return 0;
fp@583: }
fp@583:
fp@583: #define NV_SETUP_RX_RING 0x01
fp@583: #define NV_SETUP_TX_RING 0x02
fp@583:
fp@583: static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: if (rxtx_flags & NV_SETUP_RX_RING) {
fp@583: writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
fp@583: }
fp@583: if (rxtx_flags & NV_SETUP_TX_RING) {
fp@583: writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
fp@583: }
fp@583: } else {
fp@583: if (rxtx_flags & NV_SETUP_RX_RING) {
fp@583: writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
fp@583: writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
fp@583: }
fp@583: if (rxtx_flags & NV_SETUP_TX_RING) {
fp@583: writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
fp@583: writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: static void free_rings(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: if (np->rx_ring.orig)
fp@583: pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
fp@583: np->rx_ring.orig, np->ring_addr);
fp@583: } else {
fp@583: if (np->rx_ring.ex)
fp@583: pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
fp@583: np->rx_ring.ex, np->ring_addr);
fp@583: }
fp@583: if (np->rx_skbuff)
fp@583: kfree(np->rx_skbuff);
fp@583: if (np->rx_dma)
fp@583: kfree(np->rx_dma);
fp@583: if (np->tx_skbuff)
fp@583: kfree(np->tx_skbuff);
fp@583: if (np->tx_dma)
fp@583: kfree(np->tx_dma);
fp@583: if (np->tx_dma_len)
fp@583: kfree(np->tx_dma_len);
fp@583: }
fp@583:
fp@583: static int using_multi_irqs(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583:
fp@583: if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
fp@583: ((np->msi_flags & NV_MSI_X_ENABLED) &&
fp@583: ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
fp@583: return 0;
fp@583: else
fp@583: return 1;
fp@583: }
fp@583:
fp@583: static void nv_enable_irq(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583:
fp@583: if (!using_multi_irqs(dev)) {
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
fp@583: else
fp@583: enable_irq(dev->irq);
fp@583: } else {
fp@583: enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
fp@583: enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
fp@583: enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
fp@583: }
fp@583: }
fp@583:
fp@583: static void nv_disable_irq(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583:
fp@583: if (!using_multi_irqs(dev)) {
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
fp@583: else
fp@583: disable_irq(dev->irq);
fp@583: } else {
fp@583: disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
fp@583: disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
fp@583: disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
fp@583: }
fp@583: }
fp@583:
fp@583: /* In MSIX mode, a write to irqmask behaves as XOR */
fp@583: static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: writel(mask, base + NvRegIrqMask);
fp@583: }
fp@583:
fp@583: static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED) {
fp@583: writel(mask, base + NvRegIrqMask);
fp@583: } else {
fp@583: if (np->msi_flags & NV_MSI_ENABLED)
fp@583: writel(0, base + NvRegMSIIrqMask);
fp@583: writel(0, base + NvRegIrqMask);
fp@583: }
fp@583: }
fp@583:
fp@583: #define MII_READ (-1)
fp@583: /* mii_rw: read/write a register on the PHY.
fp@583: *
fp@583: * Caller must guarantee serialization
fp@583: */
fp@583: static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 reg;
fp@583: int retval;
fp@583:
fp@583: writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
fp@583:
fp@583: reg = readl(base + NvRegMIIControl);
fp@583: if (reg & NVREG_MIICTL_INUSE) {
fp@583: writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
fp@583: udelay(NV_MIIBUSY_DELAY);
fp@583: }
fp@583:
fp@583: reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
fp@583: if (value != MII_READ) {
fp@583: writel(value, base + NvRegMIIData);
fp@583: reg |= NVREG_MIICTL_WRITE;
fp@583: }
fp@583: writel(reg, base + NvRegMIIControl);
fp@583:
fp@583: if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
fp@583: NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
fp@583: dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
fp@583: dev->name, miireg, addr);
fp@583: retval = -1;
fp@583: } else if (value != MII_READ) {
fp@583: /* it was a write operation - fewer failures are detectable */
fp@583: dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
fp@583: dev->name, value, miireg, addr);
fp@583: retval = 0;
fp@583: } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
fp@583: dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
fp@583: dev->name, miireg, addr);
fp@583: retval = -1;
fp@583: } else {
fp@583: retval = readl(base + NvRegMIIData);
fp@583: dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
fp@583: dev->name, miireg, addr, retval);
fp@583: }
fp@583:
fp@583: return retval;
fp@583: }
fp@583:
fp@583: static int phy_reset(struct net_device *dev, u32 bmcr_setup)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u32 miicontrol;
fp@583: unsigned int tries = 0;
fp@583:
fp@583: miicontrol = BMCR_RESET | bmcr_setup;
fp@583: if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
fp@583: return -1;
fp@583: }
fp@583:
fp@583: /* wait for 500ms */
fp@583: msleep(500);
fp@583:
fp@583: /* must wait till reset is deasserted */
fp@583: while (miicontrol & BMCR_RESET) {
fp@583: msleep(10);
fp@583: miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: /* FIXME: 100 tries seem excessive */
fp@583: if (tries++ > 100)
fp@583: return -1;
fp@583: }
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static int phy_init(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
fp@583:
fp@583: /* phy errata for E3016 phy */
fp@583: if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
fp@583: reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
fp@583: reg &= ~PHY_MARVELL_E3016_INITMASK;
fp@583: if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
fp@583: printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583: }
fp@583:
fp@583: /* set advertise register */
fp@583: reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
fp@583: reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
fp@583: if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
fp@583: printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583:
fp@583: /* get phy interface type */
fp@583: phyinterface = readl(base + NvRegPhyInterface);
fp@583:
fp@583: /* see if gigabit phy */
fp@583: mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
fp@583: if (mii_status & PHY_GIGABIT) {
fp@583: np->gigabit = PHY_GIGABIT;
fp@583: mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
fp@583: mii_control_1000 &= ~ADVERTISE_1000HALF;
fp@583: if (phyinterface & PHY_RGMII)
fp@583: mii_control_1000 |= ADVERTISE_1000FULL;
fp@583: else
fp@583: mii_control_1000 &= ~ADVERTISE_1000FULL;
fp@583:
fp@583: if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
fp@583: printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583: }
fp@583: else
fp@583: np->gigabit = 0;
fp@583:
fp@583: mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: mii_control |= BMCR_ANENABLE;
fp@583:
fp@583: /* reset the phy
fp@583: * (certain phys need bmcr to be setup with reset)
fp@583: */
fp@583: if (phy_reset(dev, mii_control)) {
fp@583: printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583:
fp@583: /* phy vendor specific configuration */
fp@583: if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
fp@583: phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
fp@583: phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
fp@583: phy_reserved |= (PHY_INIT3 | PHY_INIT4);
fp@583: if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
fp@583: printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583: phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
fp@583: phy_reserved |= PHY_INIT5;
fp@583: if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
fp@583: printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583: }
fp@583: if (np->phy_oui == PHY_OUI_CICADA) {
fp@583: phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
fp@583: phy_reserved |= PHY_INIT6;
fp@583: if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
fp@583: printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
fp@583: return PHY_ERROR;
fp@583: }
fp@583: }
fp@583: /* some phys clear out pause advertisment on reset, set it back */
fp@583: mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
fp@583:
fp@583: /* restart auto negotiation */
fp@583: mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
fp@583: if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
fp@583: return PHY_ERROR;
fp@583: }
fp@583:
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static void nv_start_rx(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
fp@583: /* Already running? Stop it. */
fp@583: if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
fp@583: writel(0, base + NvRegReceiverControl);
fp@583: pci_push(base);
fp@583: }
fp@583: writel(np->linkspeed, base + NvRegLinkSpeed);
fp@583: pci_push(base);
fp@583: writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
fp@583: dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
fp@583: dev->name, np->duplex, np->linkspeed);
fp@583: pci_push(base);
fp@583: }
fp@583:
fp@583: static void nv_stop_rx(struct net_device *dev)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
fp@583: writel(0, base + NvRegReceiverControl);
fp@583: reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
fp@583: NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
fp@583: KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
fp@583:
fp@583: udelay(NV_RXSTOP_DELAY2);
fp@583: writel(0, base + NvRegLinkSpeed);
fp@583: }
fp@583:
fp@583: static void nv_start_tx(struct net_device *dev)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
fp@583: writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
fp@583: pci_push(base);
fp@583: }
fp@583:
fp@583: static void nv_stop_tx(struct net_device *dev)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
fp@583: writel(0, base + NvRegTransmitterControl);
fp@583: reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
fp@583: NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
fp@583: KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
fp@583:
fp@583: udelay(NV_TXSTOP_DELAY2);
fp@583: writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
fp@583: }
fp@583:
fp@583: static void nv_txrx_reset(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
fp@583: writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583: udelay(NV_TXRX_RESET_DELAY);
fp@583: writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583: }
fp@583:
fp@583: static void nv_mac_reset(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
fp@583: writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583: writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
fp@583: pci_push(base);
fp@583: udelay(NV_MAC_RESET_DELAY);
fp@583: writel(0, base + NvRegMacReset);
fp@583: pci_push(base);
fp@583: udelay(NV_MAC_RESET_DELAY);
fp@583: writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_get_stats: dev->get_stats function
fp@583: * Get latest stats value from the nic.
fp@583: * Called with read_lock(&dev_base_lock) held for read -
fp@583: * only synchronized against unregister_netdevice.
fp@583: */
fp@583: static struct net_device_stats *nv_get_stats(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: /* It seems that the nic always generates interrupts and doesn't
fp@583: * accumulate errors internally. Thus the current values in np->stats
fp@583: * are already up to date.
fp@583: */
fp@583: return &np->stats;
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_alloc_rx: fill rx ring entries.
fp@583: * Return 1 if the allocations for the skbs failed and the
fp@583: * rx engine is without Available descriptors
fp@583: */
fp@583: static int nv_alloc_rx(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: unsigned int refill_rx = np->refill_rx;
fp@583: int nr;
fp@583:
fp@583: while (np->cur_rx != refill_rx) {
fp@583: struct sk_buff *skb;
fp@583:
fp@583: nr = refill_rx % np->rx_ring_size;
fp@583: if (np->rx_skbuff[nr] == NULL) {
fp@583:
fp@583: skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
fp@583: if (!skb)
fp@583: break;
fp@583:
fp@583: skb->dev = dev;
fp@583: np->rx_skbuff[nr] = skb;
fp@583: } else {
fp@583: skb = np->rx_skbuff[nr];
fp@583: }
fp@583: np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
fp@583: skb->end-skb->data, PCI_DMA_FROMDEVICE);
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
fp@583: wmb();
fp@583: np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
fp@583: } else {
fp@583: np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
fp@583: np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
fp@583: wmb();
fp@583: np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
fp@583: dev->name, refill_rx);
fp@583: refill_rx++;
fp@583: }
fp@583: np->refill_rx = refill_rx;
fp@583: if (np->cur_rx - refill_rx == np->rx_ring_size)
fp@583: return 1;
fp@583: return 0;
fp@583: }
fp@583:
fp@583: /* If rx bufs are exhausted called after 50ms to attempt to refresh */
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: static void nv_do_rx_refill(unsigned long data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583:
fp@583: /* Just reschedule NAPI rx processing */
fp@583: netif_rx_schedule(dev);
fp@583: }
fp@583: #else
fp@583: static void nv_do_rx_refill(unsigned long data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (!using_multi_irqs(dev)) {
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
fp@583: else
fp@583: disable_irq(dev->irq);
fp@583: } else {
fp@583: disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
fp@583: }
fp@583: if (nv_alloc_rx(dev)) {
fp@583: spin_lock_irq(&np->lock);
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583: if (!using_multi_irqs(dev)) {
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
fp@583: else
fp@583: enable_irq(dev->irq);
fp@583: } else {
fp@583: enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
fp@583: }
fp@583: }
fp@583: #endif
fp@583:
fp@583: static void nv_init_rx(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int i;
fp@583:
fp@583: np->cur_rx = np->rx_ring_size;
fp@583: np->refill_rx = 0;
fp@583: for (i = 0; i < np->rx_ring_size; i++)
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
fp@583: np->rx_ring.orig[i].flaglen = 0;
fp@583: else
fp@583: np->rx_ring.ex[i].flaglen = 0;
fp@583: }
fp@583:
fp@583: static void nv_init_tx(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int i;
fp@583:
fp@583: np->next_tx = np->nic_tx = 0;
fp@583: for (i = 0; i < np->tx_ring_size; i++) {
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
fp@583: np->tx_ring.orig[i].flaglen = 0;
fp@583: else
fp@583: np->tx_ring.ex[i].flaglen = 0;
fp@583: np->tx_skbuff[i] = NULL;
fp@583: np->tx_dma[i] = 0;
fp@583: }
fp@583: }
fp@583:
fp@583: static int nv_init_ring(struct net_device *dev)
fp@583: {
fp@583: nv_init_tx(dev);
fp@583: nv_init_rx(dev);
fp@583: return nv_alloc_rx(dev);
fp@583: }
fp@583:
fp@583: static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
fp@583: dev->name, skbnr);
fp@583:
fp@583: if (np->tx_dma[skbnr]) {
fp@583: pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
fp@583: np->tx_dma_len[skbnr],
fp@583: PCI_DMA_TODEVICE);
fp@583: np->tx_dma[skbnr] = 0;
fp@583: }
fp@583:
fp@583: if (np->tx_skbuff[skbnr]) {
fp@583: if (!np->ecdev) dev_kfree_skb_any(np->tx_skbuff[skbnr]);
fp@583: np->tx_skbuff[skbnr] = NULL;
fp@583: return 1;
fp@583: } else {
fp@583: return 0;
fp@583: }
fp@583: }
fp@583:
fp@583: static void nv_drain_tx(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: unsigned int i;
fp@583:
fp@583: for (i = 0; i < np->tx_ring_size; i++) {
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
fp@583: np->tx_ring.orig[i].flaglen = 0;
fp@583: else
fp@583: np->tx_ring.ex[i].flaglen = 0;
fp@583: if (nv_release_txskb(dev, i))
fp@583: np->stats.tx_dropped++;
fp@583: }
fp@583: }
fp@583:
fp@583: static void nv_drain_rx(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int i;
fp@583: for (i = 0; i < np->rx_ring_size; i++) {
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
fp@583: np->rx_ring.orig[i].flaglen = 0;
fp@583: else
fp@583: np->rx_ring.ex[i].flaglen = 0;
fp@583: wmb();
fp@583: if (np->rx_skbuff[i]) {
fp@583: pci_unmap_single(np->pci_dev, np->rx_dma[i],
fp@583: np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
fp@583: PCI_DMA_FROMDEVICE);
fp@583: if (!np->ecdev) dev_kfree_skb(np->rx_skbuff[i]);
fp@583: np->rx_skbuff[i] = NULL;
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: static void drain_ring(struct net_device *dev)
fp@583: {
fp@583: nv_drain_tx(dev);
fp@583: nv_drain_rx(dev);
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_start_xmit: dev->hard_start_xmit function
fp@583: * Called with netif_tx_lock held.
fp@583: */
fp@583: static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u32 tx_flags = 0;
fp@583: u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
fp@583: unsigned int fragments = skb_shinfo(skb)->nr_frags;
fp@583: unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
fp@583: unsigned int start_nr = np->next_tx % np->tx_ring_size;
fp@583: unsigned int i;
fp@583: u32 offset = 0;
fp@583: u32 bcnt;
fp@583: u32 size = skb->len-skb->data_len;
fp@583: u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
fp@583: u32 tx_flags_vlan = 0;
fp@583:
fp@583: /* add fragments to entries count */
fp@583: for (i = 0; i < fragments; i++) {
fp@583: entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
fp@583: ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
fp@583: }
fp@583:
fp@583: if (!np->ecdev) {
fp@583: spin_lock_irq(&np->lock);
fp@583:
fp@583: if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
fp@583: spin_unlock_irq(&np->lock);
fp@583: netif_stop_queue(dev);
fp@583: return NETDEV_TX_BUSY;
fp@586: }
fp@583: }
fp@583:
fp@583: /* setup the header buffer */
fp@583: do {
fp@583: bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
fp@583: nr = (nr + 1) % np->tx_ring_size;
fp@583:
fp@583: np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
fp@583: PCI_DMA_TODEVICE);
fp@583: np->tx_dma_len[nr] = bcnt;
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
fp@583: np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
fp@583: } else {
fp@583: np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
fp@583: np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
fp@583: np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
fp@583: }
fp@583: tx_flags = np->tx_flags;
fp@583: offset += bcnt;
fp@583: size -= bcnt;
fp@583: } while (size);
fp@583:
fp@583: /* setup the fragments */
fp@583: for (i = 0; i < fragments; i++) {
fp@583: skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
fp@583: u32 size = frag->size;
fp@583: offset = 0;
fp@583:
fp@583: do {
fp@583: bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
fp@583: nr = (nr + 1) % np->tx_ring_size;
fp@583:
fp@583: np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
fp@583: PCI_DMA_TODEVICE);
fp@583: np->tx_dma_len[nr] = bcnt;
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
fp@583: np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
fp@583: } else {
fp@583: np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
fp@583: np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
fp@583: np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
fp@583: }
fp@583: offset += bcnt;
fp@583: size -= bcnt;
fp@583: } while (size);
fp@583: }
fp@583:
fp@583: /* set last fragment flag */
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
fp@583: } else {
fp@583: np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
fp@583: }
fp@583:
fp@583: np->tx_skbuff[nr] = skb;
fp@583:
fp@583: #ifdef NETIF_F_TSO
fp@583: if (skb_is_gso(skb))
fp@583: tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
fp@583: else
fp@583: #endif
fp@583: tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
fp@583: NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
fp@583:
fp@583: /* vlan tag */
fp@583: if (np->vlangrp && vlan_tx_tag_present(skb)) {
fp@583: tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
fp@583: }
fp@583:
fp@583: /* set tx flags */
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
fp@583: } else {
fp@583: np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
fp@583: np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
fp@583: }
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
fp@583: dev->name, np->next_tx, entries, tx_flags_extra);
fp@583: {
fp@583: int j;
fp@583: for (j=0; j<64; j++) {
fp@583: if ((j%16) == 0)
fp@583: dprintk("\n%03x:", j);
fp@583: dprintk(" %02x", ((unsigned char*)skb->data)[j]);
fp@583: }
fp@583: dprintk("\n");
fp@583: }
fp@583:
fp@583: np->next_tx += entries;
fp@583:
fp@583: dev->trans_start = jiffies;
fp@583: if (!np->ecdev) spin_unlock_irq(&np->lock);
fp@583: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
fp@583: pci_push(get_hwbase(dev));
fp@583: return NETDEV_TX_OK;
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_tx_done: check for completed packets, release the skbs.
fp@583: *
fp@583: * Caller must own np->lock.
fp@583: */
fp@583: static void nv_tx_done(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u32 flags;
fp@583: unsigned int i;
fp@583: struct sk_buff *skb;
fp@583:
fp@583: while (np->nic_tx != np->next_tx) {
fp@583: i = np->nic_tx % np->tx_ring_size;
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
fp@583: flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
fp@583: else
fp@583: flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
fp@583: dev->name, np->nic_tx, flags);
fp@583: if (flags & NV_TX_VALID)
fp@583: break;
fp@583: if (np->desc_ver == DESC_VER_1) {
fp@583: if (flags & NV_TX_LASTPACKET) {
fp@583: skb = np->tx_skbuff[i];
fp@583: if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
fp@583: NV_TX_UNDERFLOW|NV_TX_ERROR)) {
fp@583: if (flags & NV_TX_UNDERFLOW)
fp@583: np->stats.tx_fifo_errors++;
fp@583: if (flags & NV_TX_CARRIERLOST)
fp@583: np->stats.tx_carrier_errors++;
fp@583: np->stats.tx_errors++;
fp@583: } else {
fp@583: np->stats.tx_packets++;
fp@583: np->stats.tx_bytes += skb->len;
fp@583: }
fp@583: }
fp@583: } else {
fp@583: if (flags & NV_TX2_LASTPACKET) {
fp@583: skb = np->tx_skbuff[i];
fp@583: if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
fp@583: NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
fp@583: if (flags & NV_TX2_UNDERFLOW)
fp@583: np->stats.tx_fifo_errors++;
fp@583: if (flags & NV_TX2_CARRIERLOST)
fp@583: np->stats.tx_carrier_errors++;
fp@583: np->stats.tx_errors++;
fp@583: } else {
fp@583: np->stats.tx_packets++;
fp@583: np->stats.tx_bytes += skb->len;
fp@583: }
fp@583: }
fp@583: }
fp@583: nv_release_txskb(dev, i);
fp@583: np->nic_tx++;
fp@583: }
fp@583: if (!np->ecdev && np->next_tx - np->nic_tx < np->tx_limit_start)
fp@583: netif_wake_queue(dev);
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_tx_timeout: dev->tx_timeout function
fp@583: * Called with netif_tx_lock held.
fp@583: */
fp@583: static void nv_tx_timeout(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 status;
fp@583:
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
fp@583: else
fp@583: status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
fp@583:
fp@583: printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
fp@583:
fp@583: {
fp@583: int i;
fp@583:
fp@583: printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
fp@583: dev->name, (unsigned long)np->ring_addr,
fp@583: np->next_tx, np->nic_tx);
fp@583: printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
fp@583: for (i=0;i<=np->register_size;i+= 32) {
fp@583: printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
fp@583: i,
fp@583: readl(base + i + 0), readl(base + i + 4),
fp@583: readl(base + i + 8), readl(base + i + 12),
fp@583: readl(base + i + 16), readl(base + i + 20),
fp@583: readl(base + i + 24), readl(base + i + 28));
fp@583: }
fp@583: printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
fp@583: for (i=0;i<np->tx_ring_size;i+= 4) {
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
fp@583: i,
fp@583: le32_to_cpu(np->tx_ring.orig[i].buf),
fp@583: le32_to_cpu(np->tx_ring.orig[i].flaglen),
fp@583: le32_to_cpu(np->tx_ring.orig[i+1].buf),
fp@583: le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
fp@583: le32_to_cpu(np->tx_ring.orig[i+2].buf),
fp@583: le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
fp@583: le32_to_cpu(np->tx_ring.orig[i+3].buf),
fp@583: le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
fp@583: } else {
fp@583: printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
fp@583: i,
fp@583: le32_to_cpu(np->tx_ring.ex[i].bufhigh),
fp@583: le32_to_cpu(np->tx_ring.ex[i].buflow),
fp@583: le32_to_cpu(np->tx_ring.ex[i].flaglen),
fp@583: le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
fp@583: le32_to_cpu(np->tx_ring.ex[i+1].buflow),
fp@583: le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
fp@583: le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
fp@583: le32_to_cpu(np->tx_ring.ex[i+2].buflow),
fp@583: le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
fp@583: le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
fp@583: le32_to_cpu(np->tx_ring.ex[i+3].buflow),
fp@583: le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: if (!np->ecdev) spin_lock_irq(&np->lock);
fp@583:
fp@583: /* 1) stop tx engine */
fp@583: nv_stop_tx(dev);
fp@583:
fp@583: /* 2) check that the packets were not sent already: */
fp@583: nv_tx_done(dev);
fp@583:
fp@583: /* 3) if there are dead entries: clear everything */
fp@583: if (np->next_tx != np->nic_tx) {
fp@583: printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
fp@583: nv_drain_tx(dev);
fp@583: np->next_tx = np->nic_tx = 0;
fp@583: setup_hw_rings(dev, NV_SETUP_TX_RING);
fp@583: if (!np->ecdev) netif_wake_queue(dev);
fp@583: }
fp@583:
fp@583: /* 4) restart tx engine */
fp@583: nv_start_tx(dev);
fp@583: if (!np->ecdev) spin_unlock_irq(&np->lock);
fp@583: }
fp@583:
fp@583: /*
fp@583: * Called when the nic notices a mismatch between the actual data len on the
fp@583: * wire and the len indicated in the 802 header
fp@583: */
fp@583: static int nv_getlen(struct net_device *dev, void *packet, int datalen)
fp@583: {
fp@583: int hdrlen; /* length of the 802 header */
fp@583: int protolen; /* length as stored in the proto field */
fp@583:
fp@583: /* 1) calculate len according to header */
fp@583: if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
fp@583: protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
fp@583: hdrlen = VLAN_HLEN;
fp@583: } else {
fp@583: protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
fp@583: hdrlen = ETH_HLEN;
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
fp@583: dev->name, datalen, protolen, hdrlen);
fp@583: if (protolen > ETH_DATA_LEN)
fp@583: return datalen; /* Value in proto field not a len, no checks possible */
fp@583:
fp@583: protolen += hdrlen;
fp@583: /* consistency checks: */
fp@583: if (datalen > ETH_ZLEN) {
fp@583: if (datalen >= protolen) {
fp@583: /* more data on wire than in 802 header, trim of
fp@583: * additional data.
fp@583: */
fp@583: dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
fp@583: dev->name, protolen);
fp@583: return protolen;
fp@583: } else {
fp@583: /* less data on wire than mentioned in header.
fp@583: * Discard the packet.
fp@583: */
fp@583: dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
fp@583: dev->name);
fp@583: return -1;
fp@583: }
fp@583: } else {
fp@583: /* short packet. Accept only if 802 values are also short */
fp@583: if (protolen > ETH_ZLEN) {
fp@583: dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
fp@583: dev->name);
fp@583: return -1;
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
fp@583: dev->name, datalen);
fp@583: return datalen;
fp@583: }
fp@583: }
fp@583:
fp@583: static int nv_rx_process(struct net_device *dev, int limit)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u32 flags;
fp@583: u32 vlanflags = 0;
fp@583: int count;
fp@583:
fp@583: for (count = 0; count < limit; ++count) {
fp@583: struct sk_buff *skb;
fp@583: int len;
fp@583: int i;
fp@583: if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
fp@583: break; /* we scanned the whole ring - do not continue */
fp@583:
fp@583: i = np->cur_rx % np->rx_ring_size;
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
fp@583: len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
fp@583: } else {
fp@583: flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
fp@583: len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
fp@583: vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
fp@583: }
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
fp@583: dev->name, np->cur_rx, flags);
fp@583:
fp@583: if (flags & NV_RX_AVAIL)
fp@583: break; /* still owned by hardware, */
fp@583:
fp@583: /*
fp@583: * the packet is for us - immediately tear down the pci mapping.
fp@583: * TODO: check if a prefetch of the first cacheline improves
fp@583: * the performance.
fp@583: */
fp@583: pci_unmap_single(np->pci_dev, np->rx_dma[i],
fp@583: np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
fp@583: PCI_DMA_FROMDEVICE);
fp@586:
fp@583: {
fp@583: int j;
fp@583: dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
fp@583: for (j=0; j<64; j++) {
fp@583: if ((j%16) == 0)
fp@583: dprintk("\n%03x:", j);
fp@583: dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
fp@583: }
fp@583: dprintk("\n");
fp@583: }
fp@583: /* look at what we actually got: */
fp@583: if (np->desc_ver == DESC_VER_1) {
fp@583: if (!(flags & NV_RX_DESCRIPTORVALID))
fp@583: goto next_pkt;
fp@583:
fp@583: if (flags & NV_RX_ERROR) {
fp@583: if (flags & NV_RX_MISSEDFRAME) {
fp@583: np->stats.rx_missed_errors++;
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & NV_RX_CRCERR) {
fp@583: np->stats.rx_crc_errors++;
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & NV_RX_OVERFLOW) {
fp@583: np->stats.rx_over_errors++;
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & NV_RX_ERROR4) {
fp@583: len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
fp@583: if (len < 0) {
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: }
fp@583: /* framing errors are soft errors. */
fp@583: if (flags & NV_RX_FRAMINGERR) {
fp@583: if (flags & NV_RX_SUBSTRACT1) {
fp@583: len--;
fp@583: }
fp@583: }
fp@583: }
fp@583: } else {
fp@583: if (!(flags & NV_RX2_DESCRIPTORVALID))
fp@583: goto next_pkt;
fp@583:
fp@583: if (flags & NV_RX2_ERROR) {
fp@583: if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & NV_RX2_CRCERR) {
fp@583: np->stats.rx_crc_errors++;
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & NV_RX2_OVERFLOW) {
fp@583: np->stats.rx_over_errors++;
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: if (flags & NV_RX2_ERROR4) {
fp@583: len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
fp@583: if (len < 0) {
fp@583: np->stats.rx_errors++;
fp@583: goto next_pkt;
fp@583: }
fp@583: }
fp@583: /* framing errors are soft errors */
fp@583: if (flags & NV_RX2_FRAMINGERR) {
fp@583: if (flags & NV_RX2_SUBSTRACT1) {
fp@583: len--;
fp@583: }
fp@583: }
fp@583: }
fp@583: if (np->rx_csum) {
fp@583: flags &= NV_RX2_CHECKSUMMASK;
fp@583: if (flags == NV_RX2_CHECKSUMOK1 ||
fp@583: flags == NV_RX2_CHECKSUMOK2 ||
fp@583: flags == NV_RX2_CHECKSUMOK3) {
fp@583: dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
fp@583: np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
fp@583: } else {
fp@583: dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
fp@583: }
fp@583: }
fp@583: }
fp@583: if (np->ecdev) {
fp@583: ecdev_receive(np->ecdev, np->rx_skbuff[i]->data, len);
fp@583: }
fp@583: else {
fp@583: /* got a valid packet - forward it to the network core */
fp@583: skb = np->rx_skbuff[i];
fp@583: np->rx_skbuff[i] = NULL;
fp@583:
fp@583: skb_put(skb, len);
fp@583: skb->protocol = eth_type_trans(skb, dev);
fp@583: dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
fp@583: dev->name, np->cur_rx, len, skb->protocol);
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
fp@583: vlan_hwaccel_receive_skb(skb, np->vlangrp,
fp@583: vlanflags & NV_RX3_VLAN_TAG_MASK);
fp@583: else
fp@583: netif_receive_skb(skb);
fp@583: #else
fp@583: if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
fp@583: vlan_hwaccel_rx(skb, np->vlangrp,
fp@583: vlanflags & NV_RX3_VLAN_TAG_MASK);
fp@583: else
fp@583: netif_rx(skb);
fp@583: #endif
fp@583: }
fp@583: dev->last_rx = jiffies;
fp@583: np->stats.rx_packets++;
fp@583: np->stats.rx_bytes += len;
fp@583: next_pkt:
fp@583: np->cur_rx++;
fp@583: }
fp@583:
fp@583: return count;
fp@583: }
fp@583:
fp@583: static void set_bufsize(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (dev->mtu <= ETH_DATA_LEN)
fp@583: np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
fp@583: else
fp@583: np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_change_mtu: dev->change_mtu function
fp@583: * Called with dev_base_lock held for read.
fp@583: */
fp@583: static int nv_change_mtu(struct net_device *dev, int new_mtu)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int old_mtu;
fp@583:
fp@583: if (new_mtu < 64 || new_mtu > np->pkt_limit)
fp@583: return -EINVAL;
fp@583:
fp@583: old_mtu = dev->mtu;
fp@583: dev->mtu = new_mtu;
fp@583:
fp@583: /* return early if the buffer sizes will not change */
fp@583: if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
fp@583: return 0;
fp@583: if (old_mtu == new_mtu)
fp@583: return 0;
fp@583:
fp@583: /* synchronized against open : rtnl_lock() held by caller */
fp@583: if (netif_running(dev)) {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: /*
fp@583: * It seems that the nic preloads valid ring entries into an
fp@583: * internal buffer. The procedure for flushing everything is
fp@583: * guessed, there is probably a simpler approach.
fp@583: * Changing the MTU is a rare event, it shouldn't matter.
fp@583: */
fp@583: nv_disable_irq(dev);
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock(&np->lock);
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: nv_txrx_reset(dev);
fp@583: /* drain rx queue */
fp@583: nv_drain_rx(dev);
fp@583: nv_drain_tx(dev);
fp@583: /* reinit driver view of the rx queue */
fp@583: set_bufsize(dev);
fp@583: if (nv_init_ring(dev)) {
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: }
fp@583: /* reinit nic view of the rx queue */
fp@583: writel(np->rx_buf_sz, base + NvRegOffloadConfig);
fp@583: setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
fp@583: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
fp@583: base + NvRegRingSizes);
fp@583: pci_push(base);
fp@583: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583:
fp@583: /* restart rx engine */
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583: spin_unlock(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: nv_enable_irq(dev);
fp@583: }
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static void nv_copy_mac_to_hw(struct net_device *dev)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 mac[2];
fp@583:
fp@583: mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
fp@583: (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
fp@583: mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
fp@583:
fp@583: writel(mac[0], base + NvRegMacAddrA);
fp@583: writel(mac[1], base + NvRegMacAddrB);
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_set_mac_address: dev->set_mac_address function
fp@583: * Called with rtnl_lock() held.
fp@583: */
fp@583: static int nv_set_mac_address(struct net_device *dev, void *addr)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: struct sockaddr *macaddr = (struct sockaddr*)addr;
fp@583:
fp@583: if (!is_valid_ether_addr(macaddr->sa_data))
fp@583: return -EADDRNOTAVAIL;
fp@583:
fp@583: /* synchronized against open : rtnl_lock() held by caller */
fp@583: memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock_irq(&np->lock);
fp@583:
fp@583: /* stop rx engine */
fp@583: nv_stop_rx(dev);
fp@583:
fp@583: /* set mac address */
fp@583: nv_copy_mac_to_hw(dev);
fp@583:
fp@583: /* restart rx engine */
fp@583: nv_start_rx(dev);
fp@583: spin_unlock_irq(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: } else {
fp@583: nv_copy_mac_to_hw(dev);
fp@583: }
fp@583: return 0;
fp@583: }
fp@583:
fp@583: /*
fp@583: * nv_set_multicast: dev->set_multicast function
fp@583: * Called with netif_tx_lock held.
fp@583: */
fp@583: static void nv_set_multicast(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 addr[2];
fp@583: u32 mask[2];
fp@583: u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
fp@583:
fp@583: memset(addr, 0, sizeof(addr));
fp@583: memset(mask, 0, sizeof(mask));
fp@583:
fp@583: if (dev->flags & IFF_PROMISC) {
fp@583: pff |= NVREG_PFF_PROMISC;
fp@583: } else {
fp@583: pff |= NVREG_PFF_MYADDR;
fp@583:
fp@583: if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
fp@583: u32 alwaysOff[2];
fp@583: u32 alwaysOn[2];
fp@583:
fp@583: alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
fp@583: if (dev->flags & IFF_ALLMULTI) {
fp@583: alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
fp@583: } else {
fp@583: struct dev_mc_list *walk;
fp@583:
fp@583: walk = dev->mc_list;
fp@583: while (walk != NULL) {
fp@583: u32 a, b;
fp@583: a = le32_to_cpu(*(u32 *) walk->dmi_addr);
fp@583: b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
fp@583: alwaysOn[0] &= a;
fp@583: alwaysOff[0] &= ~a;
fp@583: alwaysOn[1] &= b;
fp@583: alwaysOff[1] &= ~b;
fp@583: walk = walk->next;
fp@583: }
fp@583: }
fp@583: addr[0] = alwaysOn[0];
fp@583: addr[1] = alwaysOn[1];
fp@583: mask[0] = alwaysOn[0] | alwaysOff[0];
fp@583: mask[1] = alwaysOn[1] | alwaysOff[1];
fp@583: }
fp@583: }
fp@583: addr[0] |= NVREG_MCASTADDRA_FORCE;
fp@583: pff |= NVREG_PFF_ALWAYS;
fp@583: spin_lock_irq(&np->lock);
fp@583: nv_stop_rx(dev);
fp@583: writel(addr[0], base + NvRegMulticastAddrA);
fp@583: writel(addr[1], base + NvRegMulticastAddrB);
fp@583: writel(mask[0], base + NvRegMulticastMaskA);
fp@583: writel(mask[1], base + NvRegMulticastMaskB);
fp@583: writel(pff, base + NvRegPacketFilterFlags);
fp@583: dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
fp@583: dev->name);
fp@583: nv_start_rx(dev);
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583:
fp@583: static void nv_update_pause(struct net_device *dev, u32 pause_flags)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
fp@583:
fp@583: if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
fp@583: u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
fp@583: if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
fp@583: writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
fp@583: np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
fp@583: } else {
fp@583: writel(pff, base + NvRegPacketFilterFlags);
fp@583: }
fp@583: }
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
fp@583: u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
fp@583: if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
fp@583: writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
fp@583: writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
fp@583: np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
fp@583: } else {
fp@583: writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
fp@583: writel(regmisc, base + NvRegMisc1);
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: /**
fp@583: * nv_update_linkspeed: Setup the MAC according to the link partner
fp@583: * @dev: Network device to be configured
fp@583: *
fp@583: * The function queries the PHY and checks if there is a link partner.
fp@583: * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
fp@583: * set to 10 MBit HD.
fp@583: *
fp@583: * The function returns 0 if there is no link partner and 1 if there is
fp@583: * a good link partner.
fp@583: */
fp@583: static int nv_update_linkspeed(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int adv = 0;
fp@583: int lpa = 0;
fp@583: int adv_lpa, adv_pause, lpa_pause;
fp@583: int newls = np->linkspeed;
fp@583: int newdup = np->duplex;
fp@583: int mii_status;
fp@583: int retval = 0;
fp@583: u32 control_1000, status_1000, phyreg, pause_flags, txreg;
fp@583:
fp@583: /* BMSR_LSTATUS is latched, read it twice:
fp@583: * we want the current value.
fp@583: */
fp@583: mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
fp@583: mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
fp@583:
fp@583: if (!(mii_status & BMSR_LSTATUS)) {
fp@583: dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
fp@583: dev->name);
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 0;
fp@583: retval = 0;
fp@583: goto set_speed;
fp@583: }
fp@583:
fp@583: if (np->autoneg == 0) {
fp@583: dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
fp@583: dev->name, np->fixed_mode);
fp@583: if (np->fixed_mode & LPA_100FULL) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
fp@583: newdup = 1;
fp@583: } else if (np->fixed_mode & LPA_100HALF) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
fp@583: newdup = 0;
fp@583: } else if (np->fixed_mode & LPA_10FULL) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 1;
fp@583: } else {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 0;
fp@583: }
fp@583: retval = 1;
fp@583: goto set_speed;
fp@583: }
fp@583: /* check auto negotiation is complete */
fp@583: if (!(mii_status & BMSR_ANEGCOMPLETE)) {
fp@583: /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 0;
fp@583: retval = 0;
fp@583: dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
fp@583: goto set_speed;
fp@583: }
fp@583:
fp@583: adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
fp@583: lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
fp@583: dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
fp@583: dev->name, adv, lpa);
fp@583:
fp@583: retval = 1;
fp@583: if (np->gigabit == PHY_GIGABIT) {
fp@583: control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
fp@583: status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
fp@583:
fp@583: if ((control_1000 & ADVERTISE_1000FULL) &&
fp@583: (status_1000 & LPA_1000FULL)) {
fp@583: dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
fp@583: dev->name);
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
fp@583: newdup = 1;
fp@583: goto set_speed;
fp@583: }
fp@583: }
fp@583:
fp@583: /* FIXME: handle parallel detection properly */
fp@583: adv_lpa = lpa & adv;
fp@583: if (adv_lpa & LPA_100FULL) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
fp@583: newdup = 1;
fp@583: } else if (adv_lpa & LPA_100HALF) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
fp@583: newdup = 0;
fp@583: } else if (adv_lpa & LPA_10FULL) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 1;
fp@583: } else if (adv_lpa & LPA_10HALF) {
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 0;
fp@583: } else {
fp@583: dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
fp@583: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: newdup = 0;
fp@583: }
fp@583:
fp@583: set_speed:
fp@583: if (np->duplex == newdup && np->linkspeed == newls)
fp@583: return retval;
fp@583:
fp@583: dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
fp@583: dev->name, np->linkspeed, np->duplex, newls, newdup);
fp@583:
fp@583: np->duplex = newdup;
fp@583: np->linkspeed = newls;
fp@583:
fp@583: if (np->gigabit == PHY_GIGABIT) {
fp@583: phyreg = readl(base + NvRegRandomSeed);
fp@583: phyreg &= ~(0x3FF00);
fp@583: if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
fp@583: phyreg |= NVREG_RNDSEED_FORCE3;
fp@583: else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
fp@583: phyreg |= NVREG_RNDSEED_FORCE2;
fp@583: else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
fp@583: phyreg |= NVREG_RNDSEED_FORCE;
fp@583: writel(phyreg, base + NvRegRandomSeed);
fp@583: }
fp@583:
fp@583: phyreg = readl(base + NvRegPhyInterface);
fp@583: phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
fp@583: if (np->duplex == 0)
fp@583: phyreg |= PHY_HALF;
fp@583: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
fp@583: phyreg |= PHY_100;
fp@583: else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
fp@583: phyreg |= PHY_1000;
fp@583: writel(phyreg, base + NvRegPhyInterface);
fp@583:
fp@583: if (phyreg & PHY_RGMII) {
fp@583: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
fp@583: txreg = NVREG_TX_DEFERRAL_RGMII_1000;
fp@583: else
fp@583: txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
fp@583: } else {
fp@583: txreg = NVREG_TX_DEFERRAL_DEFAULT;
fp@583: }
fp@583: writel(txreg, base + NvRegTxDeferral);
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1) {
fp@583: txreg = NVREG_TX_WM_DESC1_DEFAULT;
fp@583: } else {
fp@583: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
fp@583: txreg = NVREG_TX_WM_DESC2_3_1000;
fp@583: else
fp@583: txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
fp@583: }
fp@583: writel(txreg, base + NvRegTxWatermark);
fp@583:
fp@583: writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
fp@583: base + NvRegMisc1);
fp@583: pci_push(base);
fp@583: writel(np->linkspeed, base + NvRegLinkSpeed);
fp@583: pci_push(base);
fp@583:
fp@583: pause_flags = 0;
fp@583: /* setup pause frame */
fp@583: if (np->duplex != 0) {
fp@583: if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
fp@583: adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
fp@583: lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
fp@583:
fp@583: switch (adv_pause) {
fp@583: case ADVERTISE_PAUSE_CAP:
fp@583: if (lpa_pause & LPA_PAUSE_CAP) {
fp@583: pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
fp@583: pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
fp@583: }
fp@583: break;
fp@583: case ADVERTISE_PAUSE_ASYM:
fp@583: if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
fp@583: {
fp@583: pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
fp@583: }
fp@583: break;
fp@583: case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
fp@583: if (lpa_pause & LPA_PAUSE_CAP)
fp@583: {
fp@583: pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
fp@583: pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
fp@583: }
fp@583: if (lpa_pause == LPA_PAUSE_ASYM)
fp@583: {
fp@583: pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
fp@583: }
fp@583: break;
fp@583: }
fp@583: } else {
fp@583: pause_flags = np->pause_flags;
fp@583: }
fp@583: }
fp@583: nv_update_pause(dev, pause_flags);
fp@583:
fp@583: return retval;
fp@583: }
fp@583:
fp@583: static void nv_linkchange(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (np->ecdev) {
fp@591: int link = nv_update_linkspeed(dev);
fp@670: ecdev_set_link(np->ecdev, link);
fp@583: return;
fp@583: }
fp@583:
fp@583: if (nv_update_linkspeed(dev)) {
fp@583: if (!netif_carrier_ok(dev)) {
fp@583: netif_carrier_on(dev);
fp@583: printk(KERN_INFO "%s: link up.\n", dev->name);
fp@583: nv_start_rx(dev);
fp@583: }
fp@583: } else {
fp@583: if (netif_carrier_ok(dev)) {
fp@583: netif_carrier_off(dev);
fp@583: printk(KERN_INFO "%s: link down.\n", dev->name);
fp@583: nv_stop_rx(dev);
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: static void nv_link_irq(struct net_device *dev)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 miistat;
fp@583:
fp@583: miistat = readl(base + NvRegMIIStatus);
fp@583: writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
fp@583: dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
fp@583:
fp@583: if (miistat & (NVREG_MIISTAT_LINKCHANGE))
fp@583: nv_linkchange(dev);
fp@583: dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
fp@583: }
fp@583:
fp@583: static irqreturn_t nv_nic_irq(int foo, void *data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 events;
fp@583: int i;
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
fp@583:
fp@583: for (i=0; ; i++) {
fp@583: if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
fp@583: events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
fp@583: } else {
fp@583: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
fp@583: }
fp@583: pci_push(base);
fp@583: dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
fp@583: if (!(events & np->irqmask))
fp@583: break;
fp@583:
fp@591: if (!np->ecdev) spin_lock(&np->lock);
fp@583: nv_tx_done(dev);
fp@591: if (!np->ecdev) spin_unlock(&np->lock);
fp@583:
fp@583: if (events & NVREG_IRQ_LINK) {
fp@591: if (!np->ecdev) spin_lock(&np->lock);
fp@583: nv_link_irq(dev);
fp@591: if (!np->ecdev) spin_unlock(&np->lock);
fp@583: }
fp@583: if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
fp@591: if (!np->ecdev) spin_lock(&np->lock);
fp@583: nv_linkchange(dev);
fp@591: if (!np->ecdev) spin_unlock(&np->lock);
fp@583: np->link_timeout = jiffies + LINK_TIMEOUT;
fp@583: }
fp@583: if (events & (NVREG_IRQ_TX_ERR)) {
fp@583: dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
fp@583: dev->name, events);
fp@583: }
fp@583: if (events & (NVREG_IRQ_UNKNOWN)) {
fp@583: printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
fp@583: dev->name, events);
fp@583: }
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: if (events & NVREG_IRQ_RX_ALL) {
fp@591: if (np->ecdev) {
fp@591: nv_rx_process(dev, dev->weight);
fp@591: }
fp@591: else {
fp@591: netif_rx_schedule(dev);
fp@591:
fp@591: /* Disable furthur receive irq's */
fp@591: spin_lock(&np->lock);
fp@591: np->irqmask &= ~NVREG_IRQ_RX_ALL;
fp@591:
fp@591: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@591: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
fp@591: else
fp@591: writel(np->irqmask, base + NvRegIrqMask);
fp@591: spin_unlock(&np->lock);
fp@591: }
fp@583: }
fp@583: #else
fp@583: nv_rx_process(dev, dev->weight);
fp@591: if (nv_alloc_rx(dev) && !np->ecdev) {
fp@583: spin_lock(&np->lock);
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: spin_unlock(&np->lock);
fp@583: }
fp@583: #endif
fp@583: if (i > max_interrupt_work) {
fp@591: if (!np->ecdev) {
fp@591: spin_lock(&np->lock);
fp@591: /* disable interrupts on the nic */
fp@591: if (!(np->msi_flags & NV_MSI_X_ENABLED))
fp@591: writel(0, base + NvRegIrqMask);
fp@591: else
fp@591: writel(np->irqmask, base + NvRegIrqMask);
fp@591: pci_push(base);
fp@591:
fp@591: if (!np->in_shutdown) {
fp@591: np->nic_poll_irq = np->irqmask;
fp@591: mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
fp@591: }
fp@591: spin_unlock(&np->lock);
fp@583: }
fp@583: printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
fp@583: break;
fp@583: }
fp@583:
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
fp@583:
fp@583: return IRQ_RETVAL(i);
fp@583: }
fp@583:
fp@583: static irqreturn_t nv_nic_irq_tx(int foo, void *data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 events;
fp@583: int i;
fp@591: unsigned long flags = 0;
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
fp@583:
fp@583: for (i=0; ; i++) {
fp@583: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
fp@583: writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
fp@583: pci_push(base);
fp@583: dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
fp@583: if (!(events & np->irqmask))
fp@583: break;
fp@583:
fp@591: if (!np->ecdev) spin_lock_irqsave(&np->lock, flags);
fp@583: nv_tx_done(dev);
fp@591: if (!np->ecdev) spin_unlock_irqrestore(&np->lock, flags);
fp@583:
fp@583: if (events & (NVREG_IRQ_TX_ERR)) {
fp@583: dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
fp@583: dev->name, events);
fp@583: }
fp@583: if (i > max_interrupt_work) {
fp@591: if (!np->ecdev) {
fp@591: spin_lock_irqsave(&np->lock, flags);
fp@591: /* disable interrupts on the nic */
fp@591: writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
fp@591: pci_push(base);
fp@591:
fp@591: if (!np->in_shutdown) {
fp@591: np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
fp@591: mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
fp@591: }
fp@591: spin_unlock_irqrestore(&np->lock, flags);
fp@583: }
fp@583: printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
fp@583: break;
fp@583: }
fp@583:
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
fp@583:
fp@583: return IRQ_RETVAL(i);
fp@583: }
fp@583:
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: static int nv_napi_poll(struct net_device *dev, int *budget)
fp@583: {
fp@583: int pkts, limit = min(*budget, dev->quota);
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: pkts = nv_rx_process(dev, limit);
fp@583:
fp@583: if (nv_alloc_rx(dev)) {
fp@583: spin_lock_irq(&np->lock);
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583:
fp@583: if (pkts < limit) {
fp@583: /* all done, no more packets present */
fp@583: netif_rx_complete(dev);
fp@583:
fp@583: /* re-enable receive interrupts */
fp@583: spin_lock_irq(&np->lock);
fp@583: np->irqmask |= NVREG_IRQ_RX_ALL;
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
fp@583: else
fp@583: writel(np->irqmask, base + NvRegIrqMask);
fp@583: spin_unlock_irq(&np->lock);
fp@583: return 0;
fp@583: } else {
fp@583: /* used up our quantum, so reschedule */
fp@583: dev->quota -= pkts;
fp@583: *budget -= pkts;
fp@583: return 1;
fp@583: }
fp@583: }
fp@583: #endif
fp@583:
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: static irqreturn_t nv_nic_irq_rx(int foo, void *data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@591: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 events;
fp@583:
fp@583: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
fp@583: writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
fp@583:
fp@591: if (events && !np->ecdev) {
fp@583: netif_rx_schedule(dev);
fp@583: /* disable receive interrupts on the nic */
fp@583: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
fp@583: pci_push(base);
fp@583: }
fp@583: return IRQ_HANDLED;
fp@583: }
fp@583: #else
fp@583: static irqreturn_t nv_nic_irq_rx(int foo, void *data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 events;
fp@583: int i;
fp@583: unsigned long flags;
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
fp@583:
fp@583: for (i=0; ; i++) {
fp@583: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
fp@583: writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
fp@583: pci_push(base);
fp@583: dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
fp@583: if (!(events & np->irqmask))
fp@583: break;
fp@583:
fp@583: nv_rx_process(dev, dev->weight);
fp@591: if (nv_alloc_rx(dev) && !np->ecdev) {
fp@583: spin_lock_irqsave(&np->lock, flags);
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: spin_unlock_irqrestore(&np->lock, flags);
fp@583: }
fp@583:
fp@583: if (i > max_interrupt_work) {
fp@591: if (!np->ecdev) {
fp@591: spin_lock_irqsave(&np->lock, flags);
fp@591: /* disable interrupts on the nic */
fp@591: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
fp@591: pci_push(base);
fp@591:
fp@591: if (!np->in_shutdown) {
fp@591: np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
fp@591: mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
fp@591: }
fp@591: spin_unlock_irqrestore(&np->lock, flags);
fp@583: }
fp@583: printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
fp@583: break;
fp@583: }
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
fp@583:
fp@583: return IRQ_RETVAL(i);
fp@583: }
fp@583: #endif
fp@583:
fp@583: static irqreturn_t nv_nic_irq_other(int foo, void *data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 events;
fp@583: int i;
fp@591: unsigned long flags = 0;
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
fp@583:
fp@583: for (i=0; ; i++) {
fp@583: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
fp@583: writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
fp@583: pci_push(base);
fp@583: dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
fp@583: if (!(events & np->irqmask))
fp@583: break;
fp@583:
fp@583: if (events & NVREG_IRQ_LINK) {
fp@591: if (!np->ecdev) spin_lock_irqsave(&np->lock, flags);
fp@583: nv_link_irq(dev);
fp@591: if (!np->ecdev) spin_unlock_irqrestore(&np->lock, flags);
fp@583: }
fp@583: if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
fp@591: if (!np->ecdev) spin_lock_irqsave(&np->lock, flags);
fp@583: nv_linkchange(dev);
fp@591: if (!np->ecdev) spin_unlock_irqrestore(&np->lock, flags);
fp@583: np->link_timeout = jiffies + LINK_TIMEOUT;
fp@583: }
fp@583: if (events & (NVREG_IRQ_UNKNOWN)) {
fp@583: printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
fp@583: dev->name, events);
fp@583: }
fp@583: if (i > max_interrupt_work) {
fp@591: if (!np->ecdev) {
fp@591: spin_lock_irqsave(&np->lock, flags);
fp@591: /* disable interrupts on the nic */
fp@591: writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
fp@591: pci_push(base);
fp@591:
fp@591: if (!np->in_shutdown) {
fp@591: np->nic_poll_irq |= NVREG_IRQ_OTHER;
fp@591: mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
fp@591: }
fp@591: spin_unlock_irqrestore(&np->lock, flags);
fp@583: }
fp@583: printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
fp@583: break;
fp@583: }
fp@583:
fp@583: }
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
fp@583:
fp@583: return IRQ_RETVAL(i);
fp@583: }
fp@583:
fp@583: static irqreturn_t nv_nic_irq_test(int foo, void *data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 events;
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
fp@583:
fp@583: if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
fp@583: events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
fp@583: writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
fp@583: } else {
fp@583: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
fp@583: writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
fp@583: }
fp@583: pci_push(base);
fp@583: dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
fp@583: if (!(events & NVREG_IRQ_TIMER))
fp@583: return IRQ_RETVAL(0);
fp@583:
fp@583: spin_lock(&np->lock);
fp@583: np->intr_test = 1;
fp@583: spin_unlock(&np->lock);
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
fp@583:
fp@583: return IRQ_RETVAL(1);
fp@583: }
fp@583:
fp@583: static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int i;
fp@583: u32 msixmap = 0;
fp@583:
fp@583: /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
fp@583: * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
fp@583: * the remaining 8 interrupts.
fp@583: */
fp@583: for (i = 0; i < 8; i++) {
fp@583: if ((irqmask >> i) & 0x1) {
fp@583: msixmap |= vector << (i << 2);
fp@583: }
fp@583: }
fp@583: writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
fp@583:
fp@583: msixmap = 0;
fp@583: for (i = 0; i < 8; i++) {
fp@583: if ((irqmask >> (i + 8)) & 0x1) {
fp@583: msixmap |= vector << (i << 2);
fp@583: }
fp@583: }
fp@583: writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
fp@583: }
fp@583:
fp@583: static int nv_request_irq(struct net_device *dev, int intr_test)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int ret = 1;
fp@583: int i;
fp@583:
fp@583: if (np->msi_flags & NV_MSI_X_CAPABLE) {
fp@583: for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
fp@583: np->msi_x_entry[i].entry = i;
fp@583: }
fp@583: if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
fp@583: np->msi_flags |= NV_MSI_X_ENABLED;
fp@583: if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
fp@583: /* Request irq for rx handling */
fp@583: if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
fp@583: printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
fp@583: pci_disable_msix(np->pci_dev);
fp@583: np->msi_flags &= ~NV_MSI_X_ENABLED;
fp@583: goto out_err;
fp@583: }
fp@583: /* Request irq for tx handling */
fp@583: if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
fp@583: printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
fp@583: pci_disable_msix(np->pci_dev);
fp@583: np->msi_flags &= ~NV_MSI_X_ENABLED;
fp@583: goto out_free_rx;
fp@583: }
fp@583: /* Request irq for link and timer handling */
fp@583: if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
fp@583: printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
fp@583: pci_disable_msix(np->pci_dev);
fp@583: np->msi_flags &= ~NV_MSI_X_ENABLED;
fp@583: goto out_free_tx;
fp@583: }
fp@583: /* map interrupts to their respective vector */
fp@583: writel(0, base + NvRegMSIXMap0);
fp@583: writel(0, base + NvRegMSIXMap1);
fp@583: set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
fp@583: set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
fp@583: set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
fp@583: } else {
fp@583: /* Request irq for all interrupts */
fp@583: if ((!intr_test &&
fp@583: request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
fp@583: (intr_test &&
fp@583: request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
fp@583: printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
fp@583: pci_disable_msix(np->pci_dev);
fp@583: np->msi_flags &= ~NV_MSI_X_ENABLED;
fp@583: goto out_err;
fp@583: }
fp@583:
fp@583: /* map interrupts to vector 0 */
fp@583: writel(0, base + NvRegMSIXMap0);
fp@583: writel(0, base + NvRegMSIXMap1);
fp@583: }
fp@583: }
fp@583: }
fp@583: if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
fp@583: if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
fp@583: pci_intx(np->pci_dev, 0);
fp@583: np->msi_flags |= NV_MSI_ENABLED;
fp@583: if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
fp@583: (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
fp@583: printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
fp@583: pci_disable_msi(np->pci_dev);
fp@583: pci_intx(np->pci_dev, 1);
fp@583: np->msi_flags &= ~NV_MSI_ENABLED;
fp@583: goto out_err;
fp@583: }
fp@583:
fp@583: /* map interrupts to vector 0 */
fp@583: writel(0, base + NvRegMSIMap0);
fp@583: writel(0, base + NvRegMSIMap1);
fp@583: /* enable msi vector 0 */
fp@583: writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
fp@583: }
fp@583: }
fp@583: if (ret != 0) {
fp@583: if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
fp@583: (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
fp@583: goto out_err;
fp@583:
fp@583: }
fp@583:
fp@583: return 0;
fp@583: out_free_tx:
fp@583: free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
fp@583: out_free_rx:
fp@583: free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
fp@583: out_err:
fp@583: return 1;
fp@583: }
fp@583:
fp@583: static void nv_free_irq(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583: int i;
fp@583:
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED) {
fp@583: for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
fp@583: free_irq(np->msi_x_entry[i].vector, dev);
fp@583: }
fp@583: pci_disable_msix(np->pci_dev);
fp@583: np->msi_flags &= ~NV_MSI_X_ENABLED;
fp@583: } else {
fp@583: free_irq(np->pci_dev->irq, dev);
fp@583: if (np->msi_flags & NV_MSI_ENABLED) {
fp@583: pci_disable_msi(np->pci_dev);
fp@583: pci_intx(np->pci_dev, 1);
fp@583: np->msi_flags &= ~NV_MSI_ENABLED;
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: void ec_poll(struct net_device *dev)
fp@583: {
fp@591: struct fe_priv *np = netdev_priv(dev);
fp@591:
fp@591: if (!using_multi_irqs(dev)) {
fp@591: nv_nic_irq(0, dev);
fp@591: } else {
fp@591: if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
fp@591: nv_nic_irq_rx(0, dev);
fp@591: }
fp@591: if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
fp@591: nv_nic_irq_tx(0, dev);
fp@591: }
fp@591: if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
fp@591: nv_nic_irq_other(0, dev);
fp@591: }
fp@591: }
fp@583: }
fp@583:
fp@583: static void nv_do_nic_poll(unsigned long data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 mask = 0;
fp@583:
fp@583: /*
fp@583: * First disable irq(s) and then
fp@583: * reenable interrupts on the nic, we have to do this before calling
fp@583: * nv_nic_irq because that may decide to do otherwise
fp@583: */
fp@583:
fp@583: if (!using_multi_irqs(dev)) {
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
fp@583: else
fp@583: disable_irq_lockdep(dev->irq);
fp@583: mask = np->irqmask;
fp@583: } else {
fp@583: if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
fp@583: disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
fp@583: mask |= NVREG_IRQ_RX_ALL;
fp@583: }
fp@583: if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
fp@583: disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
fp@583: mask |= NVREG_IRQ_TX_ALL;
fp@583: }
fp@583: if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
fp@583: disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
fp@583: mask |= NVREG_IRQ_OTHER;
fp@583: }
fp@583: }
fp@583: np->nic_poll_irq = 0;
fp@583:
fp@583: /* FIXME: Do we need synchronize_irq(dev->irq) here? */
fp@583:
fp@583: writel(mask, base + NvRegIrqMask);
fp@583: pci_push(base);
fp@583:
fp@583: if (!using_multi_irqs(dev)) {
fp@583: nv_nic_irq(0, dev);
fp@583: if (np->msi_flags & NV_MSI_X_ENABLED)
fp@583: enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
fp@583: else
fp@583: enable_irq_lockdep(dev->irq);
fp@583: } else {
fp@583: if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
fp@583: nv_nic_irq_rx(0, dev);
fp@583: enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
fp@583: }
fp@583: if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
fp@583: nv_nic_irq_tx(0, dev);
fp@583: enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
fp@583: }
fp@583: if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
fp@583: nv_nic_irq_other(0, dev);
fp@583: enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: #ifdef CONFIG_NET_POLL_CONTROLLER
fp@583: static void nv_poll_controller(struct net_device *dev)
fp@583: {
fp@583: nv_do_nic_poll((unsigned long) dev);
fp@583: }
fp@583: #endif
fp@583:
fp@583: static void nv_do_stats_poll(unsigned long data)
fp@583: {
fp@583: struct net_device *dev = (struct net_device *) data;
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: np->estats.tx_bytes += readl(base + NvRegTxCnt);
fp@583: np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
fp@583: np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
fp@583: np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
fp@583: np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
fp@583: np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
fp@583: np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
fp@583: np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
fp@583: np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
fp@583: np->estats.tx_deferral += readl(base + NvRegTxDef);
fp@583: np->estats.tx_packets += readl(base + NvRegTxFrame);
fp@583: np->estats.tx_pause += readl(base + NvRegTxPause);
fp@583: np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
fp@583: np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
fp@583: np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
fp@583: np->estats.rx_runt += readl(base + NvRegRxRunt);
fp@583: np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
fp@583: np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
fp@583: np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
fp@583: np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
fp@583: np->estats.rx_length_error += readl(base + NvRegRxLenErr);
fp@583: np->estats.rx_unicast += readl(base + NvRegRxUnicast);
fp@583: np->estats.rx_multicast += readl(base + NvRegRxMulticast);
fp@583: np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
fp@583: np->estats.rx_bytes += readl(base + NvRegRxCnt);
fp@583: np->estats.rx_pause += readl(base + NvRegRxPause);
fp@583: np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
fp@583: np->estats.rx_packets =
fp@583: np->estats.rx_unicast +
fp@583: np->estats.rx_multicast +
fp@583: np->estats.rx_broadcast;
fp@583: np->estats.rx_errors_total =
fp@583: np->estats.rx_crc_errors +
fp@583: np->estats.rx_over_errors +
fp@583: np->estats.rx_frame_error +
fp@583: (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
fp@583: np->estats.rx_late_collision +
fp@583: np->estats.rx_runt +
fp@583: np->estats.rx_frame_too_long;
fp@583:
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
fp@583: }
fp@583:
fp@583: static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: strcpy(info->driver, "forcedeth");
fp@583: strcpy(info->version, FORCEDETH_VERSION);
fp@583: strcpy(info->bus_info, pci_name(np->pci_dev));
fp@583: }
fp@583:
fp@583: static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: wolinfo->supported = WAKE_MAGIC;
fp@583:
fp@583: spin_lock_irq(&np->lock);
fp@583: if (np->wolenabled)
fp@583: wolinfo->wolopts = WAKE_MAGIC;
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583:
fp@583: static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 flags = 0;
fp@583:
fp@583: if (wolinfo->wolopts == 0) {
fp@583: np->wolenabled = 0;
fp@583: } else if (wolinfo->wolopts & WAKE_MAGIC) {
fp@583: np->wolenabled = 1;
fp@583: flags = NVREG_WAKEUPFLAGS_ENABLE;
fp@583: }
fp@583: if (netif_running(dev)) {
fp@583: spin_lock_irq(&np->lock);
fp@583: writel(flags, base + NvRegWakeUpFlags);
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int adv;
fp@583:
fp@583: spin_lock_irq(&np->lock);
fp@583: ecmd->port = PORT_MII;
fp@583: if (!netif_running(dev)) {
fp@583: /* We do not track link speed / duplex setting if the
fp@583: * interface is disabled. Force a link check */
fp@583: if (nv_update_linkspeed(dev)) {
fp@583: if (!netif_carrier_ok(dev))
fp@583: netif_carrier_on(dev);
fp@583: } else {
fp@583: if (netif_carrier_ok(dev))
fp@583: netif_carrier_off(dev);
fp@583: }
fp@583: }
fp@583:
fp@583: if (netif_carrier_ok(dev)) {
fp@583: switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
fp@583: case NVREG_LINKSPEED_10:
fp@583: ecmd->speed = SPEED_10;
fp@583: break;
fp@583: case NVREG_LINKSPEED_100:
fp@583: ecmd->speed = SPEED_100;
fp@583: break;
fp@583: case NVREG_LINKSPEED_1000:
fp@583: ecmd->speed = SPEED_1000;
fp@583: break;
fp@583: }
fp@583: ecmd->duplex = DUPLEX_HALF;
fp@583: if (np->duplex)
fp@583: ecmd->duplex = DUPLEX_FULL;
fp@583: } else {
fp@583: ecmd->speed = -1;
fp@583: ecmd->duplex = -1;
fp@583: }
fp@583:
fp@583: ecmd->autoneg = np->autoneg;
fp@583:
fp@583: ecmd->advertising = ADVERTISED_MII;
fp@583: if (np->autoneg) {
fp@583: ecmd->advertising |= ADVERTISED_Autoneg;
fp@583: adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
fp@583: if (adv & ADVERTISE_10HALF)
fp@583: ecmd->advertising |= ADVERTISED_10baseT_Half;
fp@583: if (adv & ADVERTISE_10FULL)
fp@583: ecmd->advertising |= ADVERTISED_10baseT_Full;
fp@583: if (adv & ADVERTISE_100HALF)
fp@583: ecmd->advertising |= ADVERTISED_100baseT_Half;
fp@583: if (adv & ADVERTISE_100FULL)
fp@583: ecmd->advertising |= ADVERTISED_100baseT_Full;
fp@583: if (np->gigabit == PHY_GIGABIT) {
fp@583: adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
fp@583: if (adv & ADVERTISE_1000FULL)
fp@583: ecmd->advertising |= ADVERTISED_1000baseT_Full;
fp@583: }
fp@583: }
fp@583: ecmd->supported = (SUPPORTED_Autoneg |
fp@583: SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
fp@583: SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
fp@583: SUPPORTED_MII);
fp@583: if (np->gigabit == PHY_GIGABIT)
fp@583: ecmd->supported |= SUPPORTED_1000baseT_Full;
fp@583:
fp@583: ecmd->phy_address = np->phyaddr;
fp@583: ecmd->transceiver = XCVR_EXTERNAL;
fp@583:
fp@583: /* ignore maxtxpkt, maxrxpkt for now */
fp@583: spin_unlock_irq(&np->lock);
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (ecmd->port != PORT_MII)
fp@583: return -EINVAL;
fp@583: if (ecmd->transceiver != XCVR_EXTERNAL)
fp@583: return -EINVAL;
fp@583: if (ecmd->phy_address != np->phyaddr) {
fp@583: /* TODO: support switching between multiple phys. Should be
fp@583: * trivial, but not enabled due to lack of test hardware. */
fp@583: return -EINVAL;
fp@583: }
fp@583: if (ecmd->autoneg == AUTONEG_ENABLE) {
fp@583: u32 mask;
fp@583:
fp@583: mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
fp@583: ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
fp@583: if (np->gigabit == PHY_GIGABIT)
fp@583: mask |= ADVERTISED_1000baseT_Full;
fp@583:
fp@583: if ((ecmd->advertising & mask) == 0)
fp@583: return -EINVAL;
fp@583:
fp@583: } else if (ecmd->autoneg == AUTONEG_DISABLE) {
fp@583: /* Note: autonegotiation disable, speed 1000 intentionally
fp@583: * forbidden - noone should need that. */
fp@583:
fp@583: if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
fp@583: return -EINVAL;
fp@583: if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
fp@583: return -EINVAL;
fp@583: } else {
fp@583: return -EINVAL;
fp@583: }
fp@583:
fp@583: netif_carrier_off(dev);
fp@583: if (netif_running(dev)) {
fp@583: nv_disable_irq(dev);
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock(&np->lock);
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: spin_unlock(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: }
fp@583:
fp@583: if (ecmd->autoneg == AUTONEG_ENABLE) {
fp@583: int adv, bmcr;
fp@583:
fp@583: np->autoneg = 1;
fp@583:
fp@583: /* advertise only what has been requested */
fp@583: adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
fp@583: adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
fp@583: if (ecmd->advertising & ADVERTISED_10baseT_Half)
fp@583: adv |= ADVERTISE_10HALF;
fp@583: if (ecmd->advertising & ADVERTISED_10baseT_Full)
fp@583: adv |= ADVERTISE_10FULL;
fp@583: if (ecmd->advertising & ADVERTISED_100baseT_Half)
fp@583: adv |= ADVERTISE_100HALF;
fp@583: if (ecmd->advertising & ADVERTISED_100baseT_Full)
fp@583: adv |= ADVERTISE_100FULL;
fp@583: if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
fp@583: adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
fp@583: adv |= ADVERTISE_PAUSE_ASYM;
fp@583: mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
fp@583:
fp@583: if (np->gigabit == PHY_GIGABIT) {
fp@583: adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
fp@583: adv &= ~ADVERTISE_1000FULL;
fp@583: if (ecmd->advertising & ADVERTISED_1000baseT_Full)
fp@583: adv |= ADVERTISE_1000FULL;
fp@583: mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
fp@583: }
fp@583:
fp@583: if (netif_running(dev))
fp@583: printk(KERN_INFO "%s: link down.\n", dev->name);
fp@583: bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
fp@583: bmcr |= BMCR_ANENABLE;
fp@583: /* reset the phy in order for settings to stick,
fp@583: * and cause autoneg to start */
fp@583: if (phy_reset(dev, bmcr)) {
fp@583: printk(KERN_INFO "%s: phy reset failed\n", dev->name);
fp@583: return -EINVAL;
fp@583: }
fp@583: } else {
fp@583: bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
fp@583: mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
fp@583: }
fp@583: } else {
fp@583: int adv, bmcr;
fp@583:
fp@583: np->autoneg = 0;
fp@583:
fp@583: adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
fp@583: adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
fp@583: if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
fp@583: adv |= ADVERTISE_10HALF;
fp@583: if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
fp@583: adv |= ADVERTISE_10FULL;
fp@583: if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
fp@583: adv |= ADVERTISE_100HALF;
fp@583: if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
fp@583: adv |= ADVERTISE_100FULL;
fp@583: np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
fp@583: if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
fp@583: adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
fp@583: np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
fp@583: }
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
fp@583: adv |= ADVERTISE_PAUSE_ASYM;
fp@583: np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
fp@583: }
fp@583: mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
fp@583: np->fixed_mode = adv;
fp@583:
fp@583: if (np->gigabit == PHY_GIGABIT) {
fp@583: adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
fp@583: adv &= ~ADVERTISE_1000FULL;
fp@583: mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
fp@583: }
fp@583:
fp@583: bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
fp@583: if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
fp@583: bmcr |= BMCR_FULLDPLX;
fp@583: if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
fp@583: bmcr |= BMCR_SPEED100;
fp@583: if (np->phy_oui == PHY_OUI_MARVELL) {
fp@583: /* reset the phy in order for forced mode settings to stick */
fp@583: if (phy_reset(dev, bmcr)) {
fp@583: printk(KERN_INFO "%s: phy reset failed\n", dev->name);
fp@583: return -EINVAL;
fp@583: }
fp@583: } else {
fp@583: mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
fp@583: if (netif_running(dev)) {
fp@583: /* Wait a bit and then reconfigure the nic. */
fp@583: udelay(10);
fp@583: nv_linkchange(dev);
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583: nv_enable_irq(dev);
fp@583: }
fp@583:
fp@583: return 0;
fp@583: }
fp@583:
fp@583: #define FORCEDETH_REGS_VER 1
fp@583:
fp@583: static int nv_get_regs_len(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: return np->register_size;
fp@583: }
fp@583:
fp@583: static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u32 *rbuf = buf;
fp@583: int i;
fp@583:
fp@583: regs->version = FORCEDETH_REGS_VER;
fp@583: spin_lock_irq(&np->lock);
fp@583: for (i = 0;i <= np->register_size/sizeof(u32); i++)
fp@583: rbuf[i] = readl(base + i*sizeof(u32));
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583:
fp@583: static int nv_nway_reset(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int ret;
fp@583:
fp@583: if (np->autoneg) {
fp@583: int bmcr;
fp@583:
fp@583: netif_carrier_off(dev);
fp@583: if (netif_running(dev)) {
fp@583: nv_disable_irq(dev);
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock(&np->lock);
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: spin_unlock(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: printk(KERN_INFO "%s: link down.\n", dev->name);
fp@583: }
fp@583:
fp@583: bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
fp@583: bmcr |= BMCR_ANENABLE;
fp@583: /* reset the phy in order for settings to stick*/
fp@583: if (phy_reset(dev, bmcr)) {
fp@583: printk(KERN_INFO "%s: phy reset failed\n", dev->name);
fp@583: return -EINVAL;
fp@583: }
fp@583: } else {
fp@583: bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
fp@583: mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
fp@583: }
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583: nv_enable_irq(dev);
fp@583: }
fp@583: ret = 0;
fp@583: } else {
fp@583: ret = -EINVAL;
fp@583: }
fp@583:
fp@583: return ret;
fp@583: }
fp@583:
fp@583: static int nv_set_tso(struct net_device *dev, u32 value)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if ((np->driver_data & DEV_HAS_CHECKSUM))
fp@583: return ethtool_op_set_tso(dev, value);
fp@583: else
fp@583: return -EOPNOTSUPP;
fp@583: }
fp@583:
fp@583: static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
fp@583: ring->rx_mini_max_pending = 0;
fp@583: ring->rx_jumbo_max_pending = 0;
fp@583: ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
fp@583:
fp@583: ring->rx_pending = np->rx_ring_size;
fp@583: ring->rx_mini_pending = 0;
fp@583: ring->rx_jumbo_pending = 0;
fp@583: ring->tx_pending = np->tx_ring_size;
fp@583: }
fp@583:
fp@583: static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
fp@583: dma_addr_t ring_addr;
fp@583:
fp@583: if (ring->rx_pending < RX_RING_MIN ||
fp@583: ring->tx_pending < TX_RING_MIN ||
fp@583: ring->rx_mini_pending != 0 ||
fp@583: ring->rx_jumbo_pending != 0 ||
fp@583: (np->desc_ver == DESC_VER_1 &&
fp@583: (ring->rx_pending > RING_MAX_DESC_VER_1 ||
fp@583: ring->tx_pending > RING_MAX_DESC_VER_1)) ||
fp@583: (np->desc_ver != DESC_VER_1 &&
fp@583: (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
fp@583: ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
fp@583: return -EINVAL;
fp@583: }
fp@583:
fp@583: /* allocate new rings */
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: rxtx_ring = pci_alloc_consistent(np->pci_dev,
fp@583: sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
fp@583: &ring_addr);
fp@583: } else {
fp@583: rxtx_ring = pci_alloc_consistent(np->pci_dev,
fp@583: sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
fp@583: &ring_addr);
fp@583: }
fp@583: rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
fp@583: rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
fp@583: tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
fp@583: tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
fp@583: tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
fp@583: if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
fp@583: /* fall back to old rings */
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: if (rxtx_ring)
fp@583: pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
fp@583: rxtx_ring, ring_addr);
fp@583: } else {
fp@583: if (rxtx_ring)
fp@583: pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
fp@583: rxtx_ring, ring_addr);
fp@583: }
fp@583: if (rx_skbuff)
fp@583: kfree(rx_skbuff);
fp@583: if (rx_dma)
fp@583: kfree(rx_dma);
fp@583: if (tx_skbuff)
fp@583: kfree(tx_skbuff);
fp@583: if (tx_dma)
fp@583: kfree(tx_dma);
fp@583: if (tx_dma_len)
fp@583: kfree(tx_dma_len);
fp@583: goto exit;
fp@583: }
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: nv_disable_irq(dev);
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock(&np->lock);
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: nv_txrx_reset(dev);
fp@583: /* drain queues */
fp@583: nv_drain_rx(dev);
fp@583: nv_drain_tx(dev);
fp@583: /* delete queues */
fp@583: free_rings(dev);
fp@583: }
fp@583:
fp@583: /* set new values */
fp@583: np->rx_ring_size = ring->rx_pending;
fp@583: np->tx_ring_size = ring->tx_pending;
fp@583: np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
fp@583: np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
fp@583: np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
fp@583: } else {
fp@583: np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
fp@583: np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
fp@583: }
fp@583: np->rx_skbuff = (struct sk_buff**)rx_skbuff;
fp@583: np->rx_dma = (dma_addr_t*)rx_dma;
fp@583: np->tx_skbuff = (struct sk_buff**)tx_skbuff;
fp@583: np->tx_dma = (dma_addr_t*)tx_dma;
fp@583: np->tx_dma_len = (unsigned int*)tx_dma_len;
fp@583: np->ring_addr = ring_addr;
fp@583:
fp@583: memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
fp@583: memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
fp@583: memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
fp@583: memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
fp@583: memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: /* reinit driver view of the queues */
fp@583: set_bufsize(dev);
fp@583: if (nv_init_ring(dev)) {
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: }
fp@583:
fp@583: /* reinit nic view of the queues */
fp@583: writel(np->rx_buf_sz, base + NvRegOffloadConfig);
fp@583: setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
fp@583: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
fp@583: base + NvRegRingSizes);
fp@583: pci_push(base);
fp@583: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583:
fp@583: /* restart engines */
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583: spin_unlock(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: nv_enable_irq(dev);
fp@583: }
fp@583: return 0;
fp@583: exit:
fp@583: return -ENOMEM;
fp@583: }
fp@583:
fp@583: static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
fp@583: pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
fp@583: pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
fp@583: }
fp@583:
fp@583: static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int adv, bmcr;
fp@583:
fp@583: if ((!np->autoneg && np->duplex == 0) ||
fp@583: (np->autoneg && !pause->autoneg && np->duplex == 0)) {
fp@583: printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
fp@583: dev->name);
fp@583: return -EINVAL;
fp@583: }
fp@583: if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
fp@583: printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
fp@583: return -EINVAL;
fp@583: }
fp@583:
fp@583: netif_carrier_off(dev);
fp@583: if (netif_running(dev)) {
fp@583: nv_disable_irq(dev);
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock(&np->lock);
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: spin_unlock(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: }
fp@583:
fp@583: np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
fp@583: if (pause->rx_pause)
fp@583: np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
fp@583: if (pause->tx_pause)
fp@583: np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
fp@583:
fp@583: if (np->autoneg && pause->autoneg) {
fp@583: np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
fp@583:
fp@583: adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
fp@583: adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
fp@583: if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
fp@583: adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
fp@583: adv |= ADVERTISE_PAUSE_ASYM;
fp@583: mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
fp@583:
fp@583: if (netif_running(dev))
fp@583: printk(KERN_INFO "%s: link down.\n", dev->name);
fp@583: bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
fp@583: bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
fp@583: mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
fp@583: } else {
fp@583: np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
fp@583: if (pause->rx_pause)
fp@583: np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
fp@583: if (pause->tx_pause)
fp@583: np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
fp@583:
fp@583: if (!netif_running(dev))
fp@583: nv_update_linkspeed(dev);
fp@583: else
fp@583: nv_update_pause(dev, np->pause_flags);
fp@583: }
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583: nv_enable_irq(dev);
fp@583: }
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static u32 nv_get_rx_csum(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: return (np->rx_csum) != 0;
fp@583: }
fp@583:
fp@583: static int nv_set_rx_csum(struct net_device *dev, u32 data)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int retcode = 0;
fp@583:
fp@583: if (np->driver_data & DEV_HAS_CHECKSUM) {
fp@583: if (data) {
fp@583: np->rx_csum = 1;
fp@583: np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
fp@583: } else {
fp@583: np->rx_csum = 0;
fp@583: /* vlan is dependent on rx checksum offload */
fp@583: if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
fp@583: np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
fp@583: }
fp@583: if (netif_running(dev)) {
fp@583: spin_lock_irq(&np->lock);
fp@583: writel(np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: spin_unlock_irq(&np->lock);
fp@583: }
fp@583: } else {
fp@583: return -EINVAL;
fp@583: }
fp@583:
fp@583: return retcode;
fp@583: }
fp@583:
fp@583: static int nv_set_tx_csum(struct net_device *dev, u32 data)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (np->driver_data & DEV_HAS_CHECKSUM)
fp@583: return ethtool_op_set_tx_hw_csum(dev, data);
fp@583: else
fp@583: return -EOPNOTSUPP;
fp@583: }
fp@583:
fp@583: static int nv_set_sg(struct net_device *dev, u32 data)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (np->driver_data & DEV_HAS_CHECKSUM)
fp@583: return ethtool_op_set_sg(dev, data);
fp@583: else
fp@583: return -EOPNOTSUPP;
fp@583: }
fp@583:
fp@583: static int nv_get_stats_count(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (np->driver_data & DEV_HAS_STATISTICS)
fp@583: return sizeof(struct nv_ethtool_stats)/sizeof(u64);
fp@583: else
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: /* update stats */
fp@583: nv_do_stats_poll((unsigned long)dev);
fp@583:
fp@583: memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
fp@583: }
fp@583:
fp@583: static int nv_self_test_count(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583:
fp@583: if (np->driver_data & DEV_HAS_TEST_EXTENDED)
fp@583: return NV_TEST_COUNT_EXTENDED;
fp@583: else
fp@583: return NV_TEST_COUNT_BASE;
fp@583: }
fp@583:
fp@583: static int nv_link_test(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: int mii_status;
fp@583:
fp@583: mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
fp@583: mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
fp@583:
fp@583: /* check phy link status */
fp@583: if (!(mii_status & BMSR_LSTATUS))
fp@583: return 0;
fp@583: else
fp@583: return 1;
fp@583: }
fp@583:
fp@583: static int nv_register_test(struct net_device *dev)
fp@583: {
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int i = 0;
fp@583: u32 orig_read, new_read;
fp@583:
fp@583: do {
fp@583: orig_read = readl(base + nv_registers_test[i].reg);
fp@583:
fp@583: /* xor with mask to toggle bits */
fp@583: orig_read ^= nv_registers_test[i].mask;
fp@583:
fp@583: writel(orig_read, base + nv_registers_test[i].reg);
fp@583:
fp@583: new_read = readl(base + nv_registers_test[i].reg);
fp@583:
fp@583: if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
fp@583: return 0;
fp@583:
fp@583: /* restore original value */
fp@583: orig_read ^= nv_registers_test[i].mask;
fp@583: writel(orig_read, base + nv_registers_test[i].reg);
fp@583:
fp@583: } while (nv_registers_test[++i].reg != 0);
fp@583:
fp@583: return 1;
fp@583: }
fp@583:
fp@583: static int nv_interrupt_test(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int ret = 1;
fp@583: int testcnt;
fp@583: u32 save_msi_flags, save_poll_interval = 0;
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: /* free current irq */
fp@583: nv_free_irq(dev);
fp@583: save_poll_interval = readl(base+NvRegPollingInterval);
fp@583: }
fp@583:
fp@583: /* flag to test interrupt handler */
fp@583: np->intr_test = 0;
fp@583:
fp@583: /* setup test irq */
fp@583: save_msi_flags = np->msi_flags;
fp@583: np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
fp@583: np->msi_flags |= 0x001; /* setup 1 vector */
fp@583: if (nv_request_irq(dev, 1))
fp@583: return 0;
fp@583:
fp@583: /* setup timer interrupt */
fp@583: writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
fp@583: writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
fp@583:
fp@583: nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
fp@583:
fp@583: /* wait for at least one interrupt */
fp@583: msleep(100);
fp@583:
fp@583: spin_lock_irq(&np->lock);
fp@583:
fp@583: /* flag should be set within ISR */
fp@583: testcnt = np->intr_test;
fp@583: if (!testcnt)
fp@583: ret = 2;
fp@583:
fp@583: nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
fp@583: if (!(np->msi_flags & NV_MSI_X_ENABLED))
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
fp@583: else
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
fp@583:
fp@583: spin_unlock_irq(&np->lock);
fp@583:
fp@583: nv_free_irq(dev);
fp@583:
fp@583: np->msi_flags = save_msi_flags;
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: writel(save_poll_interval, base + NvRegPollingInterval);
fp@583: writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
fp@583: /* restore original irq */
fp@583: if (nv_request_irq(dev, 0))
fp@583: return 0;
fp@583: }
fp@583:
fp@583: return ret;
fp@583: }
fp@583:
fp@583: static int nv_loopback_test(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: struct sk_buff *tx_skb, *rx_skb;
fp@583: dma_addr_t test_dma_addr;
fp@583: u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
fp@583: u32 flags;
fp@583: int len, i, pkt_len;
fp@583: u8 *pkt_data;
fp@583: u32 filter_flags = 0;
fp@583: u32 misc1_flags = 0;
fp@583: int ret = 1;
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: nv_disable_irq(dev);
fp@583: filter_flags = readl(base + NvRegPacketFilterFlags);
fp@583: misc1_flags = readl(base + NvRegMisc1);
fp@583: } else {
fp@583: nv_txrx_reset(dev);
fp@583: }
fp@583:
fp@583: /* reinit driver view of the rx queue */
fp@583: set_bufsize(dev);
fp@583: nv_init_ring(dev);
fp@583:
fp@583: /* setup hardware for loopback */
fp@583: writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
fp@583: writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
fp@583:
fp@583: /* reinit nic view of the rx queue */
fp@583: writel(np->rx_buf_sz, base + NvRegOffloadConfig);
fp@583: setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
fp@583: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
fp@583: base + NvRegRingSizes);
fp@583: pci_push(base);
fp@583:
fp@583: /* restart rx engine */
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583:
fp@583: /* setup packet for tx */
fp@583: pkt_len = ETH_DATA_LEN;
fp@583: tx_skb = dev_alloc_skb(pkt_len);
fp@583: if (!tx_skb) {
fp@583: printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
fp@583: " of %s\n", dev->name);
fp@583: ret = 0;
fp@583: goto out;
fp@583: }
fp@583: pkt_data = skb_put(tx_skb, pkt_len);
fp@583: for (i = 0; i < pkt_len; i++)
fp@583: pkt_data[i] = (u8)(i & 0xff);
fp@583: test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
fp@583: tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
fp@583: np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
fp@583: } else {
fp@583: np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
fp@583: np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
fp@583: np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
fp@583: }
fp@583: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
fp@583: pci_push(get_hwbase(dev));
fp@583:
fp@583: msleep(500);
fp@583:
fp@583: /* check for rx of the packet */
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
fp@583: len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
fp@583:
fp@583: } else {
fp@583: flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
fp@583: len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
fp@583: }
fp@583:
fp@583: if (flags & NV_RX_AVAIL) {
fp@583: ret = 0;
fp@583: } else if (np->desc_ver == DESC_VER_1) {
fp@583: if (flags & NV_RX_ERROR)
fp@583: ret = 0;
fp@583: } else {
fp@583: if (flags & NV_RX2_ERROR) {
fp@583: ret = 0;
fp@583: }
fp@583: }
fp@583:
fp@583: if (ret) {
fp@583: if (len != pkt_len) {
fp@583: ret = 0;
fp@583: dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
fp@583: dev->name, len, pkt_len);
fp@583: } else {
fp@583: rx_skb = np->rx_skbuff[0];
fp@583: for (i = 0; i < pkt_len; i++) {
fp@583: if (rx_skb->data[i] != (u8)(i & 0xff)) {
fp@583: ret = 0;
fp@583: dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
fp@583: dev->name, i);
fp@583: break;
fp@583: }
fp@583: }
fp@583: }
fp@583: } else {
fp@583: dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
fp@583: }
fp@583:
fp@583: pci_unmap_page(np->pci_dev, test_dma_addr,
fp@583: tx_skb->end-tx_skb->data,
fp@583: PCI_DMA_TODEVICE);
fp@583: dev_kfree_skb_any(tx_skb);
fp@583: out:
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: nv_txrx_reset(dev);
fp@583: /* drain rx queue */
fp@583: nv_drain_rx(dev);
fp@583: nv_drain_tx(dev);
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: writel(misc1_flags, base + NvRegMisc1);
fp@583: writel(filter_flags, base + NvRegPacketFilterFlags);
fp@583: nv_enable_irq(dev);
fp@583: }
fp@583:
fp@583: return ret;
fp@583: }
fp@583:
fp@583: static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int result;
fp@583: memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
fp@583:
fp@583: if (!nv_link_test(dev)) {
fp@583: test->flags |= ETH_TEST_FL_FAILED;
fp@583: buffer[0] = 1;
fp@583: }
fp@583:
fp@583: if (test->flags & ETH_TEST_FL_OFFLINE) {
fp@583: if (netif_running(dev)) {
fp@583: netif_stop_queue(dev);
fp@583: netif_poll_disable(dev);
fp@583: netif_tx_lock_bh(dev);
fp@583: spin_lock_irq(&np->lock);
fp@583: nv_disable_hw_interrupts(dev, np->irqmask);
fp@583: if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
fp@583: } else {
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
fp@583: }
fp@583: /* stop engines */
fp@583: nv_stop_rx(dev);
fp@583: nv_stop_tx(dev);
fp@583: nv_txrx_reset(dev);
fp@583: /* drain rx queue */
fp@583: nv_drain_rx(dev);
fp@583: nv_drain_tx(dev);
fp@583: spin_unlock_irq(&np->lock);
fp@583: netif_tx_unlock_bh(dev);
fp@583: }
fp@583:
fp@583: if (!nv_register_test(dev)) {
fp@583: test->flags |= ETH_TEST_FL_FAILED;
fp@583: buffer[1] = 1;
fp@583: }
fp@583:
fp@583: result = nv_interrupt_test(dev);
fp@583: if (result != 1) {
fp@583: test->flags |= ETH_TEST_FL_FAILED;
fp@583: buffer[2] = 1;
fp@583: }
fp@583: if (result == 0) {
fp@583: /* bail out */
fp@583: return;
fp@583: }
fp@583:
fp@583: if (!nv_loopback_test(dev)) {
fp@583: test->flags |= ETH_TEST_FL_FAILED;
fp@583: buffer[3] = 1;
fp@583: }
fp@583:
fp@583: if (netif_running(dev)) {
fp@583: /* reinit driver view of the rx queue */
fp@583: set_bufsize(dev);
fp@583: if (nv_init_ring(dev)) {
fp@583: if (!np->in_shutdown)
fp@583: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@583: }
fp@583: /* reinit nic view of the rx queue */
fp@583: writel(np->rx_buf_sz, base + NvRegOffloadConfig);
fp@583: setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
fp@583: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
fp@583: base + NvRegRingSizes);
fp@583: pci_push(base);
fp@583: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
fp@583: pci_push(base);
fp@583: /* restart rx engine */
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@583: netif_start_queue(dev);
fp@583: netif_poll_enable(dev);
fp@583: nv_enable_hw_interrupts(dev, np->irqmask);
fp@583: }
fp@583: }
fp@583: }
fp@583:
fp@583: static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
fp@583: {
fp@583: switch (stringset) {
fp@583: case ETH_SS_STATS:
fp@583: memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
fp@583: break;
fp@583: case ETH_SS_TEST:
fp@583: memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
fp@583: break;
fp@583: }
fp@583: }
fp@583:
fp@583: static const struct ethtool_ops ops = {
fp@583: .get_drvinfo = nv_get_drvinfo,
fp@583: .get_link = ethtool_op_get_link,
fp@583: .get_wol = nv_get_wol,
fp@583: .set_wol = nv_set_wol,
fp@583: .get_settings = nv_get_settings,
fp@583: .set_settings = nv_set_settings,
fp@583: .get_regs_len = nv_get_regs_len,
fp@583: .get_regs = nv_get_regs,
fp@583: .nway_reset = nv_nway_reset,
fp@583: .get_perm_addr = ethtool_op_get_perm_addr,
fp@583: .get_tso = ethtool_op_get_tso,
fp@583: .set_tso = nv_set_tso,
fp@583: .get_ringparam = nv_get_ringparam,
fp@583: .set_ringparam = nv_set_ringparam,
fp@583: .get_pauseparam = nv_get_pauseparam,
fp@583: .set_pauseparam = nv_set_pauseparam,
fp@583: .get_rx_csum = nv_get_rx_csum,
fp@583: .set_rx_csum = nv_set_rx_csum,
fp@583: .get_tx_csum = ethtool_op_get_tx_csum,
fp@583: .set_tx_csum = nv_set_tx_csum,
fp@583: .get_sg = ethtool_op_get_sg,
fp@583: .set_sg = nv_set_sg,
fp@583: .get_strings = nv_get_strings,
fp@583: .get_stats_count = nv_get_stats_count,
fp@583: .get_ethtool_stats = nv_get_ethtool_stats,
fp@583: .self_test_count = nv_self_test_count,
fp@583: .self_test = nv_self_test,
fp@583: };
fp@583:
fp@583: static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
fp@583: {
fp@583: struct fe_priv *np = get_nvpriv(dev);
fp@583:
fp@583: spin_lock_irq(&np->lock);
fp@583:
fp@583: /* save vlan group */
fp@583: np->vlangrp = grp;
fp@583:
fp@583: if (grp) {
fp@583: /* enable vlan on MAC */
fp@583: np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
fp@583: } else {
fp@583: /* disable vlan on MAC */
fp@583: np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
fp@583: np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
fp@583: }
fp@583:
fp@583: writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
fp@583:
fp@583: spin_unlock_irq(&np->lock);
fp@583: };
fp@583:
fp@583: static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
fp@583: {
fp@583: /* nothing to do */
fp@583: };
fp@583:
fp@583: static int nv_open(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583: int ret = 1;
fp@583: int oom, i;
fp@583:
fp@583: dprintk(KERN_DEBUG "nv_open: begin\n");
fp@583:
fp@583: /* erase previous misconfiguration */
fp@583: if (np->driver_data & DEV_HAS_POWER_CNTRL)
fp@583: nv_mac_reset(dev);
fp@583: writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
fp@583: writel(0, base + NvRegMulticastAddrB);
fp@583: writel(0, base + NvRegMulticastMaskA);
fp@583: writel(0, base + NvRegMulticastMaskB);
fp@583: writel(0, base + NvRegPacketFilterFlags);
fp@583:
fp@583: writel(0, base + NvRegTransmitterControl);
fp@583: writel(0, base + NvRegReceiverControl);
fp@583:
fp@583: writel(0, base + NvRegAdapterControl);
fp@583:
fp@583: if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
fp@583: writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
fp@583:
fp@583: /* initialize descriptor rings */
fp@583: set_bufsize(dev);
fp@583: oom = nv_init_ring(dev);
fp@583:
fp@583: writel(0, base + NvRegLinkSpeed);
fp@583: writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
fp@583: nv_txrx_reset(dev);
fp@583: writel(0, base + NvRegUnknownSetupReg6);
fp@583:
fp@583: np->in_shutdown = 0;
fp@583:
fp@583: /* give hw rings */
fp@583: setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
fp@583: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
fp@583: base + NvRegRingSizes);
fp@583:
fp@583: writel(np->linkspeed, base + NvRegLinkSpeed);
fp@583: if (np->desc_ver == DESC_VER_1)
fp@583: writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
fp@583: else
fp@583: writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
fp@583: writel(np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: writel(np->vlanctl_bits, base + NvRegVlanControl);
fp@583: pci_push(base);
fp@583: writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
fp@583: reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
fp@583: NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
fp@583: KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
fp@583:
fp@583: writel(0, base + NvRegUnknownSetupReg4);
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
fp@583: writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
fp@583:
fp@583: writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
fp@583: writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
fp@583: writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
fp@583: writel(np->rx_buf_sz, base + NvRegOffloadConfig);
fp@583:
fp@583: writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
fp@583: get_random_bytes(&i, sizeof(i));
fp@583: writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
fp@583: writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
fp@583: writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
fp@583: if (poll_interval == -1) {
fp@583: if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
fp@583: writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
fp@583: else
fp@583: writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
fp@583: }
fp@583: else
fp@583: writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
fp@583: writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
fp@583: writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
fp@583: base + NvRegAdapterControl);
fp@583: writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
fp@583: writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
fp@583: if (np->wolenabled)
fp@583: writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
fp@583:
fp@583: i = readl(base + NvRegPowerState);
fp@583: if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
fp@583: writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
fp@583:
fp@583: pci_push(base);
fp@583: udelay(10);
fp@583: writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
fp@583:
fp@583: nv_disable_hw_interrupts(dev, np->irqmask);
fp@583: pci_push(base);
fp@583: writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
fp@583: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
fp@583: pci_push(base);
fp@583:
fp@591: if (!np->ecdev) {
fp@591: if (nv_request_irq(dev, 0)) {
fp@591: goto out_drain;
fp@591: }
fp@591:
fp@591: /* ask for interrupts */
fp@591: nv_enable_hw_interrupts(dev, np->irqmask);
fp@591:
fp@591: spin_lock_irq(&np->lock);
fp@591: }
fp@591:
fp@583: writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
fp@583: writel(0, base + NvRegMulticastAddrB);
fp@583: writel(0, base + NvRegMulticastMaskA);
fp@583: writel(0, base + NvRegMulticastMaskB);
fp@583: writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
fp@583: /* One manual link speed update: Interrupts are enabled, future link
fp@583: * speed changes cause interrupts and are handled by nv_link_irq().
fp@583: */
fp@583: {
fp@583: u32 miistat;
fp@583: miistat = readl(base + NvRegMIIStatus);
fp@583: writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
fp@583: dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
fp@583: }
fp@583: /* set linkspeed to invalid value, thus force nv_update_linkspeed
fp@583: * to init hw */
fp@583: np->linkspeed = 0;
fp@583: ret = nv_update_linkspeed(dev);
fp@583: nv_start_rx(dev);
fp@583: nv_start_tx(dev);
fp@591:
fp@591: if (np->ecdev) {
fp@670: ecdev_set_link(np->ecdev, ret);
fp@591: }
fp@591: else {
fp@591: netif_start_queue(dev);
fp@591: netif_poll_enable(dev);
fp@591:
fp@591: if (ret) {
fp@591: netif_carrier_on(dev);
fp@591: } else {
fp@591: printk("%s: no link during initialization.\n", dev->name);
fp@591: netif_carrier_off(dev);
fp@591: }
fp@591: if (oom)
fp@591: mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
fp@591:
fp@591: /* start statistics timer */
fp@591: if (np->driver_data & DEV_HAS_STATISTICS)
fp@591: mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
fp@591:
fp@591: spin_unlock_irq(&np->lock);
fp@591: }
fp@583:
fp@583: return 0;
fp@583: out_drain:
fp@583: drain_ring(dev);
fp@583: return ret;
fp@583: }
fp@583:
fp@583: static int nv_close(struct net_device *dev)
fp@583: {
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base;
fp@583:
fp@591: if (!np->ecdev) {
fp@591: spin_lock_irq(&np->lock);
fp@591: np->in_shutdown = 1;
fp@591: spin_unlock_irq(&np->lock);
fp@591: netif_poll_disable(dev);
fp@591: synchronize_irq(dev->irq);
fp@591:
fp@591: del_timer_sync(&np->oom_kick);
fp@591: del_timer_sync(&np->nic_poll);
fp@591: del_timer_sync(&np->stats_poll);
fp@591:
fp@591: netif_stop_queue(dev);
fp@591: spin_lock_irq(&np->lock);
fp@591: }
fp@591:
fp@583: nv_stop_tx(dev);
fp@583: nv_stop_rx(dev);
fp@583: nv_txrx_reset(dev);
fp@583:
fp@583: /* disable interrupts on the nic or we will lock up */
fp@591: if (!np->ecdev) {
fp@593: base = get_hwbase(dev);
fp@593: nv_disable_hw_interrupts(dev, np->irqmask);
fp@593: pci_push(base);
fp@593: dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
fp@593:
fp@591: spin_unlock_irq(&np->lock);
fp@591:
fp@591: nv_free_irq(dev);
fp@591: }
fp@583:
fp@583: drain_ring(dev);
fp@583:
fp@583: if (np->wolenabled)
fp@583: nv_start_rx(dev);
fp@583:
fp@583: /* FIXME: power down nic */
fp@583:
fp@583: return 0;
fp@583: }
fp@583:
fp@583: static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
fp@583: {
fp@583: struct net_device *dev;
fp@583: struct fe_priv *np;
fp@583: unsigned long addr;
fp@583: u8 __iomem *base;
fp@583: int err, i;
fp@583: u32 powerstate, txreg;
fp@583:
fp@583: board_idx++;
fp@583:
fp@583: dev = alloc_etherdev(sizeof(struct fe_priv));
fp@583: err = -ENOMEM;
fp@583: if (!dev)
fp@583: goto out;
fp@583:
fp@583: np = netdev_priv(dev);
fp@583: np->pci_dev = pci_dev;
fp@583: spin_lock_init(&np->lock);
fp@583: SET_MODULE_OWNER(dev);
fp@583: SET_NETDEV_DEV(dev, &pci_dev->dev);
fp@583:
fp@583: init_timer(&np->oom_kick);
fp@583: np->oom_kick.data = (unsigned long) dev;
fp@583: np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
fp@583: init_timer(&np->nic_poll);
fp@583: np->nic_poll.data = (unsigned long) dev;
fp@583: np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
fp@583: init_timer(&np->stats_poll);
fp@583: np->stats_poll.data = (unsigned long) dev;
fp@583: np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
fp@583:
fp@583: err = pci_enable_device(pci_dev);
fp@583: if (err) {
fp@583: printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
fp@583: err, pci_name(pci_dev));
fp@583: goto out_free;
fp@583: }
fp@583:
fp@583: pci_set_master(pci_dev);
fp@583:
fp@583: err = pci_request_regions(pci_dev, DRV_NAME);
fp@583: if (err < 0)
fp@583: goto out_disable;
fp@583:
fp@583: if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
fp@583: np->register_size = NV_PCI_REGSZ_VER2;
fp@583: else
fp@583: np->register_size = NV_PCI_REGSZ_VER1;
fp@583:
fp@583: err = -EINVAL;
fp@583: addr = 0;
fp@583: for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
fp@583: dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
fp@583: pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
fp@583: pci_resource_len(pci_dev, i),
fp@583: pci_resource_flags(pci_dev, i));
fp@583: if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
fp@583: pci_resource_len(pci_dev, i) >= np->register_size) {
fp@583: addr = pci_resource_start(pci_dev, i);
fp@583: break;
fp@583: }
fp@583: }
fp@583: if (i == DEVICE_COUNT_RESOURCE) {
fp@583: printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
fp@583: pci_name(pci_dev));
fp@583: goto out_relreg;
fp@583: }
fp@583:
fp@583: /* copy of driver data */
fp@583: np->driver_data = id->driver_data;
fp@583:
fp@583: /* handle different descriptor versions */
fp@583: if (id->driver_data & DEV_HAS_HIGH_DMA) {
fp@583: /* packet format 3: supports 40-bit addressing */
fp@583: np->desc_ver = DESC_VER_3;
fp@583: np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
fp@583: if (dma_64bit) {
fp@583: if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
fp@583: printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
fp@583: pci_name(pci_dev));
fp@583: } else {
fp@583: dev->features |= NETIF_F_HIGHDMA;
fp@583: printk(KERN_INFO "forcedeth: using HIGHDMA\n");
fp@583: }
fp@583: if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
fp@583: printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
fp@583: pci_name(pci_dev));
fp@583: }
fp@583: }
fp@583: } else if (id->driver_data & DEV_HAS_LARGEDESC) {
fp@583: /* packet format 2: supports jumbo frames */
fp@583: np->desc_ver = DESC_VER_2;
fp@583: np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
fp@583: } else {
fp@583: /* original packet format */
fp@583: np->desc_ver = DESC_VER_1;
fp@583: np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
fp@583: }
fp@583:
fp@583: np->pkt_limit = NV_PKTLIMIT_1;
fp@583: if (id->driver_data & DEV_HAS_LARGEDESC)
fp@583: np->pkt_limit = NV_PKTLIMIT_2;
fp@583:
fp@583: if (id->driver_data & DEV_HAS_CHECKSUM) {
fp@583: np->rx_csum = 1;
fp@583: np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
fp@583: dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
fp@583: #ifdef NETIF_F_TSO
fp@583: dev->features |= NETIF_F_TSO;
fp@583: #endif
fp@583: }
fp@583:
fp@583: np->vlanctl_bits = 0;
fp@583: if (id->driver_data & DEV_HAS_VLAN) {
fp@583: np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
fp@583: dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
fp@583: dev->vlan_rx_register = nv_vlan_rx_register;
fp@583: dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
fp@583: }
fp@583:
fp@583: np->msi_flags = 0;
fp@583: if ((id->driver_data & DEV_HAS_MSI) && msi) {
fp@583: np->msi_flags |= NV_MSI_CAPABLE;
fp@583: }
fp@583: if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
fp@583: np->msi_flags |= NV_MSI_X_CAPABLE;
fp@583: }
fp@583:
fp@583: np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
fp@583: if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
fp@583: np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
fp@583: }
fp@583:
fp@583:
fp@583: err = -ENOMEM;
fp@583: np->base = ioremap(addr, np->register_size);
fp@583: if (!np->base)
fp@583: goto out_relreg;
fp@583: dev->base_addr = (unsigned long)np->base;
fp@583:
fp@583: dev->irq = pci_dev->irq;
fp@583:
fp@583: np->rx_ring_size = RX_RING_DEFAULT;
fp@583: np->tx_ring_size = TX_RING_DEFAULT;
fp@583: np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
fp@583: np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
fp@583: np->rx_ring.orig = pci_alloc_consistent(pci_dev,
fp@583: sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
fp@583: &np->ring_addr);
fp@583: if (!np->rx_ring.orig)
fp@583: goto out_unmap;
fp@583: np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
fp@583: } else {
fp@583: np->rx_ring.ex = pci_alloc_consistent(pci_dev,
fp@583: sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
fp@583: &np->ring_addr);
fp@583: if (!np->rx_ring.ex)
fp@583: goto out_unmap;
fp@583: np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
fp@583: }
fp@583: np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
fp@583: np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
fp@583: np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
fp@583: np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
fp@583: np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
fp@583: if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
fp@583: goto out_freering;
fp@583: memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
fp@583: memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
fp@583: memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
fp@583: memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
fp@583: memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
fp@583:
fp@583: dev->open = nv_open;
fp@583: dev->stop = nv_close;
fp@583: dev->hard_start_xmit = nv_start_xmit;
fp@583: dev->get_stats = nv_get_stats;
fp@583: dev->change_mtu = nv_change_mtu;
fp@583: dev->set_mac_address = nv_set_mac_address;
fp@583: dev->set_multicast_list = nv_set_multicast;
fp@583: #ifdef CONFIG_NET_POLL_CONTROLLER
fp@583: dev->poll_controller = nv_poll_controller;
fp@583: #endif
fp@583: dev->weight = 64;
fp@583: #ifdef CONFIG_FORCEDETH_NAPI
fp@583: dev->poll = nv_napi_poll;
fp@583: #endif
fp@583: SET_ETHTOOL_OPS(dev, &ops);
fp@583: dev->tx_timeout = nv_tx_timeout;
fp@583: dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
fp@583:
fp@583: pci_set_drvdata(pci_dev, dev);
fp@583:
fp@583: /* read the mac address */
fp@583: base = get_hwbase(dev);
fp@583: np->orig_mac[0] = readl(base + NvRegMacAddrA);
fp@583: np->orig_mac[1] = readl(base + NvRegMacAddrB);
fp@583:
fp@583: /* check the workaround bit for correct mac address order */
fp@583: txreg = readl(base + NvRegTransmitPoll);
fp@583: if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
fp@583: /* mac address is already in correct order */
fp@583: dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
fp@583: dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
fp@583: dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
fp@583: dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
fp@583: dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
fp@583: dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
fp@583: } else {
fp@583: /* need to reverse mac address to correct order */
fp@583: dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
fp@583: dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
fp@583: dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
fp@583: dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
fp@583: dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
fp@583: dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
fp@583: /* set permanent address to be correct aswell */
fp@583: np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
fp@583: (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
fp@583: np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
fp@583: writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
fp@583: }
fp@583: memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
fp@583:
fp@583: if (!is_valid_ether_addr(dev->perm_addr)) {
fp@583: /*
fp@583: * Bad mac address. At least one bios sets the mac address
fp@583: * to 01:23:45:67:89:ab
fp@583: */
fp@583: printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
fp@583: pci_name(pci_dev),
fp@583: dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
fp@583: dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
fp@583: printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
fp@583: dev->dev_addr[0] = 0x00;
fp@583: dev->dev_addr[1] = 0x00;
fp@583: dev->dev_addr[2] = 0x6c;
fp@583: get_random_bytes(&dev->dev_addr[3], 3);
fp@583: }
fp@583:
fp@583: dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
fp@583: dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
fp@583: dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
fp@583:
fp@583: /* set mac address */
fp@583: nv_copy_mac_to_hw(dev);
fp@583:
fp@583: /* disable WOL */
fp@583: writel(0, base + NvRegWakeUpFlags);
fp@583: np->wolenabled = 0;
fp@583:
fp@583: if (id->driver_data & DEV_HAS_POWER_CNTRL) {
fp@583: u8 revision_id;
fp@583: pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
fp@583:
fp@583: /* take phy and nic out of low power mode */
fp@583: powerstate = readl(base + NvRegPowerState2);
fp@583: powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
fp@583: if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
fp@583: id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
fp@583: revision_id >= 0xA3)
fp@583: powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
fp@583: writel(powerstate, base + NvRegPowerState2);
fp@583: }
fp@583:
fp@583: if (np->desc_ver == DESC_VER_1) {
fp@583: np->tx_flags = NV_TX_VALID;
fp@583: } else {
fp@583: np->tx_flags = NV_TX2_VALID;
fp@583: }
fp@583: if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
fp@583: np->irqmask = NVREG_IRQMASK_THROUGHPUT;
fp@583: if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
fp@583: np->msi_flags |= 0x0003;
fp@583: } else {
fp@583: np->irqmask = NVREG_IRQMASK_CPU;
fp@583: if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
fp@583: np->msi_flags |= 0x0001;
fp@583: }
fp@583:
fp@583: if (id->driver_data & DEV_NEED_TIMERIRQ)
fp@583: np->irqmask |= NVREG_IRQ_TIMER;
fp@583: if (id->driver_data & DEV_NEED_LINKTIMER) {
fp@583: dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
fp@583: np->need_linktimer = 1;
fp@583: np->link_timeout = jiffies + LINK_TIMEOUT;
fp@583: } else {
fp@583: dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
fp@583: np->need_linktimer = 0;
fp@583: }
fp@583:
fp@583: /* find a suitable phy */
fp@583: for (i = 1; i <= 32; i++) {
fp@583: int id1, id2;
fp@583: int phyaddr = i & 0x1F;
fp@583:
fp@583: spin_lock_irq(&np->lock);
fp@583: id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
fp@583: spin_unlock_irq(&np->lock);
fp@583: if (id1 < 0 || id1 == 0xffff)
fp@583: continue;
fp@583: spin_lock_irq(&np->lock);
fp@583: id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
fp@583: spin_unlock_irq(&np->lock);
fp@583: if (id2 < 0 || id2 == 0xffff)
fp@583: continue;
fp@583:
fp@583: np->phy_model = id2 & PHYID2_MODEL_MASK;
fp@583: id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
fp@583: id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
fp@583: dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
fp@583: pci_name(pci_dev), id1, id2, phyaddr);
fp@583: np->phyaddr = phyaddr;
fp@583: np->phy_oui = id1 | id2;
fp@583: break;
fp@583: }
fp@583: if (i == 33) {
fp@583: printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
fp@583: pci_name(pci_dev));
fp@583: goto out_error;
fp@583: }
fp@583:
fp@583: /* reset it */
fp@583: phy_init(dev);
fp@583:
fp@583: /* set default link speed settings */
fp@583: np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
fp@583: np->duplex = 0;
fp@583: np->autoneg = 1;
fp@583:
fp@583: // offer device to EtherCAT master module
fp@1011: np->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);
fp@591: if (np->ecdev) {
fp@591: if (ecdev_open(np->ecdev)) {
fp@591: ecdev_withdraw(np->ecdev);
fp@591: goto out_error;
fp@591: }
fp@1011: } else {
fp@583: err = register_netdev(dev);
fp@583: if (err) {
fp@583: printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
fp@583: goto out_freering;
fp@583: }
fp@583: }
fp@583: printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
fp@583: dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
fp@583: pci_name(pci_dev));
fp@583:
fp@583: return 0;
fp@583:
fp@583: out_error:
fp@583: pci_set_drvdata(pci_dev, NULL);
fp@583: out_freering:
fp@583: free_rings(dev);
fp@583: out_unmap:
fp@583: iounmap(get_hwbase(dev));
fp@583: out_relreg:
fp@583: pci_release_regions(pci_dev);
fp@583: out_disable:
fp@583: pci_disable_device(pci_dev);
fp@583: out_free:
fp@583: free_netdev(dev);
fp@583: out:
fp@583: return err;
fp@583: }
fp@583:
fp@583: static void __devexit nv_remove(struct pci_dev *pci_dev)
fp@583: {
fp@583: struct net_device *dev = pci_get_drvdata(pci_dev);
fp@583: struct fe_priv *np = netdev_priv(dev);
fp@583: u8 __iomem *base = get_hwbase(dev);
fp@583:
fp@583: if (np->ecdev) {
fp@583: ecdev_close(np->ecdev);
fp@583: ecdev_withdraw(np->ecdev);
fp@583: }
fp@583: else {
fp@583: unregister_netdev(dev);
fp@583: }
fp@583:
fp@583: /* special op: write back the misordered MAC address - otherwise
fp@583: * the next nv_probe would see a wrong address.
fp@583: */
fp@583: writel(np->orig_mac[0], base + NvRegMacAddrA);
fp@583: writel(np->orig_mac[1], base + NvRegMacAddrB);
fp@583:
fp@583: /* free all structures */
fp@583: free_rings(dev);
fp@583: iounmap(get_hwbase(dev));
fp@583: pci_release_regions(pci_dev);
fp@583: pci_disable_device(pci_dev);
fp@583: free_netdev(dev);
fp@583: pci_set_drvdata(pci_dev, NULL);
fp@583: }
fp@583:
fp@583: static struct pci_device_id pci_tbl[] = {
fp@583: { /* nForce Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
fp@583: },
fp@583: { /* nForce2 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
fp@583: },
fp@583: { /* nForce3 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
fp@583: },
fp@583: { /* nForce3 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
fp@583: },
fp@583: { /* nForce3 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
fp@583: },
fp@583: { /* nForce3 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
fp@583: },
fp@583: { /* nForce3 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
fp@583: },
fp@583: { /* CK804 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
fp@583: },
fp@583: { /* CK804 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
fp@583: },
fp@583: { /* MCP04 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
fp@583: },
fp@583: { /* MCP04 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
fp@583: },
fp@583: { /* MCP51 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
fp@583: },
fp@583: { /* MCP51 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
fp@583: },
fp@583: { /* MCP55 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP55 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP61 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP61 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP61 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP61 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP65 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP65 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP65 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: { /* MCP65 Ethernet Controller */
fp@583: PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
fp@583: .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
fp@583: },
fp@583: {0,},
fp@583: };
fp@583:
fp@583: static struct pci_driver driver = {
fp@583: .name = "forcedeth",
fp@583: .id_table = pci_tbl,
fp@583: .probe = nv_probe,
fp@583: .remove = __devexit_p(nv_remove),
fp@583: };
fp@583:
fp@583:
fp@583: static int __init init_nic(void)
fp@583: {
fp@591: printk(KERN_INFO "forcedeth: EtherCAT-capable nForce ethernet driver."
fp@591: " Version %s, master %s.\n",
fp@591: FORCEDETH_VERSION, EC_MASTER_VERSION);
fp@583: return pci_register_driver(&driver);
fp@583: }
fp@583:
fp@583: static void __exit exit_nic(void)
fp@583: {
fp@583: pci_unregister_driver(&driver);
fp@583: }
fp@583:
fp@583: module_param(max_interrupt_work, int, 0);
fp@583: MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
fp@583: module_param(optimization_mode, int, 0);
fp@583: MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
fp@583: module_param(poll_interval, int, 0);
fp@583: MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
fp@583: module_param(msi, int, 0);
fp@583: MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
fp@583: module_param(msix, int, 0);
fp@583: MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
fp@583: module_param(dma_64bit, int, 0);
fp@583: MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
fp@583:
fp@591: MODULE_AUTHOR("Dipl.-Ing. (FH) Florian Pose <fp@igh-essen.com>");
fp@591: MODULE_DESCRIPTION("EtherCAT-capable nForce ethernet driver");
fp@583: MODULE_LICENSE("GPL");
fp@583:
fp@583: //MODULE_DEVICE_TABLE(pci, pci_tbl); // prevent auto-loading
fp@583:
fp@583: module_init(init_nic);
fp@583: module_exit(exit_nic);