fp@2324: /*******************************************************************************
fp@2324: 
fp@2324:   Intel PRO/1000 Linux driver
fp@2324:   Copyright(c) 1999 - 2009 Intel Corporation.
fp@2324: 
fp@2324:   This program is free software; you can redistribute it and/or modify it
fp@2324:   under the terms and conditions of the GNU General Public License,
fp@2324:   version 2, as published by the Free Software Foundation.
fp@2324: 
fp@2324:   This program is distributed in the hope it will be useful, but WITHOUT
fp@2324:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2324:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2324:   more details.
fp@2324: 
fp@2324:   You should have received a copy of the GNU General Public License along with
fp@2324:   this program; if not, write to the Free Software Foundation, Inc.,
fp@2324:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
fp@2324: 
fp@2324:   The full GNU General Public License is included in this distribution in
fp@2324:   the file called "COPYING".
fp@2324: 
fp@2324:   Contact Information:
fp@2324:   Linux NICS <linux.nics@intel.com>
fp@2324:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2324:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2324: 
fp@2324: *******************************************************************************/
fp@2324: 
fp@2324: /*
fp@2324:  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
fp@2324:  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
fp@2324:  */
fp@2324: 
fp@2324: #include "e1000.h"
fp@2324: 
fp@2324: #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00
fp@2324: #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02
fp@2324: #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10
fp@2324: #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F
fp@2324: 
fp@2324: #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008
fp@2324: #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800
fp@2324: #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010
fp@2324: 
fp@2324: #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
fp@2324: #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000
fp@2324: #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000
fp@2324: 
fp@2324: #define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C
fp@2324: #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004
fp@2324: 
fp@2324: #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
fp@2324: #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000
fp@2324: 
fp@2324: #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8
fp@2324: #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9
fp@2324: 
fp@2324: /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
fp@2324: #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */
fp@2324: #define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060
fp@2324: #define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */
fp@2324: #define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */
fp@2324: #define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */
fp@2324: 
fp@2324: /* PHY Specific Control Register 2 (Page 0, Register 26) */
fp@2324: #define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000
fp@2324: 						/* 1=Reverse Auto-Negotiation */
fp@2324: 
fp@2324: /* MAC Specific Control Register (Page 2, Register 21) */
fp@2324: /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
fp@2324: #define GG82563_MSCR_TX_CLK_MASK		 0x0007
fp@2324: #define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004
fp@2324: #define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005
fp@2324: #define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007
fp@2324: 
fp@2324: #define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */
fp@2324: 
fp@2324: /* DSP Distance Register (Page 5, Register 26) */
fp@2324: #define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M
fp@2324: 							   1 = 50-80M
fp@2324: 							   2 = 80-110M
fp@2324: 							   3 = 110-140M
fp@2324: 							   4 = >140M */
fp@2324: 
fp@2324: /* Kumeran Mode Control Register (Page 193, Register 16) */
fp@2324: #define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800
fp@2324: 
fp@2324: /* Max number of times Kumeran read/write should be validated */
fp@2324: #define GG82563_MAX_KMRN_RETRY  0x5
fp@2324: 
fp@2324: /* Power Management Control Register (Page 193, Register 20) */
fp@2324: #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001
fp@2324: 					   /* 1=Enable SERDES Electrical Idle */
fp@2324: 
fp@2324: /* In-Band Control Register (Page 194, Register 18) */
fp@2324: #define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */
fp@2324: 
fp@2324: /*
fp@2324:  * A table for the GG82563 cable length where the range is defined
fp@2324:  * with a lower bound at "index" and the upper bound at
fp@2324:  * "index + 5".
fp@2324:  */
fp@2324: static const u16 e1000_gg82563_cable_length_table[] =
fp@2324: 	 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
fp@2324: #define GG82563_CABLE_LENGTH_TABLE_SIZE \
fp@2324: 		ARRAY_SIZE(e1000_gg82563_cable_length_table)
fp@2324: 
fp@2324: static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
fp@2324: static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
fp@2324: static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
fp@2324: static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
fp@2324: static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
fp@2324: static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
fp@2324: static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
fp@2324: static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
fp@2324: static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
fp@2324:                                             u16 *data);
fp@2324: static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
fp@2324:                                              u16 data);
fp@2324: static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  **/
fp@2324: static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	struct e1000_phy_info *phy = &hw->phy;
fp@2324: 	s32 ret_val;
fp@2324: 
fp@2324: 	if (hw->phy.media_type != e1000_media_type_copper) {
fp@2324: 		phy->type	= e1000_phy_none;
fp@2324: 		return 0;
fp@2324: 	} else {
fp@2324: 		phy->ops.power_up = e1000_power_up_phy_copper;
fp@2324: 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
fp@2324: 	}
fp@2324: 
fp@2324: 	phy->addr		= 1;
fp@2324: 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
fp@2324: 	phy->reset_delay_us      = 100;
fp@2324: 	phy->type		= e1000_phy_gg82563;
fp@2324: 
fp@2324: 	/* This can only be done after all function pointers are setup. */
fp@2324: 	ret_val = e1000e_get_phy_id(hw);
fp@2324: 
fp@2324: 	/* Verify phy id */
fp@2324: 	if (phy->id != GG82563_E_PHY_ID)
fp@2324: 		return -E1000_ERR_PHY;
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  **/
fp@2324: static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2324: 	u32 eecd = er32(EECD);
fp@2324: 	u16 size;
fp@2324: 
fp@2324: 	nvm->opcode_bits	= 8;
fp@2324: 	nvm->delay_usec	 = 1;
fp@2324: 	switch (nvm->override) {
fp@2324: 	case e1000_nvm_override_spi_large:
fp@2324: 		nvm->page_size    = 32;
fp@2324: 		nvm->address_bits = 16;
fp@2324: 		break;
fp@2324: 	case e1000_nvm_override_spi_small:
fp@2324: 		nvm->page_size    = 8;
fp@2324: 		nvm->address_bits = 8;
fp@2324: 		break;
fp@2324: 	default:
fp@2324: 		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
fp@2324: 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
fp@2324: 		break;
fp@2324: 	}
fp@2324: 
fp@2324: 	nvm->type = e1000_nvm_eeprom_spi;
fp@2324: 
fp@2324: 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
fp@2324: 			  E1000_EECD_SIZE_EX_SHIFT);
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Added to a constant, "size" becomes the left-shift value
fp@2324: 	 * for setting word_size.
fp@2324: 	 */
fp@2324: 	size += NVM_WORD_SIZE_BASE_SHIFT;
fp@2324: 
fp@2324: 	/* EEPROM access above 16k is unsupported */
fp@2324: 	if (size > 14)
fp@2324: 		size = 14;
fp@2324: 	nvm->word_size	= 1 << size;
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  **/
fp@2324: static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
fp@2324: {
fp@2324: 	struct e1000_hw *hw = &adapter->hw;
fp@2324: 	struct e1000_mac_info *mac = &hw->mac;
fp@2324: 	struct e1000_mac_operations *func = &mac->ops;
fp@2324: 
fp@2324: 	/* Set media type */
fp@2324: 	switch (adapter->pdev->device) {
fp@2324: 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
fp@2324: 		hw->phy.media_type = e1000_media_type_internal_serdes;
fp@2324: 		break;
fp@2324: 	default:
fp@2324: 		hw->phy.media_type = e1000_media_type_copper;
fp@2324: 		break;
fp@2324: 	}
fp@2324: 
fp@2324: 	/* Set mta register count */
fp@2324: 	mac->mta_reg_count = 128;
fp@2324: 	/* Set rar entry count */
fp@2324: 	mac->rar_entry_count = E1000_RAR_ENTRIES;
fp@2324: 	/* Set if manageability features are enabled. */
fp@2324: 	mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
fp@2324:                         ? true : false;
fp@2324: 	/* Adaptive IFS not supported */
fp@2324: 	mac->adaptive_ifs = false;
fp@2324: 
fp@2324: 	/* check for link */
fp@2324: 	switch (hw->phy.media_type) {
fp@2324: 	case e1000_media_type_copper:
fp@2324: 		func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
fp@2324: 		func->check_for_link = e1000e_check_for_copper_link;
fp@2324: 		break;
fp@2324: 	case e1000_media_type_fiber:
fp@2324: 		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
fp@2324: 		func->check_for_link = e1000e_check_for_fiber_link;
fp@2324: 		break;
fp@2324: 	case e1000_media_type_internal_serdes:
fp@2324: 		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
fp@2324: 		func->check_for_link = e1000e_check_for_serdes_link;
fp@2324: 		break;
fp@2324: 	default:
fp@2324: 		return -E1000_ERR_CONFIG;
fp@2324: 		break;
fp@2324: 	}
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
fp@2324: {
fp@2324: 	struct e1000_hw *hw = &adapter->hw;
fp@2324: 	s32 rc;
fp@2324: 
fp@2324: 	rc = e1000_init_mac_params_80003es2lan(adapter);
fp@2324: 	if (rc)
fp@2324: 		return rc;
fp@2324: 
fp@2324: 	rc = e1000_init_nvm_params_80003es2lan(hw);
fp@2324: 	if (rc)
fp@2324: 		return rc;
fp@2324: 
fp@2324: 	rc = e1000_init_phy_params_80003es2lan(hw);
fp@2324: 	if (rc)
fp@2324: 		return rc;
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  A wrapper to acquire access rights to the correct PHY.
fp@2324:  **/
fp@2324: static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u16 mask;
fp@2324: 
fp@2324: 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
fp@2324: 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_release_phy_80003es2lan - Release rights to access PHY
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  A wrapper to release access rights to the correct PHY.
fp@2324:  **/
fp@2324: static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u16 mask;
fp@2324: 
fp@2324: 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
fp@2324: 	e1000_release_swfw_sync_80003es2lan(hw, mask);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Acquire the semaphore to access the Kumeran interface.
fp@2324:  *
fp@2324:  **/
fp@2324: static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u16 mask;
fp@2324: 
fp@2324: 	mask = E1000_SWFW_CSR_SM;
fp@2324: 
fp@2324: 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Release the semaphore used to access the Kumeran interface
fp@2324:  **/
fp@2324: static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u16 mask;
fp@2324: 
fp@2324: 	mask = E1000_SWFW_CSR_SM;
fp@2324: 
fp@2324: 	e1000_release_swfw_sync_80003es2lan(hw, mask);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Acquire the semaphore to access the EEPROM.
fp@2324:  **/
fp@2324: static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 
fp@2324: 	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	ret_val = e1000e_acquire_nvm(hw);
fp@2324: 
fp@2324: 	if (ret_val)
fp@2324: 		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Release the semaphore used to access the EEPROM.
fp@2324:  **/
fp@2324: static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	e1000e_release_nvm(hw);
fp@2324: 	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @mask: specifies which semaphore to acquire
fp@2324:  *
fp@2324:  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
fp@2324:  *  will also specify which port we're acquiring the lock for.
fp@2324:  **/
fp@2324: static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
fp@2324: {
fp@2324: 	u32 swfw_sync;
fp@2324: 	u32 swmask = mask;
fp@2324: 	u32 fwmask = mask << 16;
fp@2324: 	s32 i = 0;
fp@2324: 	s32 timeout = 50;
fp@2324: 
fp@2324: 	while (i < timeout) {
fp@2324: 		if (e1000e_get_hw_semaphore(hw))
fp@2324: 			return -E1000_ERR_SWFW_SYNC;
fp@2324: 
fp@2324: 		swfw_sync = er32(SW_FW_SYNC);
fp@2324: 		if (!(swfw_sync & (fwmask | swmask)))
fp@2324: 			break;
fp@2324: 
fp@2324: 		/*
fp@2324: 		 * Firmware currently using resource (fwmask)
fp@2324: 		 * or other software thread using resource (swmask)
fp@2324: 		 */
fp@2324: 		e1000e_put_hw_semaphore(hw);
fp@2324: 		mdelay(5);
fp@2324: 		i++;
fp@2324: 	}
fp@2324: 
fp@2324: 	if (i == timeout) {
fp@2324: 		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
fp@2324: 		return -E1000_ERR_SWFW_SYNC;
fp@2324: 	}
fp@2324: 
fp@2324: 	swfw_sync |= swmask;
fp@2324: 	ew32(SW_FW_SYNC, swfw_sync);
fp@2324: 
fp@2324: 	e1000e_put_hw_semaphore(hw);
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @mask: specifies which semaphore to acquire
fp@2324:  *
fp@2324:  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
fp@2324:  *  will also specify which port we're releasing the lock for.
fp@2324:  **/
fp@2324: static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
fp@2324: {
fp@2324: 	u32 swfw_sync;
fp@2324: 
fp@2324: 	while (e1000e_get_hw_semaphore(hw) != 0);
fp@2324: 	/* Empty */
fp@2324: 
fp@2324: 	swfw_sync = er32(SW_FW_SYNC);
fp@2324: 	swfw_sync &= ~mask;
fp@2324: 	ew32(SW_FW_SYNC, swfw_sync);
fp@2324: 
fp@2324: 	e1000e_put_hw_semaphore(hw);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @offset: offset of the register to read
fp@2324:  *  @data: pointer to the data returned from the operation
fp@2324:  *
fp@2324:  *  Read the GG82563 PHY register.
fp@2324:  **/
fp@2324: static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
fp@2324: 						  u32 offset, u16 *data)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 	u32 page_select;
fp@2324: 	u16 temp;
fp@2324: 
fp@2324: 	ret_val = e1000_acquire_phy_80003es2lan(hw);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/* Select Configuration Page */
fp@2324: 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
fp@2324: 		page_select = GG82563_PHY_PAGE_SELECT;
fp@2324: 	} else {
fp@2324: 		/*
fp@2324: 		 * Use Alternative Page Select register to access
fp@2324: 		 * registers 30 and 31
fp@2324: 		 */
fp@2324: 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
fp@2324: 	}
fp@2324: 
fp@2324: 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
fp@2324: 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
fp@2324: 	if (ret_val) {
fp@2324: 		e1000_release_phy_80003es2lan(hw);
fp@2324: 		return ret_val;
fp@2324: 	}
fp@2324: 
fp@2324: 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
fp@2324: 		/*
fp@2324: 		 * The "ready" bit in the MDIC register may be incorrectly set
fp@2324: 		 * before the device has completed the "Page Select" MDI
fp@2324: 		 * transaction.  So we wait 200us after each MDI command...
fp@2324: 		 */
fp@2324: 		udelay(200);
fp@2324: 
fp@2324: 		/* ...and verify the command was successful. */
fp@2324: 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
fp@2324: 
fp@2324: 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
fp@2324: 			ret_val = -E1000_ERR_PHY;
fp@2324: 			e1000_release_phy_80003es2lan(hw);
fp@2324: 			return ret_val;
fp@2324: 		}
fp@2324: 
fp@2324: 		udelay(200);
fp@2324: 
fp@2324: 		ret_val = e1000e_read_phy_reg_mdic(hw,
fp@2324: 		                                  MAX_PHY_REG_ADDRESS & offset,
fp@2324: 		                                  data);
fp@2324: 
fp@2324: 		udelay(200);
fp@2324: 	} else {
fp@2324: 		ret_val = e1000e_read_phy_reg_mdic(hw,
fp@2324: 		                                  MAX_PHY_REG_ADDRESS & offset,
fp@2324: 		                                  data);
fp@2324: 	}
fp@2324: 
fp@2324: 	e1000_release_phy_80003es2lan(hw);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @offset: offset of the register to read
fp@2324:  *  @data: value to write to the register
fp@2324:  *
fp@2324:  *  Write to the GG82563 PHY register.
fp@2324:  **/
fp@2324: static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
fp@2324: 						   u32 offset, u16 data)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 	u32 page_select;
fp@2324: 	u16 temp;
fp@2324: 
fp@2324: 	ret_val = e1000_acquire_phy_80003es2lan(hw);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/* Select Configuration Page */
fp@2324: 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
fp@2324: 		page_select = GG82563_PHY_PAGE_SELECT;
fp@2324: 	} else {
fp@2324: 		/*
fp@2324: 		 * Use Alternative Page Select register to access
fp@2324: 		 * registers 30 and 31
fp@2324: 		 */
fp@2324: 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
fp@2324: 	}
fp@2324: 
fp@2324: 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
fp@2324: 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
fp@2324: 	if (ret_val) {
fp@2324: 		e1000_release_phy_80003es2lan(hw);
fp@2324: 		return ret_val;
fp@2324: 	}
fp@2324: 
fp@2324: 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
fp@2324: 		/*
fp@2324: 		 * The "ready" bit in the MDIC register may be incorrectly set
fp@2324: 		 * before the device has completed the "Page Select" MDI
fp@2324: 		 * transaction.  So we wait 200us after each MDI command...
fp@2324: 		 */
fp@2324: 		udelay(200);
fp@2324: 
fp@2324: 		/* ...and verify the command was successful. */
fp@2324: 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
fp@2324: 
fp@2324: 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
fp@2324: 			e1000_release_phy_80003es2lan(hw);
fp@2324: 			return -E1000_ERR_PHY;
fp@2324: 		}
fp@2324: 
fp@2324: 		udelay(200);
fp@2324: 
fp@2324: 		ret_val = e1000e_write_phy_reg_mdic(hw,
fp@2324: 		                                  MAX_PHY_REG_ADDRESS & offset,
fp@2324: 		                                  data);
fp@2324: 
fp@2324: 		udelay(200);
fp@2324: 	} else {
fp@2324: 		ret_val = e1000e_write_phy_reg_mdic(hw,
fp@2324: 		                                  MAX_PHY_REG_ADDRESS & offset,
fp@2324: 		                                  data);
fp@2324: 	}
fp@2324: 
fp@2324: 	e1000_release_phy_80003es2lan(hw);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @offset: offset of the register to read
fp@2324:  *  @words: number of words to write
fp@2324:  *  @data: buffer of data to write to the NVM
fp@2324:  *
fp@2324:  *  Write "words" of data to the ESB2 NVM.
fp@2324:  **/
fp@2324: static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
fp@2324: 				       u16 words, u16 *data)
fp@2324: {
fp@2324: 	return e1000e_write_nvm_spi(hw, offset, words, data);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Wait a specific amount of time for manageability processes to complete.
fp@2324:  *  This is a function pointer entry point called by the phy module.
fp@2324:  **/
fp@2324: static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	s32 timeout = PHY_CFG_TIMEOUT;
fp@2324: 	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
fp@2324: 
fp@2324: 	if (hw->bus.func == 1)
fp@2324: 		mask = E1000_NVM_CFG_DONE_PORT_1;
fp@2324: 
fp@2324: 	while (timeout) {
fp@2324: 		if (er32(EEMNGCTL) & mask)
fp@2324: 			break;
fp@2324: 		msleep(1);
fp@2324: 		timeout--;
fp@2324: 	}
fp@2324: 	if (!timeout) {
fp@2324: 		e_dbg("MNG configuration cycle has not completed.\n");
fp@2324: 		return -E1000_ERR_RESET;
fp@2324: 	}
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Force the speed and duplex settings onto the PHY.  This is a
fp@2324:  *  function pointer entry point called by the phy module.
fp@2324:  **/
fp@2324: static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 	u16 phy_data;
fp@2324: 	bool link;
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
fp@2324: 	 * forced whenever speed and duplex are forced.
fp@2324: 	 */
fp@2324: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	e_dbg("GG82563 PSCR: %X\n", phy_data);
fp@2324: 
fp@2324: 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2324: 
fp@2324: 	/* Reset the phy to commit changes. */
fp@2324: 	phy_data |= MII_CR_RESET;
fp@2324: 
fp@2324: 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	udelay(1);
fp@2324: 
fp@2324: 	if (hw->phy.autoneg_wait_to_complete) {
fp@2324: 		e_dbg("Waiting for forced speed/duplex link "
fp@2324: 			 "on GG82563 phy.\n");
fp@2324: 
fp@2324: 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
fp@2324: 						     100000, &link);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 
fp@2324: 		if (!link) {
fp@2324: 			/*
fp@2324: 			 * We didn't get link.
fp@2324: 			 * Reset the DSP and cross our fingers.
fp@2324: 			 */
fp@2324: 			ret_val = e1000e_phy_reset_dsp(hw);
fp@2324: 			if (ret_val)
fp@2324: 				return ret_val;
fp@2324: 		}
fp@2324: 
fp@2324: 		/* Try once more */
fp@2324: 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
fp@2324: 						     100000, &link);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 	}
fp@2324: 
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Resetting the phy means we need to verify the TX_CLK corresponds
fp@2324: 	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
fp@2324: 	 */
fp@2324: 	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
fp@2324: 	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
fp@2324: 		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
fp@2324: 	else
fp@2324: 		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * In addition, we must re-enable CRS on Tx for both half and full
fp@2324: 	 * duplex.
fp@2324: 	 */
fp@2324: 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Find the approximate cable length as measured by the GG82563 PHY.
fp@2324:  *  This is a function pointer entry point called by the phy module.
fp@2324:  **/
fp@2324: static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	struct e1000_phy_info *phy = &hw->phy;
fp@2324: 	s32 ret_val = 0;
fp@2324: 	u16 phy_data, index;
fp@2324: 
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
fp@2324: 	if (ret_val)
fp@2324: 		goto out;
fp@2324: 
fp@2324: 	index = phy_data & GG82563_DSPD_CABLE_LENGTH;
fp@2324: 
fp@2324: 	if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
fp@2324: 		ret_val = -E1000_ERR_PHY;
fp@2324: 		goto out;
fp@2324: 	}
fp@2324: 
fp@2324: 	phy->min_cable_length = e1000_gg82563_cable_length_table[index];
fp@2324: 	phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
fp@2324: 
fp@2324: 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
fp@2324: 
fp@2324: out:
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @speed: pointer to speed buffer
fp@2324:  *  @duplex: pointer to duplex buffer
fp@2324:  *
fp@2324:  *  Retrieve the current speed and duplex configuration.
fp@2324:  **/
fp@2324: static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
fp@2324: 					      u16 *duplex)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 
fp@2324: 	if (hw->phy.media_type == e1000_media_type_copper) {
fp@2324: 		ret_val = e1000e_get_speed_and_duplex_copper(hw,
fp@2324: 								    speed,
fp@2324: 								    duplex);
fp@2324: 		hw->phy.ops.cfg_on_link_up(hw);
fp@2324: 	} else {
fp@2324: 		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
fp@2324: 								  speed,
fp@2324: 								  duplex);
fp@2324: 	}
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Perform a global reset to the ESB2 controller.
fp@2324:  **/
fp@2324: static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u32 ctrl, icr;
fp@2324: 	s32 ret_val;
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Prevent the PCI-E bus from sticking if there is no TLP connection
fp@2324: 	 * on the last TLP read/write transaction when MAC is reset.
fp@2324: 	 */
fp@2324: 	ret_val = e1000e_disable_pcie_master(hw);
fp@2324: 	if (ret_val)
fp@2324: 		e_dbg("PCI-E Master disable polling has failed.\n");
fp@2324: 
fp@2324: 	e_dbg("Masking off all interrupts\n");
fp@2324: 	ew32(IMC, 0xffffffff);
fp@2324: 
fp@2324: 	ew32(RCTL, 0);
fp@2324: 	ew32(TCTL, E1000_TCTL_PSP);
fp@2324: 	e1e_flush();
fp@2324: 
fp@2324: 	msleep(10);
fp@2324: 
fp@2324: 	ctrl = er32(CTRL);
fp@2324: 
fp@2324: 	ret_val = e1000_acquire_phy_80003es2lan(hw);
fp@2324: 	e_dbg("Issuing a global reset to MAC\n");
fp@2324: 	ew32(CTRL, ctrl | E1000_CTRL_RST);
fp@2324: 	e1000_release_phy_80003es2lan(hw);
fp@2324: 
fp@2324: 	ret_val = e1000e_get_auto_rd_done(hw);
fp@2324: 	if (ret_val)
fp@2324: 		/* We don't want to continue accessing MAC registers. */
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/* Clear any pending interrupt events. */
fp@2324: 	ew32(IMC, 0xffffffff);
fp@2324: 	icr = er32(ICR);
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
fp@2324:  **/
fp@2324: static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	struct e1000_mac_info *mac = &hw->mac;
fp@2324: 	u32 reg_data;
fp@2324: 	s32 ret_val;
fp@2324: 	u16 i;
fp@2324: 
fp@2324: 	e1000_initialize_hw_bits_80003es2lan(hw);
fp@2324: 
fp@2324: 	/* Initialize identification LED */
fp@2324: 	ret_val = e1000e_id_led_init(hw);
fp@2324: 	if (ret_val)
fp@2324: 		e_dbg("Error initializing identification LED\n");
fp@2324: 		/* This is not fatal and we should not stop init due to this */
fp@2324: 
fp@2324: 	/* Disabling VLAN filtering */
fp@2324: 	e_dbg("Initializing the IEEE VLAN\n");
fp@2324: 	mac->ops.clear_vfta(hw);
fp@2324: 
fp@2324: 	/* Setup the receive address. */
fp@2324: 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
fp@2324: 
fp@2324: 	/* Zero out the Multicast HASH table */
fp@2324: 	e_dbg("Zeroing the MTA\n");
fp@2324: 	for (i = 0; i < mac->mta_reg_count; i++)
fp@2324: 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
fp@2324: 
fp@2324: 	/* Setup link and flow control */
fp@2324: 	ret_val = e1000e_setup_link(hw);
fp@2324: 
fp@2324: 	/* Set the transmit descriptor write-back policy */
fp@2324: 	reg_data = er32(TXDCTL(0));
fp@2324: 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
fp@2324: 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
fp@2324: 	ew32(TXDCTL(0), reg_data);
fp@2324: 
fp@2324: 	/* ...for both queues. */
fp@2324: 	reg_data = er32(TXDCTL(1));
fp@2324: 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
fp@2324: 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
fp@2324: 	ew32(TXDCTL(1), reg_data);
fp@2324: 
fp@2324: 	/* Enable retransmit on late collisions */
fp@2324: 	reg_data = er32(TCTL);
fp@2324: 	reg_data |= E1000_TCTL_RTLC;
fp@2324: 	ew32(TCTL, reg_data);
fp@2324: 
fp@2324: 	/* Configure Gigabit Carry Extend Padding */
fp@2324: 	reg_data = er32(TCTL_EXT);
fp@2324: 	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
fp@2324: 	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
fp@2324: 	ew32(TCTL_EXT, reg_data);
fp@2324: 
fp@2324: 	/* Configure Transmit Inter-Packet Gap */
fp@2324: 	reg_data = er32(TIPG);
fp@2324: 	reg_data &= ~E1000_TIPG_IPGT_MASK;
fp@2324: 	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
fp@2324: 	ew32(TIPG, reg_data);
fp@2324: 
fp@2324: 	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
fp@2324: 	reg_data &= ~0x00100000;
fp@2324: 	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
fp@2324: 
fp@2324: 	/* default to true to enable the MDIC W/A */
fp@2324: 	hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
fp@2324: 
fp@2324: 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
fp@2324: 	                              E1000_KMRNCTRLSTA_OFFSET >>
fp@2324: 	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,
fp@2324: 	                              &i);
fp@2324: 	if (!ret_val) {
fp@2324: 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
fp@2324: 		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
fp@2324: 			hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
fp@2324: 	}
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Clear all of the statistics registers (clear on read).  It is
fp@2324: 	 * important that we do this after we have tried to establish link
fp@2324: 	 * because the symbol error count will increment wildly if there
fp@2324: 	 * is no link.
fp@2324: 	 */
fp@2324: 	e1000_clear_hw_cntrs_80003es2lan(hw);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Initializes required hardware-dependent bits needed for normal operation.
fp@2324:  **/
fp@2324: static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u32 reg;
fp@2324: 
fp@2324: 	/* Transmit Descriptor Control 0 */
fp@2324: 	reg = er32(TXDCTL(0));
fp@2324: 	reg |= (1 << 22);
fp@2324: 	ew32(TXDCTL(0), reg);
fp@2324: 
fp@2324: 	/* Transmit Descriptor Control 1 */
fp@2324: 	reg = er32(TXDCTL(1));
fp@2324: 	reg |= (1 << 22);
fp@2324: 	ew32(TXDCTL(1), reg);
fp@2324: 
fp@2324: 	/* Transmit Arbitration Control 0 */
fp@2324: 	reg = er32(TARC(0));
fp@2324: 	reg &= ~(0xF << 27); /* 30:27 */
fp@2324: 	if (hw->phy.media_type != e1000_media_type_copper)
fp@2324: 		reg &= ~(1 << 20);
fp@2324: 	ew32(TARC(0), reg);
fp@2324: 
fp@2324: 	/* Transmit Arbitration Control 1 */
fp@2324: 	reg = er32(TARC(1));
fp@2324: 	if (er32(TCTL) & E1000_TCTL_MULR)
fp@2324: 		reg &= ~(1 << 28);
fp@2324: 	else
fp@2324: 		reg |= (1 << 28);
fp@2324: 	ew32(TARC(1), reg);
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Setup some GG82563 PHY registers for obtaining link
fp@2324:  **/
fp@2324: static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	struct e1000_phy_info *phy = &hw->phy;
fp@2324: 	s32 ret_val;
fp@2324: 	u32 ctrl_ext;
fp@2324: 	u16 data;
fp@2324: 
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
fp@2324: 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
fp@2324: 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
fp@2324: 
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Options:
fp@2324: 	 *   MDI/MDI-X = 0 (default)
fp@2324: 	 *   0 - Auto for all speeds
fp@2324: 	 *   1 - MDI mode
fp@2324: 	 *   2 - MDI-X mode
fp@2324: 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
fp@2324: 	 */
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
fp@2324: 
fp@2324: 	switch (phy->mdix) {
fp@2324: 	case 1:
fp@2324: 		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
fp@2324: 		break;
fp@2324: 	case 2:
fp@2324: 		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
fp@2324: 		break;
fp@2324: 	case 0:
fp@2324: 	default:
fp@2324: 		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
fp@2324: 		break;
fp@2324: 	}
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Options:
fp@2324: 	 *   disable_polarity_correction = 0 (default)
fp@2324: 	 *       Automatic Correction for Reversed Cable Polarity
fp@2324: 	 *   0 - Disabled
fp@2324: 	 *   1 - Enabled
fp@2324: 	 */
fp@2324: 	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
fp@2324: 	if (phy->disable_polarity_correction)
fp@2324: 		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
fp@2324: 
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/* SW Reset the PHY so all changes take effect */
fp@2324: 	ret_val = e1000e_commit_phy(hw);
fp@2324: 	if (ret_val) {
fp@2324: 		e_dbg("Error Resetting the PHY\n");
fp@2324: 		return ret_val;
fp@2324: 	}
fp@2324: 
fp@2324: 	/* Bypass Rx and Tx FIFO's */
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
fp@2324: 					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
fp@2324: 					E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
fp@2324: 					E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
fp@2324: 				       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
fp@2324: 				       &data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
fp@2324: 					E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
fp@2324: 					data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	ctrl_ext = er32(CTRL_EXT);
fp@2324: 	ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
fp@2324: 	ew32(CTRL_EXT, ctrl_ext);
fp@2324: 
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Do not init these registers when the HW is in IAMT mode, since the
fp@2324: 	 * firmware will have already initialized them.  We only initialize
fp@2324: 	 * them if the HW is not in IAMT mode.
fp@2324: 	 */
fp@2324: 	if (!e1000e_check_mng_mode(hw)) {
fp@2324: 		/* Enable Electrical Idle on the PHY */
fp@2324: 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
fp@2324: 		ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 
fp@2324: 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 
fp@2324: 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
fp@2324: 		ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 	}
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Workaround: Disable padding in Kumeran interface in the MAC
fp@2324: 	 * and in the PHY to avoid CRC errors.
fp@2324: 	 */
fp@2324: 	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	data |= GG82563_ICR_DIS_PADDING;
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Essentially a wrapper for setting up all things "copper" related.
fp@2324:  *  This is a function pointer entry point called by the mac module.
fp@2324:  **/
fp@2324: static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	u32 ctrl;
fp@2324: 	s32 ret_val;
fp@2324: 	u16 reg_data;
fp@2324: 
fp@2324: 	ctrl = er32(CTRL);
fp@2324: 	ctrl |= E1000_CTRL_SLU;
fp@2324: 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
fp@2324: 	ew32(CTRL, ctrl);
fp@2324: 
fp@2324: 	/*
fp@2324: 	 * Set the mac to wait the maximum time between each
fp@2324: 	 * iteration and increase the max iterations when
fp@2324: 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
fp@2324: 	 */
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
fp@2324: 	                                           0xFFFF);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
fp@2324: 	                                          &reg_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 	reg_data |= 0x3F;
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
fp@2324: 	                                           reg_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
fp@2324: 				      E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
fp@2324: 				      &reg_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
fp@2324: 					E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
fp@2324: 					reg_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	ret_val = e1000e_setup_copper_link(hw);
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @duplex: current duplex setting
fp@2324:  *
fp@2324:  *  Configure the KMRN interface by applying last minute quirks for
fp@2324:  *  10/100 operation.
fp@2324:  **/
fp@2324: static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	s32 ret_val = 0;
fp@2324: 	u16 speed;
fp@2324: 	u16 duplex;
fp@2324: 
fp@2324: 	if (hw->phy.media_type == e1000_media_type_copper) {
fp@2324: 		ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
fp@2324: 		                                             &duplex);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 
fp@2324: 		if (speed == SPEED_1000)
fp@2324: 			ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
fp@2324: 		else
fp@2324: 			ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
fp@2324: 	}
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @duplex: current duplex setting
fp@2324:  *
fp@2324:  *  Configure the KMRN interface by applying last minute quirks for
fp@2324:  *  10/100 operation.
fp@2324:  **/
fp@2324: static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 	u32 tipg;
fp@2324: 	u32 i = 0;
fp@2324: 	u16 reg_data, reg_data2;
fp@2324: 
fp@2324: 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
fp@2324: 	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
fp@2324: 	                               reg_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/* Configure Transmit Inter-Packet Gap */
fp@2324: 	tipg = er32(TIPG);
fp@2324: 	tipg &= ~E1000_TIPG_IPGT_MASK;
fp@2324: 	tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
fp@2324: 	ew32(TIPG, tipg);
fp@2324: 
fp@2324: 	do {
fp@2324: 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 
fp@2324: 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 		i++;
fp@2324: 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
fp@2324: 
fp@2324: 	if (duplex == HALF_DUPLEX)
fp@2324: 		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
fp@2324: 	else
fp@2324: 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
fp@2324: 
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
fp@2324: 
fp@2324: 	return 0;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Configure the KMRN interface by applying last minute quirks for
fp@2324:  *  gigabit operation.
fp@2324:  **/
fp@2324: static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	s32 ret_val;
fp@2324: 	u16 reg_data, reg_data2;
fp@2324: 	u32 tipg;
fp@2324: 	u32 i = 0;
fp@2324: 
fp@2324: 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
fp@2324: 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
fp@2324: 	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
fp@2324: 	                               reg_data);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	/* Configure Transmit Inter-Packet Gap */
fp@2324: 	tipg = er32(TIPG);
fp@2324: 	tipg &= ~E1000_TIPG_IPGT_MASK;
fp@2324: 	tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
fp@2324: 	ew32(TIPG, tipg);
fp@2324: 
fp@2324: 	do {
fp@2324: 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 
fp@2324: 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
fp@2324: 		if (ret_val)
fp@2324: 			return ret_val;
fp@2324: 		i++;
fp@2324: 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
fp@2324: 
fp@2324: 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
fp@2324: 	ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @offset: register offset to be read
fp@2324:  *  @data: pointer to the read data
fp@2324:  *
fp@2324:  *  Acquire semaphore, then read the PHY register at offset
fp@2324:  *  using the kumeran interface.  The information retrieved is stored in data.
fp@2324:  *  Release the semaphore before exiting.
fp@2324:  **/
fp@2324: static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
fp@2324: 					   u16 *data)
fp@2324: {
fp@2324: 	u32 kmrnctrlsta;
fp@2324: 	s32 ret_val = 0;
fp@2324: 
fp@2324: 	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
fp@2324: 	               E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
fp@2324: 	ew32(KMRNCTRLSTA, kmrnctrlsta);
fp@2324: 
fp@2324: 	udelay(2);
fp@2324: 
fp@2324: 	kmrnctrlsta = er32(KMRNCTRLSTA);
fp@2324: 	*data = (u16)kmrnctrlsta;
fp@2324: 
fp@2324: 	e1000_release_mac_csr_80003es2lan(hw);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *  @offset: register offset to write to
fp@2324:  *  @data: data to write at register offset
fp@2324:  *
fp@2324:  *  Acquire semaphore, then write the data to PHY register
fp@2324:  *  at the offset using the kumeran interface.  Release semaphore
fp@2324:  *  before exiting.
fp@2324:  **/
fp@2324: static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
fp@2324: 					    u16 data)
fp@2324: {
fp@2324: 	u32 kmrnctrlsta;
fp@2324: 	s32 ret_val = 0;
fp@2324: 
fp@2324: 	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
fp@2324: 	if (ret_val)
fp@2324: 		return ret_val;
fp@2324: 
fp@2324: 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
fp@2324: 	               E1000_KMRNCTRLSTA_OFFSET) | data;
fp@2324: 	ew32(KMRNCTRLSTA, kmrnctrlsta);
fp@2324: 
fp@2324: 	udelay(2);
fp@2324: 
fp@2324: 	e1000_release_mac_csr_80003es2lan(hw);
fp@2324: 
fp@2324: 	return ret_val;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
fp@2324:  * @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  * In the case of a PHY power down to save power, or to turn off link during a
fp@2324:  * driver unload, or wake on lan is not enabled, remove the link.
fp@2324:  **/
fp@2324: static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	/* If the management interface is not enabled, then power down */
fp@2324: 	if (!(hw->mac.ops.check_mng_mode(hw) ||
fp@2324: 	      hw->phy.ops.check_reset_block(hw)))
fp@2324: 		e1000_power_down_phy_copper(hw);
fp@2324: 
fp@2324: 	return;
fp@2324: }
fp@2324: 
fp@2324: /**
fp@2324:  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
fp@2324:  *  @hw: pointer to the HW structure
fp@2324:  *
fp@2324:  *  Clears the hardware counters by reading the counter registers.
fp@2324:  **/
fp@2324: static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
fp@2324: {
fp@2324: 	e1000e_clear_hw_cntrs_base(hw);
fp@2324: 
fp@2324: 	er32(PRC64);
fp@2324: 	er32(PRC127);
fp@2324: 	er32(PRC255);
fp@2324: 	er32(PRC511);
fp@2324: 	er32(PRC1023);
fp@2324: 	er32(PRC1522);
fp@2324: 	er32(PTC64);
fp@2324: 	er32(PTC127);
fp@2324: 	er32(PTC255);
fp@2324: 	er32(PTC511);
fp@2324: 	er32(PTC1023);
fp@2324: 	er32(PTC1522);
fp@2324: 
fp@2324: 	er32(ALGNERRC);
fp@2324: 	er32(RXERRC);
fp@2324: 	er32(TNCRS);
fp@2324: 	er32(CEXTERR);
fp@2324: 	er32(TSCTC);
fp@2324: 	er32(TSCTFC);
fp@2324: 
fp@2324: 	er32(MGTPRC);
fp@2324: 	er32(MGTPDC);
fp@2324: 	er32(MGTPTC);
fp@2324: 
fp@2324: 	er32(IAC);
fp@2324: 	er32(ICRXOC);
fp@2324: 
fp@2324: 	er32(ICRXPTC);
fp@2324: 	er32(ICRXATC);
fp@2324: 	er32(ICTXPTC);
fp@2324: 	er32(ICTXATC);
fp@2324: 	er32(ICTXQEC);
fp@2324: 	er32(ICTXQMTC);
fp@2324: 	er32(ICRXDMTC);
fp@2324: }
fp@2324: 
fp@2324: static struct e1000_mac_operations es2_mac_ops = {
fp@2324: 	.id_led_init		= e1000e_id_led_init,
fp@2324: 	.check_mng_mode		= e1000e_check_mng_mode_generic,
fp@2324: 	/* check_for_link dependent on media type */
fp@2324: 	.cleanup_led		= e1000e_cleanup_led_generic,
fp@2324: 	.clear_hw_cntrs		= e1000_clear_hw_cntrs_80003es2lan,
fp@2324: 	.get_bus_info		= e1000e_get_bus_info_pcie,
fp@2324: 	.get_link_up_info	= e1000_get_link_up_info_80003es2lan,
fp@2324: 	.led_on			= e1000e_led_on_generic,
fp@2324: 	.led_off		= e1000e_led_off_generic,
fp@2324: 	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
fp@2324: 	.write_vfta		= e1000_write_vfta_generic,
fp@2324: 	.clear_vfta		= e1000_clear_vfta_generic,
fp@2324: 	.reset_hw		= e1000_reset_hw_80003es2lan,
fp@2324: 	.init_hw		= e1000_init_hw_80003es2lan,
fp@2324: 	.setup_link		= e1000e_setup_link,
fp@2324: 	/* setup_physical_interface dependent on media type */
fp@2324: 	.setup_led		= e1000e_setup_led_generic,
fp@2324: };
fp@2324: 
fp@2324: static struct e1000_phy_operations es2_phy_ops = {
fp@2324: 	.acquire		= e1000_acquire_phy_80003es2lan,
fp@2324: 	.check_polarity		= e1000_check_polarity_m88,
fp@2324: 	.check_reset_block	= e1000e_check_reset_block_generic,
fp@2324: 	.commit		 	= e1000e_phy_sw_reset,
fp@2324: 	.force_speed_duplex 	= e1000_phy_force_speed_duplex_80003es2lan,
fp@2324: 	.get_cfg_done       	= e1000_get_cfg_done_80003es2lan,
fp@2324: 	.get_cable_length   	= e1000_get_cable_length_80003es2lan,
fp@2324: 	.get_info       	= e1000e_get_phy_info_m88,
fp@2324: 	.read_reg       	= e1000_read_phy_reg_gg82563_80003es2lan,
fp@2324: 	.release		= e1000_release_phy_80003es2lan,
fp@2324: 	.reset		  	= e1000e_phy_hw_reset_generic,
fp@2324: 	.set_d0_lplu_state  	= NULL,
fp@2324: 	.set_d3_lplu_state  	= e1000e_set_d3_lplu_state,
fp@2324: 	.write_reg      	= e1000_write_phy_reg_gg82563_80003es2lan,
fp@2324: 	.cfg_on_link_up      	= e1000_cfg_on_link_up_80003es2lan,
fp@2324: };
fp@2324: 
fp@2324: static struct e1000_nvm_operations es2_nvm_ops = {
fp@2324: 	.acquire		= e1000_acquire_nvm_80003es2lan,
fp@2324: 	.read			= e1000e_read_nvm_eerd,
fp@2324: 	.release		= e1000_release_nvm_80003es2lan,
fp@2324: 	.update			= e1000e_update_nvm_checksum_generic,
fp@2324: 	.valid_led_default	= e1000e_valid_led_default,
fp@2324: 	.validate		= e1000e_validate_nvm_checksum_generic,
fp@2324: 	.write			= e1000_write_nvm_80003es2lan,
fp@2324: };
fp@2324: 
fp@2324: struct e1000_info e1000_es2_info = {
fp@2324: 	.mac			= e1000_80003es2lan,
fp@2324: 	.flags			= FLAG_HAS_HW_VLAN_FILTER
fp@2324: 				  | FLAG_HAS_JUMBO_FRAMES
fp@2324: 				  | FLAG_HAS_WOL
fp@2324: 				  | FLAG_APME_IN_CTRL3
fp@2324: 				  | FLAG_RX_CSUM_ENABLED
fp@2324: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2324: 				  | FLAG_RX_NEEDS_RESTART /* errata */
fp@2324: 				  | FLAG_TARC_SET_BIT_ZERO /* errata */
fp@2324: 				  | FLAG_APME_CHECK_PORT_B
fp@2324: 				  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
fp@2324: 				  | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
fp@2324: 	.pba			= 38,
fp@2324: 	.max_hw_frame_size	= DEFAULT_JUMBO,
fp@2324: 	.get_variants		= e1000_get_variants_80003es2lan,
fp@2324: 	.mac_ops		= &es2_mac_ops,
fp@2324: 	.phy_ops		= &es2_phy_ops,
fp@2324: 	.nvm_ops		= &es2_nvm_ops,
fp@2324: };
fp@2324: