fp@2405: /* fp@2405: * r8169.c: RealTek 8169/8168/8101 ethernet driver. fp@2405: * fp@2405: * Copyright (c) 2002 ShuChen fp@2405: * Copyright (c) 2003 - 2007 Francois Romieu fp@2405: * Copyright (c) a lot of people too. Please respect their work. fp@2405: * fp@2405: * See MAINTAINERS file for support contact information. fp@2405: */ fp@2405: fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: fp@2405: #include fp@2405: #include fp@2405: #include fp@2405: #include "../globals.h" fp@2405: #include "ecdev.h" fp@2405: fp@2405: #define RTL8169_VERSION "2.3LK-NAPI" fp@2405: #define MODULENAME "ec_r8169" fp@2405: #define PFX MODULENAME ": " fp@2405: fp@2405: #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" fp@2405: #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" fp@2405: #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" fp@2405: #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" fp@2405: #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" fp@2405: #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" fp@2405: #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" fp@2405: #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" fp@2405: fp@2405: #ifdef RTL8169_DEBUG fp@2405: #define assert(expr) \ fp@2405: if (!(expr)) { \ fp@2405: printk( "Assertion failed! %s,%s,%s,line=%d\n", \ fp@2405: #expr,__FILE__,__func__,__LINE__); \ fp@2405: } fp@2405: #define dprintk(fmt, args...) \ fp@2405: do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) fp@2405: #else fp@2405: #define assert(expr) do {} while (0) fp@2405: #define dprintk(fmt, args...) do {} while (0) fp@2405: #endif /* RTL8169_DEBUG */ fp@2405: fp@2405: #define R8169_MSG_DEFAULT \ fp@2405: (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) fp@2405: fp@2405: #define TX_BUFFS_AVAIL(tp) \ fp@2405: (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) fp@2405: fp@2405: /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). fp@2405: The RTL chips use a 64 element hash table based on the Ethernet CRC. */ fp@2405: static const int multicast_filter_limit = 32; fp@2405: fp@2405: /* MAC address length */ fp@2405: #define MAC_ADDR_LEN 6 fp@2405: fp@2405: #define MAX_READ_REQUEST_SHIFT 12 fp@2405: #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ fp@2405: #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ fp@2405: #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ fp@2405: fp@2405: #define R8169_REGS_SIZE 256 fp@2405: #define R8169_NAPI_WEIGHT 64 fp@2405: #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ fp@2405: #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ fp@2405: #define RX_BUF_SIZE 1536 /* Rx Buffer size */ fp@2405: #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) fp@2405: #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) fp@2405: fp@2405: #define RTL8169_TX_TIMEOUT (6*HZ) fp@2405: #define RTL8169_PHY_TIMEOUT (10*HZ) fp@2405: fp@2405: #define RTL_EEPROM_SIG cpu_to_le32(0x8129) fp@2405: #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) fp@2405: #define RTL_EEPROM_SIG_ADDR 0x0000 fp@2405: fp@2405: /* write/read MMIO register */ fp@2405: #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) fp@2405: #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) fp@2405: #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) fp@2405: #define RTL_R8(reg) readb (ioaddr + (reg)) fp@2405: #define RTL_R16(reg) readw (ioaddr + (reg)) fp@2405: #define RTL_R32(reg) readl (ioaddr + (reg)) fp@2405: fp@2405: enum mac_version { fp@2405: RTL_GIGA_MAC_VER_01 = 0, fp@2405: RTL_GIGA_MAC_VER_02, fp@2405: RTL_GIGA_MAC_VER_03, fp@2405: RTL_GIGA_MAC_VER_04, fp@2405: RTL_GIGA_MAC_VER_05, fp@2405: RTL_GIGA_MAC_VER_06, fp@2405: RTL_GIGA_MAC_VER_07, fp@2405: RTL_GIGA_MAC_VER_08, fp@2405: RTL_GIGA_MAC_VER_09, fp@2405: RTL_GIGA_MAC_VER_10, fp@2405: RTL_GIGA_MAC_VER_11, fp@2405: RTL_GIGA_MAC_VER_12, fp@2405: RTL_GIGA_MAC_VER_13, fp@2405: RTL_GIGA_MAC_VER_14, fp@2405: RTL_GIGA_MAC_VER_15, fp@2405: RTL_GIGA_MAC_VER_16, fp@2405: RTL_GIGA_MAC_VER_17, fp@2405: RTL_GIGA_MAC_VER_18, fp@2405: RTL_GIGA_MAC_VER_19, fp@2405: RTL_GIGA_MAC_VER_20, fp@2405: RTL_GIGA_MAC_VER_21, fp@2405: RTL_GIGA_MAC_VER_22, fp@2405: RTL_GIGA_MAC_VER_23, fp@2405: RTL_GIGA_MAC_VER_24, fp@2405: RTL_GIGA_MAC_VER_25, fp@2405: RTL_GIGA_MAC_VER_26, fp@2405: RTL_GIGA_MAC_VER_27, fp@2405: RTL_GIGA_MAC_VER_28, fp@2405: RTL_GIGA_MAC_VER_29, fp@2405: RTL_GIGA_MAC_VER_30, fp@2405: RTL_GIGA_MAC_VER_31, fp@2405: RTL_GIGA_MAC_VER_32, fp@2405: RTL_GIGA_MAC_VER_33, fp@2405: RTL_GIGA_MAC_VER_34, fp@2405: RTL_GIGA_MAC_VER_35, fp@2405: RTL_GIGA_MAC_VER_36, fp@2405: RTL_GIGA_MAC_NONE = 0xff, fp@2405: }; fp@2405: fp@2405: enum rtl_tx_desc_version { fp@2405: RTL_TD_0 = 0, fp@2405: RTL_TD_1 = 1, fp@2405: }; fp@2405: fp@2405: #define JUMBO_1K ETH_DATA_LEN fp@2405: #define JUMBO_4K (4*1024 - ETH_HLEN - 2) fp@2405: #define JUMBO_6K (6*1024 - ETH_HLEN - 2) fp@2405: #define JUMBO_7K (7*1024 - ETH_HLEN - 2) fp@2405: #define JUMBO_9K (9*1024 - ETH_HLEN - 2) fp@2405: fp@2405: #define _R(NAME,TD,FW,SZ,B) { \ fp@2405: .name = NAME, \ fp@2405: .txd_version = TD, \ fp@2405: .fw_name = FW, \ fp@2405: .jumbo_max = SZ, \ fp@2405: .jumbo_tx_csum = B \ fp@2405: } fp@2405: fp@2405: static const struct { fp@2405: const char *name; fp@2405: enum rtl_tx_desc_version txd_version; fp@2405: const char *fw_name; fp@2405: u16 jumbo_max; fp@2405: bool jumbo_tx_csum; fp@2405: } rtl_chip_infos[] = { fp@2405: /* PCI devices. */ fp@2405: [RTL_GIGA_MAC_VER_01] = fp@2405: _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), fp@2405: [RTL_GIGA_MAC_VER_02] = fp@2405: _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), fp@2405: [RTL_GIGA_MAC_VER_03] = fp@2405: _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), fp@2405: [RTL_GIGA_MAC_VER_04] = fp@2405: _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), fp@2405: [RTL_GIGA_MAC_VER_05] = fp@2405: _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), fp@2405: [RTL_GIGA_MAC_VER_06] = fp@2405: _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), fp@2405: /* PCI-E devices. */ fp@2405: [RTL_GIGA_MAC_VER_07] = fp@2405: _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_08] = fp@2405: _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_09] = fp@2405: _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_10] = fp@2405: _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_11] = fp@2405: _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), fp@2405: [RTL_GIGA_MAC_VER_12] = fp@2405: _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), fp@2405: [RTL_GIGA_MAC_VER_13] = fp@2405: _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_14] = fp@2405: _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_15] = fp@2405: _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_16] = fp@2405: _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_17] = fp@2405: _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), fp@2405: [RTL_GIGA_MAC_VER_18] = fp@2405: _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_19] = fp@2405: _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_20] = fp@2405: _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_21] = fp@2405: _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_22] = fp@2405: _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_23] = fp@2405: _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_24] = fp@2405: _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), fp@2405: [RTL_GIGA_MAC_VER_25] = fp@2405: _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, fp@2405: JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_26] = fp@2405: _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, fp@2405: JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_27] = fp@2405: _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_28] = fp@2405: _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_29] = fp@2405: _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, fp@2405: JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_30] = fp@2405: _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, fp@2405: JUMBO_1K, true), fp@2405: [RTL_GIGA_MAC_VER_31] = fp@2405: _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_32] = fp@2405: _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, fp@2405: JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_33] = fp@2405: _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, fp@2405: JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_34] = fp@2405: _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, fp@2405: JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_35] = fp@2405: _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, fp@2405: JUMBO_9K, false), fp@2405: [RTL_GIGA_MAC_VER_36] = fp@2405: _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, fp@2405: JUMBO_9K, false), fp@2405: }; fp@2405: #undef _R fp@2405: fp@2405: enum cfg_version { fp@2405: RTL_CFG_0 = 0x00, fp@2405: RTL_CFG_1, fp@2405: RTL_CFG_2 fp@2405: }; fp@2405: fp@2405: static void rtl_hw_start_8169(struct net_device *); fp@2405: static void rtl_hw_start_8168(struct net_device *); fp@2405: static void rtl_hw_start_8101(struct net_device *); fp@2405: fp@2405: static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, fp@2405: { PCI_VENDOR_ID_LINKSYS, 0x1032, fp@2405: PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, fp@2405: { 0x0001, 0x8168, fp@2405: PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, fp@2405: {0,}, fp@2405: }; fp@2405: fp@2405: /* prevent driver from being loaded automatically */ fp@2405: //MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); fp@2405: fp@2405: static int rx_buf_sz = 16383; fp@2405: static int use_dac; fp@2405: static struct { fp@2405: u32 msg_enable; fp@2405: } debug = { -1 }; fp@2405: fp@2405: enum rtl_registers { fp@2405: MAC0 = 0, /* Ethernet hardware address. */ fp@2405: MAC4 = 4, fp@2405: MAR0 = 8, /* Multicast filter. */ fp@2405: CounterAddrLow = 0x10, fp@2405: CounterAddrHigh = 0x14, fp@2405: TxDescStartAddrLow = 0x20, fp@2405: TxDescStartAddrHigh = 0x24, fp@2405: TxHDescStartAddrLow = 0x28, fp@2405: TxHDescStartAddrHigh = 0x2c, fp@2405: FLASH = 0x30, fp@2405: ERSR = 0x36, fp@2405: ChipCmd = 0x37, fp@2405: TxPoll = 0x38, fp@2405: IntrMask = 0x3c, fp@2405: IntrStatus = 0x3e, fp@2405: fp@2405: TxConfig = 0x40, fp@2405: #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ fp@2405: #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ fp@2405: fp@2405: RxConfig = 0x44, fp@2405: #define RX128_INT_EN (1 << 15) /* 8111c and later */ fp@2405: #define RX_MULTI_EN (1 << 14) /* 8111c only */ fp@2405: #define RXCFG_FIFO_SHIFT 13 fp@2405: /* No threshold before first PCI xfer */ fp@2405: #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) fp@2405: #define RXCFG_DMA_SHIFT 8 fp@2405: /* Unlimited maximum PCI burst. */ fp@2405: #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) fp@2405: fp@2405: RxMissed = 0x4c, fp@2405: Cfg9346 = 0x50, fp@2405: Config0 = 0x51, fp@2405: Config1 = 0x52, fp@2405: Config2 = 0x53, fp@2405: Config3 = 0x54, fp@2405: Config4 = 0x55, fp@2405: Config5 = 0x56, fp@2405: MultiIntr = 0x5c, fp@2405: PHYAR = 0x60, fp@2405: PHYstatus = 0x6c, fp@2405: RxMaxSize = 0xda, fp@2405: CPlusCmd = 0xe0, fp@2405: IntrMitigate = 0xe2, fp@2405: RxDescAddrLow = 0xe4, fp@2405: RxDescAddrHigh = 0xe8, fp@2405: EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ fp@2405: fp@2405: #define NoEarlyTx 0x3f /* Max value : no early transmit. */ fp@2405: fp@2405: MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ fp@2405: fp@2405: #define TxPacketMax (8064 >> 7) fp@2405: #define EarlySize 0x27 fp@2405: fp@2405: FuncEvent = 0xf0, fp@2405: FuncEventMask = 0xf4, fp@2405: FuncPresetState = 0xf8, fp@2405: FuncForceEvent = 0xfc, fp@2405: }; fp@2405: fp@2405: enum rtl8110_registers { fp@2405: TBICSR = 0x64, fp@2405: TBI_ANAR = 0x68, fp@2405: TBI_LPAR = 0x6a, fp@2405: }; fp@2405: fp@2405: enum rtl8168_8101_registers { fp@2405: CSIDR = 0x64, fp@2405: CSIAR = 0x68, fp@2405: #define CSIAR_FLAG 0x80000000 fp@2405: #define CSIAR_WRITE_CMD 0x80000000 fp@2405: #define CSIAR_BYTE_ENABLE 0x0f fp@2405: #define CSIAR_BYTE_ENABLE_SHIFT 12 fp@2405: #define CSIAR_ADDR_MASK 0x0fff fp@2405: PMCH = 0x6f, fp@2405: EPHYAR = 0x80, fp@2405: #define EPHYAR_FLAG 0x80000000 fp@2405: #define EPHYAR_WRITE_CMD 0x80000000 fp@2405: #define EPHYAR_REG_MASK 0x1f fp@2405: #define EPHYAR_REG_SHIFT 16 fp@2405: #define EPHYAR_DATA_MASK 0xffff fp@2405: DLLPR = 0xd0, fp@2405: #define PFM_EN (1 << 6) fp@2405: DBG_REG = 0xd1, fp@2405: #define FIX_NAK_1 (1 << 4) fp@2405: #define FIX_NAK_2 (1 << 3) fp@2405: TWSI = 0xd2, fp@2405: MCU = 0xd3, fp@2405: #define NOW_IS_OOB (1 << 7) fp@2405: #define EN_NDP (1 << 3) fp@2405: #define EN_OOB_RESET (1 << 2) fp@2405: EFUSEAR = 0xdc, fp@2405: #define EFUSEAR_FLAG 0x80000000 fp@2405: #define EFUSEAR_WRITE_CMD 0x80000000 fp@2405: #define EFUSEAR_READ_CMD 0x00000000 fp@2405: #define EFUSEAR_REG_MASK 0x03ff fp@2405: #define EFUSEAR_REG_SHIFT 8 fp@2405: #define EFUSEAR_DATA_MASK 0xff fp@2405: }; fp@2405: fp@2405: enum rtl8168_registers { fp@2405: LED_FREQ = 0x1a, fp@2405: EEE_LED = 0x1b, fp@2405: ERIDR = 0x70, fp@2405: ERIAR = 0x74, fp@2405: #define ERIAR_FLAG 0x80000000 fp@2405: #define ERIAR_WRITE_CMD 0x80000000 fp@2405: #define ERIAR_READ_CMD 0x00000000 fp@2405: #define ERIAR_ADDR_BYTE_ALIGN 4 fp@2405: #define ERIAR_TYPE_SHIFT 16 fp@2405: #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) fp@2405: #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) fp@2405: #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) fp@2405: #define ERIAR_MASK_SHIFT 12 fp@2405: #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) fp@2405: #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) fp@2405: #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) fp@2405: EPHY_RXER_NUM = 0x7c, fp@2405: OCPDR = 0xb0, /* OCP GPHY access */ fp@2405: #define OCPDR_WRITE_CMD 0x80000000 fp@2405: #define OCPDR_READ_CMD 0x00000000 fp@2405: #define OCPDR_REG_MASK 0x7f fp@2405: #define OCPDR_GPHY_REG_SHIFT 16 fp@2405: #define OCPDR_DATA_MASK 0xffff fp@2405: OCPAR = 0xb4, fp@2405: #define OCPAR_FLAG 0x80000000 fp@2405: #define OCPAR_GPHY_WRITE_CMD 0x8000f060 fp@2405: #define OCPAR_GPHY_READ_CMD 0x0000f060 fp@2405: RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ fp@2405: MISC = 0xf0, /* 8168e only. */ fp@2405: #define TXPLA_RST (1 << 29) fp@2405: #define PWM_EN (1 << 22) fp@2405: }; fp@2405: fp@2405: enum rtl_register_content { fp@2405: /* InterruptStatusBits */ fp@2405: SYSErr = 0x8000, fp@2405: PCSTimeout = 0x4000, fp@2405: SWInt = 0x0100, fp@2405: TxDescUnavail = 0x0080, fp@2405: RxFIFOOver = 0x0040, fp@2405: LinkChg = 0x0020, fp@2405: RxOverflow = 0x0010, fp@2405: TxErr = 0x0008, fp@2405: TxOK = 0x0004, fp@2405: RxErr = 0x0002, fp@2405: RxOK = 0x0001, fp@2405: fp@2405: /* RxStatusDesc */ fp@2405: RxBOVF = (1 << 24), fp@2405: RxFOVF = (1 << 23), fp@2405: RxRWT = (1 << 22), fp@2405: RxRES = (1 << 21), fp@2405: RxRUNT = (1 << 20), fp@2405: RxCRC = (1 << 19), fp@2405: fp@2405: /* ChipCmdBits */ fp@2405: StopReq = 0x80, fp@2405: CmdReset = 0x10, fp@2405: CmdRxEnb = 0x08, fp@2405: CmdTxEnb = 0x04, fp@2405: RxBufEmpty = 0x01, fp@2405: fp@2405: /* TXPoll register p.5 */ fp@2405: HPQ = 0x80, /* Poll cmd on the high prio queue */ fp@2405: NPQ = 0x40, /* Poll cmd on the low prio queue */ fp@2405: FSWInt = 0x01, /* Forced software interrupt */ fp@2405: fp@2405: /* Cfg9346Bits */ fp@2405: Cfg9346_Lock = 0x00, fp@2405: Cfg9346_Unlock = 0xc0, fp@2405: fp@2405: /* rx_mode_bits */ fp@2405: AcceptErr = 0x20, fp@2405: AcceptRunt = 0x10, fp@2405: AcceptBroadcast = 0x08, fp@2405: AcceptMulticast = 0x04, fp@2405: AcceptMyPhys = 0x02, fp@2405: AcceptAllPhys = 0x01, fp@2405: #define RX_CONFIG_ACCEPT_MASK 0x3f fp@2405: fp@2405: /* TxConfigBits */ fp@2405: TxInterFrameGapShift = 24, fp@2405: TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ fp@2405: fp@2405: /* Config1 register p.24 */ fp@2405: LEDS1 = (1 << 7), fp@2405: LEDS0 = (1 << 6), fp@2405: Speed_down = (1 << 4), fp@2405: MEMMAP = (1 << 3), fp@2405: IOMAP = (1 << 2), fp@2405: VPD = (1 << 1), fp@2405: PMEnable = (1 << 0), /* Power Management Enable */ fp@2405: fp@2405: /* Config2 register p. 25 */ fp@2405: MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ fp@2405: PCI_Clock_66MHz = 0x01, fp@2405: PCI_Clock_33MHz = 0x00, fp@2405: fp@2405: /* Config3 register p.25 */ fp@2405: MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ fp@2405: LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ fp@2405: Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ fp@2405: Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ fp@2405: fp@2405: /* Config4 register */ fp@2405: Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ fp@2405: fp@2405: /* Config5 register p.27 */ fp@2405: BWF = (1 << 6), /* Accept Broadcast wakeup frame */ fp@2405: MWF = (1 << 5), /* Accept Multicast wakeup frame */ fp@2405: UWF = (1 << 4), /* Accept Unicast wakeup frame */ fp@2405: Spi_en = (1 << 3), fp@2405: LanWake = (1 << 1), /* LanWake enable/disable */ fp@2405: PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ fp@2405: fp@2405: /* TBICSR p.28 */ fp@2405: TBIReset = 0x80000000, fp@2405: TBILoopback = 0x40000000, fp@2405: TBINwEnable = 0x20000000, fp@2405: TBINwRestart = 0x10000000, fp@2405: TBILinkOk = 0x02000000, fp@2405: TBINwComplete = 0x01000000, fp@2405: fp@2405: /* CPlusCmd p.31 */ fp@2405: EnableBist = (1 << 15), // 8168 8101 fp@2405: Mac_dbgo_oe = (1 << 14), // 8168 8101 fp@2405: Normal_mode = (1 << 13), // unused fp@2405: Force_half_dup = (1 << 12), // 8168 8101 fp@2405: Force_rxflow_en = (1 << 11), // 8168 8101 fp@2405: Force_txflow_en = (1 << 10), // 8168 8101 fp@2405: Cxpl_dbg_sel = (1 << 9), // 8168 8101 fp@2405: ASF = (1 << 8), // 8168 8101 fp@2405: PktCntrDisable = (1 << 7), // 8168 8101 fp@2405: Mac_dbgo_sel = 0x001c, // 8168 fp@2405: RxVlan = (1 << 6), fp@2405: RxChkSum = (1 << 5), fp@2405: PCIDAC = (1 << 4), fp@2405: PCIMulRW = (1 << 3), fp@2405: INTT_0 = 0x0000, // 8168 fp@2405: INTT_1 = 0x0001, // 8168 fp@2405: INTT_2 = 0x0002, // 8168 fp@2405: INTT_3 = 0x0003, // 8168 fp@2405: fp@2405: /* rtl8169_PHYstatus */ fp@2405: TBI_Enable = 0x80, fp@2405: TxFlowCtrl = 0x40, fp@2405: RxFlowCtrl = 0x20, fp@2405: _1000bpsF = 0x10, fp@2405: _100bps = 0x08, fp@2405: _10bps = 0x04, fp@2405: LinkStatus = 0x02, fp@2405: FullDup = 0x01, fp@2405: fp@2405: /* _TBICSRBit */ fp@2405: TBILinkOK = 0x02000000, fp@2405: fp@2405: /* DumpCounterCommand */ fp@2405: CounterDump = 0x8, fp@2405: }; fp@2405: fp@2405: enum rtl_desc_bit { fp@2405: /* First doubleword. */ fp@2405: DescOwn = (1 << 31), /* Descriptor is owned by NIC */ fp@2405: RingEnd = (1 << 30), /* End of descriptor ring */ fp@2405: FirstFrag = (1 << 29), /* First segment of a packet */ fp@2405: LastFrag = (1 << 28), /* Final segment of a packet */ fp@2405: }; fp@2405: fp@2405: /* Generic case. */ fp@2405: enum rtl_tx_desc_bit { fp@2405: /* First doubleword. */ fp@2405: TD_LSO = (1 << 27), /* Large Send Offload */ fp@2405: #define TD_MSS_MAX 0x07ffu /* MSS value */ fp@2405: fp@2405: /* Second doubleword. */ fp@2405: TxVlanTag = (1 << 17), /* Add VLAN tag */ fp@2405: }; fp@2405: fp@2405: /* 8169, 8168b and 810x except 8102e. */ fp@2405: enum rtl_tx_desc_bit_0 { fp@2405: /* First doubleword. */ fp@2405: #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ fp@2405: TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ fp@2405: TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ fp@2405: TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ fp@2405: }; fp@2405: fp@2405: /* 8102e, 8168c and beyond. */ fp@2405: enum rtl_tx_desc_bit_1 { fp@2405: /* Second doubleword. */ fp@2405: #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ fp@2405: TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ fp@2405: TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ fp@2405: TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ fp@2405: }; fp@2405: fp@2405: static const struct rtl_tx_desc_info { fp@2405: struct { fp@2405: u32 udp; fp@2405: u32 tcp; fp@2405: } checksum; fp@2405: u16 mss_shift; fp@2405: u16 opts_offset; fp@2405: } tx_desc_info [] = { fp@2405: [RTL_TD_0] = { fp@2405: .checksum = { fp@2405: .udp = TD0_IP_CS | TD0_UDP_CS, fp@2405: .tcp = TD0_IP_CS | TD0_TCP_CS fp@2405: }, fp@2405: .mss_shift = TD0_MSS_SHIFT, fp@2405: .opts_offset = 0 fp@2405: }, fp@2405: [RTL_TD_1] = { fp@2405: .checksum = { fp@2405: .udp = TD1_IP_CS | TD1_UDP_CS, fp@2405: .tcp = TD1_IP_CS | TD1_TCP_CS fp@2405: }, fp@2405: .mss_shift = TD1_MSS_SHIFT, fp@2405: .opts_offset = 1 fp@2405: } fp@2405: }; fp@2405: fp@2405: enum rtl_rx_desc_bit { fp@2405: /* Rx private */ fp@2405: PID1 = (1 << 18), /* Protocol ID bit 1/2 */ fp@2405: PID0 = (1 << 17), /* Protocol ID bit 2/2 */ fp@2405: fp@2405: #define RxProtoUDP (PID1) fp@2405: #define RxProtoTCP (PID0) fp@2405: #define RxProtoIP (PID1 | PID0) fp@2405: #define RxProtoMask RxProtoIP fp@2405: fp@2405: IPFail = (1 << 16), /* IP checksum failed */ fp@2405: UDPFail = (1 << 15), /* UDP/IP checksum failed */ fp@2405: TCPFail = (1 << 14), /* TCP/IP checksum failed */ fp@2405: RxVlanTag = (1 << 16), /* VLAN tag available */ fp@2405: }; fp@2405: fp@2405: #define RsvdMask 0x3fffc000 fp@2405: fp@2405: struct TxDesc { fp@2405: __le32 opts1; fp@2405: __le32 opts2; fp@2405: __le64 addr; fp@2405: }; fp@2405: fp@2405: struct RxDesc { fp@2405: __le32 opts1; fp@2405: __le32 opts2; fp@2405: __le64 addr; fp@2405: }; fp@2405: fp@2405: struct ring_info { fp@2405: struct sk_buff *skb; fp@2405: u32 len; fp@2405: u8 __pad[sizeof(void *) - sizeof(u32)]; fp@2405: }; fp@2405: fp@2405: enum features { fp@2405: RTL_FEATURE_WOL = (1 << 0), fp@2405: RTL_FEATURE_MSI = (1 << 1), fp@2405: RTL_FEATURE_GMII = (1 << 2), fp@2405: }; fp@2405: fp@2405: struct rtl8169_counters { fp@2405: __le64 tx_packets; fp@2405: __le64 rx_packets; fp@2405: __le64 tx_errors; fp@2405: __le32 rx_errors; fp@2405: __le16 rx_missed; fp@2405: __le16 align_errors; fp@2405: __le32 tx_one_collision; fp@2405: __le32 tx_multi_collision; fp@2405: __le64 rx_unicast; fp@2405: __le64 rx_broadcast; fp@2405: __le32 rx_multicast; fp@2405: __le16 tx_aborted; fp@2405: __le16 tx_underun; fp@2405: }; fp@2405: fp@2405: struct rtl8169_private { fp@2405: void __iomem *mmio_addr; /* memory map physical address */ fp@2405: struct pci_dev *pci_dev; fp@2405: struct net_device *dev; fp@2405: struct napi_struct napi; fp@2405: spinlock_t lock; fp@2405: u32 msg_enable; fp@2405: u16 txd_version; fp@2405: u16 mac_version; fp@2405: u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ fp@2405: u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ fp@2405: u32 dirty_rx; fp@2405: u32 dirty_tx; fp@2405: struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ fp@2405: struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ fp@2405: dma_addr_t TxPhyAddr; fp@2405: dma_addr_t RxPhyAddr; fp@2405: void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ fp@2405: struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ fp@2405: struct timer_list timer; fp@2405: u16 cp_cmd; fp@2405: u16 intr_event; fp@2405: u16 napi_event; fp@2405: u16 intr_mask; fp@2405: fp@2405: struct mdio_ops { fp@2405: void (*write)(void __iomem *, int, int); fp@2405: int (*read)(void __iomem *, int); fp@2405: } mdio_ops; fp@2405: fp@2405: struct pll_power_ops { fp@2405: void (*down)(struct rtl8169_private *); fp@2405: void (*up)(struct rtl8169_private *); fp@2405: } pll_power_ops; fp@2405: fp@2405: struct jumbo_ops { fp@2405: void (*enable)(struct rtl8169_private *); fp@2405: void (*disable)(struct rtl8169_private *); fp@2405: } jumbo_ops; fp@2405: fp@2405: int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); fp@2405: int (*get_settings)(struct net_device *, struct ethtool_cmd *); fp@2405: void (*phy_reset_enable)(struct rtl8169_private *tp); fp@2405: void (*hw_start)(struct net_device *); fp@2405: unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); fp@2405: unsigned int (*link_ok)(void __iomem *); fp@2405: int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); fp@2405: struct delayed_work task; fp@2405: unsigned features; fp@2405: fp@2405: struct mii_if_info mii; fp@2405: struct rtl8169_counters counters; fp@2405: u32 saved_wolopts; fp@2405: fp@2405: ec_device_t *ecdev; fp@2405: unsigned long ec_watchdog_jiffies; fp@2405: u32 opts1_mask; fp@2405: fp@2405: struct rtl_fw { fp@2405: const struct firmware *fw; fp@2405: fp@2405: #define RTL_VER_SIZE 32 fp@2405: fp@2405: char version[RTL_VER_SIZE]; fp@2405: fp@2405: struct rtl_fw_phy_action { fp@2405: __le32 *code; fp@2405: size_t size; fp@2405: } phy_action; fp@2405: } *rtl_fw; fp@2405: #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) fp@2405: }; fp@2405: fp@2405: MODULE_AUTHOR("Realtek and the Linux r8169 crew "); fp@2405: MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver (EtherCAT)"); fp@2405: module_param(use_dac, int, 0); fp@2405: MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); fp@2405: module_param_named(debug, debug.msg_enable, int, 0); fp@2405: MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); fp@2405: MODULE_LICENSE("GPL"); fp@2405: MODULE_VERSION(EC_MASTER_VERSION); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168D_1); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168D_2); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168E_1); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168E_2); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168E_3); fp@2405: MODULE_FIRMWARE(FIRMWARE_8105E_1); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168F_1); fp@2405: MODULE_FIRMWARE(FIRMWARE_8168F_2); fp@2405: fp@2405: static int rtl8169_open(struct net_device *dev); fp@2405: static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, fp@2405: struct net_device *dev); fp@2405: static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); fp@2405: static int rtl8169_init_ring(struct net_device *dev); fp@2405: static void rtl_hw_start(struct net_device *dev); fp@2405: static int rtl8169_close(struct net_device *dev); fp@2405: static void rtl_set_rx_mode(struct net_device *dev); fp@2405: static void rtl8169_tx_timeout(struct net_device *dev); fp@2405: static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); fp@2405: static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, fp@2405: void __iomem *, u32 budget); fp@2405: static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); fp@2405: static void rtl8169_down(struct net_device *dev); fp@2405: static void rtl8169_rx_clear(struct rtl8169_private *tp); fp@2405: static void ec_poll(struct net_device *dev); fp@2405: static int rtl8169_poll(struct napi_struct *napi, int budget); fp@2405: fp@2405: static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) fp@2405: { fp@2405: int cap = pci_pcie_cap(pdev); fp@2405: fp@2405: if (cap) { fp@2405: u16 ctl; fp@2405: fp@2405: pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); fp@2405: ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; fp@2405: pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); fp@2405: } fp@2405: } fp@2405: fp@2405: static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int i; fp@2405: fp@2405: RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); fp@2405: for (i = 0; i < 20; i++) { fp@2405: udelay(100); fp@2405: if (RTL_R32(OCPAR) & OCPAR_FLAG) fp@2405: break; fp@2405: } fp@2405: return RTL_R32(OCPDR); fp@2405: } fp@2405: fp@2405: static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int i; fp@2405: fp@2405: RTL_W32(OCPDR, data); fp@2405: RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); fp@2405: for (i = 0; i < 20; i++) { fp@2405: udelay(100); fp@2405: if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int i; fp@2405: fp@2405: RTL_W8(ERIDR, cmd); fp@2405: RTL_W32(ERIAR, 0x800010e8); fp@2405: msleep(2); fp@2405: for (i = 0; i < 5; i++) { fp@2405: udelay(100); fp@2405: if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) fp@2405: break; fp@2405: } fp@2405: fp@2405: ocp_write(tp, 0x1, 0x30, 0x00000001); fp@2405: } fp@2405: fp@2405: #define OOB_CMD_RESET 0x00 fp@2405: #define OOB_CMD_DRIVER_START 0x05 fp@2405: #define OOB_CMD_DRIVER_STOP 0x06 fp@2405: fp@2405: static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) fp@2405: { fp@2405: return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; fp@2405: } fp@2405: fp@2405: static void rtl8168_driver_start(struct rtl8169_private *tp) fp@2405: { fp@2405: u16 reg; fp@2405: int i; fp@2405: fp@2405: rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); fp@2405: fp@2405: reg = rtl8168_get_ocp_reg(tp); fp@2405: fp@2405: for (i = 0; i < 10; i++) { fp@2405: msleep(10); fp@2405: if (ocp_read(tp, 0x0f, reg) & 0x00000800) fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8168_driver_stop(struct rtl8169_private *tp) fp@2405: { fp@2405: u16 reg; fp@2405: int i; fp@2405: fp@2405: rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); fp@2405: fp@2405: reg = rtl8168_get_ocp_reg(tp); fp@2405: fp@2405: for (i = 0; i < 10; i++) { fp@2405: msleep(10); fp@2405: if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static int r8168dp_check_dash(struct rtl8169_private *tp) fp@2405: { fp@2405: u16 reg = rtl8168_get_ocp_reg(tp); fp@2405: fp@2405: return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; fp@2405: } fp@2405: fp@2405: static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) fp@2405: { fp@2405: int i; fp@2405: fp@2405: RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); fp@2405: fp@2405: for (i = 20; i > 0; i--) { fp@2405: /* fp@2405: * Check if the RTL8169 has completed writing to the specified fp@2405: * MII register. fp@2405: */ fp@2405: if (!(RTL_R32(PHYAR) & 0x80000000)) fp@2405: break; fp@2405: udelay(25); fp@2405: } fp@2405: /* fp@2405: * According to hardware specs a 20us delay is required after write fp@2405: * complete indication, but before sending next command. fp@2405: */ fp@2405: udelay(20); fp@2405: } fp@2405: fp@2405: static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) fp@2405: { fp@2405: int i, value = -1; fp@2405: fp@2405: RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); fp@2405: fp@2405: for (i = 20; i > 0; i--) { fp@2405: /* fp@2405: * Check if the RTL8169 has completed retrieving data from fp@2405: * the specified MII register. fp@2405: */ fp@2405: if (RTL_R32(PHYAR) & 0x80000000) { fp@2405: value = RTL_R32(PHYAR) & 0xffff; fp@2405: break; fp@2405: } fp@2405: udelay(25); fp@2405: } fp@2405: /* fp@2405: * According to hardware specs a 20us delay is required after read fp@2405: * complete indication, but before sending next command. fp@2405: */ fp@2405: udelay(20); fp@2405: fp@2405: return value; fp@2405: } fp@2405: fp@2405: static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) fp@2405: { fp@2405: int i; fp@2405: fp@2405: RTL_W32(OCPDR, data | fp@2405: ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); fp@2405: RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); fp@2405: RTL_W32(EPHY_RXER_NUM, 0); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: mdelay(1); fp@2405: if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) fp@2405: { fp@2405: r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | fp@2405: (value & OCPDR_DATA_MASK)); fp@2405: } fp@2405: fp@2405: static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) fp@2405: { fp@2405: int i; fp@2405: fp@2405: r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); fp@2405: fp@2405: mdelay(1); fp@2405: RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); fp@2405: RTL_W32(EPHY_RXER_NUM, 0); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: mdelay(1); fp@2405: if (RTL_R32(OCPAR) & OCPAR_FLAG) fp@2405: break; fp@2405: } fp@2405: fp@2405: return RTL_R32(OCPDR) & OCPDR_DATA_MASK; fp@2405: } fp@2405: fp@2405: #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 fp@2405: fp@2405: static void r8168dp_2_mdio_start(void __iomem *ioaddr) fp@2405: { fp@2405: RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); fp@2405: } fp@2405: fp@2405: static void r8168dp_2_mdio_stop(void __iomem *ioaddr) fp@2405: { fp@2405: RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); fp@2405: } fp@2405: fp@2405: static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) fp@2405: { fp@2405: r8168dp_2_mdio_start(ioaddr); fp@2405: fp@2405: r8169_mdio_write(ioaddr, reg_addr, value); fp@2405: fp@2405: r8168dp_2_mdio_stop(ioaddr); fp@2405: } fp@2405: fp@2405: static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) fp@2405: { fp@2405: int value; fp@2405: fp@2405: r8168dp_2_mdio_start(ioaddr); fp@2405: fp@2405: value = r8169_mdio_read(ioaddr, reg_addr); fp@2405: fp@2405: r8168dp_2_mdio_stop(ioaddr); fp@2405: fp@2405: return value; fp@2405: } fp@2405: fp@2405: static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) fp@2405: { fp@2405: tp->mdio_ops.write(tp->mmio_addr, location, val); fp@2405: } fp@2405: fp@2405: static int rtl_readphy(struct rtl8169_private *tp, int location) fp@2405: { fp@2405: return tp->mdio_ops.read(tp->mmio_addr, location); fp@2405: } fp@2405: fp@2405: static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) fp@2405: { fp@2405: rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); fp@2405: } fp@2405: fp@2405: static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) fp@2405: { fp@2405: int val; fp@2405: fp@2405: val = rtl_readphy(tp, reg_addr); fp@2405: rtl_writephy(tp, reg_addr, (val | p) & ~m); fp@2405: } fp@2405: fp@2405: static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, fp@2405: int val) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: rtl_writephy(tp, location, val); fp@2405: } fp@2405: fp@2405: static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: return rtl_readphy(tp, location); fp@2405: } fp@2405: fp@2405: static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | fp@2405: (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) fp@2405: break; fp@2405: udelay(10); fp@2405: } fp@2405: } fp@2405: fp@2405: static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) fp@2405: { fp@2405: u16 value = 0xffff; fp@2405: unsigned int i; fp@2405: fp@2405: RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { fp@2405: value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; fp@2405: break; fp@2405: } fp@2405: udelay(10); fp@2405: } fp@2405: fp@2405: return value; fp@2405: } fp@2405: fp@2405: static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: RTL_W32(CSIDR, value); fp@2405: RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | fp@2405: CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) fp@2405: break; fp@2405: udelay(10); fp@2405: } fp@2405: } fp@2405: fp@2405: static u32 rtl_csi_read(void __iomem *ioaddr, int addr) fp@2405: { fp@2405: u32 value = ~0x00; fp@2405: unsigned int i; fp@2405: fp@2405: RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | fp@2405: CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (RTL_R32(CSIAR) & CSIAR_FLAG) { fp@2405: value = RTL_R32(CSIDR); fp@2405: break; fp@2405: } fp@2405: udelay(10); fp@2405: } fp@2405: fp@2405: return value; fp@2405: } fp@2405: fp@2405: static fp@2405: void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: BUG_ON((addr & 3) || (mask == 0)); fp@2405: RTL_W32(ERIDR, val); fp@2405: RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) fp@2405: break; fp@2405: udelay(100); fp@2405: } fp@2405: } fp@2405: fp@2405: static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) fp@2405: { fp@2405: u32 value = ~0x00; fp@2405: unsigned int i; fp@2405: fp@2405: RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); fp@2405: fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (RTL_R32(ERIAR) & ERIAR_FLAG) { fp@2405: value = RTL_R32(ERIDR); fp@2405: break; fp@2405: } fp@2405: udelay(100); fp@2405: } fp@2405: fp@2405: return value; fp@2405: } fp@2405: fp@2405: static void fp@2405: rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) fp@2405: { fp@2405: u32 val; fp@2405: fp@2405: val = rtl_eri_read(ioaddr, addr, type); fp@2405: rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); fp@2405: } fp@2405: fp@2405: struct exgmac_reg { fp@2405: u16 addr; fp@2405: u16 mask; fp@2405: u32 val; fp@2405: }; fp@2405: fp@2405: static void rtl_write_exgmac_batch(void __iomem *ioaddr, fp@2405: const struct exgmac_reg *r, int len) fp@2405: { fp@2405: while (len-- > 0) { fp@2405: rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); fp@2405: r++; fp@2405: } fp@2405: } fp@2405: fp@2405: static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) fp@2405: { fp@2405: u8 value = 0xff; fp@2405: unsigned int i; fp@2405: fp@2405: RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); fp@2405: fp@2405: for (i = 0; i < 300; i++) { fp@2405: if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { fp@2405: value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; fp@2405: break; fp@2405: } fp@2405: udelay(100); fp@2405: } fp@2405: fp@2405: return value; fp@2405: } fp@2405: fp@2405: static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W16(IntrMask, 0x0000); fp@2405: RTL_W16(IntrStatus, tp->intr_event); fp@2405: RTL_R8(ChipCmd); fp@2405: } fp@2405: fp@2405: static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: return RTL_R32(TBICSR) & TBIReset; fp@2405: } fp@2405: fp@2405: static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) fp@2405: { fp@2405: return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; fp@2405: } fp@2405: fp@2405: static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) fp@2405: { fp@2405: return RTL_R32(TBICSR) & TBILinkOk; fp@2405: } fp@2405: fp@2405: static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) fp@2405: { fp@2405: return RTL_R8(PHYstatus) & LinkStatus; fp@2405: } fp@2405: fp@2405: static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); fp@2405: } fp@2405: fp@2405: static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: unsigned int val; fp@2405: fp@2405: val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; fp@2405: rtl_writephy(tp, MII_BMCR, val & 0xffff); fp@2405: } fp@2405: fp@2405: static void rtl_link_chg_patch(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct net_device *dev = tp->dev; fp@2405: fp@2405: if (!netif_running(dev)) fp@2405: return; fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_34) { fp@2405: if (RTL_R8(PHYstatus) & _1000bpsF) { fp@2405: rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, fp@2405: 0x00000011, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, fp@2405: 0x00000005, ERIAR_EXGMAC); fp@2405: } else if (RTL_R8(PHYstatus) & _100bps) { fp@2405: rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, fp@2405: 0x0000001f, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, fp@2405: 0x00000005, ERIAR_EXGMAC); fp@2405: } else { fp@2405: rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, fp@2405: 0x0000001f, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, fp@2405: 0x0000003f, ERIAR_EXGMAC); fp@2405: } fp@2405: /* Reset packet filter */ fp@2405: rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, fp@2405: ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, fp@2405: ERIAR_EXGMAC); fp@2405: } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_36) { fp@2405: if (RTL_R8(PHYstatus) & _1000bpsF) { fp@2405: rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, fp@2405: 0x00000011, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, fp@2405: 0x00000005, ERIAR_EXGMAC); fp@2405: } else { fp@2405: rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, fp@2405: 0x0000001f, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, fp@2405: 0x0000003f, ERIAR_EXGMAC); fp@2405: } fp@2405: } fp@2405: } fp@2405: fp@2405: static void __rtl8169_check_link_status(struct net_device *dev, fp@2405: struct rtl8169_private *tp, fp@2405: void __iomem *ioaddr, bool pm) fp@2405: { fp@2405: unsigned long flags; fp@2405: fp@2405: if (tp->ecdev) { fp@2405: ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); fp@2405: return; fp@2405: } fp@2405: fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: if (tp->link_ok(ioaddr)) { fp@2405: rtl_link_chg_patch(tp); fp@2405: /* This is to cancel a scheduled suspend if there's one. */ fp@2405: if (pm) fp@2405: pm_request_resume(&tp->pci_dev->dev); fp@2405: netif_carrier_on(dev); fp@2405: if (net_ratelimit()) fp@2405: netif_info(tp, ifup, dev, "link up\n"); fp@2405: } else { fp@2405: netif_carrier_off(dev); fp@2405: netif_info(tp, ifdown, dev, "link down\n"); fp@2405: if (pm) fp@2405: pm_schedule_suspend(&tp->pci_dev->dev, 5000); fp@2405: } fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: } fp@2405: fp@2405: static void rtl8169_check_link_status(struct net_device *dev, fp@2405: struct rtl8169_private *tp, fp@2405: void __iomem *ioaddr) fp@2405: { fp@2405: __rtl8169_check_link_status(dev, tp, ioaddr, false); fp@2405: } fp@2405: fp@2405: #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) fp@2405: fp@2405: static u32 __rtl8169_get_wol(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: u8 options; fp@2405: u32 wolopts = 0; fp@2405: fp@2405: options = RTL_R8(Config1); fp@2405: if (!(options & PMEnable)) fp@2405: return 0; fp@2405: fp@2405: options = RTL_R8(Config3); fp@2405: if (options & LinkUp) fp@2405: wolopts |= WAKE_PHY; fp@2405: if (options & MagicPacket) fp@2405: wolopts |= WAKE_MAGIC; fp@2405: fp@2405: options = RTL_R8(Config5); fp@2405: if (options & UWF) fp@2405: wolopts |= WAKE_UCAST; fp@2405: if (options & BWF) fp@2405: wolopts |= WAKE_BCAST; fp@2405: if (options & MWF) fp@2405: wolopts |= WAKE_MCAST; fp@2405: fp@2405: return wolopts; fp@2405: } fp@2405: fp@2405: static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: spin_lock_irq(&tp->lock); fp@2405: fp@2405: wol->supported = WAKE_ANY; fp@2405: wol->wolopts = __rtl8169_get_wol(tp); fp@2405: fp@2405: spin_unlock_irq(&tp->lock); fp@2405: } fp@2405: fp@2405: static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: unsigned int i; fp@2405: static const struct { fp@2405: u32 opt; fp@2405: u16 reg; fp@2405: u8 mask; fp@2405: } cfg[] = { fp@2405: { WAKE_ANY, Config1, PMEnable }, fp@2405: { WAKE_PHY, Config3, LinkUp }, fp@2405: { WAKE_MAGIC, Config3, MagicPacket }, fp@2405: { WAKE_UCAST, Config5, UWF }, fp@2405: { WAKE_BCAST, Config5, BWF }, fp@2405: { WAKE_MCAST, Config5, MWF }, fp@2405: { WAKE_ANY, Config5, LanWake } fp@2405: }; fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: fp@2405: for (i = 0; i < ARRAY_SIZE(cfg); i++) { fp@2405: u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; fp@2405: if (wolopts & cfg[i].opt) fp@2405: options |= cfg[i].mask; fp@2405: RTL_W8(cfg[i].reg, options); fp@2405: } fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: } fp@2405: fp@2405: static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: spin_lock_irq(&tp->lock); fp@2405: fp@2405: if (wol->wolopts) fp@2405: tp->features |= RTL_FEATURE_WOL; fp@2405: else fp@2405: tp->features &= ~RTL_FEATURE_WOL; fp@2405: __rtl8169_set_wol(tp, wol->wolopts); fp@2405: spin_unlock_irq(&tp->lock); fp@2405: fp@2405: device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) fp@2405: { fp@2405: return rtl_chip_infos[tp->mac_version].fw_name; fp@2405: } fp@2405: fp@2405: static void rtl8169_get_drvinfo(struct net_device *dev, fp@2405: struct ethtool_drvinfo *info) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct rtl_fw *rtl_fw = tp->rtl_fw; fp@2405: fp@2405: strlcpy(info->driver, MODULENAME, sizeof(info->driver)); fp@2405: strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); fp@2405: strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); fp@2405: BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); fp@2405: strlcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" : fp@2405: rtl_fw->version, sizeof(info->fw_version)); fp@2405: } fp@2405: fp@2405: static int rtl8169_get_regs_len(struct net_device *dev) fp@2405: { fp@2405: return R8169_REGS_SIZE; fp@2405: } fp@2405: fp@2405: static int rtl8169_set_speed_tbi(struct net_device *dev, fp@2405: u8 autoneg, u16 speed, u8 duplex, u32 ignored) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int ret = 0; fp@2405: u32 reg; fp@2405: fp@2405: reg = RTL_R32(TBICSR); fp@2405: if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && fp@2405: (duplex == DUPLEX_FULL)) { fp@2405: RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); fp@2405: } else if (autoneg == AUTONEG_ENABLE) fp@2405: RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); fp@2405: else { fp@2405: netif_warn(tp, link, dev, fp@2405: "incorrect speed setting refused in TBI mode\n"); fp@2405: ret = -EOPNOTSUPP; fp@2405: } fp@2405: fp@2405: return ret; fp@2405: } fp@2405: fp@2405: static int rtl8169_set_speed_xmii(struct net_device *dev, fp@2405: u8 autoneg, u16 speed, u8 duplex, u32 adv) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: int giga_ctrl, bmcr; fp@2405: int rc = -EINVAL; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: if (autoneg == AUTONEG_ENABLE) { fp@2405: int auto_nego; fp@2405: fp@2405: auto_nego = rtl_readphy(tp, MII_ADVERTISE); fp@2405: auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | fp@2405: ADVERTISE_100HALF | ADVERTISE_100FULL); fp@2405: fp@2405: if (adv & ADVERTISED_10baseT_Half) fp@2405: auto_nego |= ADVERTISE_10HALF; fp@2405: if (adv & ADVERTISED_10baseT_Full) fp@2405: auto_nego |= ADVERTISE_10FULL; fp@2405: if (adv & ADVERTISED_100baseT_Half) fp@2405: auto_nego |= ADVERTISE_100HALF; fp@2405: if (adv & ADVERTISED_100baseT_Full) fp@2405: auto_nego |= ADVERTISE_100FULL; fp@2405: fp@2405: auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; fp@2405: fp@2405: giga_ctrl = rtl_readphy(tp, MII_CTRL1000); fp@2405: giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); fp@2405: fp@2405: /* The 8100e/8101e/8102e do Fast Ethernet only. */ fp@2405: if (tp->mii.supports_gmii) { fp@2405: if (adv & ADVERTISED_1000baseT_Half) fp@2405: giga_ctrl |= ADVERTISE_1000HALF; fp@2405: if (adv & ADVERTISED_1000baseT_Full) fp@2405: giga_ctrl |= ADVERTISE_1000FULL; fp@2405: } else if (adv & (ADVERTISED_1000baseT_Half | fp@2405: ADVERTISED_1000baseT_Full)) { fp@2405: netif_info(tp, link, dev, fp@2405: "PHY does not support 1000Mbps\n"); fp@2405: goto out; fp@2405: } fp@2405: fp@2405: bmcr = BMCR_ANENABLE | BMCR_ANRESTART; fp@2405: fp@2405: rtl_writephy(tp, MII_ADVERTISE, auto_nego); fp@2405: rtl_writephy(tp, MII_CTRL1000, giga_ctrl); fp@2405: } else { fp@2405: giga_ctrl = 0; fp@2405: fp@2405: if (speed == SPEED_10) fp@2405: bmcr = 0; fp@2405: else if (speed == SPEED_100) fp@2405: bmcr = BMCR_SPEED100; fp@2405: else fp@2405: goto out; fp@2405: fp@2405: if (duplex == DUPLEX_FULL) fp@2405: bmcr |= BMCR_FULLDPLX; fp@2405: } fp@2405: fp@2405: rtl_writephy(tp, MII_BMCR, bmcr); fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_02 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_03) { fp@2405: if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { fp@2405: rtl_writephy(tp, 0x17, 0x2138); fp@2405: rtl_writephy(tp, 0x0e, 0x0260); fp@2405: } else { fp@2405: rtl_writephy(tp, 0x17, 0x2108); fp@2405: rtl_writephy(tp, 0x0e, 0x0000); fp@2405: } fp@2405: } fp@2405: fp@2405: rc = 0; fp@2405: out: fp@2405: return rc; fp@2405: } fp@2405: fp@2405: static int rtl8169_set_speed(struct net_device *dev, fp@2405: u8 autoneg, u16 speed, u8 duplex, u32 advertising) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: int ret; fp@2405: fp@2405: ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); fp@2405: if (ret < 0) fp@2405: goto out; fp@2405: fp@2405: if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && fp@2405: (advertising & ADVERTISED_1000baseT_Full)) { fp@2405: mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); fp@2405: } fp@2405: out: fp@2405: return ret; fp@2405: } fp@2405: fp@2405: static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: unsigned long flags; fp@2405: int ret; fp@2405: fp@2405: del_timer_sync(&tp->timer); fp@2405: fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), fp@2405: cmd->duplex, cmd->advertising); fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: fp@2405: return ret; fp@2405: } fp@2405: fp@2405: static u32 rtl8169_fix_features(struct net_device *dev, u32 features) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (dev->mtu > TD_MSS_MAX) fp@2405: features &= ~NETIF_F_ALL_TSO; fp@2405: fp@2405: if (dev->mtu > JUMBO_1K && fp@2405: !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) fp@2405: features &= ~NETIF_F_IP_CSUM; fp@2405: fp@2405: return features; fp@2405: } fp@2405: fp@2405: static int rtl8169_set_features(struct net_device *dev, u32 features) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: unsigned long flags; fp@2405: fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: fp@2405: if (features & NETIF_F_RXCSUM) fp@2405: tp->cp_cmd |= RxChkSum; fp@2405: else fp@2405: tp->cp_cmd &= ~RxChkSum; fp@2405: fp@2405: if (dev->features & NETIF_F_HW_VLAN_RX) fp@2405: tp->cp_cmd |= RxVlan; fp@2405: else fp@2405: tp->cp_cmd &= ~RxVlan; fp@2405: fp@2405: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2405: RTL_R16(CPlusCmd); fp@2405: fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, fp@2405: struct sk_buff *skb) fp@2405: { fp@2405: return (vlan_tx_tag_present(skb)) ? fp@2405: TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; fp@2405: } fp@2405: fp@2405: static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) fp@2405: { fp@2405: u32 opts2 = le32_to_cpu(desc->opts2); fp@2405: fp@2405: if (opts2 & RxVlanTag) fp@2405: __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); fp@2405: fp@2405: desc->opts2 = 0; fp@2405: } fp@2405: fp@2405: static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: u32 status; fp@2405: fp@2405: cmd->supported = fp@2405: SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; fp@2405: cmd->port = PORT_FIBRE; fp@2405: cmd->transceiver = XCVR_INTERNAL; fp@2405: fp@2405: status = RTL_R32(TBICSR); fp@2405: cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; fp@2405: cmd->autoneg = !!(status & TBINwEnable); fp@2405: fp@2405: ethtool_cmd_speed_set(cmd, SPEED_1000); fp@2405: cmd->duplex = DUPLEX_FULL; /* Always set */ fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: return mii_ethtool_gset(&tp->mii, cmd); fp@2405: } fp@2405: fp@2405: static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: unsigned long flags; fp@2405: int rc; fp@2405: fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: fp@2405: rc = tp->get_settings(dev, cmd); fp@2405: fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: return rc; fp@2405: } fp@2405: fp@2405: static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, fp@2405: void *p) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: unsigned long flags; fp@2405: fp@2405: if (regs->len > R8169_REGS_SIZE) fp@2405: regs->len = R8169_REGS_SIZE; fp@2405: fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: memcpy_fromio(p, tp->mmio_addr, regs->len); fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: } fp@2405: fp@2405: static u32 rtl8169_get_msglevel(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: return tp->msg_enable; fp@2405: } fp@2405: fp@2405: static void rtl8169_set_msglevel(struct net_device *dev, u32 value) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: tp->msg_enable = value; fp@2405: } fp@2405: fp@2405: static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { fp@2405: "tx_packets", fp@2405: "rx_packets", fp@2405: "tx_errors", fp@2405: "rx_errors", fp@2405: "rx_missed", fp@2405: "align_errors", fp@2405: "tx_single_collisions", fp@2405: "tx_multi_collisions", fp@2405: "unicast", fp@2405: "broadcast", fp@2405: "multicast", fp@2405: "tx_aborted", fp@2405: "tx_underrun", fp@2405: }; fp@2405: fp@2405: static int rtl8169_get_sset_count(struct net_device *dev, int sset) fp@2405: { fp@2405: switch (sset) { fp@2405: case ETH_SS_STATS: fp@2405: return ARRAY_SIZE(rtl8169_gstrings); fp@2405: default: fp@2405: return -EOPNOTSUPP; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8169_update_counters(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct device *d = &tp->pci_dev->dev; fp@2405: struct rtl8169_counters *counters; fp@2405: dma_addr_t paddr; fp@2405: u32 cmd; fp@2405: int wait = 1000; fp@2405: fp@2405: /* fp@2405: * Some chips are unable to dump tally counters when the receiver fp@2405: * is disabled. fp@2405: */ fp@2405: if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) fp@2405: return; fp@2405: fp@2405: counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); fp@2405: if (!counters) fp@2405: return; fp@2405: fp@2405: RTL_W32(CounterAddrHigh, (u64)paddr >> 32); fp@2405: cmd = (u64)paddr & DMA_BIT_MASK(32); fp@2405: RTL_W32(CounterAddrLow, cmd); fp@2405: RTL_W32(CounterAddrLow, cmd | CounterDump); fp@2405: fp@2405: while (wait--) { fp@2405: if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { fp@2405: memcpy(&tp->counters, counters, sizeof(*counters)); fp@2405: break; fp@2405: } fp@2405: udelay(10); fp@2405: } fp@2405: fp@2405: RTL_W32(CounterAddrLow, 0); fp@2405: RTL_W32(CounterAddrHigh, 0); fp@2405: fp@2405: dma_free_coherent(d, sizeof(*counters), counters, paddr); fp@2405: } fp@2405: fp@2405: static void rtl8169_get_ethtool_stats(struct net_device *dev, fp@2405: struct ethtool_stats *stats, u64 *data) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: ASSERT_RTNL(); fp@2405: fp@2405: rtl8169_update_counters(dev); fp@2405: fp@2405: data[0] = le64_to_cpu(tp->counters.tx_packets); fp@2405: data[1] = le64_to_cpu(tp->counters.rx_packets); fp@2405: data[2] = le64_to_cpu(tp->counters.tx_errors); fp@2405: data[3] = le32_to_cpu(tp->counters.rx_errors); fp@2405: data[4] = le16_to_cpu(tp->counters.rx_missed); fp@2405: data[5] = le16_to_cpu(tp->counters.align_errors); fp@2405: data[6] = le32_to_cpu(tp->counters.tx_one_collision); fp@2405: data[7] = le32_to_cpu(tp->counters.tx_multi_collision); fp@2405: data[8] = le64_to_cpu(tp->counters.rx_unicast); fp@2405: data[9] = le64_to_cpu(tp->counters.rx_broadcast); fp@2405: data[10] = le32_to_cpu(tp->counters.rx_multicast); fp@2405: data[11] = le16_to_cpu(tp->counters.tx_aborted); fp@2405: data[12] = le16_to_cpu(tp->counters.tx_underun); fp@2405: } fp@2405: fp@2405: static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) fp@2405: { fp@2405: switch(stringset) { fp@2405: case ETH_SS_STATS: fp@2405: memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static const struct ethtool_ops rtl8169_ethtool_ops = { fp@2405: .get_drvinfo = rtl8169_get_drvinfo, fp@2405: .get_regs_len = rtl8169_get_regs_len, fp@2405: .get_link = ethtool_op_get_link, fp@2405: .get_settings = rtl8169_get_settings, fp@2405: .set_settings = rtl8169_set_settings, fp@2405: .get_msglevel = rtl8169_get_msglevel, fp@2405: .set_msglevel = rtl8169_set_msglevel, fp@2405: .get_regs = rtl8169_get_regs, fp@2405: .get_wol = rtl8169_get_wol, fp@2405: .set_wol = rtl8169_set_wol, fp@2405: .get_strings = rtl8169_get_strings, fp@2405: .get_sset_count = rtl8169_get_sset_count, fp@2405: .get_ethtool_stats = rtl8169_get_ethtool_stats, fp@2405: }; fp@2405: fp@2405: static void rtl8169_get_mac_version(struct rtl8169_private *tp, fp@2405: struct net_device *dev, u8 default_version) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: /* fp@2405: * The driver currently handles the 8168Bf and the 8168Be identically fp@2405: * but they can be identified more specifically through the test below fp@2405: * if needed: fp@2405: * fp@2405: * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be fp@2405: * fp@2405: * Same thing for the 8101Eb and the 8101Ec: fp@2405: * fp@2405: * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec fp@2405: */ fp@2405: static const struct rtl_mac_info { fp@2405: u32 mask; fp@2405: u32 val; fp@2405: int mac_version; fp@2405: } mac_info[] = { fp@2405: /* 8168F family. */ fp@2405: { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, fp@2405: { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, fp@2405: fp@2405: /* 8168E family. */ fp@2405: { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, fp@2405: { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, fp@2405: { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, fp@2405: { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, fp@2405: fp@2405: /* 8168D family. */ fp@2405: { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, fp@2405: { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, fp@2405: { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, fp@2405: fp@2405: /* 8168DP family. */ fp@2405: { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, fp@2405: { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, fp@2405: { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, fp@2405: fp@2405: /* 8168C family. */ fp@2405: { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, fp@2405: { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, fp@2405: { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, fp@2405: { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, fp@2405: { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, fp@2405: { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, fp@2405: { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, fp@2405: { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, fp@2405: { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, fp@2405: fp@2405: /* 8168B family. */ fp@2405: { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, fp@2405: { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, fp@2405: { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, fp@2405: { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, fp@2405: fp@2405: /* 8101 family. */ fp@2405: { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, fp@2405: { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, fp@2405: { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, fp@2405: { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, fp@2405: { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, fp@2405: { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, fp@2405: { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, fp@2405: { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, fp@2405: { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, fp@2405: { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, fp@2405: { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, fp@2405: { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, fp@2405: { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, fp@2405: { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, fp@2405: { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, fp@2405: { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, fp@2405: /* FIXME: where did these entries come from ? -- FR */ fp@2405: { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, fp@2405: { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, fp@2405: fp@2405: /* 8110 family. */ fp@2405: { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, fp@2405: { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, fp@2405: { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, fp@2405: { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, fp@2405: { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, fp@2405: { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, fp@2405: fp@2405: /* Catch-all */ fp@2405: { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } fp@2405: }; fp@2405: const struct rtl_mac_info *p = mac_info; fp@2405: u32 reg; fp@2405: fp@2405: reg = RTL_R32(TxConfig); fp@2405: while ((reg & p->mask) != p->val) fp@2405: p++; fp@2405: tp->mac_version = p->mac_version; fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_NONE) { fp@2405: netif_notice(tp, probe, dev, fp@2405: "unknown MAC, using family default\n"); fp@2405: tp->mac_version = default_version; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8169_print_mac_version(struct rtl8169_private *tp) fp@2405: { fp@2405: dprintk("mac_version = 0x%02x\n", tp->mac_version); fp@2405: } fp@2405: fp@2405: struct phy_reg { fp@2405: u16 reg; fp@2405: u16 val; fp@2405: }; fp@2405: fp@2405: static void rtl_writephy_batch(struct rtl8169_private *tp, fp@2405: const struct phy_reg *regs, int len) fp@2405: { fp@2405: while (len-- > 0) { fp@2405: rtl_writephy(tp, regs->reg, regs->val); fp@2405: regs++; fp@2405: } fp@2405: } fp@2405: fp@2405: #define PHY_READ 0x00000000 fp@2405: #define PHY_DATA_OR 0x10000000 fp@2405: #define PHY_DATA_AND 0x20000000 fp@2405: #define PHY_BJMPN 0x30000000 fp@2405: #define PHY_READ_EFUSE 0x40000000 fp@2405: #define PHY_READ_MAC_BYTE 0x50000000 fp@2405: #define PHY_WRITE_MAC_BYTE 0x60000000 fp@2405: #define PHY_CLEAR_READCOUNT 0x70000000 fp@2405: #define PHY_WRITE 0x80000000 fp@2405: #define PHY_READCOUNT_EQ_SKIP 0x90000000 fp@2405: #define PHY_COMP_EQ_SKIPN 0xa0000000 fp@2405: #define PHY_COMP_NEQ_SKIPN 0xb0000000 fp@2405: #define PHY_WRITE_PREVIOUS 0xc0000000 fp@2405: #define PHY_SKIPN 0xd0000000 fp@2405: #define PHY_DELAY_MS 0xe0000000 fp@2405: #define PHY_WRITE_ERI_WORD 0xf0000000 fp@2405: fp@2405: struct fw_info { fp@2405: u32 magic; fp@2405: char version[RTL_VER_SIZE]; fp@2405: __le32 fw_start; fp@2405: __le32 fw_len; fp@2405: u8 chksum; fp@2405: } __packed; fp@2405: fp@2405: #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) fp@2405: fp@2405: static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) fp@2405: { fp@2405: const struct firmware *fw = rtl_fw->fw; fp@2405: struct fw_info *fw_info = (struct fw_info *)fw->data; fp@2405: struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; fp@2405: char *version = rtl_fw->version; fp@2405: bool rc = false; fp@2405: fp@2405: if (fw->size < FW_OPCODE_SIZE) fp@2405: goto out; fp@2405: fp@2405: if (!fw_info->magic) { fp@2405: size_t i, size, start; fp@2405: u8 checksum = 0; fp@2405: fp@2405: if (fw->size < sizeof(*fw_info)) fp@2405: goto out; fp@2405: fp@2405: for (i = 0; i < fw->size; i++) fp@2405: checksum += fw->data[i]; fp@2405: if (checksum != 0) fp@2405: goto out; fp@2405: fp@2405: start = le32_to_cpu(fw_info->fw_start); fp@2405: if (start > fw->size) fp@2405: goto out; fp@2405: fp@2405: size = le32_to_cpu(fw_info->fw_len); fp@2405: if (size > (fw->size - start) / FW_OPCODE_SIZE) fp@2405: goto out; fp@2405: fp@2405: memcpy(version, fw_info->version, RTL_VER_SIZE); fp@2405: fp@2405: pa->code = (__le32 *)(fw->data + start); fp@2405: pa->size = size; fp@2405: } else { fp@2405: if (fw->size % FW_OPCODE_SIZE) fp@2405: goto out; fp@2405: fp@2405: strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); fp@2405: fp@2405: pa->code = (__le32 *)fw->data; fp@2405: pa->size = fw->size / FW_OPCODE_SIZE; fp@2405: } fp@2405: version[RTL_VER_SIZE - 1] = 0; fp@2405: fp@2405: rc = true; fp@2405: out: fp@2405: return rc; fp@2405: } fp@2405: fp@2405: static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, fp@2405: struct rtl_fw_phy_action *pa) fp@2405: { fp@2405: bool rc = false; fp@2405: size_t index; fp@2405: fp@2405: for (index = 0; index < pa->size; index++) { fp@2405: u32 action = le32_to_cpu(pa->code[index]); fp@2405: u32 regno = (action & 0x0fff0000) >> 16; fp@2405: fp@2405: switch(action & 0xf0000000) { fp@2405: case PHY_READ: fp@2405: case PHY_DATA_OR: fp@2405: case PHY_DATA_AND: fp@2405: case PHY_READ_EFUSE: fp@2405: case PHY_CLEAR_READCOUNT: fp@2405: case PHY_WRITE: fp@2405: case PHY_WRITE_PREVIOUS: fp@2405: case PHY_DELAY_MS: fp@2405: break; fp@2405: fp@2405: case PHY_BJMPN: fp@2405: if (regno > index) { fp@2405: netif_err(tp, ifup, tp->dev, fp@2405: "Out of range of firmware\n"); fp@2405: goto out; fp@2405: } fp@2405: break; fp@2405: case PHY_READCOUNT_EQ_SKIP: fp@2405: if (index + 2 >= pa->size) { fp@2405: netif_err(tp, ifup, tp->dev, fp@2405: "Out of range of firmware\n"); fp@2405: goto out; fp@2405: } fp@2405: break; fp@2405: case PHY_COMP_EQ_SKIPN: fp@2405: case PHY_COMP_NEQ_SKIPN: fp@2405: case PHY_SKIPN: fp@2405: if (index + 1 + regno >= pa->size) { fp@2405: netif_err(tp, ifup, tp->dev, fp@2405: "Out of range of firmware\n"); fp@2405: goto out; fp@2405: } fp@2405: break; fp@2405: fp@2405: case PHY_READ_MAC_BYTE: fp@2405: case PHY_WRITE_MAC_BYTE: fp@2405: case PHY_WRITE_ERI_WORD: fp@2405: default: fp@2405: netif_err(tp, ifup, tp->dev, fp@2405: "Invalid action 0x%08x\n", action); fp@2405: goto out; fp@2405: } fp@2405: } fp@2405: rc = true; fp@2405: out: fp@2405: return rc; fp@2405: } fp@2405: fp@2405: static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) fp@2405: { fp@2405: struct net_device *dev = tp->dev; fp@2405: int rc = -EINVAL; fp@2405: fp@2405: if (!rtl_fw_format_ok(tp, rtl_fw)) { fp@2405: netif_err(tp, ifup, dev, "invalid firwmare\n"); fp@2405: goto out; fp@2405: } fp@2405: fp@2405: if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) fp@2405: rc = 0; fp@2405: out: fp@2405: return rc; fp@2405: } fp@2405: fp@2405: static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) fp@2405: { fp@2405: struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; fp@2405: u32 predata, count; fp@2405: size_t index; fp@2405: fp@2405: predata = count = 0; fp@2405: fp@2405: for (index = 0; index < pa->size; ) { fp@2405: u32 action = le32_to_cpu(pa->code[index]); fp@2405: u32 data = action & 0x0000ffff; fp@2405: u32 regno = (action & 0x0fff0000) >> 16; fp@2405: fp@2405: if (!action) fp@2405: break; fp@2405: fp@2405: switch(action & 0xf0000000) { fp@2405: case PHY_READ: fp@2405: predata = rtl_readphy(tp, regno); fp@2405: count++; fp@2405: index++; fp@2405: break; fp@2405: case PHY_DATA_OR: fp@2405: predata |= data; fp@2405: index++; fp@2405: break; fp@2405: case PHY_DATA_AND: fp@2405: predata &= data; fp@2405: index++; fp@2405: break; fp@2405: case PHY_BJMPN: fp@2405: index -= regno; fp@2405: break; fp@2405: case PHY_READ_EFUSE: fp@2405: predata = rtl8168d_efuse_read(tp->mmio_addr, regno); fp@2405: index++; fp@2405: break; fp@2405: case PHY_CLEAR_READCOUNT: fp@2405: count = 0; fp@2405: index++; fp@2405: break; fp@2405: case PHY_WRITE: fp@2405: rtl_writephy(tp, regno, data); fp@2405: index++; fp@2405: break; fp@2405: case PHY_READCOUNT_EQ_SKIP: fp@2405: index += (count == data) ? 2 : 1; fp@2405: break; fp@2405: case PHY_COMP_EQ_SKIPN: fp@2405: if (predata == data) fp@2405: index += regno; fp@2405: index++; fp@2405: break; fp@2405: case PHY_COMP_NEQ_SKIPN: fp@2405: if (predata != data) fp@2405: index += regno; fp@2405: index++; fp@2405: break; fp@2405: case PHY_WRITE_PREVIOUS: fp@2405: rtl_writephy(tp, regno, predata); fp@2405: index++; fp@2405: break; fp@2405: case PHY_SKIPN: fp@2405: index += regno + 1; fp@2405: break; fp@2405: case PHY_DELAY_MS: fp@2405: mdelay(data); fp@2405: index++; fp@2405: break; fp@2405: fp@2405: case PHY_READ_MAC_BYTE: fp@2405: case PHY_WRITE_MAC_BYTE: fp@2405: case PHY_WRITE_ERI_WORD: fp@2405: default: fp@2405: BUG(); fp@2405: } fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_release_firmware(struct rtl8169_private *tp) fp@2405: { fp@2405: if (!IS_ERR_OR_NULL(tp->rtl_fw)) { fp@2405: release_firmware(tp->rtl_fw->fw); fp@2405: kfree(tp->rtl_fw); fp@2405: } fp@2405: tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; fp@2405: } fp@2405: fp@2405: static void rtl_apply_firmware(struct rtl8169_private *tp) fp@2405: { fp@2405: struct rtl_fw *rtl_fw = tp->rtl_fw; fp@2405: fp@2405: /* TODO: release firmware once rtl_phy_write_fw signals failures. */ fp@2405: if (!IS_ERR_OR_NULL(rtl_fw)) fp@2405: rtl_phy_write_fw(tp, rtl_fw); fp@2405: } fp@2405: fp@2405: static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) fp@2405: { fp@2405: if (rtl_readphy(tp, reg) != val) fp@2405: netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); fp@2405: else fp@2405: rtl_apply_firmware(tp); fp@2405: } fp@2405: fp@2405: static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x06, 0x006e }, fp@2405: { 0x08, 0x0708 }, fp@2405: { 0x15, 0x4000 }, fp@2405: { 0x18, 0x65c7 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x03, 0x00a1 }, fp@2405: { 0x02, 0x0008 }, fp@2405: { 0x01, 0x0120 }, fp@2405: { 0x00, 0x1000 }, fp@2405: { 0x04, 0x0800 }, fp@2405: { 0x04, 0x0000 }, fp@2405: fp@2405: { 0x03, 0xff41 }, fp@2405: { 0x02, 0xdf60 }, fp@2405: { 0x01, 0x0140 }, fp@2405: { 0x00, 0x0077 }, fp@2405: { 0x04, 0x7800 }, fp@2405: { 0x04, 0x7000 }, fp@2405: fp@2405: { 0x03, 0x802f }, fp@2405: { 0x02, 0x4f02 }, fp@2405: { 0x01, 0x0409 }, fp@2405: { 0x00, 0xf0f9 }, fp@2405: { 0x04, 0x9800 }, fp@2405: { 0x04, 0x9000 }, fp@2405: fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0xff95 }, fp@2405: { 0x00, 0xba00 }, fp@2405: { 0x04, 0xa800 }, fp@2405: { 0x04, 0xa000 }, fp@2405: fp@2405: { 0x03, 0xff41 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0x0140 }, fp@2405: { 0x00, 0x00bb }, fp@2405: { 0x04, 0xb800 }, fp@2405: { 0x04, 0xb000 }, fp@2405: fp@2405: { 0x03, 0xdf41 }, fp@2405: { 0x02, 0xdc60 }, fp@2405: { 0x01, 0x6340 }, fp@2405: { 0x00, 0x007d }, fp@2405: { 0x04, 0xd800 }, fp@2405: { 0x04, 0xd000 }, fp@2405: fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0x100a }, fp@2405: { 0x00, 0xa0ff }, fp@2405: { 0x04, 0xf800 }, fp@2405: { 0x04, 0xf000 }, fp@2405: fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x0b, 0x0000 }, fp@2405: { 0x00, 0x9200 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x01, 0x90d0 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) fp@2405: { fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || fp@2405: (pdev->subsystem_device != 0xe000)) fp@2405: return; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0001); fp@2405: rtl_writephy(tp, 0x10, 0xf01b); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x04, 0x0000 }, fp@2405: { 0x03, 0x00a1 }, fp@2405: { 0x02, 0x0008 }, fp@2405: { 0x01, 0x0120 }, fp@2405: { 0x00, 0x1000 }, fp@2405: { 0x04, 0x0800 }, fp@2405: { 0x04, 0x9000 }, fp@2405: { 0x03, 0x802f }, fp@2405: { 0x02, 0x4f02 }, fp@2405: { 0x01, 0x0409 }, fp@2405: { 0x00, 0xf099 }, fp@2405: { 0x04, 0x9800 }, fp@2405: { 0x04, 0xa000 }, fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0xff95 }, fp@2405: { 0x00, 0xba00 }, fp@2405: { 0x04, 0xa800 }, fp@2405: { 0x04, 0xf000 }, fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0x101a }, fp@2405: { 0x00, 0xa0ff }, fp@2405: { 0x04, 0xf800 }, fp@2405: { 0x04, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x10, 0xf41b }, fp@2405: { 0x14, 0xfb54 }, fp@2405: { 0x18, 0xf5c7 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x17, 0x0cc0 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: rtl8169scd_hw_phy_config_quirk(tp); fp@2405: } fp@2405: fp@2405: static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x04, 0x0000 }, fp@2405: { 0x03, 0x00a1 }, fp@2405: { 0x02, 0x0008 }, fp@2405: { 0x01, 0x0120 }, fp@2405: { 0x00, 0x1000 }, fp@2405: { 0x04, 0x0800 }, fp@2405: { 0x04, 0x9000 }, fp@2405: { 0x03, 0x802f }, fp@2405: { 0x02, 0x4f02 }, fp@2405: { 0x01, 0x0409 }, fp@2405: { 0x00, 0xf099 }, fp@2405: { 0x04, 0x9800 }, fp@2405: { 0x04, 0xa000 }, fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0xff95 }, fp@2405: { 0x00, 0xba00 }, fp@2405: { 0x04, 0xa800 }, fp@2405: { 0x04, 0xf000 }, fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0x101a }, fp@2405: { 0x00, 0xa0ff }, fp@2405: { 0x04, 0xf800 }, fp@2405: { 0x04, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x0b, 0x8480 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x18, 0x67c7 }, fp@2405: { 0x04, 0x2000 }, fp@2405: { 0x03, 0x002f }, fp@2405: { 0x02, 0x4360 }, fp@2405: { 0x01, 0x0109 }, fp@2405: { 0x00, 0x3022 }, fp@2405: { 0x04, 0x2800 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x17, 0x0cc0 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x10, 0xf41b }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0001); fp@2405: rtl_patchphy(tp, 0x16, 1 << 0); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x10, 0xf41b }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x1d, 0x0f00 }, fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x0c, 0x1ec8 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x1d, 0x3d98 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_patchphy(tp, 0x14, 1 << 5); fp@2405: rtl_patchphy(tp, 0x0d, 1 << 5); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x12, 0x2300 }, fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x00, 0x88d4 }, fp@2405: { 0x01, 0x82b1 }, fp@2405: { 0x03, 0x7002 }, fp@2405: { 0x08, 0x9e30 }, fp@2405: { 0x09, 0x01f0 }, fp@2405: { 0x0a, 0x5500 }, fp@2405: { 0x0c, 0x00c8 }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x12, 0xc096 }, fp@2405: { 0x16, 0x000a }, fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x09, 0x2000 }, fp@2405: { 0x09, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: rtl_patchphy(tp, 0x14, 1 << 5); fp@2405: rtl_patchphy(tp, 0x0d, 1 << 5); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x12, 0x2300 }, fp@2405: { 0x03, 0x802f }, fp@2405: { 0x02, 0x4f02 }, fp@2405: { 0x01, 0x0409 }, fp@2405: { 0x00, 0xf099 }, fp@2405: { 0x04, 0x9800 }, fp@2405: { 0x04, 0x9000 }, fp@2405: { 0x1d, 0x3d98 }, fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x0c, 0x7eb8 }, fp@2405: { 0x06, 0x0761 }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x16, 0x0f0a }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: rtl_patchphy(tp, 0x16, 1 << 0); fp@2405: rtl_patchphy(tp, 0x14, 1 << 5); fp@2405: rtl_patchphy(tp, 0x0d, 1 << 5); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x12, 0x2300 }, fp@2405: { 0x1d, 0x3d98 }, fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x0c, 0x7eb8 }, fp@2405: { 0x06, 0x5461 }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x16, 0x0f0a }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: rtl_patchphy(tp, 0x16, 1 << 0); fp@2405: rtl_patchphy(tp, 0x14, 1 << 5); fp@2405: rtl_patchphy(tp, 0x0d, 1 << 5); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl8168c_3_hw_phy_config(tp); fp@2405: } fp@2405: fp@2405: static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init_0[] = { fp@2405: /* Channel Estimation */ fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x06, 0x4064 }, fp@2405: { 0x07, 0x2863 }, fp@2405: { 0x08, 0x059c }, fp@2405: { 0x09, 0x26b4 }, fp@2405: { 0x0a, 0x6a19 }, fp@2405: { 0x0b, 0xdcc8 }, fp@2405: { 0x10, 0xf06d }, fp@2405: { 0x14, 0x7f68 }, fp@2405: { 0x18, 0x7fd9 }, fp@2405: { 0x1c, 0xf0ff }, fp@2405: { 0x1d, 0x3d9c }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x12, 0xf49f }, fp@2405: { 0x13, 0x070b }, fp@2405: { 0x1a, 0x05ad }, fp@2405: { 0x14, 0x94c0 }, fp@2405: fp@2405: /* fp@2405: * Tx Error Issue fp@2405: * Enhance line driver power fp@2405: */ fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x06, 0x5561 }, fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8332 }, fp@2405: { 0x06, 0x5561 }, fp@2405: fp@2405: /* fp@2405: * Can not link to 1Gbps with bad cable fp@2405: * Decrease SNR threshold form 21.07dB to 19.04dB fp@2405: */ fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x17, 0x0cc0 }, fp@2405: fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x0d, 0xf880 } fp@2405: }; fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); fp@2405: fp@2405: /* fp@2405: * Rx Error Issue fp@2405: * Fine Tune Switching regulator parameter fp@2405: */ fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); fp@2405: rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); fp@2405: fp@2405: if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x05, 0x669a }, fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8330 }, fp@2405: { 0x06, 0x669a }, fp@2405: { 0x1f, 0x0002 } fp@2405: }; fp@2405: int val; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: val = rtl_readphy(tp, 0x0d); fp@2405: fp@2405: if ((val & 0x00ff) != 0x006c) { fp@2405: static const u32 set[] = { fp@2405: 0x0065, 0x0066, 0x0067, 0x0068, fp@2405: 0x0069, 0x006a, 0x006b, 0x006c fp@2405: }; fp@2405: int i; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: fp@2405: val &= 0xff00; fp@2405: for (i = 0; i < ARRAY_SIZE(set); i++) fp@2405: rtl_writephy(tp, 0x0d, val | set[i]); fp@2405: } fp@2405: } else { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x05, 0x6662 }, fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8330 }, fp@2405: { 0x06, 0x6662 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: /* RSET couple improve */ fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_patchphy(tp, 0x0d, 0x0300); fp@2405: rtl_patchphy(tp, 0x0f, 0x0010); fp@2405: fp@2405: /* Fine tune PLL performance */ fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); fp@2405: rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x001b); fp@2405: fp@2405: rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init_0[] = { fp@2405: /* Channel Estimation */ fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x06, 0x4064 }, fp@2405: { 0x07, 0x2863 }, fp@2405: { 0x08, 0x059c }, fp@2405: { 0x09, 0x26b4 }, fp@2405: { 0x0a, 0x6a19 }, fp@2405: { 0x0b, 0xdcc8 }, fp@2405: { 0x10, 0xf06d }, fp@2405: { 0x14, 0x7f68 }, fp@2405: { 0x18, 0x7fd9 }, fp@2405: { 0x1c, 0xf0ff }, fp@2405: { 0x1d, 0x3d9c }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x12, 0xf49f }, fp@2405: { 0x13, 0x070b }, fp@2405: { 0x1a, 0x05ad }, fp@2405: { 0x14, 0x94c0 }, fp@2405: fp@2405: /* fp@2405: * Tx Error Issue fp@2405: * Enhance line driver power fp@2405: */ fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x06, 0x5561 }, fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8332 }, fp@2405: { 0x06, 0x5561 }, fp@2405: fp@2405: /* fp@2405: * Can not link to 1Gbps with bad cable fp@2405: * Decrease SNR threshold form 21.07dB to 19.04dB fp@2405: */ fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x17, 0x0cc0 }, fp@2405: fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x0d, 0xf880 } fp@2405: }; fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); fp@2405: fp@2405: if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x05, 0x669a }, fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8330 }, fp@2405: { 0x06, 0x669a }, fp@2405: fp@2405: { 0x1f, 0x0002 } fp@2405: }; fp@2405: int val; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: val = rtl_readphy(tp, 0x0d); fp@2405: if ((val & 0x00ff) != 0x006c) { fp@2405: static const u32 set[] = { fp@2405: 0x0065, 0x0066, 0x0067, 0x0068, fp@2405: 0x0069, 0x006a, 0x006b, 0x006c fp@2405: }; fp@2405: int i; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: fp@2405: val &= 0xff00; fp@2405: for (i = 0; i < ARRAY_SIZE(set); i++) fp@2405: rtl_writephy(tp, 0x0d, val | set[i]); fp@2405: } fp@2405: } else { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x05, 0x2642 }, fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8330 }, fp@2405: { 0x06, 0x2642 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: /* Fine tune PLL performance */ fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); fp@2405: rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); fp@2405: fp@2405: /* Switching regulator Slew rate */ fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_patchphy(tp, 0x0f, 0x0017); fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x001b); fp@2405: fp@2405: rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x10, 0x0008 }, fp@2405: { 0x0d, 0x006c }, fp@2405: fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x0d, 0xf880 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x17, 0x0cc0 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x0b, 0xa4d8 }, fp@2405: { 0x09, 0x281c }, fp@2405: { 0x07, 0x2883 }, fp@2405: { 0x0a, 0x6b35 }, fp@2405: { 0x1d, 0x3da4 }, fp@2405: { 0x1c, 0xeffd }, fp@2405: { 0x14, 0x7f52 }, fp@2405: { 0x18, 0x7fc6 }, fp@2405: { 0x08, 0x0601 }, fp@2405: { 0x06, 0x4063 }, fp@2405: { 0x10, 0xf074 }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x13, 0x0789 }, fp@2405: { 0x12, 0xf4bd }, fp@2405: { 0x1a, 0x04fd }, fp@2405: { 0x14, 0x84b0 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x00, 0x9200 }, fp@2405: fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x01, 0x0340 }, fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x04, 0x4000 }, fp@2405: { 0x03, 0x1d21 }, fp@2405: { 0x02, 0x0c32 }, fp@2405: { 0x01, 0x0200 }, fp@2405: { 0x00, 0x5554 }, fp@2405: { 0x04, 0x4800 }, fp@2405: { 0x04, 0x4000 }, fp@2405: { 0x04, 0xf000 }, fp@2405: { 0x03, 0xdf01 }, fp@2405: { 0x02, 0xdf20 }, fp@2405: { 0x01, 0x101a }, fp@2405: { 0x00, 0xa0ff }, fp@2405: { 0x04, 0xf800 }, fp@2405: { 0x04, 0xf000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0007 }, fp@2405: { 0x1e, 0x0023 }, fp@2405: { 0x16, 0x0000 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x17, 0x0cc0 }, fp@2405: fp@2405: { 0x1f, 0x0007 }, fp@2405: { 0x1e, 0x002d }, fp@2405: { 0x18, 0x0040 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: rtl_patchphy(tp, 0x0d, 1 << 5); fp@2405: } fp@2405: fp@2405: static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: /* Enable Delay cap */ fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8b80 }, fp@2405: { 0x06, 0xc896 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Channel estimation fine tune */ fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x0b, 0x6c20 }, fp@2405: { 0x07, 0x2872 }, fp@2405: { 0x1c, 0xefff }, fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x14, 0x6420 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Update PFM & 10M TX idle timer */ fp@2405: { 0x1f, 0x0007 }, fp@2405: { 0x1e, 0x002f }, fp@2405: { 0x15, 0x1919 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0007 }, fp@2405: { 0x1e, 0x00ac }, fp@2405: { 0x18, 0x0006 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_apply_firmware(tp); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: /* DCO enable for 10M IDLE Power */ fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x0023); fp@2405: rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* For impedance matching */ fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* PHY auto speed down */ fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x002d); fp@2405: rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b86); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b85); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x0020); fp@2405: rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); fp@2405: rtl_writephy(tp, 0x1f, 0x0006); fp@2405: rtl_writephy(tp, 0x00, 0x5a00); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_writephy(tp, 0x0d, 0x0007); fp@2405: rtl_writephy(tp, 0x0e, 0x003c); fp@2405: rtl_writephy(tp, 0x0d, 0x4007); fp@2405: rtl_writephy(tp, 0x0e, 0x0000); fp@2405: rtl_writephy(tp, 0x0d, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: /* Enable Delay cap */ fp@2405: { 0x1f, 0x0004 }, fp@2405: { 0x1f, 0x0007 }, fp@2405: { 0x1e, 0x00ac }, fp@2405: { 0x18, 0x0006 }, fp@2405: { 0x1f, 0x0002 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Channel estimation fine tune */ fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x09, 0xa20f }, fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Green Setting */ fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8b5b }, fp@2405: { 0x06, 0x9222 }, fp@2405: { 0x05, 0x8b6d }, fp@2405: { 0x06, 0x8000 }, fp@2405: { 0x05, 0x8b76 }, fp@2405: { 0x06, 0x8000 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_apply_firmware(tp); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: /* For 4-corner performance improve */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b80); fp@2405: rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* PHY auto speed down */ fp@2405: rtl_writephy(tp, 0x1f, 0x0004); fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x002d); fp@2405: rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); fp@2405: fp@2405: /* improve 10M EEE waveform */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b86); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* Improve 2-pair detection performance */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b85); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* EEE setting */ fp@2405: rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, fp@2405: ERIAR_EXGMAC); fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b85); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); fp@2405: rtl_writephy(tp, 0x1f, 0x0004); fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x0020); fp@2405: rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); fp@2405: rtl_writephy(tp, 0x1f, 0x0002); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_writephy(tp, 0x0d, 0x0007); fp@2405: rtl_writephy(tp, 0x0e, 0x003c); fp@2405: rtl_writephy(tp, 0x0d, 0x4007); fp@2405: rtl_writephy(tp, 0x0e, 0x0000); fp@2405: rtl_writephy(tp, 0x0d, 0x0000); fp@2405: fp@2405: /* Green feature */ fp@2405: rtl_writephy(tp, 0x1f, 0x0003); fp@2405: rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); fp@2405: rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: /* Channel estimation fine tune */ fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x09, 0xa20f }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Modify green table for giga & fnet */ fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8b55 }, fp@2405: { 0x06, 0x0000 }, fp@2405: { 0x05, 0x8b5e }, fp@2405: { 0x06, 0x0000 }, fp@2405: { 0x05, 0x8b67 }, fp@2405: { 0x06, 0x0000 }, fp@2405: { 0x05, 0x8b70 }, fp@2405: { 0x06, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: { 0x1f, 0x0007 }, fp@2405: { 0x1e, 0x0078 }, fp@2405: { 0x17, 0x0000 }, fp@2405: { 0x19, 0x00fb }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Modify green table for 10M */ fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x05, 0x8b79 }, fp@2405: { 0x06, 0xaa00 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: /* Disable hiimpedance detection (RTCT) */ fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x01, 0x328a }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_apply_firmware(tp); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: fp@2405: /* For 4-corner performance improve */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b80); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* PHY auto speed down */ fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x002d); fp@2405: rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); fp@2405: fp@2405: /* Improve 10M EEE waveform */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b86); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* Improve 2-pair detection performance */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b85); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_apply_firmware(tp); fp@2405: fp@2405: /* For 4-corner performance improve */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b80); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: fp@2405: /* PHY auto speed down */ fp@2405: rtl_writephy(tp, 0x1f, 0x0007); fp@2405: rtl_writephy(tp, 0x1e, 0x002d); fp@2405: rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); fp@2405: fp@2405: /* Improve 10M EEE waveform */ fp@2405: rtl_writephy(tp, 0x1f, 0x0005); fp@2405: rtl_writephy(tp, 0x05, 0x8b86); fp@2405: rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: } fp@2405: fp@2405: static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0003 }, fp@2405: { 0x08, 0x441d }, fp@2405: { 0x01, 0x9100 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_patchphy(tp, 0x11, 1 << 12); fp@2405: rtl_patchphy(tp, 0x19, 1 << 13); fp@2405: rtl_patchphy(tp, 0x10, 1 << 15); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) fp@2405: { fp@2405: static const struct phy_reg phy_reg_init[] = { fp@2405: { 0x1f, 0x0005 }, fp@2405: { 0x1a, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0004 }, fp@2405: { 0x1c, 0x0000 }, fp@2405: { 0x1f, 0x0000 }, fp@2405: fp@2405: { 0x1f, 0x0001 }, fp@2405: { 0x15, 0x7701 }, fp@2405: { 0x1f, 0x0000 } fp@2405: }; fp@2405: fp@2405: /* Disable ALDPS before ram code */ fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_writephy(tp, 0x18, 0x0310); fp@2405: msleep(100); fp@2405: fp@2405: rtl_apply_firmware(tp); fp@2405: fp@2405: rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2405: } fp@2405: fp@2405: static void rtl_hw_phy_config(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: rtl8169_print_mac_version(tp); fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_01: fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_02: fp@2405: case RTL_GIGA_MAC_VER_03: fp@2405: rtl8169s_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_04: fp@2405: rtl8169sb_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_05: fp@2405: rtl8169scd_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_06: fp@2405: rtl8169sce_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_07: fp@2405: case RTL_GIGA_MAC_VER_08: fp@2405: case RTL_GIGA_MAC_VER_09: fp@2405: rtl8102e_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: rtl8168bb_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: rtl8168bef_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: rtl8168bef_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_18: fp@2405: rtl8168cp_1_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: rtl8168c_1_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: rtl8168c_2_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_21: fp@2405: rtl8168c_3_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: rtl8168c_4_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: rtl8168cp_2_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: rtl8168d_1_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: rtl8168d_2_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: rtl8168d_3_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: rtl8168d_4_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_29: fp@2405: case RTL_GIGA_MAC_VER_30: fp@2405: rtl8105e_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: /* None. */ fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: rtl8168e_1_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_34: fp@2405: rtl8168e_2_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_35: fp@2405: rtl8168f_1_hw_phy_config(tp); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_36: fp@2405: rtl8168f_2_hw_phy_config(tp); fp@2405: break; fp@2405: fp@2405: default: fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8169_phy_timer(unsigned long __opaque) fp@2405: { fp@2405: struct net_device *dev = (struct net_device *)__opaque; fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct timer_list *timer = &tp->timer; fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: unsigned long timeout = RTL8169_PHY_TIMEOUT; fp@2405: fp@2405: assert(tp->mac_version > RTL_GIGA_MAC_VER_01); fp@2405: fp@2405: if (!tp->ecdev) fp@2405: spin_lock_irq(&tp->lock); fp@2405: fp@2405: if (tp->phy_reset_pending(tp)) { fp@2405: /* fp@2405: * A busy loop could burn quite a few cycles on nowadays CPU. fp@2405: * Let's delay the execution of the timer for a few ticks. fp@2405: */ fp@2405: timeout = HZ/10; fp@2405: goto out_mod_timer; fp@2405: } fp@2405: fp@2405: if (tp->link_ok(ioaddr)) fp@2405: goto out_unlock; fp@2405: fp@2405: netif_warn(tp, link, dev, "PHY reset until link up\n"); fp@2405: fp@2405: tp->phy_reset_enable(tp); fp@2405: fp@2405: out_mod_timer: fp@2405: if (!tp->ecdev) fp@2405: mod_timer(timer, jiffies + timeout); fp@2405: out_unlock: fp@2405: if (!tp->ecdev) fp@2405: spin_unlock_irq(&tp->lock); fp@2405: } fp@2405: fp@2405: #ifdef CONFIG_NET_POLL_CONTROLLER fp@2405: /* fp@2405: * Polling 'interrupt' - used by things like netconsole to send skbs fp@2405: * without having to re-enable interrupts. It's not called while fp@2405: * the interrupt routine is executing. fp@2405: */ fp@2405: static void rtl8169_netpoll(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: disable_irq(pdev->irq); fp@2405: rtl8169_interrupt(pdev->irq, dev); fp@2405: enable_irq(pdev->irq); fp@2405: } fp@2405: #endif fp@2405: fp@2405: static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, fp@2405: void __iomem *ioaddr) fp@2405: { fp@2405: iounmap(ioaddr); fp@2405: pci_release_regions(pdev); fp@2405: pci_clear_mwi(pdev); fp@2405: pci_disable_device(pdev); fp@2405: free_netdev(dev); fp@2405: } fp@2405: fp@2405: static void rtl8169_phy_reset(struct net_device *dev, fp@2405: struct rtl8169_private *tp) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: tp->phy_reset_enable(tp); fp@2405: for (i = 0; i < 100; i++) { fp@2405: if (!tp->phy_reset_pending(tp)) fp@2405: return; fp@2405: msleep(1); fp@2405: } fp@2405: netif_err(tp, link, dev, "PHY reset failed\n"); fp@2405: } fp@2405: fp@2405: static bool rtl_tbi_enabled(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: return (tp->mac_version == RTL_GIGA_MAC_VER_01) && fp@2405: (RTL_R8(PHYstatus) & TBI_Enable); fp@2405: } fp@2405: fp@2405: static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: rtl_hw_phy_config(dev); fp@2405: fp@2405: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { fp@2405: dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); fp@2405: RTL_W8(0x82, 0x01); fp@2405: } fp@2405: fp@2405: pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); fp@2405: fp@2405: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) fp@2405: pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_02) { fp@2405: dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); fp@2405: RTL_W8(0x82, 0x01); fp@2405: dprintk("Set PHY Reg 0x0bh = 0x00h\n"); fp@2405: rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 fp@2405: } fp@2405: fp@2405: rtl8169_phy_reset(dev, tp); fp@2405: fp@2405: rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, fp@2405: ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | fp@2405: ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | fp@2405: (tp->mii.supports_gmii ? fp@2405: ADVERTISED_1000baseT_Half | fp@2405: ADVERTISED_1000baseT_Full : 0)); fp@2405: fp@2405: if (rtl_tbi_enabled(tp)) fp@2405: netif_info(tp, link, dev, "TBI auto-negotiating\n"); fp@2405: } fp@2405: fp@2405: static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: u32 high; fp@2405: u32 low; fp@2405: fp@2405: low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); fp@2405: high = addr[4] | (addr[5] << 8); fp@2405: fp@2405: spin_lock_irq(&tp->lock); fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: fp@2405: RTL_W32(MAC4, high); fp@2405: RTL_R32(MAC4); fp@2405: fp@2405: RTL_W32(MAC0, low); fp@2405: RTL_R32(MAC0); fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_34) { fp@2405: const struct exgmac_reg e[] = { fp@2405: { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, fp@2405: { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, fp@2405: { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, fp@2405: { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | fp@2405: low >> 16 }, fp@2405: }; fp@2405: fp@2405: rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); fp@2405: } fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: fp@2405: spin_unlock_irq(&tp->lock); fp@2405: } fp@2405: fp@2405: static int rtl_set_mac_address(struct net_device *dev, void *p) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct sockaddr *addr = p; fp@2405: fp@2405: if (!is_valid_ether_addr(addr->sa_data)) fp@2405: return -EADDRNOTAVAIL; fp@2405: fp@2405: memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); fp@2405: fp@2405: rtl_rar_set(tp, dev->dev_addr); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct mii_ioctl_data *data = if_mii(ifr); fp@2405: fp@2405: return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; fp@2405: } fp@2405: fp@2405: static int rtl_xmii_ioctl(struct rtl8169_private *tp, fp@2405: struct mii_ioctl_data *data, int cmd) fp@2405: { fp@2405: switch (cmd) { fp@2405: case SIOCGMIIPHY: fp@2405: data->phy_id = 32; /* Internal PHY */ fp@2405: return 0; fp@2405: fp@2405: case SIOCGMIIREG: fp@2405: data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); fp@2405: return 0; fp@2405: fp@2405: case SIOCSMIIREG: fp@2405: rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); fp@2405: return 0; fp@2405: } fp@2405: return -EOPNOTSUPP; fp@2405: } fp@2405: fp@2405: static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) fp@2405: { fp@2405: return -EOPNOTSUPP; fp@2405: } fp@2405: fp@2405: static const struct rtl_cfg_info { fp@2405: void (*hw_start)(struct net_device *); fp@2405: unsigned int region; fp@2405: unsigned int align; fp@2405: u16 intr_event; fp@2405: u16 napi_event; fp@2405: unsigned features; fp@2405: u8 default_ver; fp@2405: } rtl_cfg_infos [] = { fp@2405: [RTL_CFG_0] = { fp@2405: .hw_start = rtl_hw_start_8169, fp@2405: .region = 1, fp@2405: .align = 0, fp@2405: .intr_event = SYSErr | LinkChg | RxOverflow | fp@2405: RxFIFOOver | TxErr | TxOK | RxOK | RxErr, fp@2405: .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, fp@2405: .features = RTL_FEATURE_GMII, fp@2405: .default_ver = RTL_GIGA_MAC_VER_01, fp@2405: }, fp@2405: [RTL_CFG_1] = { fp@2405: .hw_start = rtl_hw_start_8168, fp@2405: .region = 2, fp@2405: .align = 8, fp@2405: .intr_event = SYSErr | LinkChg | RxOverflow | fp@2405: TxErr | TxOK | RxOK | RxErr, fp@2405: .napi_event = TxErr | TxOK | RxOK | RxOverflow, fp@2405: .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, fp@2405: .default_ver = RTL_GIGA_MAC_VER_11, fp@2405: }, fp@2405: [RTL_CFG_2] = { fp@2405: .hw_start = rtl_hw_start_8101, fp@2405: .region = 2, fp@2405: .align = 8, fp@2405: .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | fp@2405: RxFIFOOver | TxErr | TxOK | RxOK | RxErr, fp@2405: .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, fp@2405: .features = RTL_FEATURE_MSI, fp@2405: .default_ver = RTL_GIGA_MAC_VER_13, fp@2405: } fp@2405: }; fp@2405: fp@2405: /* Cfg9346_Unlock assumed. */ fp@2405: static unsigned rtl_try_msi(struct rtl8169_private *tp, fp@2405: const struct rtl_cfg_info *cfg) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: unsigned msi = 0; fp@2405: u8 cfg2; fp@2405: fp@2405: cfg2 = RTL_R8(Config2) & ~MSIEnable; fp@2405: if (cfg->features & RTL_FEATURE_MSI) { fp@2405: if (pci_enable_msi(tp->pci_dev)) { fp@2405: netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); fp@2405: } else { fp@2405: cfg2 |= MSIEnable; fp@2405: msi = RTL_FEATURE_MSI; fp@2405: } fp@2405: } fp@2405: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) fp@2405: RTL_W8(Config2, cfg2); fp@2405: return msi; fp@2405: } fp@2405: fp@2405: static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) fp@2405: { fp@2405: if (tp->features & RTL_FEATURE_MSI) { fp@2405: pci_disable_msi(pdev); fp@2405: tp->features &= ~RTL_FEATURE_MSI; fp@2405: } fp@2405: } fp@2405: fp@2405: static const struct net_device_ops rtl8169_netdev_ops = { fp@2405: .ndo_open = rtl8169_open, fp@2405: .ndo_stop = rtl8169_close, fp@2405: .ndo_get_stats = rtl8169_get_stats, fp@2405: .ndo_start_xmit = rtl8169_start_xmit, fp@2405: .ndo_tx_timeout = rtl8169_tx_timeout, fp@2405: .ndo_validate_addr = eth_validate_addr, fp@2405: .ndo_change_mtu = rtl8169_change_mtu, fp@2405: .ndo_fix_features = rtl8169_fix_features, fp@2405: .ndo_set_features = rtl8169_set_features, fp@2405: .ndo_set_mac_address = rtl_set_mac_address, fp@2405: .ndo_do_ioctl = rtl8169_ioctl, fp@2405: .ndo_set_rx_mode = rtl_set_rx_mode, fp@2405: #ifdef CONFIG_NET_POLL_CONTROLLER fp@2405: .ndo_poll_controller = rtl8169_netpoll, fp@2405: #endif fp@2405: fp@2405: }; fp@2405: fp@2405: static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) fp@2405: { fp@2405: struct mdio_ops *ops = &tp->mdio_ops; fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: ops->write = r8168dp_1_mdio_write; fp@2405: ops->read = r8168dp_1_mdio_read; fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: ops->write = r8168dp_2_mdio_write; fp@2405: ops->read = r8168dp_2_mdio_read; fp@2405: break; fp@2405: default: fp@2405: ops->write = r8169_mdio_write; fp@2405: ops->read = r8169_mdio_read; fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_29: fp@2405: case RTL_GIGA_MAC_VER_30: fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: case RTL_GIGA_MAC_VER_34: fp@2405: RTL_W32(RxConfig, RTL_R32(RxConfig) | fp@2405: AcceptBroadcast | AcceptMulticast | AcceptMyPhys); fp@2405: break; fp@2405: default: fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) fp@2405: { fp@2405: if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) fp@2405: return false; fp@2405: fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_writephy(tp, MII_BMCR, 0x0000); fp@2405: fp@2405: rtl_wol_suspend_quirk(tp); fp@2405: fp@2405: return true; fp@2405: } fp@2405: fp@2405: static void r810x_phy_power_down(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); fp@2405: } fp@2405: fp@2405: static void r810x_phy_power_up(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); fp@2405: } fp@2405: fp@2405: static void r810x_pll_power_down(struct rtl8169_private *tp) fp@2405: { fp@2405: if (rtl_wol_pll_power_down(tp)) fp@2405: return; fp@2405: fp@2405: r810x_phy_power_down(tp); fp@2405: } fp@2405: fp@2405: static void r810x_pll_power_up(struct rtl8169_private *tp) fp@2405: { fp@2405: r810x_phy_power_up(tp); fp@2405: } fp@2405: fp@2405: static void r8168_phy_power_up(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: case RTL_GIGA_MAC_VER_18: fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: case RTL_GIGA_MAC_VER_21: fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: rtl_writephy(tp, 0x0e, 0x0000); fp@2405: break; fp@2405: default: fp@2405: break; fp@2405: } fp@2405: rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); fp@2405: } fp@2405: fp@2405: static void r8168_phy_power_down(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_writephy(tp, 0x1f, 0x0000); fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: case RTL_GIGA_MAC_VER_18: fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: case RTL_GIGA_MAC_VER_21: fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: rtl_writephy(tp, 0x0e, 0x0200); fp@2405: default: fp@2405: rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void r8168_pll_power_down(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_28 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_31) && fp@2405: r8168dp_check_dash(tp)) { fp@2405: return; fp@2405: } fp@2405: fp@2405: if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_24) && fp@2405: (RTL_R16(CPlusCmd) & ASF)) { fp@2405: return; fp@2405: } fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_32 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_33) fp@2405: rtl_ephy_write(ioaddr, 0x19, 0xff64); fp@2405: fp@2405: if (rtl_wol_pll_power_down(tp)) fp@2405: return; fp@2405: fp@2405: r8168_phy_power_down(tp); fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void r8168_pll_power_up(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_28 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_31) && fp@2405: r8168dp_check_dash(tp)) { fp@2405: return; fp@2405: } fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); fp@2405: break; fp@2405: } fp@2405: fp@2405: r8168_phy_power_up(tp); fp@2405: } fp@2405: fp@2405: static void rtl_generic_op(struct rtl8169_private *tp, fp@2405: void (*op)(struct rtl8169_private *)) fp@2405: { fp@2405: if (op) fp@2405: op(tp); fp@2405: } fp@2405: fp@2405: static void rtl_pll_power_down(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_generic_op(tp, tp->pll_power_ops.down); fp@2405: } fp@2405: fp@2405: static void rtl_pll_power_up(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_generic_op(tp, tp->pll_power_ops.up); fp@2405: } fp@2405: fp@2405: static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) fp@2405: { fp@2405: struct pll_power_ops *ops = &tp->pll_power_ops; fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_07: fp@2405: case RTL_GIGA_MAC_VER_08: fp@2405: case RTL_GIGA_MAC_VER_09: fp@2405: case RTL_GIGA_MAC_VER_10: fp@2405: case RTL_GIGA_MAC_VER_16: fp@2405: case RTL_GIGA_MAC_VER_29: fp@2405: case RTL_GIGA_MAC_VER_30: fp@2405: ops->down = r810x_pll_power_down; fp@2405: ops->up = r810x_pll_power_up; fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: case RTL_GIGA_MAC_VER_18: fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: case RTL_GIGA_MAC_VER_21: fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: case RTL_GIGA_MAC_VER_34: fp@2405: case RTL_GIGA_MAC_VER_35: fp@2405: case RTL_GIGA_MAC_VER_36: fp@2405: ops->down = r8168_pll_power_down; fp@2405: ops->up = r8168_pll_power_up; fp@2405: break; fp@2405: fp@2405: default: fp@2405: ops->down = NULL; fp@2405: ops->up = NULL; fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_init_rxcfg(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_01: fp@2405: case RTL_GIGA_MAC_VER_02: fp@2405: case RTL_GIGA_MAC_VER_03: fp@2405: case RTL_GIGA_MAC_VER_04: fp@2405: case RTL_GIGA_MAC_VER_05: fp@2405: case RTL_GIGA_MAC_VER_06: fp@2405: case RTL_GIGA_MAC_VER_10: fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_13: fp@2405: case RTL_GIGA_MAC_VER_14: fp@2405: case RTL_GIGA_MAC_VER_15: fp@2405: case RTL_GIGA_MAC_VER_16: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_18: fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: case RTL_GIGA_MAC_VER_21: fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); fp@2405: break; fp@2405: default: fp@2405: RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) fp@2405: { fp@2405: tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; fp@2405: } fp@2405: fp@2405: static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: rtl_generic_op(tp, tp->jumbo_ops.enable); fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: } fp@2405: fp@2405: static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: rtl_generic_op(tp, tp->jumbo_ops.disable); fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: } fp@2405: fp@2405: static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); fp@2405: RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); fp@2405: rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); fp@2405: } fp@2405: fp@2405: static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); fp@2405: RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); fp@2405: rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: } fp@2405: fp@2405: static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); fp@2405: } fp@2405: fp@2405: static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); fp@2405: } fp@2405: fp@2405: static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, 0x3f); fp@2405: RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); fp@2405: RTL_W8(Config4, RTL_R8(Config4) | 0x01); fp@2405: pci_write_config_byte(pdev, 0x79, 0x20); fp@2405: } fp@2405: fp@2405: static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, 0x0c); fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); fp@2405: RTL_W8(Config4, RTL_R8(Config4) & ~0x01); fp@2405: pci_write_config_byte(pdev, 0x79, 0x50); fp@2405: } fp@2405: fp@2405: static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_tx_performance_tweak(tp->pci_dev, fp@2405: (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); fp@2405: } fp@2405: fp@2405: static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl_tx_performance_tweak(tp->pci_dev, fp@2405: (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); fp@2405: } fp@2405: fp@2405: static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: r8168b_0_hw_jumbo_enable(tp); fp@2405: fp@2405: RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); fp@2405: } fp@2405: fp@2405: static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: r8168b_0_hw_jumbo_disable(tp); fp@2405: fp@2405: RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); fp@2405: } fp@2405: fp@2405: static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) fp@2405: { fp@2405: struct jumbo_ops *ops = &tp->jumbo_ops; fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: ops->disable = r8168b_0_hw_jumbo_disable; fp@2405: ops->enable = r8168b_0_hw_jumbo_enable; fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: ops->disable = r8168b_1_hw_jumbo_disable; fp@2405: ops->enable = r8168b_1_hw_jumbo_enable; fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: ops->disable = r8168c_hw_jumbo_disable; fp@2405: ops->enable = r8168c_hw_jumbo_enable; fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: ops->disable = r8168dp_hw_jumbo_disable; fp@2405: ops->enable = r8168dp_hw_jumbo_enable; fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: case RTL_GIGA_MAC_VER_34: fp@2405: ops->disable = r8168e_hw_jumbo_disable; fp@2405: ops->enable = r8168e_hw_jumbo_enable; fp@2405: break; fp@2405: fp@2405: /* fp@2405: * No action needed for jumbo frames with 8169. fp@2405: * No jumbo for 810x at all. fp@2405: */ fp@2405: default: fp@2405: ops->disable = NULL; fp@2405: ops->enable = NULL; fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_hw_reset(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int i; fp@2405: fp@2405: /* Soft reset the chip. */ fp@2405: RTL_W8(ChipCmd, CmdReset); fp@2405: fp@2405: /* Check that the chip has finished the reset. */ fp@2405: for (i = 0; i < 100; i++) { fp@2405: if ((RTL_R8(ChipCmd) & CmdReset) == 0) fp@2405: break; fp@2405: udelay(100); fp@2405: } fp@2405: } fp@2405: fp@2405: static int __devinit fp@2405: rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) fp@2405: { fp@2405: const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; fp@2405: const unsigned int region = cfg->region; fp@2405: struct rtl8169_private *tp; fp@2405: struct mii_if_info *mii; fp@2405: struct net_device *dev; fp@2405: void __iomem *ioaddr; fp@2405: int chipset, i; fp@2405: int rc; fp@2405: fp@2405: if (netif_msg_drv(&debug)) { fp@2405: printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", fp@2405: MODULENAME, RTL8169_VERSION); fp@2405: } fp@2405: fp@2405: dev = alloc_etherdev(sizeof (*tp)); fp@2405: if (!dev) { fp@2405: if (netif_msg_drv(&debug)) fp@2405: dev_err(&pdev->dev, "unable to alloc new ethernet\n"); fp@2405: rc = -ENOMEM; fp@2405: goto out; fp@2405: } fp@2405: fp@2405: SET_NETDEV_DEV(dev, &pdev->dev); fp@2405: dev->netdev_ops = &rtl8169_netdev_ops; fp@2405: tp = netdev_priv(dev); fp@2405: tp->dev = dev; fp@2405: tp->pci_dev = pdev; fp@2405: tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); fp@2405: fp@2405: mii = &tp->mii; fp@2405: mii->dev = dev; fp@2405: mii->mdio_read = rtl_mdio_read; fp@2405: mii->mdio_write = rtl_mdio_write; fp@2405: mii->phy_id_mask = 0x1f; fp@2405: mii->reg_num_mask = 0x1f; fp@2405: mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); fp@2405: fp@2405: /* disable ASPM completely as that cause random device stop working fp@2405: * problems as well as full system hangs for some PCIe devices users */ fp@2405: pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | fp@2405: PCIE_LINK_STATE_CLKPM); fp@2405: fp@2405: /* enable device (incl. PCI PM wakeup and hotplug setup) */ fp@2405: rc = pci_enable_device(pdev); fp@2405: if (rc < 0) { fp@2405: netif_err(tp, probe, dev, "enable failure\n"); fp@2405: goto err_out_free_dev_1; fp@2405: } fp@2405: fp@2405: if (pci_set_mwi(pdev) < 0) fp@2405: netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); fp@2405: fp@2405: /* make sure PCI base addr 1 is MMIO */ fp@2405: if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { fp@2405: netif_err(tp, probe, dev, fp@2405: "region #%d not an MMIO resource, aborting\n", fp@2405: region); fp@2405: rc = -ENODEV; fp@2405: goto err_out_mwi_2; fp@2405: } fp@2405: fp@2405: /* check for weird/broken PCI region reporting */ fp@2405: if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { fp@2405: netif_err(tp, probe, dev, fp@2405: "Invalid PCI region size(s), aborting\n"); fp@2405: rc = -ENODEV; fp@2405: goto err_out_mwi_2; fp@2405: } fp@2405: fp@2405: rc = pci_request_regions(pdev, MODULENAME); fp@2405: if (rc < 0) { fp@2405: netif_err(tp, probe, dev, "could not request regions\n"); fp@2405: goto err_out_mwi_2; fp@2405: } fp@2405: fp@2405: tp->cp_cmd = RxChkSum; fp@2405: fp@2405: if ((sizeof(dma_addr_t) > 4) && fp@2405: !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { fp@2405: tp->cp_cmd |= PCIDAC; fp@2405: dev->features |= NETIF_F_HIGHDMA; fp@2405: } else { fp@2405: rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); fp@2405: if (rc < 0) { fp@2405: netif_err(tp, probe, dev, "DMA configuration failed\n"); fp@2405: goto err_out_free_res_3; fp@2405: } fp@2405: } fp@2405: fp@2405: /* ioremap MMIO region */ fp@2405: ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); fp@2405: if (!ioaddr) { fp@2405: netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); fp@2405: rc = -EIO; fp@2405: goto err_out_free_res_3; fp@2405: } fp@2405: tp->mmio_addr = ioaddr; fp@2405: fp@2405: if (!pci_is_pcie(pdev)) fp@2405: netif_info(tp, probe, dev, "not PCI Express\n"); fp@2405: fp@2405: /* Identify chip attached to board */ fp@2405: rtl8169_get_mac_version(tp, dev, cfg->default_ver); fp@2405: fp@2405: rtl_init_rxcfg(tp); fp@2405: fp@2405: RTL_W16(IntrMask, 0x0000); fp@2405: fp@2405: rtl_hw_reset(tp); fp@2405: fp@2405: RTL_W16(IntrStatus, 0xffff); fp@2405: fp@2405: pci_set_master(pdev); fp@2405: fp@2405: /* fp@2405: * Pretend we are using VLANs; This bypasses a nasty bug where fp@2405: * Interrupts stop flowing on high load on 8110SCd controllers. fp@2405: */ fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_05) fp@2405: tp->cp_cmd |= RxVlan; fp@2405: fp@2405: rtl_init_mdio_ops(tp); fp@2405: rtl_init_pll_power_ops(tp); fp@2405: rtl_init_jumbo_ops(tp); fp@2405: fp@2405: rtl8169_print_mac_version(tp); fp@2405: fp@2405: chipset = tp->mac_version; fp@2405: tp->txd_version = rtl_chip_infos[chipset].txd_version; fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: RTL_W8(Config1, RTL_R8(Config1) | PMEnable); fp@2405: RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); fp@2405: if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) fp@2405: tp->features |= RTL_FEATURE_WOL; fp@2405: if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) fp@2405: tp->features |= RTL_FEATURE_WOL; fp@2405: tp->features |= rtl_try_msi(tp, cfg); fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: fp@2405: if (rtl_tbi_enabled(tp)) { fp@2405: tp->set_speed = rtl8169_set_speed_tbi; fp@2405: tp->get_settings = rtl8169_gset_tbi; fp@2405: tp->phy_reset_enable = rtl8169_tbi_reset_enable; fp@2405: tp->phy_reset_pending = rtl8169_tbi_reset_pending; fp@2405: tp->link_ok = rtl8169_tbi_link_ok; fp@2405: tp->do_ioctl = rtl_tbi_ioctl; fp@2405: } else { fp@2405: tp->set_speed = rtl8169_set_speed_xmii; fp@2405: tp->get_settings = rtl8169_gset_xmii; fp@2405: tp->phy_reset_enable = rtl8169_xmii_reset_enable; fp@2405: tp->phy_reset_pending = rtl8169_xmii_reset_pending; fp@2405: tp->link_ok = rtl8169_xmii_link_ok; fp@2405: tp->do_ioctl = rtl_xmii_ioctl; fp@2405: } fp@2405: fp@2405: spin_lock_init(&tp->lock); fp@2405: fp@2405: /* Get MAC address */ fp@2405: for (i = 0; i < MAC_ADDR_LEN; i++) fp@2405: dev->dev_addr[i] = RTL_R8(MAC0 + i); fp@2405: memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); fp@2405: fp@2405: SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); fp@2405: dev->watchdog_timeo = RTL8169_TX_TIMEOUT; fp@2405: dev->irq = pdev->irq; fp@2405: dev->base_addr = (unsigned long) ioaddr; fp@2405: fp@2405: netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); fp@2405: fp@2405: /* don't enable SG, IP_CSUM and TSO by default - it might not work fp@2405: * properly for all devices */ fp@2405: dev->features |= NETIF_F_RXCSUM | fp@2405: NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; fp@2405: fp@2405: dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | fp@2405: NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; fp@2405: dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | fp@2405: NETIF_F_HIGHDMA; fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_05) fp@2405: /* 8110SCd requires hardware Rx VLAN - disallow toggling */ fp@2405: dev->hw_features &= ~NETIF_F_HW_VLAN_RX; fp@2405: fp@2405: tp->intr_mask = 0xffff; fp@2405: tp->hw_start = cfg->hw_start; fp@2405: tp->intr_event = cfg->intr_event; fp@2405: tp->napi_event = cfg->napi_event; fp@2405: fp@2405: tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? fp@2405: ~(RxBOVF | RxFOVF) : ~0; fp@2405: fp@2405: init_timer(&tp->timer); fp@2405: tp->timer.data = (unsigned long) dev; fp@2405: tp->timer.function = rtl8169_phy_timer; fp@2405: fp@2405: tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; fp@2405: fp@2405: // offer device to EtherCAT master module fp@2405: tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); fp@2405: tp->ec_watchdog_jiffies = jiffies; fp@2405: fp@2405: if (!tp->ecdev) { fp@2405: rc = register_netdev(dev); fp@2405: if (rc < 0) fp@2405: goto err_out_msi_4; fp@2405: } fp@2405: fp@2405: pci_set_drvdata(pdev, dev); fp@2405: fp@2405: netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", fp@2405: rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr, fp@2405: (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); fp@2405: if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { fp@2405: netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " fp@2405: "tx checksumming: %s]\n", fp@2405: rtl_chip_infos[chipset].jumbo_max, fp@2405: rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); fp@2405: } fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_27 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_28 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_31) { fp@2405: rtl8168_driver_start(tp); fp@2405: } fp@2405: fp@2405: device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); fp@2405: fp@2405: if (pci_dev_run_wake(pdev)) fp@2405: pm_runtime_put_noidle(&pdev->dev); fp@2405: fp@2582: if (tp->ecdev) { fp@2582: rc = ecdev_open(tp->ecdev); fp@2582: if (rc) { fp@2582: ecdev_withdraw(tp->ecdev); fp@2582: goto err_out_msi_4; fp@2582: } fp@2582: } fp@2582: else { fp@2582: netif_carrier_off(dev); fp@2405: } fp@2405: fp@2405: out: fp@2405: return rc; fp@2405: fp@2405: err_out_msi_4: fp@2405: rtl_disable_msi(pdev, tp); fp@2405: iounmap(ioaddr); fp@2405: err_out_free_res_3: fp@2405: pci_release_regions(pdev); fp@2405: err_out_mwi_2: fp@2405: pci_clear_mwi(pdev); fp@2405: pci_disable_device(pdev); fp@2405: err_out_free_dev_1: fp@2405: free_netdev(dev); fp@2405: goto out; fp@2405: } fp@2405: fp@2405: static void __devexit rtl8169_remove_one(struct pci_dev *pdev) fp@2405: { fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_27 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_28 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_31) { fp@2405: rtl8168_driver_stop(tp); fp@2405: } fp@2405: fp@2405: cancel_delayed_work_sync(&tp->task); fp@2405: fp@2405: if (tp->ecdev) { fp@2405: ecdev_close(tp->ecdev); fp@2405: ecdev_withdraw(tp->ecdev); fp@2405: } else { fp@2405: unregister_netdev(dev); fp@2405: } fp@2405: fp@2405: rtl_release_firmware(tp); fp@2405: fp@2405: if (pci_dev_run_wake(pdev)) fp@2405: pm_runtime_get_noresume(&pdev->dev); fp@2405: fp@2405: /* restore original MAC address */ fp@2405: rtl_rar_set(tp, dev->perm_addr); fp@2405: fp@2405: rtl_disable_msi(pdev, tp); fp@2405: rtl8169_release_board(pdev, dev, tp->mmio_addr); fp@2405: pci_set_drvdata(pdev, NULL); fp@2405: } fp@2405: fp@2405: static void rtl_request_uncached_firmware(struct rtl8169_private *tp) fp@2405: { fp@2405: struct rtl_fw *rtl_fw; fp@2405: const char *name; fp@2405: int rc = -ENOMEM; fp@2405: fp@2405: name = rtl_lookup_firmware_name(tp); fp@2405: if (!name) fp@2405: goto out_no_firmware; fp@2405: fp@2405: rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); fp@2405: if (!rtl_fw) fp@2405: goto err_warn; fp@2405: fp@2405: rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); fp@2405: if (rc < 0) fp@2405: goto err_free; fp@2405: fp@2405: rc = rtl_check_firmware(tp, rtl_fw); fp@2405: if (rc < 0) fp@2405: goto err_release_firmware; fp@2405: fp@2405: tp->rtl_fw = rtl_fw; fp@2405: out: fp@2405: return; fp@2405: fp@2405: err_release_firmware: fp@2405: release_firmware(rtl_fw->fw); fp@2405: err_free: fp@2405: kfree(rtl_fw); fp@2405: err_warn: fp@2405: netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", fp@2405: name, rc); fp@2405: out_no_firmware: fp@2405: tp->rtl_fw = NULL; fp@2405: goto out; fp@2405: } fp@2405: fp@2405: static void rtl_request_firmware(struct rtl8169_private *tp) fp@2405: { fp@2405: if (IS_ERR(tp->rtl_fw)) fp@2405: rtl_request_uncached_firmware(tp); fp@2405: } fp@2405: fp@2405: static int rtl8169_open(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: int retval = -ENOMEM; fp@2405: fp@2405: pm_runtime_get_sync(&pdev->dev); fp@2405: fp@2405: /* fp@2405: * Rx and Tx desscriptors needs 256 bytes alignment. fp@2405: * dma_alloc_coherent provides more. fp@2405: */ fp@2405: tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, fp@2405: &tp->TxPhyAddr, GFP_KERNEL); fp@2405: if (!tp->TxDescArray) fp@2405: goto err_pm_runtime_put; fp@2405: fp@2405: tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, fp@2405: &tp->RxPhyAddr, GFP_KERNEL); fp@2405: if (!tp->RxDescArray) fp@2405: goto err_free_tx_0; fp@2405: fp@2405: retval = rtl8169_init_ring(dev); fp@2405: if (retval < 0) fp@2405: goto err_free_rx_1; fp@2405: fp@2405: INIT_DELAYED_WORK(&tp->task, NULL); fp@2405: fp@2405: smp_mb(); fp@2405: fp@2405: rtl_request_firmware(tp); fp@2405: if (!tp->ecdev) { fp@2405: fp@2405: retval = request_irq(dev->irq, rtl8169_interrupt, fp@2405: (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, fp@2405: dev->name, dev); fp@2405: if (retval < 0) fp@2405: goto err_release_fw_2; fp@2405: fp@2405: napi_enable(&tp->napi); fp@2405: } fp@2405: fp@2405: rtl8169_init_phy(dev, tp); fp@2405: fp@2405: rtl8169_set_features(dev, dev->features); fp@2405: fp@2405: rtl_pll_power_up(tp); fp@2405: fp@2405: rtl_hw_start(dev); fp@2405: fp@2405: tp->saved_wolopts = 0; fp@2405: pm_runtime_put_noidle(&pdev->dev); fp@2405: fp@2405: rtl8169_check_link_status(dev, tp, ioaddr); fp@2405: out: fp@2405: return retval; fp@2405: fp@2405: err_release_fw_2: fp@2405: rtl_release_firmware(tp); fp@2405: rtl8169_rx_clear(tp); fp@2405: err_free_rx_1: fp@2405: dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, fp@2405: tp->RxPhyAddr); fp@2405: tp->RxDescArray = NULL; fp@2405: err_free_tx_0: fp@2405: dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, fp@2405: tp->TxPhyAddr); fp@2405: tp->TxDescArray = NULL; fp@2405: err_pm_runtime_put: fp@2405: pm_runtime_put_noidle(&pdev->dev); fp@2405: goto out; fp@2405: } fp@2405: fp@2405: static void rtl_rx_close(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); fp@2405: } fp@2405: fp@2405: static void rtl8169_hw_reset(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: /* Disable interrupts */ fp@2405: rtl8169_irq_mask_and_ack(tp); fp@2405: fp@2405: rtl_rx_close(tp); fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_27 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_28 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_31) { fp@2405: while (RTL_R8(TxPoll) & NPQ) fp@2405: udelay(20); fp@2405: } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_35 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_36) { fp@2405: RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); fp@2405: while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) fp@2405: udelay(100); fp@2405: } else { fp@2405: RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); fp@2405: udelay(100); fp@2405: } fp@2405: fp@2405: rtl_hw_reset(tp); fp@2405: } fp@2405: fp@2405: static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: /* Set DMA burst size and Interframe Gap Time */ fp@2405: RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | fp@2405: (InterFrameGap << TxInterFrameGapShift)); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: tp->hw_start(dev); fp@2405: fp@2405: if (!tp->ecdev) fp@2405: netif_start_queue(dev); fp@2405: } fp@2405: fp@2405: static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, fp@2405: void __iomem *ioaddr) fp@2405: { fp@2405: /* fp@2405: * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh fp@2405: * register to be written before TxDescAddrLow to work. fp@2405: * Switching from MMIO to I/O access fixes the issue as well. fp@2405: */ fp@2405: RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); fp@2405: RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); fp@2405: RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); fp@2405: RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); fp@2405: } fp@2405: fp@2405: static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) fp@2405: { fp@2405: u16 cmd; fp@2405: fp@2405: cmd = RTL_R16(CPlusCmd); fp@2405: RTL_W16(CPlusCmd, cmd); fp@2405: return cmd; fp@2405: } fp@2405: fp@2405: static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) fp@2405: { fp@2405: /* Low hurts. Let's disable the filtering. */ fp@2405: RTL_W16(RxMaxSize, rx_buf_sz + 1); fp@2405: } fp@2405: fp@2405: static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) fp@2405: { fp@2405: static const struct rtl_cfg2_info { fp@2405: u32 mac_version; fp@2405: u32 clk; fp@2405: u32 val; fp@2405: } cfg2_info [] = { fp@2405: { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd fp@2405: { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, fp@2405: { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe fp@2405: { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } fp@2405: }; fp@2405: const struct rtl_cfg2_info *p = cfg2_info; fp@2405: unsigned int i; fp@2405: u32 clk; fp@2405: fp@2405: clk = RTL_R8(Config2) & PCI_Clock_66MHz; fp@2405: for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { fp@2405: if ((p->mac_version == mac_version) && (p->clk == clk)) { fp@2405: RTL_W32(0x7c, p->val); fp@2405: break; fp@2405: } fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8169(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_05) { fp@2405: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); fp@2405: pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); fp@2405: } fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_01 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_02 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_03 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_04) fp@2405: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2405: fp@2405: rtl_init_rxcfg(tp); fp@2405: fp@2405: RTL_W8(EarlyTxThres, NoEarlyTx); fp@2405: fp@2405: rtl_set_rx_max_size(ioaddr, rx_buf_sz); fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_01 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_02 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_03 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_04) fp@2405: rtl_set_rx_tx_config_registers(tp); fp@2405: fp@2405: tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_02 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_03) { fp@2405: dprintk("Set MAC Reg C+CR Offset 0xE0. " fp@2405: "Bit-3 and bit-14 MUST be 1\n"); fp@2405: tp->cp_cmd |= (1 << 14); fp@2405: } fp@2405: fp@2405: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2405: fp@2405: rtl8169_set_magic_reg(ioaddr, tp->mac_version); fp@2405: fp@2405: /* fp@2405: * Undocumented corner. Supposedly: fp@2405: * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets fp@2405: */ fp@2405: RTL_W16(IntrMitigate, 0x0000); fp@2405: fp@2405: rtl_set_rx_tx_desc_registers(tp, ioaddr); fp@2405: fp@2405: if (tp->mac_version != RTL_GIGA_MAC_VER_01 && fp@2405: tp->mac_version != RTL_GIGA_MAC_VER_02 && fp@2405: tp->mac_version != RTL_GIGA_MAC_VER_03 && fp@2405: tp->mac_version != RTL_GIGA_MAC_VER_04) { fp@2405: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2405: rtl_set_rx_tx_config_registers(tp); fp@2405: } fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: fp@2405: /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ fp@2405: RTL_R8(IntrMask); fp@2405: fp@2405: RTL_W32(RxMissed, 0); fp@2405: fp@2405: rtl_set_rx_mode(dev); fp@2405: fp@2405: /* no early-rx interrupts */ fp@2405: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); fp@2405: fp@2405: /* Enable all known interrupts by setting the interrupt mask. */ fp@2405: if (!tp->ecdev) fp@2405: RTL_W16(IntrMask, tp->intr_event); fp@2405: } fp@2405: fp@2405: static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) fp@2405: { fp@2405: u32 csi; fp@2405: fp@2405: csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; fp@2405: rtl_csi_write(ioaddr, 0x070c, csi | bits); fp@2405: } fp@2405: fp@2405: static void rtl_csi_access_enable_1(void __iomem *ioaddr) fp@2405: { fp@2405: rtl_csi_access_enable(ioaddr, 0x17000000); fp@2405: } fp@2405: fp@2405: static void rtl_csi_access_enable_2(void __iomem *ioaddr) fp@2405: { fp@2405: rtl_csi_access_enable(ioaddr, 0x27000000); fp@2405: } fp@2405: fp@2405: struct ephy_info { fp@2405: unsigned int offset; fp@2405: u16 mask; fp@2405: u16 bits; fp@2405: }; fp@2405: fp@2405: static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) fp@2405: { fp@2405: u16 w; fp@2405: fp@2405: while (len-- > 0) { fp@2405: w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; fp@2405: rtl_ephy_write(ioaddr, e->offset, w); fp@2405: e++; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_disable_clock_request(struct pci_dev *pdev) fp@2405: { fp@2405: int cap = pci_pcie_cap(pdev); fp@2405: fp@2405: if (cap) { fp@2405: u16 ctl; fp@2405: fp@2405: pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); fp@2405: ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; fp@2405: pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_enable_clock_request(struct pci_dev *pdev) fp@2405: { fp@2405: int cap = pci_pcie_cap(pdev); fp@2405: fp@2405: if (cap) { fp@2405: u16 ctl; fp@2405: fp@2405: pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); fp@2405: ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; fp@2405: pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); fp@2405: } fp@2405: } fp@2405: fp@2405: #define R8168_CPCMD_QUIRK_MASK (\ fp@2405: EnableBist | \ fp@2405: Mac_dbgo_oe | \ fp@2405: Force_half_dup | \ fp@2405: Force_rxflow_en | \ fp@2405: Force_txflow_en | \ fp@2405: Cxpl_dbg_sel | \ fp@2405: ASF | \ fp@2405: PktCntrDisable | \ fp@2405: Mac_dbgo_sel) fp@2405: fp@2405: static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2405: fp@2405: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, fp@2405: (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_hw_start_8168bb(ioaddr, pdev); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); fp@2405: } fp@2405: fp@2405: static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: RTL_W8(Config1, RTL_R8(Config1) | Speed_down); fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: rtl_disable_clock_request(pdev); fp@2405: fp@2405: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168cp[] = { fp@2405: { 0x01, 0, 0x0001 }, fp@2405: { 0x02, 0x0800, 0x1000 }, fp@2405: { 0x03, 0, 0x0042 }, fp@2405: { 0x06, 0x0080, 0x0000 }, fp@2405: { 0x07, 0, 0x2000 } fp@2405: }; fp@2405: fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); fp@2405: fp@2405: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2405: fp@2405: /* Magic. */ fp@2405: RTL_W8(DBG_REG, 0x20); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168c_1[] = { fp@2405: { 0x02, 0x0800, 0x1000 }, fp@2405: { 0x03, 0, 0x0002 }, fp@2405: { 0x06, 0x0080, 0x0000 } fp@2405: }; fp@2405: fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); fp@2405: fp@2405: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168c_2[] = { fp@2405: { 0x01, 0, 0x0001 }, fp@2405: { 0x03, 0x0400, 0x0220 } fp@2405: }; fp@2405: fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); fp@2405: fp@2405: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_hw_start_8168c_2(ioaddr, pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: rtl_disable_clock_request(pdev); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_csi_access_enable_1(ioaddr); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: rtl_disable_clock_request(pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168d_4[] = { fp@2405: { 0x0b, ~0, 0x48 }, fp@2405: { 0x19, 0x20, 0x50 }, fp@2405: { 0x0c, ~0, 0x20 } fp@2405: }; fp@2405: int i; fp@2405: fp@2405: rtl_csi_access_enable_1(ioaddr); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { fp@2405: const struct ephy_info *e = e_info_8168d_4 + i; fp@2405: u16 w; fp@2405: fp@2405: w = rtl_ephy_read(ioaddr, e->offset); fp@2405: rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); fp@2405: } fp@2405: fp@2405: rtl_enable_clock_request(pdev); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168e_1[] = { fp@2405: { 0x00, 0x0200, 0x0100 }, fp@2405: { 0x00, 0x0000, 0x0004 }, fp@2405: { 0x06, 0x0002, 0x0001 }, fp@2405: { 0x06, 0x0000, 0x0030 }, fp@2405: { 0x07, 0x0000, 0x2000 }, fp@2405: { 0x00, 0x0000, 0x0020 }, fp@2405: { 0x03, 0x5800, 0x2000 }, fp@2405: { 0x03, 0x0000, 0x0001 }, fp@2405: { 0x01, 0x0800, 0x1000 }, fp@2405: { 0x07, 0x0000, 0x4000 }, fp@2405: { 0x1e, 0x0000, 0x2000 }, fp@2405: { 0x19, 0xffff, 0xfe6c }, fp@2405: { 0x0a, 0x0000, 0x0040 } fp@2405: }; fp@2405: fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: rtl_disable_clock_request(pdev); fp@2405: fp@2405: /* Reset tx FIFO pointer */ fp@2405: RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); fp@2405: RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); fp@2405: fp@2405: RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168e_2[] = { fp@2405: { 0x09, 0x0000, 0x0080 }, fp@2405: { 0x19, 0x0000, 0x0224 } fp@2405: }; fp@2405: fp@2405: rtl_csi_access_enable_1(ioaddr); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, fp@2405: ERIAR_EXGMAC); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, EarlySize); fp@2405: fp@2405: rtl_disable_clock_request(pdev); fp@2405: fp@2405: RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); fp@2405: RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); fp@2405: fp@2405: /* Adjust EEE LED frequency */ fp@2405: RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); fp@2405: fp@2405: RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); fp@2405: RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); fp@2405: RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8168f_1[] = { fp@2405: { 0x06, 0x00c0, 0x0020 }, fp@2405: { 0x08, 0x0001, 0x0002 }, fp@2405: { 0x09, 0x0000, 0x0080 }, fp@2405: { 0x19, 0x0000, 0x0224 } fp@2405: }; fp@2405: fp@2405: rtl_csi_access_enable_1(ioaddr); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); fp@2405: rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); fp@2405: rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, fp@2405: ERIAR_EXGMAC); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, EarlySize); fp@2405: fp@2405: rtl_disable_clock_request(pdev); fp@2405: fp@2405: RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); fp@2405: RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); fp@2405: fp@2405: /* Adjust EEE LED frequency */ fp@2405: RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); fp@2405: fp@2405: RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); fp@2405: RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); fp@2405: RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8168(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: rtl_set_rx_max_size(ioaddr, rx_buf_sz); fp@2405: fp@2405: tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; fp@2405: fp@2405: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2405: fp@2405: RTL_W16(IntrMitigate, 0x5151); fp@2405: fp@2405: /* Work around for RxFIFO overflow. */ fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_11) { fp@2405: tp->intr_event |= RxFIFOOver | PCSTimeout; fp@2405: tp->intr_event &= ~RxOverflow; fp@2405: } fp@2405: fp@2405: rtl_set_rx_tx_desc_registers(tp, ioaddr); fp@2405: fp@2405: rtl_set_rx_mode(dev); fp@2405: fp@2405: RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | fp@2405: (InterFrameGap << TxInterFrameGapShift)); fp@2405: fp@2405: RTL_R8(IntrMask); fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: rtl_hw_start_8168bb(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: rtl_hw_start_8168bef(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_18: fp@2405: rtl_hw_start_8168cp_1(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_19: fp@2405: rtl_hw_start_8168c_1(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_20: fp@2405: rtl_hw_start_8168c_2(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_21: fp@2405: rtl_hw_start_8168c_3(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_22: fp@2405: rtl_hw_start_8168c_4(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_23: fp@2405: rtl_hw_start_8168cp_2(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_24: fp@2405: rtl_hw_start_8168cp_3(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_25: fp@2405: case RTL_GIGA_MAC_VER_26: fp@2405: case RTL_GIGA_MAC_VER_27: fp@2405: rtl_hw_start_8168d(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_28: fp@2405: rtl_hw_start_8168d_4(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_31: fp@2405: rtl_hw_start_8168dp(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_32: fp@2405: case RTL_GIGA_MAC_VER_33: fp@2405: rtl_hw_start_8168e_1(ioaddr, pdev); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_34: fp@2405: rtl_hw_start_8168e_2(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_35: fp@2405: case RTL_GIGA_MAC_VER_36: fp@2405: rtl_hw_start_8168f_1(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: default: fp@2405: printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", fp@2405: dev->name, tp->mac_version); fp@2405: break; fp@2405: } fp@2405: fp@2405: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: fp@2405: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); fp@2405: fp@2405: if (!tp->ecdev) fp@2405: RTL_W16(IntrMask, tp->intr_event); fp@2405: } fp@2405: fp@2405: #define R810X_CPCMD_QUIRK_MASK (\ fp@2405: EnableBist | \ fp@2405: Mac_dbgo_oe | \ fp@2405: Force_half_dup | \ fp@2405: Force_rxflow_en | \ fp@2405: Force_txflow_en | \ fp@2405: Cxpl_dbg_sel | \ fp@2405: ASF | \ fp@2405: PktCntrDisable | \ fp@2405: Mac_dbgo_sel) fp@2405: fp@2405: static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8102e_1[] = { fp@2405: { 0x01, 0, 0x6e65 }, fp@2405: { 0x02, 0, 0x091f }, fp@2405: { 0x03, 0, 0xc2f9 }, fp@2405: { 0x06, 0, 0xafb5 }, fp@2405: { 0x07, 0, 0x0e00 }, fp@2405: { 0x19, 0, 0xec80 }, fp@2405: { 0x01, 0, 0x2e65 }, fp@2405: { 0x01, 0, 0x6e65 } fp@2405: }; fp@2405: u8 cfg1; fp@2405: fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: RTL_W8(DBG_REG, FIX_NAK_1); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W8(Config1, fp@2405: LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2405: fp@2405: cfg1 = RTL_R8(Config1); fp@2405: if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) fp@2405: RTL_W8(Config1, cfg1 & ~LEDS0); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_csi_access_enable_2(ioaddr); fp@2405: fp@2405: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2405: fp@2405: RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); fp@2405: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_hw_start_8102e_2(ioaddr, pdev); fp@2405: fp@2405: rtl_ephy_write(ioaddr, 0x03, 0xc2f9); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: static const struct ephy_info e_info_8105e_1[] = { fp@2405: { 0x07, 0, 0x4000 }, fp@2405: { 0x19, 0, 0x0200 }, fp@2405: { 0x19, 0, 0x0020 }, fp@2405: { 0x1e, 0, 0x2000 }, fp@2405: { 0x03, 0, 0x0001 }, fp@2405: { 0x19, 0, 0x0100 }, fp@2405: { 0x19, 0, 0x0004 }, fp@2405: { 0x0a, 0, 0x0020 } fp@2405: }; fp@2405: fp@2405: /* Force LAN exit from ASPM if Rx/Tx are not idle */ fp@2405: RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); fp@2405: fp@2405: /* Disable Early Tally Counter */ fp@2405: RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); fp@2405: fp@2405: RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); fp@2405: RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); fp@2405: fp@2405: rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2405: { fp@2405: rtl_hw_start_8105e_1(ioaddr, pdev); fp@2405: rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); fp@2405: } fp@2405: fp@2405: static void rtl_hw_start_8101(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: if (tp->mac_version >= RTL_GIGA_MAC_VER_30) { fp@2405: tp->intr_event &= ~RxFIFOOver; fp@2405: tp->napi_event &= ~RxFIFOOver; fp@2405: } fp@2405: fp@2405: if (tp->mac_version == RTL_GIGA_MAC_VER_13 || fp@2405: tp->mac_version == RTL_GIGA_MAC_VER_16) { fp@2405: int cap = pci_pcie_cap(pdev); fp@2405: fp@2405: if (cap) { fp@2405: pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, fp@2405: PCI_EXP_DEVCTL_NOSNOOP_EN); fp@2405: } fp@2405: } fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2405: fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_07: fp@2405: rtl_hw_start_8102e_1(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_08: fp@2405: rtl_hw_start_8102e_3(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_09: fp@2405: rtl_hw_start_8102e_2(ioaddr, pdev); fp@2405: break; fp@2405: fp@2405: case RTL_GIGA_MAC_VER_29: fp@2405: rtl_hw_start_8105e_1(ioaddr, pdev); fp@2405: break; fp@2405: case RTL_GIGA_MAC_VER_30: fp@2405: rtl_hw_start_8105e_2(ioaddr, pdev); fp@2405: break; fp@2405: } fp@2405: fp@2405: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2405: fp@2405: RTL_W8(MaxTxPacketSize, TxPacketMax); fp@2405: fp@2405: rtl_set_rx_max_size(ioaddr, rx_buf_sz); fp@2405: fp@2405: tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; fp@2405: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2405: fp@2405: RTL_W16(IntrMitigate, 0x0000); fp@2405: fp@2405: rtl_set_rx_tx_desc_registers(tp, ioaddr); fp@2405: fp@2405: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2405: rtl_set_rx_tx_config_registers(tp); fp@2405: fp@2405: RTL_R8(IntrMask); fp@2405: fp@2405: rtl_set_rx_mode(dev); fp@2405: fp@2405: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); fp@2405: fp@2405: if (!tp->ecdev) fp@2405: RTL_W16(IntrMask, tp->intr_event); fp@2405: } fp@2405: fp@2405: static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (new_mtu < ETH_ZLEN || fp@2405: new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) fp@2405: return -EINVAL; fp@2405: fp@2405: if (new_mtu > ETH_DATA_LEN) fp@2405: rtl_hw_jumbo_enable(tp); fp@2405: else fp@2405: rtl_hw_jumbo_disable(tp); fp@2405: fp@2405: dev->mtu = new_mtu; fp@2405: netdev_update_features(dev); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) fp@2405: { fp@2405: desc->addr = cpu_to_le64(0x0badbadbadbadbadull); fp@2405: desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); fp@2405: } fp@2405: fp@2405: static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, fp@2405: void **data_buff, struct RxDesc *desc) fp@2405: { fp@2405: dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, fp@2405: DMA_FROM_DEVICE); fp@2405: fp@2405: kfree(*data_buff); fp@2405: *data_buff = NULL; fp@2405: rtl8169_make_unusable_by_asic(desc); fp@2405: } fp@2405: fp@2405: static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) fp@2405: { fp@2405: u32 eor = le32_to_cpu(desc->opts1) & RingEnd; fp@2405: fp@2405: desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); fp@2405: } fp@2405: fp@2405: static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, fp@2405: u32 rx_buf_sz) fp@2405: { fp@2405: desc->addr = cpu_to_le64(mapping); fp@2405: wmb(); fp@2405: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2405: } fp@2405: fp@2405: static inline void *rtl8169_align(void *data) fp@2405: { fp@2405: return (void *)ALIGN((long)data, 16); fp@2405: } fp@2405: fp@2405: static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, fp@2405: struct RxDesc *desc) fp@2405: { fp@2405: void *data; fp@2405: dma_addr_t mapping; fp@2405: struct device *d = &tp->pci_dev->dev; fp@2405: struct net_device *dev = tp->dev; fp@2405: int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; fp@2405: fp@2405: data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); fp@2405: if (!data) fp@2405: return NULL; fp@2405: fp@2405: if (rtl8169_align(data) != data) { fp@2405: kfree(data); fp@2405: data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); fp@2405: if (!data) fp@2405: return NULL; fp@2405: } fp@2405: fp@2405: mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, fp@2405: DMA_FROM_DEVICE); fp@2405: if (unlikely(dma_mapping_error(d, mapping))) { fp@2405: if (net_ratelimit()) fp@2405: netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); fp@2405: goto err_out; fp@2405: } fp@2405: fp@2405: rtl8169_map_to_asic(desc, mapping, rx_buf_sz); fp@2405: return data; fp@2405: fp@2405: err_out: fp@2405: kfree(data); fp@2405: return NULL; fp@2405: } fp@2405: fp@2405: static void rtl8169_rx_clear(struct rtl8169_private *tp) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: for (i = 0; i < NUM_RX_DESC; i++) { fp@2405: if (tp->Rx_databuff[i]) { fp@2405: rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, fp@2405: tp->RxDescArray + i); fp@2405: } fp@2405: } fp@2405: } fp@2405: fp@2405: static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) fp@2405: { fp@2405: desc->opts1 |= cpu_to_le32(RingEnd); fp@2405: } fp@2405: fp@2405: static int rtl8169_rx_fill(struct rtl8169_private *tp) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: for (i = 0; i < NUM_RX_DESC; i++) { fp@2405: void *data; fp@2405: fp@2405: if (tp->Rx_databuff[i]) fp@2405: continue; fp@2405: fp@2405: data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); fp@2405: if (!data) { fp@2405: rtl8169_make_unusable_by_asic(tp->RxDescArray + i); fp@2405: goto err_out; fp@2405: } fp@2405: tp->Rx_databuff[i] = data; fp@2405: } fp@2405: fp@2405: rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); fp@2405: return 0; fp@2405: fp@2405: err_out: fp@2405: rtl8169_rx_clear(tp); fp@2405: return -ENOMEM; fp@2405: } fp@2405: fp@2405: static int rtl8169_init_ring(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: rtl8169_init_ring_indexes(tp); fp@2405: fp@2405: memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); fp@2405: memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); fp@2405: fp@2405: return rtl8169_rx_fill(tp); fp@2405: } fp@2405: fp@2405: static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, fp@2405: struct TxDesc *desc) fp@2405: { fp@2405: unsigned int len = tx_skb->len; fp@2405: fp@2405: dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); fp@2405: fp@2405: desc->opts1 = 0x00; fp@2405: desc->opts2 = 0x00; fp@2405: desc->addr = 0x00; fp@2405: tx_skb->len = 0; fp@2405: } fp@2405: fp@2405: static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, fp@2405: unsigned int n) fp@2405: { fp@2405: unsigned int i; fp@2405: fp@2405: for (i = 0; i < n; i++) { fp@2405: unsigned int entry = (start + i) % NUM_TX_DESC; fp@2405: struct ring_info *tx_skb = tp->tx_skb + entry; fp@2405: unsigned int len = tx_skb->len; fp@2405: fp@2405: if (len) { fp@2405: struct sk_buff *skb = tx_skb->skb; fp@2405: fp@2405: rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, fp@2405: tp->TxDescArray + entry); fp@2405: if (skb) { fp@2405: tp->dev->stats.tx_dropped++; fp@2405: if (!tp->ecdev) fp@2405: dev_kfree_skb(skb); fp@2405: tx_skb->skb = NULL; fp@2405: } fp@2405: } fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl8169_tx_clear(struct rtl8169_private *tp) fp@2405: { fp@2405: rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); fp@2405: tp->cur_tx = tp->dirty_tx = 0; fp@2405: } fp@2405: fp@2405: static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: PREPARE_DELAYED_WORK(&tp->task, task); fp@2405: schedule_delayed_work(&tp->task, 4); fp@2405: } fp@2405: fp@2405: static void rtl8169_wait_for_quiescence(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: synchronize_irq(dev->irq); fp@2405: fp@2405: /* Wait for any pending NAPI task to complete */ fp@2405: napi_disable(&tp->napi); fp@2405: fp@2405: rtl8169_irq_mask_and_ack(tp); fp@2405: fp@2405: tp->intr_mask = 0xffff; fp@2405: RTL_W16(IntrMask, tp->intr_event); fp@2405: napi_enable(&tp->napi); fp@2405: } fp@2405: fp@2405: static void rtl8169_reinit_task(struct work_struct *work) fp@2405: { fp@2405: struct rtl8169_private *tp = fp@2405: container_of(work, struct rtl8169_private, task.work); fp@2405: struct net_device *dev = tp->dev; fp@2405: int ret; fp@2405: fp@2405: rtnl_lock(); fp@2405: fp@2405: if (!netif_running(dev)) fp@2405: goto out_unlock; fp@2405: fp@2405: rtl8169_wait_for_quiescence(dev); fp@2405: rtl8169_close(dev); fp@2405: fp@2405: ret = rtl8169_open(dev); fp@2405: if (unlikely(ret < 0)) { fp@2405: if (net_ratelimit()) fp@2405: netif_err(tp, drv, dev, fp@2405: "reinit failure (status = %d). Rescheduling\n", fp@2405: ret); fp@2405: rtl8169_schedule_work(dev, rtl8169_reinit_task); fp@2405: } fp@2405: fp@2405: out_unlock: fp@2405: rtnl_unlock(); fp@2405: } fp@2405: fp@2405: static void rtl8169_reset_task(struct work_struct *work) fp@2405: { fp@2405: struct rtl8169_private *tp = fp@2405: container_of(work, struct rtl8169_private, task.work); fp@2405: struct net_device *dev = tp->dev; fp@2405: int i; fp@2405: fp@2405: rtnl_lock(); fp@2405: fp@2405: if (!netif_running(dev)) fp@2405: goto out_unlock; fp@2405: fp@2405: rtl8169_hw_reset(tp); fp@2405: fp@2405: rtl8169_wait_for_quiescence(dev); fp@2405: fp@2405: for (i = 0; i < NUM_RX_DESC; i++) fp@2405: rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); fp@2405: fp@2405: rtl8169_tx_clear(tp); fp@2405: rtl8169_init_ring_indexes(tp); fp@2405: fp@2405: rtl_hw_start(dev); fp@2405: netif_wake_queue(dev); fp@2405: rtl8169_check_link_status(dev, tp, tp->mmio_addr); fp@2405: fp@2405: out_unlock: fp@2405: rtnl_unlock(); fp@2405: } fp@2405: fp@2405: static void rtl8169_tx_timeout(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: if (tp->ecdev) fp@2405: return; fp@2405: fp@2405: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2405: } fp@2405: fp@2405: static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, fp@2405: u32 *opts) fp@2405: { fp@2405: struct skb_shared_info *info = skb_shinfo(skb); fp@2405: unsigned int cur_frag, entry; fp@2405: struct TxDesc * uninitialized_var(txd); fp@2405: struct device *d = &tp->pci_dev->dev; fp@2405: fp@2405: entry = tp->cur_tx; fp@2405: for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { fp@2405: const skb_frag_t *frag = info->frags + cur_frag; fp@2405: dma_addr_t mapping; fp@2405: u32 status, len; fp@2405: void *addr; fp@2405: fp@2405: entry = (entry + 1) % NUM_TX_DESC; fp@2405: fp@2405: txd = tp->TxDescArray + entry; fp@2405: len = skb_frag_size(frag); fp@2405: addr = skb_frag_address(frag); fp@2405: mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); fp@2405: if (unlikely(dma_mapping_error(d, mapping))) { fp@2405: if (net_ratelimit()) fp@2405: netif_err(tp, drv, tp->dev, fp@2405: "Failed to map TX fragments DMA!\n"); fp@2405: goto err_out; fp@2405: } fp@2405: fp@2405: /* Anti gcc 2.95.3 bugware (sic) */ fp@2405: status = opts[0] | len | fp@2405: (RingEnd * !((entry + 1) % NUM_TX_DESC)); fp@2405: fp@2405: txd->opts1 = cpu_to_le32(status); fp@2405: txd->opts2 = cpu_to_le32(opts[1]); fp@2405: txd->addr = cpu_to_le64(mapping); fp@2405: fp@2405: tp->tx_skb[entry].len = len; fp@2405: } fp@2405: fp@2405: if (cur_frag) { fp@2405: tp->tx_skb[entry].skb = skb; fp@2405: txd->opts1 |= cpu_to_le32(LastFrag); fp@2405: } fp@2405: fp@2405: return cur_frag; fp@2405: fp@2405: err_out: fp@2405: rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); fp@2405: return -EIO; fp@2405: } fp@2405: fp@2405: static inline void rtl8169_tso_csum(struct rtl8169_private *tp, fp@2405: struct sk_buff *skb, u32 *opts) fp@2405: { fp@2405: const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; fp@2405: u32 mss = skb_shinfo(skb)->gso_size; fp@2405: int offset = info->opts_offset; fp@2405: fp@2405: if (mss) { fp@2405: opts[0] |= TD_LSO; fp@2405: opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; fp@2405: } else if (skb->ip_summed == CHECKSUM_PARTIAL) { fp@2405: const struct iphdr *ip = ip_hdr(skb); fp@2405: fp@2405: if (ip->protocol == IPPROTO_TCP) fp@2405: opts[offset] |= info->checksum.tcp; fp@2405: else if (ip->protocol == IPPROTO_UDP) fp@2405: opts[offset] |= info->checksum.udp; fp@2405: else fp@2405: WARN_ON_ONCE(1); fp@2405: } fp@2405: } fp@2405: fp@2405: static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, fp@2405: struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: unsigned int entry = tp->cur_tx % NUM_TX_DESC; fp@2405: struct TxDesc *txd = tp->TxDescArray + entry; fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: struct device *d = &tp->pci_dev->dev; fp@2405: dma_addr_t mapping; fp@2405: u32 status, len; fp@2405: u32 opts[2]; fp@2405: int frags; fp@2405: fp@2405: if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { fp@2405: netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); fp@2405: goto err_stop_0; fp@2405: } fp@2405: fp@2405: if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) fp@2405: goto err_stop_0; fp@2405: fp@2405: len = skb_headlen(skb); fp@2405: mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); fp@2405: if (unlikely(dma_mapping_error(d, mapping))) { fp@2405: if (net_ratelimit()) fp@2405: netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); fp@2405: goto err_dma_0; fp@2405: } fp@2405: fp@2405: tp->tx_skb[entry].len = len; fp@2405: txd->addr = cpu_to_le64(mapping); fp@2405: fp@2405: opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); fp@2405: opts[0] = DescOwn; fp@2405: fp@2405: rtl8169_tso_csum(tp, skb, opts); fp@2405: fp@2405: frags = rtl8169_xmit_frags(tp, skb, opts); fp@2405: if (frags < 0) fp@2405: goto err_dma_1; fp@2405: else if (frags) fp@2405: opts[0] |= FirstFrag; fp@2405: else { fp@2405: opts[0] |= FirstFrag | LastFrag; fp@2405: tp->tx_skb[entry].skb = skb; fp@2405: } fp@2405: fp@2405: txd->opts2 = cpu_to_le32(opts[1]); fp@2405: fp@2405: wmb(); fp@2405: fp@2405: /* Anti gcc 2.95.3 bugware (sic) */ fp@2405: status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); fp@2405: txd->opts1 = cpu_to_le32(status); fp@2405: fp@2405: tp->cur_tx += frags + 1; fp@2405: fp@2405: wmb(); fp@2405: fp@2405: RTL_W8(TxPoll, NPQ); fp@2405: fp@2405: if (!tp->ecdev && TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { fp@2405: netif_stop_queue(dev); fp@2405: smp_rmb(); fp@2405: if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) fp@2405: netif_wake_queue(dev); fp@2405: } fp@2405: fp@2405: return NETDEV_TX_OK; fp@2405: fp@2405: err_dma_1: fp@2405: rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); fp@2405: err_dma_0: fp@2405: if (!tp->ecdev) fp@2405: dev_kfree_skb(skb); fp@2405: dev->stats.tx_dropped++; fp@2405: return NETDEV_TX_OK; fp@2405: fp@2405: err_stop_0: fp@2405: if (!tp->ecdev) fp@2405: netif_stop_queue(dev); fp@2405: dev->stats.tx_dropped++; fp@2405: return NETDEV_TX_BUSY; fp@2405: } fp@2405: fp@2405: static void rtl8169_pcierr_interrupt(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: u16 pci_status, pci_cmd; fp@2405: fp@2405: pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); fp@2405: pci_read_config_word(pdev, PCI_STATUS, &pci_status); fp@2405: fp@2405: netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", fp@2405: pci_cmd, pci_status); fp@2405: fp@2405: /* fp@2405: * The recovery sequence below admits a very elaborated explanation: fp@2405: * - it seems to work; fp@2405: * - I did not see what else could be done; fp@2405: * - it makes iop3xx happy. fp@2405: * fp@2405: * Feel free to adjust to your needs. fp@2405: */ fp@2405: if (pdev->broken_parity_status) fp@2405: pci_cmd &= ~PCI_COMMAND_PARITY; fp@2405: else fp@2405: pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; fp@2405: fp@2405: pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); fp@2405: fp@2405: pci_write_config_word(pdev, PCI_STATUS, fp@2405: pci_status & (PCI_STATUS_DETECTED_PARITY | fp@2405: PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | fp@2405: PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); fp@2405: fp@2405: /* The infamous DAC f*ckup only happens at boot time */ fp@2405: if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: netif_info(tp, intr, dev, "disabling PCI DAC\n"); fp@2405: tp->cp_cmd &= ~PCIDAC; fp@2405: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2405: dev->features &= ~NETIF_F_HIGHDMA; fp@2405: } fp@2405: fp@2405: rtl8169_hw_reset(tp); fp@2405: fp@2405: rtl8169_schedule_work(dev, rtl8169_reinit_task); fp@2405: } fp@2405: fp@2405: static void rtl8169_tx_interrupt(struct net_device *dev, fp@2405: struct rtl8169_private *tp, fp@2405: void __iomem *ioaddr) fp@2405: { fp@2405: unsigned int dirty_tx, tx_left; fp@2405: fp@2405: dirty_tx = tp->dirty_tx; fp@2405: smp_rmb(); fp@2405: tx_left = tp->cur_tx - dirty_tx; fp@2405: fp@2405: while (tx_left > 0) { fp@2405: unsigned int entry = dirty_tx % NUM_TX_DESC; fp@2405: struct ring_info *tx_skb = tp->tx_skb + entry; fp@2405: u32 status; fp@2405: fp@2405: rmb(); fp@2405: status = le32_to_cpu(tp->TxDescArray[entry].opts1); fp@2405: if (status & DescOwn) fp@2405: break; fp@2405: fp@2405: rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, fp@2405: tp->TxDescArray + entry); fp@2405: if (status & LastFrag) { fp@2405: dev->stats.tx_packets++; fp@2405: dev->stats.tx_bytes += tx_skb->skb->len; fp@2405: if (!tp->ecdev) fp@2405: dev_kfree_skb(tx_skb->skb); fp@2405: tx_skb->skb = NULL; fp@2405: } fp@2405: dirty_tx++; fp@2405: tx_left--; fp@2405: } fp@2405: fp@2405: if (tp->dirty_tx != dirty_tx) { fp@2405: tp->dirty_tx = dirty_tx; fp@2405: smp_wmb(); fp@2405: if (!tp->ecdev && netif_queue_stopped(dev) && fp@2405: (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { fp@2405: netif_wake_queue(dev); fp@2405: } fp@2405: /* fp@2405: * 8168 hack: TxPoll requests are lost when the Tx packets are fp@2405: * too close. Let's kick an extra TxPoll request when a burst fp@2405: * of start_xmit activity is detected (if it is not detected, fp@2405: * it is slow enough). -- FR fp@2405: */ fp@2405: smp_rmb(); fp@2405: if (tp->cur_tx != dirty_tx) fp@2405: RTL_W8(TxPoll, NPQ); fp@2405: } fp@2405: } fp@2405: fp@2405: static inline int rtl8169_fragmented_frame(u32 status) fp@2405: { fp@2405: return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); fp@2405: } fp@2405: fp@2405: static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) fp@2405: { fp@2405: u32 status = opts1 & RxProtoMask; fp@2405: fp@2405: if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || fp@2405: ((status == RxProtoUDP) && !(opts1 & UDPFail))) fp@2405: skb->ip_summed = CHECKSUM_UNNECESSARY; fp@2405: else fp@2405: skb_checksum_none_assert(skb); fp@2405: } fp@2405: fp@2405: static struct sk_buff *rtl8169_try_rx_copy(void *data, fp@2405: struct rtl8169_private *tp, fp@2405: int pkt_size, fp@2405: dma_addr_t addr) fp@2405: { fp@2405: struct sk_buff *skb; fp@2405: struct device *d = &tp->pci_dev->dev; fp@2405: fp@2405: data = rtl8169_align(data); fp@2405: dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); fp@2405: prefetch(data); fp@2405: skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); fp@2405: if (skb) fp@2405: memcpy(skb->data, data, pkt_size); fp@2405: dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); fp@2405: fp@2405: return skb; fp@2405: } fp@2405: fp@2405: static int rtl8169_rx_interrupt(struct net_device *dev, fp@2405: struct rtl8169_private *tp, fp@2405: void __iomem *ioaddr, u32 budget) fp@2405: { fp@2405: unsigned int cur_rx, rx_left; fp@2405: unsigned int count; fp@2405: fp@2405: cur_rx = tp->cur_rx; fp@2405: rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; fp@2405: rx_left = min(rx_left, budget); fp@2405: fp@2405: for (; rx_left > 0; rx_left--, cur_rx++) { fp@2405: unsigned int entry = cur_rx % NUM_RX_DESC; fp@2405: struct RxDesc *desc = tp->RxDescArray + entry; fp@2405: u32 status; fp@2405: fp@2405: rmb(); fp@2405: status = le32_to_cpu(desc->opts1) & tp->opts1_mask; fp@2405: fp@2405: if (status & DescOwn) fp@2405: break; fp@2405: if (unlikely(status & RxRES)) { fp@2405: netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", fp@2405: status); fp@2405: dev->stats.rx_errors++; fp@2405: if (status & (RxRWT | RxRUNT)) fp@2405: dev->stats.rx_length_errors++; fp@2405: if (status & RxCRC) fp@2405: dev->stats.rx_crc_errors++; fp@2405: if (status & RxFOVF) { fp@2405: if (!tp->ecdev) fp@2405: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2405: dev->stats.rx_fifo_errors++; fp@2405: } fp@2405: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2405: } else { fp@2405: struct sk_buff *skb; fp@2405: dma_addr_t addr = le64_to_cpu(desc->addr); fp@2405: int pkt_size = (status & 0x00003fff) - 4; fp@2405: fp@2405: /* fp@2405: * The driver does not support incoming fragmented fp@2405: * frames. They are seen as a symptom of over-mtu fp@2405: * sized frames. fp@2405: */ fp@2405: if (unlikely(rtl8169_fragmented_frame(status))) { fp@2405: dev->stats.rx_dropped++; fp@2405: dev->stats.rx_length_errors++; fp@2405: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2405: continue; fp@2405: } fp@2405: fp@2405: if (tp->ecdev) { fp@2405: struct device *d = &tp->pci_dev->dev; fp@2405: fp@2405: /* reusing parts of rtl8169_try_rx_copy() */ fp@2405: tp->Rx_databuff[entry] = rtl8169_align(tp->Rx_databuff[entry]); fp@2405: dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); fp@2405: prefetch(tp->Rx_databuff[entry]); fp@2405: fp@2405: ecdev_receive(tp->ecdev, tp->Rx_databuff[entry], pkt_size); fp@2405: fp@2405: dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); fp@2405: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2405: fp@2405: rtl8169_rx_csum(tp->Rx_databuff[entry], status); fp@2405: fp@2405: // No need to detect link status as fp@2405: // long as frames are received: Reset watchdog. fp@2405: tp->ec_watchdog_jiffies = jiffies; fp@2405: } else { fp@2405: skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], fp@2405: tp, pkt_size, addr); fp@2405: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2405: if (!skb) { fp@2405: dev->stats.rx_dropped++; fp@2405: continue; fp@2405: } fp@2405: fp@2405: rtl8169_rx_csum(skb, status); fp@2405: skb_put(skb, pkt_size); fp@2405: skb->protocol = eth_type_trans(skb, dev); fp@2405: fp@2405: rtl8169_rx_vlan_tag(desc, skb); fp@2405: fp@2405: napi_gro_receive(&tp->napi, skb); fp@2405: fp@2405: } fp@2405: fp@2405: dev->stats.rx_bytes += pkt_size; fp@2405: dev->stats.rx_packets++; fp@2405: } fp@2405: fp@2405: /* Work around for AMD plateform. */ fp@2405: if ((desc->opts2 & cpu_to_le32(0xfffe000)) && fp@2405: (tp->mac_version == RTL_GIGA_MAC_VER_05)) { fp@2405: desc->opts2 = 0; fp@2405: cur_rx++; fp@2405: } fp@2405: } fp@2405: fp@2405: count = cur_rx - tp->cur_rx; fp@2405: tp->cur_rx = cur_rx; fp@2405: fp@2405: tp->dirty_rx += count; fp@2405: fp@2405: return count; fp@2405: } fp@2405: fp@2405: static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) fp@2405: { fp@2405: struct net_device *dev = dev_instance; fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int handled = 0; fp@2405: int status; fp@2405: fp@2405: /* loop handling interrupts until we have no new ones or fp@2405: * we hit a invalid/hotplug case. fp@2405: */ fp@2405: status = RTL_R16(IntrStatus); fp@2405: while (status && status != 0xffff) { fp@2405: status &= tp->intr_event; fp@2405: if (!status) fp@2405: break; fp@2405: fp@2405: handled = 1; fp@2405: fp@2405: /* Handle all of the error cases first. These will reset fp@2405: * the chip, so just exit the loop. fp@2405: */ fp@2405: if (unlikely(!tp->ecdev && !netif_running(dev))) { fp@2405: rtl8169_hw_reset(tp); fp@2405: break; fp@2405: } fp@2405: fp@2405: if (unlikely(!tp->ecdev && (status & RxFIFOOver))) { fp@2405: switch (tp->mac_version) { fp@2405: /* Work around for rx fifo overflow */ fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: netif_stop_queue(dev); fp@2405: rtl8169_tx_timeout(dev); fp@2405: goto done; fp@2405: default: fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: if (unlikely(status & SYSErr)) { fp@2405: rtl8169_pcierr_interrupt(dev); fp@2405: break; fp@2405: } fp@2405: fp@2405: if (status & LinkChg) fp@2405: __rtl8169_check_link_status(dev, tp, ioaddr, true); fp@2405: fp@2405: /* We need to see the lastest version of tp->intr_mask to fp@2405: * avoid ignoring an MSI interrupt and having to wait for fp@2405: * another event which may never come. fp@2405: */ fp@2405: smp_rmb(); fp@2405: if (status & tp->intr_mask & tp->napi_event) { fp@2405: RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); fp@2405: tp->intr_mask = ~tp->napi_event; fp@2405: fp@2405: if (likely(napi_schedule_prep(&tp->napi))) fp@2405: __napi_schedule(&tp->napi); fp@2405: else fp@2405: netif_info(tp, intr, dev, fp@2405: "interrupt %04x in poll\n", status); fp@2405: } fp@2405: fp@2405: /* We only get a new MSI interrupt when all active irq fp@2405: * sources on the chip have been acknowledged. So, ack fp@2405: * everything we've seen and check if new sources have become fp@2405: * active to avoid blocking all interrupts from the chip. fp@2405: */ fp@2405: RTL_W16(IntrStatus, fp@2405: (status & RxFIFOOver) ? (status | RxOverflow) : status); fp@2405: status = RTL_R16(IntrStatus); fp@2405: } fp@2405: done: fp@2405: return IRQ_RETVAL(handled); fp@2405: } fp@2405: fp@2405: static void ec_poll(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: rtl8169_interrupt(pdev->irq, dev); fp@2405: rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, 100); // FIXME fp@2405: rtl8169_tx_interrupt(dev, tp, tp->mmio_addr); fp@2405: fp@2405: if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) { fp@2405: rtl8169_phy_timer((unsigned long) dev); fp@2405: tp->ec_watchdog_jiffies = jiffies; fp@2405: } fp@2405: } fp@2405: fp@2405: static int rtl8169_poll(struct napi_struct *napi, int budget) fp@2405: { fp@2405: struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); fp@2405: struct net_device *dev = tp->dev; fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: int work_done; fp@2405: fp@2405: work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); fp@2405: rtl8169_tx_interrupt(dev, tp, ioaddr); fp@2405: fp@2405: if (work_done < budget) { fp@2405: napi_complete(napi); fp@2405: fp@2405: /* We need for force the visibility of tp->intr_mask fp@2405: * for other CPUs, as we can loose an MSI interrupt fp@2405: * and potentially wait for a retransmit timeout if we don't. fp@2405: * The posted write to IntrMask is safe, as it will fp@2405: * eventually make it to the chip and we won't loose anything fp@2405: * until it does. fp@2405: */ fp@2405: tp->intr_mask = 0xffff; fp@2405: wmb(); fp@2405: RTL_W16(IntrMask, tp->intr_event); fp@2405: } fp@2405: fp@2405: return work_done; fp@2405: } fp@2405: fp@2405: static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (tp->mac_version > RTL_GIGA_MAC_VER_06) fp@2405: return; fp@2405: fp@2405: dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); fp@2405: RTL_W32(RxMissed, 0); fp@2405: } fp@2405: fp@2405: static void rtl8169_down(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: if (!tp->ecdev) { fp@2405: del_timer_sync(&tp->timer); fp@2405: fp@2405: netif_stop_queue(dev); fp@2405: fp@2405: napi_disable(&tp->napi); fp@2405: } fp@2405: fp@2405: if (!tp->ecdev) { fp@2405: spin_lock_irq(&tp->lock); fp@2405: } fp@2405: fp@2405: rtl8169_hw_reset(tp); fp@2405: /* fp@2405: * At this point device interrupts can not be enabled in any function, fp@2405: * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, fp@2405: * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). fp@2405: */ fp@2405: rtl8169_rx_missed(dev, ioaddr); fp@2405: fp@2405: if (!tp->ecdev) { fp@2405: spin_unlock_irq(&tp->lock); fp@2405: fp@2405: synchronize_irq(dev->irq); fp@2405: } fp@2405: fp@2405: /* Give a racing hard_start_xmit a few cycles to complete. */ fp@2405: synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ fp@2405: fp@2405: rtl8169_tx_clear(tp); fp@2405: fp@2405: rtl8169_rx_clear(tp); fp@2405: fp@2405: rtl_pll_power_down(tp); fp@2405: } fp@2405: fp@2405: static int rtl8169_close(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: struct pci_dev *pdev = tp->pci_dev; fp@2405: fp@2405: pm_runtime_get_sync(&pdev->dev); fp@2405: fp@2405: /* Update counters before going down */ fp@2405: rtl8169_update_counters(dev); fp@2405: fp@2405: rtl8169_down(dev); fp@2405: fp@2405: if (!tp->ecdev) fp@2405: free_irq(dev->irq, dev); fp@2405: fp@2405: dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, fp@2405: tp->RxPhyAddr); fp@2405: dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, fp@2405: tp->TxPhyAddr); fp@2405: tp->TxDescArray = NULL; fp@2405: tp->RxDescArray = NULL; fp@2405: fp@2405: pm_runtime_put_sync(&pdev->dev); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static void rtl_set_rx_mode(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: unsigned long flags; fp@2405: u32 mc_filter[2]; /* Multicast hash filter */ fp@2405: int rx_mode; fp@2405: u32 tmp = 0; fp@2405: fp@2405: if (dev->flags & IFF_PROMISC) { fp@2405: /* Unconditionally log net taps. */ fp@2405: netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); fp@2405: rx_mode = fp@2405: AcceptBroadcast | AcceptMulticast | AcceptMyPhys | fp@2405: AcceptAllPhys; fp@2405: mc_filter[1] = mc_filter[0] = 0xffffffff; fp@2405: } else if ((netdev_mc_count(dev) > multicast_filter_limit) || fp@2405: (dev->flags & IFF_ALLMULTI)) { fp@2405: /* Too many to filter perfectly -- accept all multicasts. */ fp@2405: rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; fp@2405: mc_filter[1] = mc_filter[0] = 0xffffffff; fp@2405: } else { fp@2405: struct netdev_hw_addr *ha; fp@2405: fp@2405: rx_mode = AcceptBroadcast | AcceptMyPhys; fp@2405: mc_filter[1] = mc_filter[0] = 0; fp@2405: netdev_for_each_mc_addr(ha, dev) { fp@2405: int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; fp@2405: mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); fp@2405: rx_mode |= AcceptMulticast; fp@2405: } fp@2405: } fp@2405: fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: fp@2405: tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; fp@2405: fp@2405: if (tp->mac_version > RTL_GIGA_MAC_VER_06) { fp@2405: u32 data = mc_filter[0]; fp@2405: fp@2405: mc_filter[0] = swab32(mc_filter[1]); fp@2405: mc_filter[1] = swab32(data); fp@2405: } fp@2405: fp@2405: RTL_W32(MAR0 + 4, mc_filter[1]); fp@2405: RTL_W32(MAR0 + 0, mc_filter[0]); fp@2405: fp@2405: RTL_W32(RxConfig, tmp); fp@2405: fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: } fp@2405: fp@2405: /** fp@2405: * rtl8169_get_stats - Get rtl8169 read/write statistics fp@2405: * @dev: The Ethernet Device to get statistics for fp@2405: * fp@2405: * Get TX/RX statistics for rtl8169 fp@2405: */ fp@2405: static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: unsigned long flags; fp@2405: fp@2405: if (netif_running(dev)) { fp@2405: spin_lock_irqsave(&tp->lock, flags); fp@2405: rtl8169_rx_missed(dev, ioaddr); fp@2405: spin_unlock_irqrestore(&tp->lock, flags); fp@2405: } fp@2405: fp@2405: return &dev->stats; fp@2405: } fp@2405: fp@2405: static void rtl8169_net_suspend(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (!netif_running(dev)) fp@2405: return; fp@2405: fp@2405: rtl_pll_power_down(tp); fp@2405: fp@2405: netif_device_detach(dev); fp@2405: netif_stop_queue(dev); fp@2405: } fp@2405: fp@2405: #ifdef CONFIG_PM fp@2405: fp@2405: static int rtl8169_suspend(struct device *device) fp@2405: { fp@2405: struct pci_dev *pdev = to_pci_dev(device); fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (tp->ecdev) fp@2405: return -EBUSY; fp@2405: fp@2405: rtl8169_net_suspend(dev); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static void __rtl8169_resume(struct net_device *dev) fp@2405: { fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: netif_device_attach(dev); fp@2405: fp@2405: rtl_pll_power_up(tp); fp@2405: fp@2405: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2405: } fp@2405: fp@2405: static int rtl8169_resume(struct device *device) fp@2405: { fp@2405: struct pci_dev *pdev = to_pci_dev(device); fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: rtl8169_init_phy(dev, tp); fp@2405: fp@2405: if (tp->ecdev) fp@2405: return -EBUSY; fp@2405: fp@2405: if (netif_running(dev)) fp@2405: __rtl8169_resume(dev); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static int rtl8169_runtime_suspend(struct device *device) fp@2405: { fp@2405: struct pci_dev *pdev = to_pci_dev(device); fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (!tp->TxDescArray) fp@2405: return 0; fp@2405: fp@2405: spin_lock_irq(&tp->lock); fp@2405: tp->saved_wolopts = __rtl8169_get_wol(tp); fp@2405: __rtl8169_set_wol(tp, WAKE_ANY); fp@2405: spin_unlock_irq(&tp->lock); fp@2405: fp@2405: rtl8169_net_suspend(dev); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static int rtl8169_runtime_resume(struct device *device) fp@2405: { fp@2405: struct pci_dev *pdev = to_pci_dev(device); fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: if (!tp->TxDescArray) fp@2405: return 0; fp@2405: fp@2405: spin_lock_irq(&tp->lock); fp@2405: __rtl8169_set_wol(tp, tp->saved_wolopts); fp@2405: tp->saved_wolopts = 0; fp@2405: spin_unlock_irq(&tp->lock); fp@2405: fp@2405: rtl8169_init_phy(dev, tp); fp@2405: fp@2405: __rtl8169_resume(dev); fp@2405: fp@2405: return 0; fp@2405: } fp@2405: fp@2405: static int rtl8169_runtime_idle(struct device *device) fp@2405: { fp@2405: struct pci_dev *pdev = to_pci_dev(device); fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: return tp->TxDescArray ? -EBUSY : 0; fp@2405: } fp@2405: fp@2405: static const struct dev_pm_ops rtl8169_pm_ops = { fp@2405: .suspend = rtl8169_suspend, fp@2405: .resume = rtl8169_resume, fp@2405: .freeze = rtl8169_suspend, fp@2405: .thaw = rtl8169_resume, fp@2405: .poweroff = rtl8169_suspend, fp@2405: .restore = rtl8169_resume, fp@2405: .runtime_suspend = rtl8169_runtime_suspend, fp@2405: .runtime_resume = rtl8169_runtime_resume, fp@2405: .runtime_idle = rtl8169_runtime_idle, fp@2405: }; fp@2405: fp@2405: #define RTL8169_PM_OPS (&rtl8169_pm_ops) fp@2405: fp@2405: #else /* !CONFIG_PM */ fp@2405: fp@2405: #define RTL8169_PM_OPS NULL fp@2405: fp@2405: #endif /* !CONFIG_PM */ fp@2405: fp@2405: static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) fp@2405: { fp@2405: void __iomem *ioaddr = tp->mmio_addr; fp@2405: fp@2405: /* WoL fails with 8168b when the receiver is disabled. */ fp@2405: switch (tp->mac_version) { fp@2405: case RTL_GIGA_MAC_VER_11: fp@2405: case RTL_GIGA_MAC_VER_12: fp@2405: case RTL_GIGA_MAC_VER_17: fp@2405: pci_clear_master(tp->pci_dev); fp@2405: fp@2405: RTL_W8(ChipCmd, CmdRxEnb); fp@2405: /* PCI commit */ fp@2405: RTL_R8(ChipCmd); fp@2405: break; fp@2405: default: fp@2405: break; fp@2405: } fp@2405: } fp@2405: fp@2405: static void rtl_shutdown(struct pci_dev *pdev) fp@2405: { fp@2405: struct net_device *dev = pci_get_drvdata(pdev); fp@2405: struct rtl8169_private *tp = netdev_priv(dev); fp@2405: fp@2405: rtl8169_net_suspend(dev); fp@2405: fp@2405: /* Restore original MAC address */ fp@2405: rtl_rar_set(tp, dev->perm_addr); fp@2405: fp@2405: spin_lock_irq(&tp->lock); fp@2405: fp@2405: rtl8169_hw_reset(tp); fp@2405: fp@2405: spin_unlock_irq(&tp->lock); fp@2405: fp@2405: if (system_state == SYSTEM_POWER_OFF) { fp@2405: if (__rtl8169_get_wol(tp) & WAKE_ANY) { fp@2405: rtl_wol_suspend_quirk(tp); fp@2405: rtl_wol_shutdown_quirk(tp); fp@2405: } fp@2405: fp@2405: pci_wake_from_d3(pdev, true); fp@2405: pci_set_power_state(pdev, PCI_D3hot); fp@2405: } fp@2405: } fp@2405: fp@2405: static struct pci_driver rtl8169_pci_driver = { fp@2405: .name = MODULENAME, fp@2405: .id_table = rtl8169_pci_tbl, fp@2405: .probe = rtl8169_init_one, fp@2405: .remove = __devexit_p(rtl8169_remove_one), fp@2405: .shutdown = rtl_shutdown, fp@2405: .driver.pm = RTL8169_PM_OPS, fp@2405: }; fp@2405: fp@2405: static int __init rtl8169_init_module(void) fp@2405: { fp@2405: return pci_register_driver(&rtl8169_pci_driver); fp@2405: } fp@2405: fp@2405: static void __exit rtl8169_cleanup_module(void) fp@2405: { fp@2405: pci_unregister_driver(&rtl8169_pci_driver); fp@2405: } fp@2405: fp@2405: module_init(rtl8169_init_module); fp@2405: module_exit(rtl8169_cleanup_module);