fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685: * Copyright(c) 2007-2014 Intel Corporation.
fp@2685: *
fp@2685: * This program is free software; you can redistribute it and/or modify it
fp@2685: * under the terms and conditions of the GNU General Public License,
fp@2685: * version 2, as published by the Free Software Foundation.
fp@2685: *
fp@2685: * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
fp@2685: * more details.
fp@2685: *
fp@2685: * You should have received a copy of the GNU General Public License along with
fp@2685: * this program; if not, see .
fp@2685: *
fp@2685: * The full GNU General Public License is included in this distribution in
fp@2685: * the file called "COPYING".
fp@2685: *
fp@2685: * Contact Information:
fp@2685: * e1000-devel Mailing List
fp@2685: * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685: */
fp@2685:
fp@2685: #include
fp@2685: #include
fp@2685:
fp@2685: #include "e1000_mac-3.18-ethercat.h"
fp@2685: #include "e1000_phy-3.18-ethercat.h"
fp@2685:
fp@2685: static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
fp@2685: static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
fp@2685: u16 *phy_ctrl);
fp@2685: static s32 igb_wait_autoneg(struct e1000_hw *hw);
fp@2685: static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
fp@2685:
fp@2685: /* Cable length tables */
fp@2685: static const u16 e1000_m88_cable_length_table[] = {
fp@2685: 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
fp@2685: #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
fp@2685: (sizeof(e1000_m88_cable_length_table) / \
fp@2685: sizeof(e1000_m88_cable_length_table[0]))
fp@2685:
fp@2685: static const u16 e1000_igp_2_cable_length_table[] = {
fp@2685: 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
fp@2685: 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
fp@2685: 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
fp@2685: 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
fp@2685: 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
fp@2685: 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
fp@2685: 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
fp@2685: 104, 109, 114, 118, 121, 124};
fp@2685: #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
fp@2685: (sizeof(e1000_igp_2_cable_length_table) / \
fp@2685: sizeof(e1000_igp_2_cable_length_table[0]))
fp@2685:
fp@2685: /**
fp@2685: * igb_check_reset_block - Check if PHY reset is blocked
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Read the PHY management control register and check whether a PHY reset
fp@2685: * is blocked. If a reset is not blocked return 0, otherwise
fp@2685: * return E1000_BLK_PHY_RESET (12).
fp@2685: **/
fp@2685: s32 igb_check_reset_block(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 manc;
fp@2685:
fp@2685: manc = rd32(E1000_MANC);
fp@2685:
fp@2685: return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_phy_id - Retrieve the PHY ID and revision
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Reads the PHY registers and stores the PHY ID and possibly the PHY
fp@2685: * revision in the hardware structure.
fp@2685: **/
fp@2685: s32 igb_get_phy_id(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u16 phy_id;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->id = (u32)(phy_id << 16);
fp@2685: udelay(20);
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
fp@2685: phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_reset_dsp - Reset PHY DSP
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Reset the digital signal processor.
fp@2685: **/
fp@2685: static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: if (!(hw->phy.ops.write_reg))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_phy_reg_mdic - Read MDI control register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to be read
fp@2685: * @data: pointer to the read data
fp@2685: *
fp@2685: * Reads the MDI control regsiter in the PHY at offset and stores the
fp@2685: * information read to data.
fp@2685: **/
fp@2685: s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: u32 i, mdic = 0;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: if (offset > MAX_PHY_REG_ADDRESS) {
fp@2685: hw_dbg("PHY Address %d is out of range\n", offset);
fp@2685: ret_val = -E1000_ERR_PARAM;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Set up Op-code, Phy Address, and register offset in the MDI
fp@2685: * Control register. The MAC will take care of interfacing with the
fp@2685: * PHY to retrieve the desired data.
fp@2685: */
fp@2685: mdic = ((offset << E1000_MDIC_REG_SHIFT) |
fp@2685: (phy->addr << E1000_MDIC_PHY_SHIFT) |
fp@2685: (E1000_MDIC_OP_READ));
fp@2685:
fp@2685: wr32(E1000_MDIC, mdic);
fp@2685:
fp@2685: /* Poll the ready bit to see if the MDI read completed
fp@2685: * Increasing the time out as testing showed failures with
fp@2685: * the lower time out
fp@2685: */
fp@2685: for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
fp@2685: udelay(50);
fp@2685: mdic = rd32(E1000_MDIC);
fp@2685: if (mdic & E1000_MDIC_READY)
fp@2685: break;
fp@2685: }
fp@2685: if (!(mdic & E1000_MDIC_READY)) {
fp@2685: hw_dbg("MDI Read did not complete\n");
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685: if (mdic & E1000_MDIC_ERROR) {
fp@2685: hw_dbg("MDI Error\n");
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685: *data = (u16) mdic;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_phy_reg_mdic - Write MDI control register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to write to
fp@2685: * @data: data to write to register at offset
fp@2685: *
fp@2685: * Writes data to MDI control register in the PHY at offset.
fp@2685: **/
fp@2685: s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: u32 i, mdic = 0;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: if (offset > MAX_PHY_REG_ADDRESS) {
fp@2685: hw_dbg("PHY Address %d is out of range\n", offset);
fp@2685: ret_val = -E1000_ERR_PARAM;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Set up Op-code, Phy Address, and register offset in the MDI
fp@2685: * Control register. The MAC will take care of interfacing with the
fp@2685: * PHY to retrieve the desired data.
fp@2685: */
fp@2685: mdic = (((u32)data) |
fp@2685: (offset << E1000_MDIC_REG_SHIFT) |
fp@2685: (phy->addr << E1000_MDIC_PHY_SHIFT) |
fp@2685: (E1000_MDIC_OP_WRITE));
fp@2685:
fp@2685: wr32(E1000_MDIC, mdic);
fp@2685:
fp@2685: /* Poll the ready bit to see if the MDI read completed
fp@2685: * Increasing the time out as testing showed failures with
fp@2685: * the lower time out
fp@2685: */
fp@2685: for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
fp@2685: udelay(50);
fp@2685: mdic = rd32(E1000_MDIC);
fp@2685: if (mdic & E1000_MDIC_READY)
fp@2685: break;
fp@2685: }
fp@2685: if (!(mdic & E1000_MDIC_READY)) {
fp@2685: hw_dbg("MDI Write did not complete\n");
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685: if (mdic & E1000_MDIC_ERROR) {
fp@2685: hw_dbg("MDI Error\n");
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_phy_reg_i2c - Read PHY register using i2c
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to be read
fp@2685: * @data: pointer to the read data
fp@2685: *
fp@2685: * Reads the PHY register at offset using the i2c interface and stores the
fp@2685: * retrieved information in data.
fp@2685: **/
fp@2685: s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: u32 i, i2ccmd = 0;
fp@2685:
fp@2685: /* Set up Op-code, Phy Address, and register address in the I2CCMD
fp@2685: * register. The MAC will take care of interfacing with the
fp@2685: * PHY to retrieve the desired data.
fp@2685: */
fp@2685: i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
fp@2685: (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
fp@2685: (E1000_I2CCMD_OPCODE_READ));
fp@2685:
fp@2685: wr32(E1000_I2CCMD, i2ccmd);
fp@2685:
fp@2685: /* Poll the ready bit to see if the I2C read completed */
fp@2685: for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
fp@2685: udelay(50);
fp@2685: i2ccmd = rd32(E1000_I2CCMD);
fp@2685: if (i2ccmd & E1000_I2CCMD_READY)
fp@2685: break;
fp@2685: }
fp@2685: if (!(i2ccmd & E1000_I2CCMD_READY)) {
fp@2685: hw_dbg("I2CCMD Read did not complete\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685: if (i2ccmd & E1000_I2CCMD_ERROR) {
fp@2685: hw_dbg("I2CCMD Error bit set\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685:
fp@2685: /* Need to byte-swap the 16-bit value. */
fp@2685: *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_phy_reg_i2c - Write PHY register using i2c
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to write to
fp@2685: * @data: data to write at register offset
fp@2685: *
fp@2685: * Writes the data to PHY register at the offset using the i2c interface.
fp@2685: **/
fp@2685: s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: u32 i, i2ccmd = 0;
fp@2685: u16 phy_data_swapped;
fp@2685:
fp@2685: /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
fp@2685: if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
fp@2685: hw_dbg("PHY I2C Address %d is out of range.\n",
fp@2685: hw->phy.addr);
fp@2685: return -E1000_ERR_CONFIG;
fp@2685: }
fp@2685:
fp@2685: /* Swap the data bytes for the I2C interface */
fp@2685: phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
fp@2685:
fp@2685: /* Set up Op-code, Phy Address, and register address in the I2CCMD
fp@2685: * register. The MAC will take care of interfacing with the
fp@2685: * PHY to retrieve the desired data.
fp@2685: */
fp@2685: i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
fp@2685: (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
fp@2685: E1000_I2CCMD_OPCODE_WRITE |
fp@2685: phy_data_swapped);
fp@2685:
fp@2685: wr32(E1000_I2CCMD, i2ccmd);
fp@2685:
fp@2685: /* Poll the ready bit to see if the I2C read completed */
fp@2685: for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
fp@2685: udelay(50);
fp@2685: i2ccmd = rd32(E1000_I2CCMD);
fp@2685: if (i2ccmd & E1000_I2CCMD_READY)
fp@2685: break;
fp@2685: }
fp@2685: if (!(i2ccmd & E1000_I2CCMD_READY)) {
fp@2685: hw_dbg("I2CCMD Write did not complete\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685: if (i2ccmd & E1000_I2CCMD_ERROR) {
fp@2685: hw_dbg("I2CCMD Error bit set\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_sfp_data_byte - Reads SFP module data.
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: byte location offset to be read
fp@2685: * @data: read data buffer pointer
fp@2685: *
fp@2685: * Reads one byte from SFP module data stored
fp@2685: * in SFP resided EEPROM memory or SFP diagnostic area.
fp@2685: * Function should be called with
fp@2685: * E1000_I2CCMD_SFP_DATA_ADDR() for SFP module database access
fp@2685: * E1000_I2CCMD_SFP_DIAG_ADDR() for SFP diagnostics parameters
fp@2685: * access
fp@2685: **/
fp@2685: s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
fp@2685: {
fp@2685: u32 i = 0;
fp@2685: u32 i2ccmd = 0;
fp@2685: u32 data_local = 0;
fp@2685:
fp@2685: if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
fp@2685: hw_dbg("I2CCMD command address exceeds upper limit\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685:
fp@2685: /* Set up Op-code, EEPROM Address,in the I2CCMD
fp@2685: * register. The MAC will take care of interfacing with the
fp@2685: * EEPROM to retrieve the desired data.
fp@2685: */
fp@2685: i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
fp@2685: E1000_I2CCMD_OPCODE_READ);
fp@2685:
fp@2685: wr32(E1000_I2CCMD, i2ccmd);
fp@2685:
fp@2685: /* Poll the ready bit to see if the I2C read completed */
fp@2685: for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
fp@2685: udelay(50);
fp@2685: data_local = rd32(E1000_I2CCMD);
fp@2685: if (data_local & E1000_I2CCMD_READY)
fp@2685: break;
fp@2685: }
fp@2685: if (!(data_local & E1000_I2CCMD_READY)) {
fp@2685: hw_dbg("I2CCMD Read did not complete\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685: if (data_local & E1000_I2CCMD_ERROR) {
fp@2685: hw_dbg("I2CCMD Error bit set\n");
fp@2685: return -E1000_ERR_PHY;
fp@2685: }
fp@2685: *data = (u8) data_local & 0xFF;
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_phy_reg_igp - Read igp PHY register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to be read
fp@2685: * @data: pointer to the read data
fp@2685: *
fp@2685: * Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2685: * and storing the retrieved information in data. Release any acquired
fp@2685: * semaphores before exiting.
fp@2685: **/
fp@2685: s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: if (!(hw->phy.ops.acquire))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2685: ret_val = igb_write_phy_reg_mdic(hw,
fp@2685: IGP01E1000_PHY_PAGE_SELECT,
fp@2685: (u16)offset);
fp@2685: if (ret_val) {
fp@2685: hw->phy.ops.release(hw);
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2685: data);
fp@2685:
fp@2685: hw->phy.ops.release(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_phy_reg_igp - Write igp PHY register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to write to
fp@2685: * @data: data to write at register offset
fp@2685: *
fp@2685: * Acquires semaphore, if necessary, then writes the data to PHY register
fp@2685: * at the offset. Release any acquired semaphores before exiting.
fp@2685: **/
fp@2685: s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: if (!(hw->phy.ops.acquire))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2685: ret_val = igb_write_phy_reg_mdic(hw,
fp@2685: IGP01E1000_PHY_PAGE_SELECT,
fp@2685: (u16)offset);
fp@2685: if (ret_val) {
fp@2685: hw->phy.ops.release(hw);
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2685: data);
fp@2685:
fp@2685: hw->phy.ops.release(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Sets up Carrier-sense on Transmit and downshift values.
fp@2685: **/
fp@2685: s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685:
fp@2685: if (phy->reset_disable) {
fp@2685: ret_val = 0;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if (phy->type == e1000_phy_82580) {
fp@2685: ret_val = hw->phy.ops.reset(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error resetting the PHY.\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /* Enable CRS on TX. This must be set for half-duplex operation. */
fp@2685: ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
fp@2685:
fp@2685: /* Enable downshift */
fp@2685: phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Set MDI/MDIX mode */
fp@2685: ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
fp@2685: /* Options:
fp@2685: * 0 - Auto (default)
fp@2685: * 1 - MDI mode
fp@2685: * 2 - MDI-X mode
fp@2685: */
fp@2685: switch (hw->phy.mdix) {
fp@2685: case 1:
fp@2685: break;
fp@2685: case 2:
fp@2685: phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
fp@2685: break;
fp@2685: case 0:
fp@2685: default:
fp@2685: phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
fp@2685: break;
fp@2685: }
fp@2685: ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
fp@2685: * and downshift values are set also.
fp@2685: **/
fp@2685: s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685:
fp@2685: if (phy->reset_disable) {
fp@2685: ret_val = 0;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Enable CRS on TX. This must be set for half-duplex operation. */
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
fp@2685:
fp@2685: /* Options:
fp@2685: * MDI/MDI-X = 0 (default)
fp@2685: * 0 - Auto for all speeds
fp@2685: * 1 - MDI mode
fp@2685: * 2 - MDI-X mode
fp@2685: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
fp@2685: */
fp@2685: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
fp@2685:
fp@2685: switch (phy->mdix) {
fp@2685: case 1:
fp@2685: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
fp@2685: break;
fp@2685: case 2:
fp@2685: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
fp@2685: break;
fp@2685: case 3:
fp@2685: phy_data |= M88E1000_PSCR_AUTO_X_1000T;
fp@2685: break;
fp@2685: case 0:
fp@2685: default:
fp@2685: phy_data |= M88E1000_PSCR_AUTO_X_MODE;
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: /* Options:
fp@2685: * disable_polarity_correction = 0 (default)
fp@2685: * Automatic Correction for Reversed Cable Polarity
fp@2685: * 0 - Disabled
fp@2685: * 1 - Enabled
fp@2685: */
fp@2685: phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
fp@2685: if (phy->disable_polarity_correction == 1)
fp@2685: phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (phy->revision < E1000_REVISION_4) {
fp@2685: /* Force TX_CLK in the Extended PHY Specific Control Register
fp@2685: * to 25MHz clock.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data |= M88E1000_EPSCR_TX_CLK_25;
fp@2685:
fp@2685: if ((phy->revision == E1000_REVISION_2) &&
fp@2685: (phy->id == M88E1111_I_PHY_ID)) {
fp@2685: /* 82573L PHY - set the downshift counter to 5x. */
fp@2685: phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
fp@2685: phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
fp@2685: } else {
fp@2685: /* Configure Master and Slave downshift values */
fp@2685: phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
fp@2685: M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
fp@2685: phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
fp@2685: M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
fp@2685: }
fp@2685: ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
fp@2685: phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Commit the changes. */
fp@2685: ret_val = igb_phy_sw_reset(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error committing the PHY changes\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
fp@2685: * Also enables and sets the downshift parameters.
fp@2685: **/
fp@2685: s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685:
fp@2685: if (phy->reset_disable)
fp@2685: return 0;
fp@2685:
fp@2685: /* Enable CRS on Tx. This must be set for half-duplex operation. */
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: /* Options:
fp@2685: * MDI/MDI-X = 0 (default)
fp@2685: * 0 - Auto for all speeds
fp@2685: * 1 - MDI mode
fp@2685: * 2 - MDI-X mode
fp@2685: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
fp@2685: */
fp@2685: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
fp@2685:
fp@2685: switch (phy->mdix) {
fp@2685: case 1:
fp@2685: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
fp@2685: break;
fp@2685: case 2:
fp@2685: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
fp@2685: break;
fp@2685: case 3:
fp@2685: /* M88E1112 does not support this mode) */
fp@2685: if (phy->id != M88E1112_E_PHY_ID) {
fp@2685: phy_data |= M88E1000_PSCR_AUTO_X_1000T;
fp@2685: break;
fp@2685: }
fp@2685: case 0:
fp@2685: default:
fp@2685: phy_data |= M88E1000_PSCR_AUTO_X_MODE;
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: /* Options:
fp@2685: * disable_polarity_correction = 0 (default)
fp@2685: * Automatic Correction for Reversed Cable Polarity
fp@2685: * 0 - Disabled
fp@2685: * 1 - Enabled
fp@2685: */
fp@2685: phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
fp@2685: if (phy->disable_polarity_correction == 1)
fp@2685: phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
fp@2685:
fp@2685: /* Enable downshift and setting it to X6 */
fp@2685: if (phy->id == M88E1543_E_PHY_ID) {
fp@2685: phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
fp@2685: ret_val =
fp@2685: phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: ret_val = igb_phy_sw_reset(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error committing the PHY changes\n");
fp@2685: return ret_val;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
fp@2685: phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
fp@2685: phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: /* Commit the changes. */
fp@2685: ret_val = igb_phy_sw_reset(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error committing the PHY changes\n");
fp@2685: return ret_val;
fp@2685: }
fp@2685: ret_val = igb_set_master_slave_mode(hw);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_copper_link_setup_igp - Setup igp PHY's for copper link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
fp@2685: * igp PHY's.
fp@2685: **/
fp@2685: s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685:
fp@2685: if (phy->reset_disable) {
fp@2685: ret_val = 0;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.reset(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error resetting the PHY.\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
fp@2685: * timeout issues when LFS is enabled.
fp@2685: */
fp@2685: msleep(100);
fp@2685:
fp@2685: /* The NVM settings will configure LPLU in D3 for
fp@2685: * non-IGP1 PHYs.
fp@2685: */
fp@2685: if (phy->type == e1000_phy_igp) {
fp@2685: /* disable lplu d3 during driver init */
fp@2685: if (phy->ops.set_d3_lplu_state)
fp@2685: ret_val = phy->ops.set_d3_lplu_state(hw, false);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error Disabling LPLU D3\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /* disable lplu d0 during driver init */
fp@2685: ret_val = phy->ops.set_d0_lplu_state(hw, false);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error Disabling LPLU D0\n");
fp@2685: goto out;
fp@2685: }
fp@2685: /* Configure mdi-mdix settings */
fp@2685: ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data &= ~IGP01E1000_PSCR_AUTO_MDIX;
fp@2685:
fp@2685: switch (phy->mdix) {
fp@2685: case 1:
fp@2685: data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
fp@2685: break;
fp@2685: case 2:
fp@2685: data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
fp@2685: break;
fp@2685: case 0:
fp@2685: default:
fp@2685: data |= IGP01E1000_PSCR_AUTO_MDIX;
fp@2685: break;
fp@2685: }
fp@2685: ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* set auto-master slave resolution settings */
fp@2685: if (hw->mac.autoneg) {
fp@2685: /* when autonegotiation advertisement is only 1000Mbps then we
fp@2685: * should disable SmartSpeed and enable Auto MasterSlave
fp@2685: * resolution as hardware default.
fp@2685: */
fp@2685: if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
fp@2685: /* Disable SmartSpeed */
fp@2685: ret_val = phy->ops.read_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG,
fp@2685: &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Set auto Master/Slave resolution process */
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data &= ~CR_1000T_MS_ENABLE;
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* load defaults for future use */
fp@2685: phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
fp@2685: ((data & CR_1000T_MS_VALUE) ?
fp@2685: e1000_ms_force_master :
fp@2685: e1000_ms_force_slave) :
fp@2685: e1000_ms_auto;
fp@2685:
fp@2685: switch (phy->ms_type) {
fp@2685: case e1000_ms_force_master:
fp@2685: data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
fp@2685: break;
fp@2685: case e1000_ms_force_slave:
fp@2685: data |= CR_1000T_MS_ENABLE;
fp@2685: data &= ~(CR_1000T_MS_VALUE);
fp@2685: break;
fp@2685: case e1000_ms_auto:
fp@2685: data &= ~CR_1000T_MS_ENABLE;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Performs initial bounds checking on autoneg advertisement parameter, then
fp@2685: * configure to advertise the full capability. Setup the PHY to autoneg
fp@2685: * and restart the negotiation process between the link partner. If
fp@2685: * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
fp@2685: **/
fp@2685: static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_ctrl;
fp@2685:
fp@2685: /* Perform some bounds checking on the autoneg advertisement
fp@2685: * parameter.
fp@2685: */
fp@2685: phy->autoneg_advertised &= phy->autoneg_mask;
fp@2685:
fp@2685: /* If autoneg_advertised is zero, we assume it was not defaulted
fp@2685: * by the calling code so we set to advertise full capability.
fp@2685: */
fp@2685: if (phy->autoneg_advertised == 0)
fp@2685: phy->autoneg_advertised = phy->autoneg_mask;
fp@2685:
fp@2685: hw_dbg("Reconfiguring auto-neg advertisement params\n");
fp@2685: ret_val = igb_phy_setup_autoneg(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error Setting up Auto-Negotiation\n");
fp@2685: goto out;
fp@2685: }
fp@2685: hw_dbg("Restarting Auto-Neg\n");
fp@2685:
fp@2685: /* Restart auto-negotiation by setting the Auto Neg Enable bit and
fp@2685: * the Auto Neg Restart bit in the PHY control register.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Does the user want to wait for Auto-Neg to complete here, or
fp@2685: * check at a later time (for example, callback routine).
fp@2685: */
fp@2685: if (phy->autoneg_wait_to_complete) {
fp@2685: ret_val = igb_wait_autoneg(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error while waiting for autoneg to complete\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: hw->mac.get_link_status = true;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Reads the MII auto-neg advertisement register and/or the 1000T control
fp@2685: * register and if the PHY is already setup for auto-negotiation, then
fp@2685: * return successful. Otherwise, setup advertisement and flow control to
fp@2685: * the appropriate values for the wanted auto-negotiation.
fp@2685: **/
fp@2685: static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 mii_autoneg_adv_reg;
fp@2685: u16 mii_1000t_ctrl_reg = 0;
fp@2685:
fp@2685: phy->autoneg_advertised &= phy->autoneg_mask;
fp@2685:
fp@2685: /* Read the MII Auto-Neg Advertisement Register (Address 4). */
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
fp@2685: /* Read the MII 1000Base-T Control Register (Address 9). */
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
fp@2685: &mii_1000t_ctrl_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Need to parse both autoneg_advertised and fc and set up
fp@2685: * the appropriate PHY registers. First we will parse for
fp@2685: * autoneg_advertised software override. Since we can advertise
fp@2685: * a plethora of combinations, we need to check each bit
fp@2685: * individually.
fp@2685: */
fp@2685:
fp@2685: /* First we clear all the 10/100 mb speed bits in the Auto-Neg
fp@2685: * Advertisement Register (Address 4) and the 1000 mb speed bits in
fp@2685: * the 1000Base-T Control Register (Address 9).
fp@2685: */
fp@2685: mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
fp@2685: NWAY_AR_100TX_HD_CAPS |
fp@2685: NWAY_AR_10T_FD_CAPS |
fp@2685: NWAY_AR_10T_HD_CAPS);
fp@2685: mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
fp@2685:
fp@2685: hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
fp@2685:
fp@2685: /* Do we want to advertise 10 Mb Half Duplex? */
fp@2685: if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
fp@2685: hw_dbg("Advertise 10mb Half duplex\n");
fp@2685: mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
fp@2685: }
fp@2685:
fp@2685: /* Do we want to advertise 10 Mb Full Duplex? */
fp@2685: if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
fp@2685: hw_dbg("Advertise 10mb Full duplex\n");
fp@2685: mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
fp@2685: }
fp@2685:
fp@2685: /* Do we want to advertise 100 Mb Half Duplex? */
fp@2685: if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
fp@2685: hw_dbg("Advertise 100mb Half duplex\n");
fp@2685: mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
fp@2685: }
fp@2685:
fp@2685: /* Do we want to advertise 100 Mb Full Duplex? */
fp@2685: if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
fp@2685: hw_dbg("Advertise 100mb Full duplex\n");
fp@2685: mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
fp@2685: }
fp@2685:
fp@2685: /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
fp@2685: if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
fp@2685: hw_dbg("Advertise 1000mb Half duplex request denied!\n");
fp@2685:
fp@2685: /* Do we want to advertise 1000 Mb Full Duplex? */
fp@2685: if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
fp@2685: hw_dbg("Advertise 1000mb Full duplex\n");
fp@2685: mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
fp@2685: }
fp@2685:
fp@2685: /* Check for a software override of the flow control settings, and
fp@2685: * setup the PHY advertisement registers accordingly. If
fp@2685: * auto-negotiation is enabled, then software will have to set the
fp@2685: * "PAUSE" bits to the correct value in the Auto-Negotiation
fp@2685: * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
fp@2685: * negotiation.
fp@2685: *
fp@2685: * The possible values of the "fc" parameter are:
fp@2685: * 0: Flow control is completely disabled
fp@2685: * 1: Rx flow control is enabled (we can receive pause frames
fp@2685: * but not send pause frames).
fp@2685: * 2: Tx flow control is enabled (we can send pause frames
fp@2685: * but we do not support receiving pause frames).
fp@2685: * 3: Both Rx and TX flow control (symmetric) are enabled.
fp@2685: * other: No software override. The flow control configuration
fp@2685: * in the EEPROM is used.
fp@2685: */
fp@2685: switch (hw->fc.current_mode) {
fp@2685: case e1000_fc_none:
fp@2685: /* Flow control (RX & TX) is completely disabled by a
fp@2685: * software over-ride.
fp@2685: */
fp@2685: mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
fp@2685: break;
fp@2685: case e1000_fc_rx_pause:
fp@2685: /* RX Flow control is enabled, and TX Flow control is
fp@2685: * disabled, by a software over-ride.
fp@2685: *
fp@2685: * Since there really isn't a way to advertise that we are
fp@2685: * capable of RX Pause ONLY, we will advertise that we
fp@2685: * support both symmetric and asymmetric RX PAUSE. Later
fp@2685: * (in e1000_config_fc_after_link_up) we will disable the
fp@2685: * hw's ability to send PAUSE frames.
fp@2685: */
fp@2685: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
fp@2685: break;
fp@2685: case e1000_fc_tx_pause:
fp@2685: /* TX Flow control is enabled, and RX Flow control is
fp@2685: * disabled, by a software over-ride.
fp@2685: */
fp@2685: mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
fp@2685: mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
fp@2685: break;
fp@2685: case e1000_fc_full:
fp@2685: /* Flow control (both RX and TX) is enabled by a software
fp@2685: * over-ride.
fp@2685: */
fp@2685: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
fp@2685: break;
fp@2685: default:
fp@2685: hw_dbg("Flow control param set incorrectly\n");
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
fp@2685:
fp@2685: if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: PHY_1000T_CTRL,
fp@2685: mii_1000t_ctrl_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_setup_copper_link - Configure copper link settings
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Calls the appropriate function to configure the link for auto-neg or forced
fp@2685: * speed and duplex. Then we check for link, once link is established calls
fp@2685: * to configure collision distance and flow control are called. If link is
fp@2685: * not established, we return -E1000_ERR_PHY (-2).
fp@2685: **/
fp@2685: s32 igb_setup_copper_link(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: bool link;
fp@2685:
fp@2685: if (hw->mac.autoneg) {
fp@2685: /* Setup autoneg and flow control advertisement and perform
fp@2685: * autonegotiation.
fp@2685: */
fp@2685: ret_val = igb_copper_link_autoneg(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: } else {
fp@2685: /* PHY will be set to 10H, 10F, 100H or 100F
fp@2685: * depending on user settings.
fp@2685: */
fp@2685: hw_dbg("Forcing Speed and Duplex\n");
fp@2685: ret_val = hw->phy.ops.force_speed_duplex(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error Forcing Speed and Duplex\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /* Check link status. Wait up to 100 microseconds for link to become
fp@2685: * valid.
fp@2685: */
fp@2685: ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (link) {
fp@2685: hw_dbg("Valid link established!!!\n");
fp@2685: igb_config_collision_dist(hw);
fp@2685: ret_val = igb_config_fc_after_link_up(hw);
fp@2685: } else {
fp@2685: hw_dbg("Unable to establish link!!!\n");
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Calls the PHY setup function to force speed and duplex. Clears the
fp@2685: * auto-crossover to force MDI manually. Waits for link and returns
fp@2685: * successful if link up is successful, else -E1000_ERR_PHY (-2).
fp@2685: **/
fp@2685: s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685: bool link;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: igb_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
fp@2685: * forced whenever speed and duplex are forced.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
fp@2685: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: hw_dbg("IGP PSCR: %X\n", phy_data);
fp@2685:
fp@2685: udelay(1);
fp@2685:
fp@2685: if (phy->autoneg_wait_to_complete) {
fp@2685: hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
fp@2685:
fp@2685: ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link)
fp@2685: hw_dbg("Link taking longer than expected.\n");
fp@2685:
fp@2685: /* Try once more */
fp@2685: ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Calls the PHY setup function to force speed and duplex. Clears the
fp@2685: * auto-crossover to force MDI manually. Resets the PHY to commit the
fp@2685: * changes. If time expires while waiting for link up, we reset the DSP.
fp@2685: * After reset, TX_CLK and CRS on TX must be set. Return successful upon
fp@2685: * successful completion, else return corresponding error code.
fp@2685: **/
fp@2685: s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685: bool link;
fp@2685:
fp@2685: /* I210 and I211 devices support Auto-Crossover in forced operation. */
fp@2685: if (phy->type != e1000_phy_i210) {
fp@2685: /* Clear Auto-Crossover to force MDI manually. M88E1000
fp@2685: * requires MDI forced whenever speed and duplex are forced.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
fp@2685: ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
fp@2685: phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: hw_dbg("M88E1000 PSCR: %X\n", phy_data);
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: igb_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Reset the phy to commit changes. */
fp@2685: ret_val = igb_phy_sw_reset(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (phy->autoneg_wait_to_complete) {
fp@2685: hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
fp@2685:
fp@2685: ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link) {
fp@2685: bool reset_dsp = true;
fp@2685:
fp@2685: switch (hw->phy.id) {
fp@2685: case I347AT4_E_PHY_ID:
fp@2685: case M88E1112_E_PHY_ID:
fp@2685: case I210_I_PHY_ID:
fp@2685: reset_dsp = false;
fp@2685: break;
fp@2685: default:
fp@2685: if (hw->phy.type != e1000_phy_m88)
fp@2685: reset_dsp = false;
fp@2685: break;
fp@2685: }
fp@2685: if (!reset_dsp)
fp@2685: hw_dbg("Link taking longer than expected.\n");
fp@2685: else {
fp@2685: /* We didn't get link.
fp@2685: * Reset the DSP and cross our fingers.
fp@2685: */
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: M88E1000_PHY_PAGE_SELECT,
fp@2685: 0x001d);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: ret_val = igb_phy_reset_dsp(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /* Try once more */
fp@2685: ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
fp@2685: 100000, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if (hw->phy.type != e1000_phy_m88 ||
fp@2685: hw->phy.id == I347AT4_E_PHY_ID ||
fp@2685: hw->phy.id == M88E1112_E_PHY_ID ||
fp@2685: hw->phy.id == I210_I_PHY_ID)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Resetting the phy means we need to re-force TX_CLK in the
fp@2685: * Extended PHY Specific Control Register to 25MHz clock from
fp@2685: * the reset value of 2.5MHz.
fp@2685: */
fp@2685: phy_data |= M88E1000_EPSCR_TX_CLK_25;
fp@2685: ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* In addition, we must re-enable CRS on Tx for both half and full
fp@2685: * duplex.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
fp@2685: ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @phy_ctrl: pointer to current value of PHY_CONTROL
fp@2685: *
fp@2685: * Forces speed and duplex on the PHY by doing the following: disable flow
fp@2685: * control, force speed/duplex on the MAC, disable auto speed detection,
fp@2685: * disable auto-negotiation, configure duplex, configure speed, configure
fp@2685: * the collision distance, write configuration to CTRL register. The
fp@2685: * caller must write to the PHY_CONTROL register for these settings to
fp@2685: * take affect.
fp@2685: **/
fp@2685: static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
fp@2685: u16 *phy_ctrl)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: u32 ctrl;
fp@2685:
fp@2685: /* Turn off flow control when forcing speed/duplex */
fp@2685: hw->fc.current_mode = e1000_fc_none;
fp@2685:
fp@2685: /* Force speed/duplex on the mac */
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
fp@2685: ctrl &= ~E1000_CTRL_SPD_SEL;
fp@2685:
fp@2685: /* Disable Auto Speed Detection */
fp@2685: ctrl &= ~E1000_CTRL_ASDE;
fp@2685:
fp@2685: /* Disable autoneg on the phy */
fp@2685: *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
fp@2685:
fp@2685: /* Forcing Full or Half Duplex? */
fp@2685: if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
fp@2685: ctrl &= ~E1000_CTRL_FD;
fp@2685: *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
fp@2685: hw_dbg("Half Duplex\n");
fp@2685: } else {
fp@2685: ctrl |= E1000_CTRL_FD;
fp@2685: *phy_ctrl |= MII_CR_FULL_DUPLEX;
fp@2685: hw_dbg("Full Duplex\n");
fp@2685: }
fp@2685:
fp@2685: /* Forcing 10mb or 100mb? */
fp@2685: if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
fp@2685: ctrl |= E1000_CTRL_SPD_100;
fp@2685: *phy_ctrl |= MII_CR_SPEED_100;
fp@2685: *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
fp@2685: hw_dbg("Forcing 100mb\n");
fp@2685: } else {
fp@2685: ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
fp@2685: *phy_ctrl |= MII_CR_SPEED_10;
fp@2685: *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
fp@2685: hw_dbg("Forcing 10mb\n");
fp@2685: }
fp@2685:
fp@2685: igb_config_collision_dist(hw);
fp@2685:
fp@2685: wr32(E1000_CTRL, ctrl);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_d3_lplu_state - Sets low power link up state for D3
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @active: boolean used to enable/disable lplu
fp@2685: *
fp@2685: * Success returns 0, Failure returns 1
fp@2685: *
fp@2685: * The low power link up (lplu) state is set to the power management level D3
fp@2685: * and SmartSpeed is disabled when active is true, else clear lplu for D3
fp@2685: * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
fp@2685: * is used during Dx states where the power conservation is most important.
fp@2685: * During driver activity, SmartSpeed should be enabled so performance is
fp@2685: * maintained.
fp@2685: **/
fp@2685: s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u16 data;
fp@2685:
fp@2685: if (!(hw->phy.ops.read_reg))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!active) {
fp@2685: data &= ~IGP02E1000_PM_D3_LPLU;
fp@2685: ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
fp@2685: * during Dx states where the power conservation is most
fp@2685: * important. During driver activity we should enable
fp@2685: * SmartSpeed, so performance is maintained.
fp@2685: */
fp@2685: if (phy->smart_speed == e1000_smart_speed_on) {
fp@2685: ret_val = phy->ops.read_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG,
fp@2685: &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data |= IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: } else if (phy->smart_speed == e1000_smart_speed_off) {
fp@2685: ret_val = phy->ops.read_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG,
fp@2685: &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685: } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
fp@2685: (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
fp@2685: (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
fp@2685: data |= IGP02E1000_PM_D3_LPLU;
fp@2685: ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* When LPLU is enabled, we should disable SmartSpeed */
fp@2685: ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2685: &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2685: data);
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_downshift - Checks whether a downshift in speed occurred
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Success returns 0, Failure returns 1
fp@2685: *
fp@2685: * A downshift is detected by querying the PHY link health.
fp@2685: **/
fp@2685: s32 igb_check_downshift(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data, offset, mask;
fp@2685:
fp@2685: switch (phy->type) {
fp@2685: case e1000_phy_i210:
fp@2685: case e1000_phy_m88:
fp@2685: case e1000_phy_gg82563:
fp@2685: offset = M88E1000_PHY_SPEC_STATUS;
fp@2685: mask = M88E1000_PSSR_DOWNSHIFT;
fp@2685: break;
fp@2685: case e1000_phy_igp_2:
fp@2685: case e1000_phy_igp:
fp@2685: case e1000_phy_igp_3:
fp@2685: offset = IGP01E1000_PHY_LINK_HEALTH;
fp@2685: mask = IGP01E1000_PLHR_SS_DOWNGRADE;
fp@2685: break;
fp@2685: default:
fp@2685: /* speed downshift not supported */
fp@2685: phy->speed_downgraded = false;
fp@2685: ret_val = 0;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, offset, &phy_data);
fp@2685:
fp@2685: if (!ret_val)
fp@2685: phy->speed_downgraded = (phy_data & mask) ? true : false;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_polarity_m88 - Checks the polarity.
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2685: *
fp@2685: * Polarity is determined based on the PHY specific status register.
fp@2685: **/
fp@2685: s32 igb_check_polarity_m88(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
fp@2685:
fp@2685: if (!ret_val)
fp@2685: phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
fp@2685: ? e1000_rev_polarity_reversed
fp@2685: : e1000_rev_polarity_normal;
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_polarity_igp - Checks the polarity.
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2685: *
fp@2685: * Polarity is determined based on the PHY port status register, and the
fp@2685: * current speed (since there is no polarity at 100Mbps).
fp@2685: **/
fp@2685: static s32 igb_check_polarity_igp(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data, offset, mask;
fp@2685:
fp@2685: /* Polarity is determined based on the speed of
fp@2685: * our connection.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
fp@2685: IGP01E1000_PSSR_SPEED_1000MBPS) {
fp@2685: offset = IGP01E1000_PHY_PCS_INIT_REG;
fp@2685: mask = IGP01E1000_PHY_POLARITY_MASK;
fp@2685: } else {
fp@2685: /* This really only applies to 10Mbps since
fp@2685: * there is no polarity for 100Mbps (always 0).
fp@2685: */
fp@2685: offset = IGP01E1000_PHY_PORT_STATUS;
fp@2685: mask = IGP01E1000_PSSR_POLARITY_REVERSED;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, offset, &data);
fp@2685:
fp@2685: if (!ret_val)
fp@2685: phy->cable_polarity = (data & mask)
fp@2685: ? e1000_rev_polarity_reversed
fp@2685: : e1000_rev_polarity_normal;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_wait_autoneg - Wait for auto-neg completion
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Waits for auto-negotiation to complete or for the auto-negotiation time
fp@2685: * limit to expire, which ever happens first.
fp@2685: **/
fp@2685: static s32 igb_wait_autoneg(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 i, phy_status;
fp@2685:
fp@2685: /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
fp@2685: for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
fp@2685: if (ret_val)
fp@2685: break;
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
fp@2685: if (ret_val)
fp@2685: break;
fp@2685: if (phy_status & MII_SR_AUTONEG_COMPLETE)
fp@2685: break;
fp@2685: msleep(100);
fp@2685: }
fp@2685:
fp@2685: /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
fp@2685: * has completed.
fp@2685: */
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_has_link - Polls PHY for link
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @iterations: number of times to poll for link
fp@2685: * @usec_interval: delay between polling attempts
fp@2685: * @success: pointer to whether polling was successful or not
fp@2685: *
fp@2685: * Polls the PHY status register for link, 'iterations' number of times.
fp@2685: **/
fp@2685: s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
fp@2685: u32 usec_interval, bool *success)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 i, phy_status;
fp@2685:
fp@2685: for (i = 0; i < iterations; i++) {
fp@2685: /* Some PHYs require the PHY_STATUS register to be read
fp@2685: * twice due to the link bit being sticky. No harm doing
fp@2685: * it across the board.
fp@2685: */
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
fp@2685: if (ret_val && usec_interval > 0) {
fp@2685: /* If the first read fails, another entity may have
fp@2685: * ownership of the resources, wait and try again to
fp@2685: * see if they have relinquished the resources yet.
fp@2685: */
fp@2685: if (usec_interval >= 1000)
fp@2685: mdelay(usec_interval/1000);
fp@2685: else
fp@2685: udelay(usec_interval);
fp@2685: }
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
fp@2685: if (ret_val)
fp@2685: break;
fp@2685: if (phy_status & MII_SR_LINK_STATUS)
fp@2685: break;
fp@2685: if (usec_interval >= 1000)
fp@2685: mdelay(usec_interval/1000);
fp@2685: else
fp@2685: udelay(usec_interval);
fp@2685: }
fp@2685:
fp@2685: *success = (i < iterations) ? true : false;
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_cable_length_m88 - Determine cable length for m88 PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Reads the PHY specific status register to retrieve the cable length
fp@2685: * information. The cable length is determined by averaging the minimum and
fp@2685: * maximum values to get the "average" cable length. The m88 PHY has four
fp@2685: * possible cable length values, which are:
fp@2685: * Register Value Cable Length
fp@2685: * 0 < 50 meters
fp@2685: * 1 50 - 80 meters
fp@2685: * 2 80 - 110 meters
fp@2685: * 3 110 - 140 meters
fp@2685: * 4 > 140 meters
fp@2685: **/
fp@2685: s32 igb_get_cable_length_m88(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data, index;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
fp@2685: M88E1000_PSSR_CABLE_LENGTH_SHIFT;
fp@2685: if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: phy->min_cable_length = e1000_m88_cable_length_table[index];
fp@2685: phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
fp@2685:
fp@2685: phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data, phy_data2, index, default_page, is_cm;
fp@2685:
fp@2685: switch (hw->phy.id) {
fp@2685: case I210_I_PHY_ID:
fp@2685: /* Get cable length from PHY Cable Diagnostics Control Reg */
fp@2685: ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
fp@2685: (I347AT4_PCDL + phy->addr),
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: /* Check if the unit of cable length is meters or cm */
fp@2685: ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
fp@2685: I347AT4_PCDC, &phy_data2);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
fp@2685:
fp@2685: /* Populate the phy structure with cable length in meters */
fp@2685: phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
fp@2685: phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
fp@2685: phy->cable_length = phy_data / (is_cm ? 100 : 1);
fp@2685: break;
fp@2685: case M88E1543_E_PHY_ID:
fp@2685: case I347AT4_E_PHY_ID:
fp@2685: /* Remember the original page select and set it to 7 */
fp@2685: ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
fp@2685: &default_page);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Get cable length from PHY Cable Diagnostics Control Reg */
fp@2685: ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Check if the unit of cable length is meters or cm */
fp@2685: ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
fp@2685:
fp@2685: /* Populate the phy structure with cable length in meters */
fp@2685: phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
fp@2685: phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
fp@2685: phy->cable_length = phy_data / (is_cm ? 100 : 1);
fp@2685:
fp@2685: /* Reset the page selec to its original value */
fp@2685: ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
fp@2685: default_page);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: break;
fp@2685: case M88E1112_E_PHY_ID:
fp@2685: /* Remember the original page select and set it to 5 */
fp@2685: ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
fp@2685: &default_page);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
fp@2685: M88E1000_PSSR_CABLE_LENGTH_SHIFT;
fp@2685: if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: phy->min_cable_length = e1000_m88_cable_length_table[index];
fp@2685: phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
fp@2685:
fp@2685: phy->cable_length = (phy->min_cable_length +
fp@2685: phy->max_cable_length) / 2;
fp@2685:
fp@2685: /* Reset the page select to its original value */
fp@2685: ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
fp@2685: default_page);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: break;
fp@2685: default:
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * The automatic gain control (agc) normalizes the amplitude of the
fp@2685: * received signal, adjusting for the attenuation produced by the
fp@2685: * cable. By reading the AGC registers, which represent the
fp@2685: * combination of coarse and fine gain value, the value can be put
fp@2685: * into a lookup table to obtain the approximate cable length
fp@2685: * for each channel.
fp@2685: **/
fp@2685: s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u16 phy_data, i, agc_value = 0;
fp@2685: u16 cur_agc_index, max_agc_index = 0;
fp@2685: u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
fp@2685: static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
fp@2685: IGP02E1000_PHY_AGC_A,
fp@2685: IGP02E1000_PHY_AGC_B,
fp@2685: IGP02E1000_PHY_AGC_C,
fp@2685: IGP02E1000_PHY_AGC_D
fp@2685: };
fp@2685:
fp@2685: /* Read the AGC registers for all channels */
fp@2685: for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
fp@2685: ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Getting bits 15:9, which represent the combination of
fp@2685: * coarse and fine gain values. The result is a number
fp@2685: * that can be put into the lookup table to obtain the
fp@2685: * approximate cable length.
fp@2685: */
fp@2685: cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
fp@2685: IGP02E1000_AGC_LENGTH_MASK;
fp@2685:
fp@2685: /* Array index bound check. */
fp@2685: if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
fp@2685: (cur_agc_index == 0)) {
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Remove min & max AGC values from calculation. */
fp@2685: if (e1000_igp_2_cable_length_table[min_agc_index] >
fp@2685: e1000_igp_2_cable_length_table[cur_agc_index])
fp@2685: min_agc_index = cur_agc_index;
fp@2685: if (e1000_igp_2_cable_length_table[max_agc_index] <
fp@2685: e1000_igp_2_cable_length_table[cur_agc_index])
fp@2685: max_agc_index = cur_agc_index;
fp@2685:
fp@2685: agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
fp@2685: }
fp@2685:
fp@2685: agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
fp@2685: e1000_igp_2_cable_length_table[max_agc_index]);
fp@2685: agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
fp@2685:
fp@2685: /* Calculate cable length with the error range of +/- 10 meters. */
fp@2685: phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
fp@2685: (agc_value - IGP02E1000_AGC_RANGE) : 0;
fp@2685: phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
fp@2685:
fp@2685: phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_phy_info_m88 - Retrieve PHY information
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Valid for only copper links. Read the PHY status register (sticky read)
fp@2685: * to verify that link is up. Read the PHY special control register to
fp@2685: * determine the polarity and 10base-T extended distance. Read the PHY
fp@2685: * special status register to determine MDI/MDIx and current speed. If
fp@2685: * speed is 1000, then determine cable length, local and remote receiver.
fp@2685: **/
fp@2685: s32 igb_get_phy_info_m88(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685: bool link;
fp@2685:
fp@2685: if (phy->media_type != e1000_media_type_copper) {
fp@2685: hw_dbg("Phy info is only valid for copper media\n");
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = igb_phy_has_link(hw, 1, 0, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link) {
fp@2685: hw_dbg("Phy info is only valid if link is up\n");
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
fp@2685: ? true : false;
fp@2685:
fp@2685: ret_val = igb_check_polarity_m88(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
fp@2685:
fp@2685: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
fp@2685: ret_val = phy->ops.get_cable_length(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
fp@2685: ? e1000_1000t_rx_status_ok
fp@2685: : e1000_1000t_rx_status_not_ok;
fp@2685:
fp@2685: phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
fp@2685: ? e1000_1000t_rx_status_ok
fp@2685: : e1000_1000t_rx_status_not_ok;
fp@2685: } else {
fp@2685: /* Set values to "undefined" */
fp@2685: phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
fp@2685: phy->local_rx = e1000_1000t_rx_status_undefined;
fp@2685: phy->remote_rx = e1000_1000t_rx_status_undefined;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_phy_info_igp - Retrieve igp PHY information
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Read PHY status to determine if link is up. If link is up, then
fp@2685: * set/determine 10base-T extended distance and polarity correction. Read
fp@2685: * PHY port status to determine MDI/MDIx and speed. Based on the speed,
fp@2685: * determine on the cable length, local and remote receiver.
fp@2685: **/
fp@2685: s32 igb_get_phy_info_igp(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685: bool link;
fp@2685:
fp@2685: ret_val = igb_phy_has_link(hw, 1, 0, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link) {
fp@2685: hw_dbg("Phy info is only valid if link is up\n");
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: phy->polarity_correction = true;
fp@2685:
fp@2685: ret_val = igb_check_polarity_igp(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
fp@2685:
fp@2685: if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
fp@2685: IGP01E1000_PSSR_SPEED_1000MBPS) {
fp@2685: ret_val = phy->ops.get_cable_length(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
fp@2685: ? e1000_1000t_rx_status_ok
fp@2685: : e1000_1000t_rx_status_not_ok;
fp@2685:
fp@2685: phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
fp@2685: ? e1000_1000t_rx_status_ok
fp@2685: : e1000_1000t_rx_status_not_ok;
fp@2685: } else {
fp@2685: phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
fp@2685: phy->local_rx = e1000_1000t_rx_status_undefined;
fp@2685: phy->remote_rx = e1000_1000t_rx_status_undefined;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_sw_reset - PHY software reset
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Does a software reset of the PHY by reading the PHY control register and
fp@2685: * setting/write the control register reset bit to the PHY.
fp@2685: **/
fp@2685: s32 igb_phy_sw_reset(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 phy_ctrl;
fp@2685:
fp@2685: if (!(hw->phy.ops.read_reg))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_ctrl |= MII_CR_RESET;
fp@2685: ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: udelay(1);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_hw_reset - PHY hardware reset
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Verify the reset block is not blocking us from resetting. Acquire
fp@2685: * semaphore (if necessary) and read/set/write the device control reset
fp@2685: * bit in the PHY. Wait the appropriate delay time for the device to
fp@2685: * reset and release the semaphore (if necessary).
fp@2685: **/
fp@2685: s32 igb_phy_hw_reset(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u32 ctrl;
fp@2685:
fp@2685: ret_val = igb_check_reset_block(hw);
fp@2685: if (ret_val) {
fp@2685: ret_val = 0;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = phy->ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685: wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
fp@2685: wrfl();
fp@2685:
fp@2685: udelay(phy->reset_delay_us);
fp@2685:
fp@2685: wr32(E1000_CTRL, ctrl);
fp@2685: wrfl();
fp@2685:
fp@2685: udelay(150);
fp@2685:
fp@2685: phy->ops.release(hw);
fp@2685:
fp@2685: ret_val = phy->ops.get_cfg_done(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_init_script_igp3 - Inits the IGP3 PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
fp@2685: **/
fp@2685: s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
fp@2685: {
fp@2685: hw_dbg("Running IGP 3 PHY init script\n");
fp@2685:
fp@2685: /* PHY init IGP 3 */
fp@2685: /* Enable rise/fall, 10-mode work in class-A */
fp@2685: hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
fp@2685: /* Remove all caps from Replica path filter */
fp@2685: hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
fp@2685: /* Bias trimming for ADC, AFE and Driver (Default) */
fp@2685: hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
fp@2685: /* Increase Hybrid poly bias */
fp@2685: hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
fp@2685: /* Add 4% to TX amplitude in Giga mode */
fp@2685: hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
fp@2685: /* Disable trimming (TTT) */
fp@2685: hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
fp@2685: /* Poly DC correction to 94.6% + 2% for all channels */
fp@2685: hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
fp@2685: /* ABS DC correction to 95.9% */
fp@2685: hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
fp@2685: /* BG temp curve trim */
fp@2685: hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
fp@2685: /* Increasing ADC OPAMP stage 1 currents to max */
fp@2685: hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
fp@2685: /* Force 1000 ( required for enabling PHY regs configuration) */
fp@2685: hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
fp@2685: /* Set upd_freq to 6 */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
fp@2685: /* Disable NPDFE */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
fp@2685: /* Disable adaptive fixed FFE (Default) */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
fp@2685: /* Enable FFE hysteresis */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
fp@2685: /* Fixed FFE for short cable lengths */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
fp@2685: /* Fixed FFE for medium cable lengths */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
fp@2685: /* Fixed FFE for long cable lengths */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
fp@2685: /* Enable Adaptive Clip Threshold */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
fp@2685: /* AHT reset limit to 1 */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
fp@2685: /* Set AHT master delay to 127 msec */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
fp@2685: /* Set scan bits for AHT */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
fp@2685: /* Set AHT Preset bits */
fp@2685: hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
fp@2685: /* Change integ_factor of channel A to 3 */
fp@2685: hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
fp@2685: /* Change prop_factor of channels BCD to 8 */
fp@2685: hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
fp@2685: /* Change cg_icount + enable integbp for channels BCD */
fp@2685: hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
fp@2685: /* Change cg_icount + enable integbp + change prop_factor_master
fp@2685: * to 8 for channel A
fp@2685: */
fp@2685: hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
fp@2685: /* Disable AHT in Slave mode on channel A */
fp@2685: hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
fp@2685: /* Enable LPLU and disable AN to 1000 in non-D0a states,
fp@2685: * Enable SPD+B2B
fp@2685: */
fp@2685: hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
fp@2685: /* Enable restart AN on an1000_dis change */
fp@2685: hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
fp@2685: /* Enable wh_fifo read clock in 10/100 modes */
fp@2685: hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
fp@2685: /* Restart AN, Speed selection is 1000 */
fp@2685: hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_power_up_phy_copper - Restore copper link in case of PHY power down
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * In the case of a PHY power down to save power, or to turn off link during a
fp@2685: * driver unload, restore the link to previous settings.
fp@2685: **/
fp@2685: void igb_power_up_phy_copper(struct e1000_hw *hw)
fp@2685: {
fp@2685: u16 mii_reg = 0;
fp@2685:
fp@2685: /* The PHY will retain its settings across a power down/up cycle */
fp@2685: hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
fp@2685: mii_reg &= ~MII_CR_POWER_DOWN;
fp@2685: hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_power_down_phy_copper - Power down copper PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Power down PHY to save power when interface is down and wake on lan
fp@2685: * is not enabled.
fp@2685: **/
fp@2685: void igb_power_down_phy_copper(struct e1000_hw *hw)
fp@2685: {
fp@2685: u16 mii_reg = 0;
fp@2685:
fp@2685: /* The PHY will retain its settings across a power down/up cycle */
fp@2685: hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
fp@2685: mii_reg |= MII_CR_POWER_DOWN;
fp@2685: hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
fp@2685: usleep_range(1000, 2000);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_polarity_82580 - Checks the polarity.
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2685: *
fp@2685: * Polarity is determined based on the PHY specific status register.
fp@2685: **/
fp@2685: static s32 igb_check_polarity_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685:
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
fp@2685:
fp@2685: if (!ret_val)
fp@2685: phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
fp@2685: ? e1000_rev_polarity_reversed
fp@2685: : e1000_rev_polarity_normal;
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Calls the PHY setup function to force speed and duplex. Clears the
fp@2685: * auto-crossover to force MDI manually. Waits for link and returns
fp@2685: * successful if link up is successful, else -E1000_ERR_PHY (-2).
fp@2685: **/
fp@2685: s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685: bool link;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: igb_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
fp@2685: * forced whenever speed and duplex are forced.
fp@2685: */
fp@2685: ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
fp@2685:
fp@2685: udelay(1);
fp@2685:
fp@2685: if (phy->autoneg_wait_to_complete) {
fp@2685: hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
fp@2685:
fp@2685: ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link)
fp@2685: hw_dbg("Link taking longer than expected.\n");
fp@2685:
fp@2685: /* Try once more */
fp@2685: ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_phy_info_82580 - Retrieve I82580 PHY information
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Read PHY status to determine if link is up. If link is up, then
fp@2685: * set/determine 10base-T extended distance and polarity correction. Read
fp@2685: * PHY port status to determine MDI/MDIx and speed. Based on the speed,
fp@2685: * determine on the cable length, local and remote receiver.
fp@2685: **/
fp@2685: s32 igb_get_phy_info_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685: bool link;
fp@2685:
fp@2685: ret_val = igb_phy_has_link(hw, 1, 0, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link) {
fp@2685: hw_dbg("Phy info is only valid if link is up\n");
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: phy->polarity_correction = true;
fp@2685:
fp@2685: ret_val = igb_check_polarity_82580(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
fp@2685:
fp@2685: if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
fp@2685: I82580_PHY_STATUS2_SPEED_1000MBPS) {
fp@2685: ret_val = hw->phy.ops.get_cable_length(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
fp@2685: ? e1000_1000t_rx_status_ok
fp@2685: : e1000_1000t_rx_status_not_ok;
fp@2685:
fp@2685: phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
fp@2685: ? e1000_1000t_rx_status_ok
fp@2685: : e1000_1000t_rx_status_not_ok;
fp@2685: } else {
fp@2685: phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
fp@2685: phy->local_rx = e1000_1000t_rx_status_undefined;
fp@2685: phy->remote_rx = e1000_1000t_rx_status_undefined;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Reads the diagnostic status register and verifies result is valid before
fp@2685: * placing it in the phy_cable_length field.
fp@2685: **/
fp@2685: s32 igb_get_cable_length_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 phy_data, length;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
fp@2685: I82580_DSTATUS_CABLE_LENGTH_SHIFT;
fp@2685:
fp@2685: if (length == E1000_CABLE_LENGTH_UNDEFINED)
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685:
fp@2685: phy->cable_length = length;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_phy_reg_gs40g - Write GS40G PHY register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: lower half is register offset to write to
fp@2685: * upper half is page to use.
fp@2685: * @data: data to write at register offset
fp@2685: *
fp@2685: * Acquires semaphore, if necessary, then writes the data to PHY register
fp@2685: * at the offset. Release any acquired semaphores before exiting.
fp@2685: **/
fp@2685: s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: u16 page = offset >> GS40G_PAGE_SHIFT;
fp@2685:
fp@2685: offset = offset & GS40G_OFFSET_MASK;
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
fp@2685: if (ret_val)
fp@2685: goto release;
fp@2685: ret_val = igb_write_phy_reg_mdic(hw, offset, data);
fp@2685:
fp@2685: release:
fp@2685: hw->phy.ops.release(hw);
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_phy_reg_gs40g - Read GS40G PHY register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: lower half is register offset to read to
fp@2685: * upper half is page to use.
fp@2685: * @data: data to read at register offset
fp@2685: *
fp@2685: * Acquires semaphore, if necessary, then reads the data in the PHY register
fp@2685: * at the offset. Release any acquired semaphores before exiting.
fp@2685: **/
fp@2685: s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: u16 page = offset >> GS40G_PAGE_SHIFT;
fp@2685:
fp@2685: offset = offset & GS40G_OFFSET_MASK;
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
fp@2685: if (ret_val)
fp@2685: goto release;
fp@2685: ret_val = igb_read_phy_reg_mdic(hw, offset, data);
fp@2685:
fp@2685: release:
fp@2685: hw->phy.ops.release(hw);
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_master_slave_mode - Setup PHY for Master/slave mode
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Sets up Master/slave mode
fp@2685: **/
fp@2685: static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: u16 phy_data;
fp@2685:
fp@2685: /* Resolve Master/Slave mode */
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: /* load defaults for future use */
fp@2685: hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
fp@2685: ((phy_data & CR_1000T_MS_VALUE) ?
fp@2685: e1000_ms_force_master :
fp@2685: e1000_ms_force_slave) : e1000_ms_auto;
fp@2685:
fp@2685: switch (hw->phy.ms_type) {
fp@2685: case e1000_ms_force_master:
fp@2685: phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
fp@2685: break;
fp@2685: case e1000_ms_force_slave:
fp@2685: phy_data |= CR_1000T_MS_ENABLE;
fp@2685: phy_data &= ~(CR_1000T_MS_VALUE);
fp@2685: break;
fp@2685: case e1000_ms_auto:
fp@2685: phy_data &= ~CR_1000T_MS_ENABLE;
fp@2685: /* fall-through */
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
fp@2685: }