fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685:  * Copyright(c) 2007-2014 Intel Corporation.
fp@2685:  * This program is free software; you can redistribute it and/or modify it
fp@2685:  * under the terms and conditions of the GNU General Public License,
fp@2685:  * version 2, as published by the Free Software Foundation.
fp@2685:  *
fp@2685:  * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2685:  * more details.
fp@2685:  *
fp@2685:  * You should have received a copy of the GNU General Public License along with
fp@2685:  * this program; if not, see <http://www.gnu.org/licenses/>.
fp@2685:  *
fp@2685:  * The full GNU General Public License is included in this distribution in
fp@2685:  * the file called "COPYING".
fp@2685:  *
fp@2685:  * Contact Information:
fp@2685:  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2685:  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685:  */
fp@2685: 
fp@2685: #include <linux/if_ether.h>
fp@2685: #include <linux/delay.h>
fp@2685: 
fp@2685: #include "e1000_mac-3.18-ethercat.h"
fp@2685: #include "e1000_nvm-3.18-ethercat.h"
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_raise_eec_clk - Raise EEPROM clock
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @eecd: pointer to the EEPROM
fp@2685:  *
fp@2685:  *  Enable/Raise the EEPROM clock bit.
fp@2685:  **/
fp@2685: static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
fp@2685: {
fp@2685: 	*eecd = *eecd | E1000_EECD_SK;
fp@2685: 	wr32(E1000_EECD, *eecd);
fp@2685: 	wrfl();
fp@2685: 	udelay(hw->nvm.delay_usec);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_lower_eec_clk - Lower EEPROM clock
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @eecd: pointer to the EEPROM
fp@2685:  *
fp@2685:  *  Clear/Lower the EEPROM clock bit.
fp@2685:  **/
fp@2685: static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
fp@2685: {
fp@2685: 	*eecd = *eecd & ~E1000_EECD_SK;
fp@2685: 	wr32(E1000_EECD, *eecd);
fp@2685: 	wrfl();
fp@2685: 	udelay(hw->nvm.delay_usec);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_shift_out_eec_bits - Shift data bits our to the EEPROM
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @data: data to send to the EEPROM
fp@2685:  *  @count: number of bits to shift out
fp@2685:  *
fp@2685:  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
fp@2685:  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
fp@2685:  *  In order to do this, "data" must be broken down into bits.
fp@2685:  **/
fp@2685: static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	u32 eecd = rd32(E1000_EECD);
fp@2685: 	u32 mask;
fp@2685: 
fp@2685: 	mask = 0x01 << (count - 1);
fp@2685: 	if (nvm->type == e1000_nvm_eeprom_spi)
fp@2685: 		eecd |= E1000_EECD_DO;
fp@2685: 
fp@2685: 	do {
fp@2685: 		eecd &= ~E1000_EECD_DI;
fp@2685: 
fp@2685: 		if (data & mask)
fp@2685: 			eecd |= E1000_EECD_DI;
fp@2685: 
fp@2685: 		wr32(E1000_EECD, eecd);
fp@2685: 		wrfl();
fp@2685: 
fp@2685: 		udelay(nvm->delay_usec);
fp@2685: 
fp@2685: 		igb_raise_eec_clk(hw, &eecd);
fp@2685: 		igb_lower_eec_clk(hw, &eecd);
fp@2685: 
fp@2685: 		mask >>= 1;
fp@2685: 	} while (mask);
fp@2685: 
fp@2685: 	eecd &= ~E1000_EECD_DI;
fp@2685: 	wr32(E1000_EECD, eecd);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_shift_in_eec_bits - Shift data bits in from the EEPROM
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @count: number of bits to shift in
fp@2685:  *
fp@2685:  *  In order to read a register from the EEPROM, we need to shift 'count' bits
fp@2685:  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
fp@2685:  *  the EEPROM (setting the SK bit), and then reading the value of the data out
fp@2685:  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
fp@2685:  *  always be clear.
fp@2685:  **/
fp@2685: static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
fp@2685: {
fp@2685: 	u32 eecd;
fp@2685: 	u32 i;
fp@2685: 	u16 data;
fp@2685: 
fp@2685: 	eecd = rd32(E1000_EECD);
fp@2685: 
fp@2685: 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
fp@2685: 	data = 0;
fp@2685: 
fp@2685: 	for (i = 0; i < count; i++) {
fp@2685: 		data <<= 1;
fp@2685: 		igb_raise_eec_clk(hw, &eecd);
fp@2685: 
fp@2685: 		eecd = rd32(E1000_EECD);
fp@2685: 
fp@2685: 		eecd &= ~E1000_EECD_DI;
fp@2685: 		if (eecd & E1000_EECD_DO)
fp@2685: 			data |= 1;
fp@2685: 
fp@2685: 		igb_lower_eec_clk(hw, &eecd);
fp@2685: 	}
fp@2685: 
fp@2685: 	return data;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @ee_reg: EEPROM flag for polling
fp@2685:  *
fp@2685:  *  Polls the EEPROM status bit for either read or write completion based
fp@2685:  *  upon the value of 'ee_reg'.
fp@2685:  **/
fp@2685: static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
fp@2685: {
fp@2685: 	u32 attempts = 100000;
fp@2685: 	u32 i, reg = 0;
fp@2685: 	s32 ret_val = -E1000_ERR_NVM;
fp@2685: 
fp@2685: 	for (i = 0; i < attempts; i++) {
fp@2685: 		if (ee_reg == E1000_NVM_POLL_READ)
fp@2685: 			reg = rd32(E1000_EERD);
fp@2685: 		else
fp@2685: 			reg = rd32(E1000_EEWR);
fp@2685: 
fp@2685: 		if (reg & E1000_NVM_RW_REG_DONE) {
fp@2685: 			ret_val = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 
fp@2685: 		udelay(5);
fp@2685: 	}
fp@2685: 
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_acquire_nvm - Generic request for access to EEPROM
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
fp@2685:  *  Return successful if access grant bit set, else clear the request for
fp@2685:  *  EEPROM access and return -E1000_ERR_NVM (-1).
fp@2685:  **/
fp@2685: s32 igb_acquire_nvm(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	u32 eecd = rd32(E1000_EECD);
fp@2685: 	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
fp@2685: 	s32 ret_val = 0;
fp@2685: 
fp@2685: 
fp@2685: 	wr32(E1000_EECD, eecd | E1000_EECD_REQ);
fp@2685: 	eecd = rd32(E1000_EECD);
fp@2685: 
fp@2685: 	while (timeout) {
fp@2685: 		if (eecd & E1000_EECD_GNT)
fp@2685: 			break;
fp@2685: 		udelay(5);
fp@2685: 		eecd = rd32(E1000_EECD);
fp@2685: 		timeout--;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (!timeout) {
fp@2685: 		eecd &= ~E1000_EECD_REQ;
fp@2685: 		wr32(E1000_EECD, eecd);
fp@2685: 		hw_dbg("Could not acquire NVM grant\n");
fp@2685: 		ret_val = -E1000_ERR_NVM;
fp@2685: 	}
fp@2685: 
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_standby_nvm - Return EEPROM to standby state
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Return the EEPROM to a standby state.
fp@2685:  **/
fp@2685: static void igb_standby_nvm(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	u32 eecd = rd32(E1000_EECD);
fp@2685: 
fp@2685: 	if (nvm->type == e1000_nvm_eeprom_spi) {
fp@2685: 		/* Toggle CS to flush commands */
fp@2685: 		eecd |= E1000_EECD_CS;
fp@2685: 		wr32(E1000_EECD, eecd);
fp@2685: 		wrfl();
fp@2685: 		udelay(nvm->delay_usec);
fp@2685: 		eecd &= ~E1000_EECD_CS;
fp@2685: 		wr32(E1000_EECD, eecd);
fp@2685: 		wrfl();
fp@2685: 		udelay(nvm->delay_usec);
fp@2685: 	}
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  e1000_stop_nvm - Terminate EEPROM command
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Terminates the current command by inverting the EEPROM's chip select pin.
fp@2685:  **/
fp@2685: static void e1000_stop_nvm(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	u32 eecd;
fp@2685: 
fp@2685: 	eecd = rd32(E1000_EECD);
fp@2685: 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
fp@2685: 		/* Pull CS high */
fp@2685: 		eecd |= E1000_EECD_CS;
fp@2685: 		igb_lower_eec_clk(hw, &eecd);
fp@2685: 	}
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_release_nvm - Release exclusive access to EEPROM
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
fp@2685:  **/
fp@2685: void igb_release_nvm(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	u32 eecd;
fp@2685: 
fp@2685: 	e1000_stop_nvm(hw);
fp@2685: 
fp@2685: 	eecd = rd32(E1000_EECD);
fp@2685: 	eecd &= ~E1000_EECD_REQ;
fp@2685: 	wr32(E1000_EECD, eecd);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_ready_nvm_eeprom - Prepares EEPROM for read/write
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Setups the EEPROM for reading and writing.
fp@2685:  **/
fp@2685: static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	u32 eecd = rd32(E1000_EECD);
fp@2685: 	s32 ret_val = 0;
fp@2685: 	u16 timeout = 0;
fp@2685: 	u8 spi_stat_reg;
fp@2685: 
fp@2685: 
fp@2685: 	if (nvm->type == e1000_nvm_eeprom_spi) {
fp@2685: 		/* Clear SK and CS */
fp@2685: 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
fp@2685: 		wr32(E1000_EECD, eecd);
fp@2685: 		wrfl();
fp@2685: 		udelay(1);
fp@2685: 		timeout = NVM_MAX_RETRY_SPI;
fp@2685: 
fp@2685: 		/* Read "Status Register" repeatedly until the LSB is cleared.
fp@2685: 		 * The EEPROM will signal that the command has been completed
fp@2685: 		 * by clearing bit 0 of the internal status register.  If it's
fp@2685: 		 * not cleared within 'timeout', then error out.
fp@2685: 		 */
fp@2685: 		while (timeout) {
fp@2685: 			igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
fp@2685: 					       hw->nvm.opcode_bits);
fp@2685: 			spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
fp@2685: 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
fp@2685: 				break;
fp@2685: 
fp@2685: 			udelay(5);
fp@2685: 			igb_standby_nvm(hw);
fp@2685: 			timeout--;
fp@2685: 		}
fp@2685: 
fp@2685: 		if (!timeout) {
fp@2685: 			hw_dbg("SPI NVM Status error\n");
fp@2685: 			ret_val = -E1000_ERR_NVM;
fp@2685: 			goto out;
fp@2685: 		}
fp@2685: 	}
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_nvm_spi - Read EEPROM's using SPI
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @offset: offset of word in the EEPROM to read
fp@2685:  *  @words: number of words to read
fp@2685:  *  @data: word read from the EEPROM
fp@2685:  *
fp@2685:  *  Reads a 16 bit word from the EEPROM.
fp@2685:  **/
fp@2685: s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	u32 i = 0;
fp@2685: 	s32 ret_val;
fp@2685: 	u16 word_in;
fp@2685: 	u8 read_opcode = NVM_READ_OPCODE_SPI;
fp@2685: 
fp@2685: 	/* A check for invalid values:  offset too large, too many words,
fp@2685: 	 * and not enough words.
fp@2685: 	 */
fp@2685: 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
fp@2685: 	    (words == 0)) {
fp@2685: 		hw_dbg("nvm parameter(s) out of bounds\n");
fp@2685: 		ret_val = -E1000_ERR_NVM;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	ret_val = nvm->ops.acquire(hw);
fp@2685: 	if (ret_val)
fp@2685: 		goto out;
fp@2685: 
fp@2685: 	ret_val = igb_ready_nvm_eeprom(hw);
fp@2685: 	if (ret_val)
fp@2685: 		goto release;
fp@2685: 
fp@2685: 	igb_standby_nvm(hw);
fp@2685: 
fp@2685: 	if ((nvm->address_bits == 8) && (offset >= 128))
fp@2685: 		read_opcode |= NVM_A8_OPCODE_SPI;
fp@2685: 
fp@2685: 	/* Send the READ command (opcode + addr) */
fp@2685: 	igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
fp@2685: 	igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
fp@2685: 
fp@2685: 	/* Read the data.  SPI NVMs increment the address with each byte
fp@2685: 	 * read and will roll over if reading beyond the end.  This allows
fp@2685: 	 * us to read the whole NVM from any offset
fp@2685: 	 */
fp@2685: 	for (i = 0; i < words; i++) {
fp@2685: 		word_in = igb_shift_in_eec_bits(hw, 16);
fp@2685: 		data[i] = (word_in >> 8) | (word_in << 8);
fp@2685: 	}
fp@2685: 
fp@2685: release:
fp@2685: 	nvm->ops.release(hw);
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_nvm_eerd - Reads EEPROM using EERD register
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @offset: offset of word in the EEPROM to read
fp@2685:  *  @words: number of words to read
fp@2685:  *  @data: word read from the EEPROM
fp@2685:  *
fp@2685:  *  Reads a 16 bit word from the EEPROM using the EERD register.
fp@2685:  **/
fp@2685: s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	u32 i, eerd = 0;
fp@2685: 	s32 ret_val = 0;
fp@2685: 
fp@2685: 	/* A check for invalid values:  offset too large, too many words,
fp@2685: 	 * and not enough words.
fp@2685: 	 */
fp@2685: 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
fp@2685: 	    (words == 0)) {
fp@2685: 		hw_dbg("nvm parameter(s) out of bounds\n");
fp@2685: 		ret_val = -E1000_ERR_NVM;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	for (i = 0; i < words; i++) {
fp@2685: 		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
fp@2685: 			E1000_NVM_RW_REG_START;
fp@2685: 
fp@2685: 		wr32(E1000_EERD, eerd);
fp@2685: 		ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
fp@2685: 		if (ret_val)
fp@2685: 			break;
fp@2685: 
fp@2685: 		data[i] = (rd32(E1000_EERD) >>
fp@2685: 			E1000_NVM_RW_REG_DATA);
fp@2685: 	}
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_write_nvm_spi - Write to EEPROM using SPI
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @offset: offset within the EEPROM to be written to
fp@2685:  *  @words: number of words to write
fp@2685:  *  @data: 16 bit word(s) to be written to the EEPROM
fp@2685:  *
fp@2685:  *  Writes data to EEPROM at offset using SPI interface.
fp@2685:  *
fp@2685:  *  If e1000_update_nvm_checksum is not called after this function , the
fp@2685:  *  EEPROM will most likley contain an invalid checksum.
fp@2685:  **/
fp@2685: s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	s32 ret_val = -E1000_ERR_NVM;
fp@2685: 	u16 widx = 0;
fp@2685: 
fp@2685: 	/* A check for invalid values:  offset too large, too many words,
fp@2685: 	 * and not enough words.
fp@2685: 	 */
fp@2685: 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
fp@2685: 	    (words == 0)) {
fp@2685: 		hw_dbg("nvm parameter(s) out of bounds\n");
fp@2685: 		return ret_val;
fp@2685: 	}
fp@2685: 
fp@2685: 	while (widx < words) {
fp@2685: 		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
fp@2685: 
fp@2685: 		ret_val = nvm->ops.acquire(hw);
fp@2685: 		if (ret_val)
fp@2685: 			return ret_val;
fp@2685: 
fp@2685: 		ret_val = igb_ready_nvm_eeprom(hw);
fp@2685: 		if (ret_val) {
fp@2685: 			nvm->ops.release(hw);
fp@2685: 			return ret_val;
fp@2685: 		}
fp@2685: 
fp@2685: 		igb_standby_nvm(hw);
fp@2685: 
fp@2685: 		/* Send the WRITE ENABLE command (8 bit opcode) */
fp@2685: 		igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
fp@2685: 					 nvm->opcode_bits);
fp@2685: 
fp@2685: 		igb_standby_nvm(hw);
fp@2685: 
fp@2685: 		/* Some SPI eeproms use the 8th address bit embedded in the
fp@2685: 		 * opcode
fp@2685: 		 */
fp@2685: 		if ((nvm->address_bits == 8) && (offset >= 128))
fp@2685: 			write_opcode |= NVM_A8_OPCODE_SPI;
fp@2685: 
fp@2685: 		/* Send the Write command (8-bit opcode + addr) */
fp@2685: 		igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
fp@2685: 		igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
fp@2685: 					 nvm->address_bits);
fp@2685: 
fp@2685: 		/* Loop to allow for up to whole page write of eeprom */
fp@2685: 		while (widx < words) {
fp@2685: 			u16 word_out = data[widx];
fp@2685: 
fp@2685: 			word_out = (word_out >> 8) | (word_out << 8);
fp@2685: 			igb_shift_out_eec_bits(hw, word_out, 16);
fp@2685: 			widx++;
fp@2685: 
fp@2685: 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
fp@2685: 				igb_standby_nvm(hw);
fp@2685: 				break;
fp@2685: 			}
fp@2685: 		}
fp@2685: 		usleep_range(1000, 2000);
fp@2685: 		nvm->ops.release(hw);
fp@2685: 	}
fp@2685: 
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_part_string - Read device part number
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @part_num: pointer to device part number
fp@2685:  *  @part_num_size: size of part number buffer
fp@2685:  *
fp@2685:  *  Reads the product board assembly (PBA) number from the EEPROM and stores
fp@2685:  *  the value in part_num.
fp@2685:  **/
fp@2685: s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
fp@2685: {
fp@2685: 	s32 ret_val;
fp@2685: 	u16 nvm_data;
fp@2685: 	u16 pointer;
fp@2685: 	u16 offset;
fp@2685: 	u16 length;
fp@2685: 
fp@2685: 	if (part_num == NULL) {
fp@2685: 		hw_dbg("PBA string buffer was null\n");
fp@2685: 		ret_val = E1000_ERR_INVALID_ARGUMENT;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
fp@2685: 	if (ret_val) {
fp@2685: 		hw_dbg("NVM Read Error\n");
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
fp@2685: 	if (ret_val) {
fp@2685: 		hw_dbg("NVM Read Error\n");
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	/* if nvm_data is not ptr guard the PBA must be in legacy format which
fp@2685: 	 * means pointer is actually our second data word for the PBA number
fp@2685: 	 * and we can decode it into an ascii string
fp@2685: 	 */
fp@2685: 	if (nvm_data != NVM_PBA_PTR_GUARD) {
fp@2685: 		hw_dbg("NVM PBA number is not stored as string\n");
fp@2685: 
fp@2685: 		/* we will need 11 characters to store the PBA */
fp@2685: 		if (part_num_size < 11) {
fp@2685: 			hw_dbg("PBA string buffer too small\n");
fp@2685: 			return E1000_ERR_NO_SPACE;
fp@2685: 		}
fp@2685: 
fp@2685: 		/* extract hex string from data and pointer */
fp@2685: 		part_num[0] = (nvm_data >> 12) & 0xF;
fp@2685: 		part_num[1] = (nvm_data >> 8) & 0xF;
fp@2685: 		part_num[2] = (nvm_data >> 4) & 0xF;
fp@2685: 		part_num[3] = nvm_data & 0xF;
fp@2685: 		part_num[4] = (pointer >> 12) & 0xF;
fp@2685: 		part_num[5] = (pointer >> 8) & 0xF;
fp@2685: 		part_num[6] = '-';
fp@2685: 		part_num[7] = 0;
fp@2685: 		part_num[8] = (pointer >> 4) & 0xF;
fp@2685: 		part_num[9] = pointer & 0xF;
fp@2685: 
fp@2685: 		/* put a null character on the end of our string */
fp@2685: 		part_num[10] = '\0';
fp@2685: 
fp@2685: 		/* switch all the data but the '-' to hex char */
fp@2685: 		for (offset = 0; offset < 10; offset++) {
fp@2685: 			if (part_num[offset] < 0xA)
fp@2685: 				part_num[offset] += '0';
fp@2685: 			else if (part_num[offset] < 0x10)
fp@2685: 				part_num[offset] += 'A' - 0xA;
fp@2685: 		}
fp@2685: 
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
fp@2685: 	if (ret_val) {
fp@2685: 		hw_dbg("NVM Read Error\n");
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (length == 0xFFFF || length == 0) {
fp@2685: 		hw_dbg("NVM PBA number section invalid length\n");
fp@2685: 		ret_val = E1000_ERR_NVM_PBA_SECTION;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 	/* check if part_num buffer is big enough */
fp@2685: 	if (part_num_size < (((u32)length * 2) - 1)) {
fp@2685: 		hw_dbg("PBA string buffer too small\n");
fp@2685: 		ret_val = E1000_ERR_NO_SPACE;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	/* trim pba length from start of string */
fp@2685: 	pointer++;
fp@2685: 	length--;
fp@2685: 
fp@2685: 	for (offset = 0; offset < length; offset++) {
fp@2685: 		ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
fp@2685: 		if (ret_val) {
fp@2685: 			hw_dbg("NVM Read Error\n");
fp@2685: 			goto out;
fp@2685: 		}
fp@2685: 		part_num[offset * 2] = (u8)(nvm_data >> 8);
fp@2685: 		part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
fp@2685: 	}
fp@2685: 	part_num[offset * 2] = '\0';
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_mac_addr - Read device MAC address
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Reads the device MAC address from the EEPROM and stores the value.
fp@2685:  *  Since devices with two ports use the same EEPROM, we increment the
fp@2685:  *  last bit in the MAC address for the second port.
fp@2685:  **/
fp@2685: s32 igb_read_mac_addr(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	u32 rar_high;
fp@2685: 	u32 rar_low;
fp@2685: 	u16 i;
fp@2685: 
fp@2685: 	rar_high = rd32(E1000_RAH(0));
fp@2685: 	rar_low = rd32(E1000_RAL(0));
fp@2685: 
fp@2685: 	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
fp@2685: 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
fp@2685: 
fp@2685: 	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
fp@2685: 		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
fp@2685: 
fp@2685: 	for (i = 0; i < ETH_ALEN; i++)
fp@2685: 		hw->mac.addr[i] = hw->mac.perm_addr[i];
fp@2685: 
fp@2685: 	return 0;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_validate_nvm_checksum - Validate EEPROM checksum
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2685:  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
fp@2685:  **/
fp@2685: s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 ret_val = 0;
fp@2685: 	u16 checksum = 0;
fp@2685: 	u16 i, nvm_data;
fp@2685: 
fp@2685: 	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
fp@2685: 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
fp@2685: 		if (ret_val) {
fp@2685: 			hw_dbg("NVM Read Error\n");
fp@2685: 			goto out;
fp@2685: 		}
fp@2685: 		checksum += nvm_data;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (checksum != (u16) NVM_SUM) {
fp@2685: 		hw_dbg("NVM Checksum Invalid\n");
fp@2685: 		ret_val = -E1000_ERR_NVM;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_update_nvm_checksum - Update EEPROM checksum
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2685:  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
fp@2685:  *  value to the EEPROM.
fp@2685:  **/
fp@2685: s32 igb_update_nvm_checksum(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32  ret_val;
fp@2685: 	u16 checksum = 0;
fp@2685: 	u16 i, nvm_data;
fp@2685: 
fp@2685: 	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
fp@2685: 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
fp@2685: 		if (ret_val) {
fp@2685: 			hw_dbg("NVM Read Error while updating checksum.\n");
fp@2685: 			goto out;
fp@2685: 		}
fp@2685: 		checksum += nvm_data;
fp@2685: 	}
fp@2685: 	checksum = (u16) NVM_SUM - checksum;
fp@2685: 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
fp@2685: 	if (ret_val)
fp@2685: 		hw_dbg("NVM Write Error while updating checksum.\n");
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_get_fw_version - Get firmware version information
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @fw_vers: pointer to output structure
fp@2685:  *
fp@2685:  *  unsupported MAC types will return all 0 version structure
fp@2685:  **/
fp@2685: void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
fp@2685: {
fp@2685: 	u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
fp@2685: 	u8 q, hval, rem, result;
fp@2685: 	u16 comb_verh, comb_verl, comb_offset;
fp@2685: 
fp@2685: 	memset(fw_vers, 0, sizeof(struct e1000_fw_version));
fp@2685: 
fp@2685: 	/* basic eeprom version numbers and bits used vary by part and by tool
fp@2685: 	 * used to create the nvm images. Check which data format we have.
fp@2685: 	 */
fp@2685: 	hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
fp@2685: 	switch (hw->mac.type) {
fp@2685: 	case e1000_i211:
fp@2685: 		igb_read_invm_version(hw, fw_vers);
fp@2685: 		return;
fp@2685: 	case e1000_82575:
fp@2685: 	case e1000_82576:
fp@2685: 	case e1000_82580:
fp@2685: 		/* Use this format, unless EETRACK ID exists,
fp@2685: 		 * then use alternate format
fp@2685: 		 */
fp@2685: 		if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
fp@2685: 			hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
fp@2685: 			fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
fp@2685: 					      >> NVM_MAJOR_SHIFT;
fp@2685: 			fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
fp@2685: 					      >> NVM_MINOR_SHIFT;
fp@2685: 			fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
fp@2685: 			goto etrack_id;
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	case e1000_i210:
fp@2685: 		if (!(igb_get_flash_presence_i210(hw))) {
fp@2685: 			igb_read_invm_version(hw, fw_vers);
fp@2685: 			return;
fp@2685: 		}
fp@2685: 		/* fall through */
fp@2685: 	case e1000_i350:
fp@2685: 		/* find combo image version */
fp@2685: 		hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
fp@2685: 		if ((comb_offset != 0x0) &&
fp@2685: 		    (comb_offset != NVM_VER_INVALID)) {
fp@2685: 
fp@2685: 			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
fp@2685: 					 + 1), 1, &comb_verh);
fp@2685: 			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
fp@2685: 					 1, &comb_verl);
fp@2685: 
fp@2685: 			/* get Option Rom version if it exists and is valid */
fp@2685: 			if ((comb_verh && comb_verl) &&
fp@2685: 			    ((comb_verh != NVM_VER_INVALID) &&
fp@2685: 			     (comb_verl != NVM_VER_INVALID))) {
fp@2685: 
fp@2685: 				fw_vers->or_valid = true;
fp@2685: 				fw_vers->or_major =
fp@2685: 					comb_verl >> NVM_COMB_VER_SHFT;
fp@2685: 				fw_vers->or_build =
fp@2685: 					(comb_verl << NVM_COMB_VER_SHFT)
fp@2685: 					| (comb_verh >> NVM_COMB_VER_SHFT);
fp@2685: 				fw_vers->or_patch =
fp@2685: 					comb_verh & NVM_COMB_VER_MASK;
fp@2685: 			}
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	default:
fp@2685: 		return;
fp@2685: 	}
fp@2685: 	hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
fp@2685: 	fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
fp@2685: 			      >> NVM_MAJOR_SHIFT;
fp@2685: 
fp@2685: 	/* check for old style version format in newer images*/
fp@2685: 	if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
fp@2685: 		eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
fp@2685: 	} else {
fp@2685: 		eeprom_verl = (fw_version & NVM_MINOR_MASK)
fp@2685: 				>> NVM_MINOR_SHIFT;
fp@2685: 	}
fp@2685: 	/* Convert minor value to hex before assigning to output struct
fp@2685: 	 * Val to be converted will not be higher than 99, per tool output
fp@2685: 	 */
fp@2685: 	q = eeprom_verl / NVM_HEX_CONV;
fp@2685: 	hval = q * NVM_HEX_TENS;
fp@2685: 	rem = eeprom_verl % NVM_HEX_CONV;
fp@2685: 	result = hval + rem;
fp@2685: 	fw_vers->eep_minor = result;
fp@2685: 
fp@2685: etrack_id:
fp@2685: 	if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
fp@2685: 		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
fp@2685: 		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
fp@2685: 		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
fp@2685: 			| eeprom_verl;
fp@2685: 	}
fp@2685: }