fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685: * Copyright(c) 2007-2014 Intel Corporation.
fp@2685: *
fp@2685: * This program is free software; you can redistribute it and/or modify it
fp@2685: * under the terms and conditions of the GNU General Public License,
fp@2685: * version 2, as published by the Free Software Foundation.
fp@2685: *
fp@2685: * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
fp@2685: * more details.
fp@2685: *
fp@2685: * You should have received a copy of the GNU General Public License along with
fp@2685: * this program; if not, see .
fp@2685: *
fp@2685: * The full GNU General Public License is included in this distribution in
fp@2685: * the file called "COPYING".
fp@2685: *
fp@2685: * Contact Information:
fp@2685: * e1000-devel Mailing List
fp@2685: * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685: */
fp@2685:
fp@2685: /* e1000_82575
fp@2685: * e1000_82576
fp@2685: */
fp@2685:
fp@2685: #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
fp@2685:
fp@2685: #include
fp@2685: #include
fp@2685: #include
fp@2685:
fp@2685: #include "e1000_mac-3.18-ethercat.h"
fp@2685: #include "e1000_82575-3.18-ethercat.h"
fp@2685: #include "e1000_i210-3.18-ethercat.h"
fp@2685:
fp@2685: static s32 igb_get_invariants_82575(struct e1000_hw *);
fp@2685: static s32 igb_acquire_phy_82575(struct e1000_hw *);
fp@2685: static void igb_release_phy_82575(struct e1000_hw *);
fp@2685: static s32 igb_acquire_nvm_82575(struct e1000_hw *);
fp@2685: static void igb_release_nvm_82575(struct e1000_hw *);
fp@2685: static s32 igb_check_for_link_82575(struct e1000_hw *);
fp@2685: static s32 igb_get_cfg_done_82575(struct e1000_hw *);
fp@2685: static s32 igb_init_hw_82575(struct e1000_hw *);
fp@2685: static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
fp@2685: static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
fp@2685: static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
fp@2685: static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
fp@2685: static s32 igb_reset_hw_82575(struct e1000_hw *);
fp@2685: static s32 igb_reset_hw_82580(struct e1000_hw *);
fp@2685: static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
fp@2685: static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
fp@2685: static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
fp@2685: static s32 igb_setup_copper_link_82575(struct e1000_hw *);
fp@2685: static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
fp@2685: static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
fp@2685: static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
fp@2685: static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
fp@2685: static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
fp@2685: u16 *);
fp@2685: static s32 igb_get_phy_id_82575(struct e1000_hw *);
fp@2685: static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
fp@2685: static bool igb_sgmii_active_82575(struct e1000_hw *);
fp@2685: static s32 igb_reset_init_script_82575(struct e1000_hw *);
fp@2685: static s32 igb_read_mac_addr_82575(struct e1000_hw *);
fp@2685: static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
fp@2685: static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
fp@2685: static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
fp@2685: static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
fp@2685: static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
fp@2685: static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
fp@2685: static const u16 e1000_82580_rxpbs_table[] = {
fp@2685: 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
fp@2685:
fp@2685: /**
fp@2685: * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Called to determine if the I2C pins are being used for I2C or as an
fp@2685: * external MDIO interface since the two options are mutually exclusive.
fp@2685: **/
fp@2685: static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 reg = 0;
fp@2685: bool ext_mdio = false;
fp@2685:
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82575:
fp@2685: case e1000_82576:
fp@2685: reg = rd32(E1000_MDIC);
fp@2685: ext_mdio = !!(reg & E1000_MDIC_DEST);
fp@2685: break;
fp@2685: case e1000_82580:
fp@2685: case e1000_i350:
fp@2685: case e1000_i354:
fp@2685: case e1000_i210:
fp@2685: case e1000_i211:
fp@2685: reg = rd32(E1000_MDICNFG);
fp@2685: ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685: return ext_mdio;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_for_link_media_swap - Check which M88E1112 interface linked
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Poll the M88E1112 interfaces to see which interface achieved link.
fp@2685: */
fp@2685: static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685: u8 port = 0;
fp@2685:
fp@2685: /* Check the copper medium. */
fp@2685: ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: if (data & E1000_M88E1112_STATUS_LINK)
fp@2685: port = E1000_MEDIA_PORT_COPPER;
fp@2685:
fp@2685: /* Check the other medium. */
fp@2685: ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: /* reset page to 0 */
fp@2685: ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: if (data & E1000_M88E1112_STATUS_LINK)
fp@2685: port = E1000_MEDIA_PORT_OTHER;
fp@2685:
fp@2685: /* Determine if a swap needs to happen. */
fp@2685: if (port && (hw->dev_spec._82575.media_port != port)) {
fp@2685: hw->dev_spec._82575.media_port = port;
fp@2685: hw->dev_spec._82575.media_changed = true;
fp@2685: } else {
fp@2685: ret_val = igb_check_for_link_82575(hw);
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_init_phy_params_82575 - Init PHY func ptrs.
fp@2685: * @hw: pointer to the HW structure
fp@2685: **/
fp@2685: static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u32 ctrl_ext;
fp@2685:
fp@2685: if (hw->phy.media_type != e1000_media_type_copper) {
fp@2685: phy->type = e1000_phy_none;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
fp@2685: phy->reset_delay_us = 100;
fp@2685:
fp@2685: ctrl_ext = rd32(E1000_CTRL_EXT);
fp@2685:
fp@2685: if (igb_sgmii_active_82575(hw)) {
fp@2685: phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
fp@2685: ctrl_ext |= E1000_CTRL_I2C_ENA;
fp@2685: } else {
fp@2685: phy->ops.reset = igb_phy_hw_reset;
fp@2685: ctrl_ext &= ~E1000_CTRL_I2C_ENA;
fp@2685: }
fp@2685:
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext);
fp@2685: igb_reset_mdicnfg_82580(hw);
fp@2685:
fp@2685: if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
fp@2685: phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
fp@2685: phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
fp@2685: } else {
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82580:
fp@2685: case e1000_i350:
fp@2685: case e1000_i354:
fp@2685: phy->ops.read_reg = igb_read_phy_reg_82580;
fp@2685: phy->ops.write_reg = igb_write_phy_reg_82580;
fp@2685: break;
fp@2685: case e1000_i210:
fp@2685: case e1000_i211:
fp@2685: phy->ops.read_reg = igb_read_phy_reg_gs40g;
fp@2685: phy->ops.write_reg = igb_write_phy_reg_gs40g;
fp@2685: break;
fp@2685: default:
fp@2685: phy->ops.read_reg = igb_read_phy_reg_igp;
fp@2685: phy->ops.write_reg = igb_write_phy_reg_igp;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /* set lan id */
fp@2685: hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
fp@2685: E1000_STATUS_FUNC_SHIFT;
fp@2685:
fp@2685: /* Set phy->phy_addr and phy->id. */
fp@2685: ret_val = igb_get_phy_id_82575(hw);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: /* Verify phy id and set remaining function pointers */
fp@2685: switch (phy->id) {
fp@2685: case M88E1543_E_PHY_ID:
fp@2685: case I347AT4_E_PHY_ID:
fp@2685: case M88E1112_E_PHY_ID:
fp@2685: case M88E1111_I_PHY_ID:
fp@2685: phy->type = e1000_phy_m88;
fp@2685: phy->ops.check_polarity = igb_check_polarity_m88;
fp@2685: phy->ops.get_phy_info = igb_get_phy_info_m88;
fp@2685: if (phy->id != M88E1111_I_PHY_ID)
fp@2685: phy->ops.get_cable_length =
fp@2685: igb_get_cable_length_m88_gen2;
fp@2685: else
fp@2685: phy->ops.get_cable_length = igb_get_cable_length_m88;
fp@2685: phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
fp@2685: /* Check if this PHY is confgured for media swap. */
fp@2685: if (phy->id == M88E1112_E_PHY_ID) {
fp@2685: u16 data;
fp@2685:
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: E1000_M88E1112_PAGE_ADDR,
fp@2685: 2);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw,
fp@2685: E1000_M88E1112_MAC_CTRL_1,
fp@2685: &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
fp@2685: E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
fp@2685: if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
fp@2685: data == E1000_M88E1112_AUTO_COPPER_BASEX)
fp@2685: hw->mac.ops.check_for_link =
fp@2685: igb_check_for_link_media_swap;
fp@2685: }
fp@2685: break;
fp@2685: case IGP03E1000_E_PHY_ID:
fp@2685: phy->type = e1000_phy_igp_3;
fp@2685: phy->ops.get_phy_info = igb_get_phy_info_igp;
fp@2685: phy->ops.get_cable_length = igb_get_cable_length_igp_2;
fp@2685: phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
fp@2685: phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
fp@2685: phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
fp@2685: break;
fp@2685: case I82580_I_PHY_ID:
fp@2685: case I350_I_PHY_ID:
fp@2685: phy->type = e1000_phy_82580;
fp@2685: phy->ops.force_speed_duplex =
fp@2685: igb_phy_force_speed_duplex_82580;
fp@2685: phy->ops.get_cable_length = igb_get_cable_length_82580;
fp@2685: phy->ops.get_phy_info = igb_get_phy_info_82580;
fp@2685: phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
fp@2685: phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
fp@2685: break;
fp@2685: case I210_I_PHY_ID:
fp@2685: phy->type = e1000_phy_i210;
fp@2685: phy->ops.check_polarity = igb_check_polarity_m88;
fp@2685: phy->ops.get_phy_info = igb_get_phy_info_m88;
fp@2685: phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
fp@2685: phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
fp@2685: phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
fp@2685: phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
fp@2685: break;
fp@2685: default:
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_init_nvm_params_82575 - Init NVM func ptrs.
fp@2685: * @hw: pointer to the HW structure
fp@2685: **/
fp@2685: static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: u32 eecd = rd32(E1000_EECD);
fp@2685: u16 size;
fp@2685:
fp@2685: size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
fp@2685: E1000_EECD_SIZE_EX_SHIFT);
fp@2685:
fp@2685: /* Added to a constant, "size" becomes the left-shift value
fp@2685: * for setting word_size.
fp@2685: */
fp@2685: size += NVM_WORD_SIZE_BASE_SHIFT;
fp@2685:
fp@2685: /* Just in case size is out of range, cap it to the largest
fp@2685: * EEPROM size supported
fp@2685: */
fp@2685: if (size > 15)
fp@2685: size = 15;
fp@2685:
fp@2685: nvm->word_size = 1 << size;
fp@2685: nvm->opcode_bits = 8;
fp@2685: nvm->delay_usec = 1;
fp@2685:
fp@2685: switch (nvm->override) {
fp@2685: case e1000_nvm_override_spi_large:
fp@2685: nvm->page_size = 32;
fp@2685: nvm->address_bits = 16;
fp@2685: break;
fp@2685: case e1000_nvm_override_spi_small:
fp@2685: nvm->page_size = 8;
fp@2685: nvm->address_bits = 8;
fp@2685: break;
fp@2685: default:
fp@2685: nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
fp@2685: nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
fp@2685: 16 : 8;
fp@2685: break;
fp@2685: }
fp@2685: if (nvm->word_size == (1 << 15))
fp@2685: nvm->page_size = 128;
fp@2685:
fp@2685: nvm->type = e1000_nvm_eeprom_spi;
fp@2685:
fp@2685: /* NVM Function Pointers */
fp@2685: nvm->ops.acquire = igb_acquire_nvm_82575;
fp@2685: nvm->ops.release = igb_release_nvm_82575;
fp@2685: nvm->ops.write = igb_write_nvm_spi;
fp@2685: nvm->ops.validate = igb_validate_nvm_checksum;
fp@2685: nvm->ops.update = igb_update_nvm_checksum;
fp@2685: if (nvm->word_size < (1 << 15))
fp@2685: nvm->ops.read = igb_read_nvm_eerd;
fp@2685: else
fp@2685: nvm->ops.read = igb_read_nvm_spi;
fp@2685:
fp@2685: /* override generic family function pointers for specific descendants */
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82580:
fp@2685: nvm->ops.validate = igb_validate_nvm_checksum_82580;
fp@2685: nvm->ops.update = igb_update_nvm_checksum_82580;
fp@2685: break;
fp@2685: case e1000_i354:
fp@2685: case e1000_i350:
fp@2685: nvm->ops.validate = igb_validate_nvm_checksum_i350;
fp@2685: nvm->ops.update = igb_update_nvm_checksum_i350;
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_init_mac_params_82575 - Init MAC func ptrs.
fp@2685: * @hw: pointer to the HW structure
fp@2685: **/
fp@2685: static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
fp@2685:
fp@2685: /* Set mta register count */
fp@2685: mac->mta_reg_count = 128;
fp@2685: /* Set rar entry count */
fp@2685: switch (mac->type) {
fp@2685: case e1000_82576:
fp@2685: mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
fp@2685: break;
fp@2685: case e1000_82580:
fp@2685: mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
fp@2685: break;
fp@2685: case e1000_i350:
fp@2685: case e1000_i354:
fp@2685: mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
fp@2685: break;
fp@2685: default:
fp@2685: mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
fp@2685: break;
fp@2685: }
fp@2685: /* reset */
fp@2685: if (mac->type >= e1000_82580)
fp@2685: mac->ops.reset_hw = igb_reset_hw_82580;
fp@2685: else
fp@2685: mac->ops.reset_hw = igb_reset_hw_82575;
fp@2685:
fp@2685: if (mac->type >= e1000_i210) {
fp@2685: mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
fp@2685: mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
fp@2685:
fp@2685: } else {
fp@2685: mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
fp@2685: mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
fp@2685: }
fp@2685:
fp@2685: /* Set if part includes ASF firmware */
fp@2685: mac->asf_firmware_present = true;
fp@2685: /* Set if manageability features are enabled. */
fp@2685: mac->arc_subsystem_valid =
fp@2685: (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
fp@2685: ? true : false;
fp@2685: /* enable EEE on i350 parts and later parts */
fp@2685: if (mac->type >= e1000_i350)
fp@2685: dev_spec->eee_disable = false;
fp@2685: else
fp@2685: dev_spec->eee_disable = true;
fp@2685: /* Allow a single clear of the SW semaphore on I210 and newer */
fp@2685: if (mac->type >= e1000_i210)
fp@2685: dev_spec->clear_semaphore_once = true;
fp@2685: /* physical interface link setup */
fp@2685: mac->ops.setup_physical_interface =
fp@2685: (hw->phy.media_type == e1000_media_type_copper)
fp@2685: ? igb_setup_copper_link_82575
fp@2685: : igb_setup_serdes_link_82575;
fp@2685:
fp@2685: if (mac->type == e1000_82580) {
fp@2685: switch (hw->device_id) {
fp@2685: /* feature not supported on these id's */
fp@2685: case E1000_DEV_ID_DH89XXCC_SGMII:
fp@2685: case E1000_DEV_ID_DH89XXCC_SERDES:
fp@2685: case E1000_DEV_ID_DH89XXCC_BACKPLANE:
fp@2685: case E1000_DEV_ID_DH89XXCC_SFP:
fp@2685: break;
fp@2685: default:
fp@2685: hw->dev_spec._82575.mas_capable = true;
fp@2685: break;
fp@2685: }
fp@2685: }
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_sfp_media_type_82575 - derives SFP module media type.
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * The media type is chosen based on SFP module.
fp@2685: * compatibility flags retrieved from SFP ID EEPROM.
fp@2685: **/
fp@2685: static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = E1000_ERR_CONFIG;
fp@2685: u32 ctrl_ext = 0;
fp@2685: struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
fp@2685: struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
fp@2685: u8 tranceiver_type = 0;
fp@2685: s32 timeout = 3;
fp@2685:
fp@2685: /* Turn I2C interface ON and power on sfp cage */
fp@2685: ctrl_ext = rd32(E1000_CTRL_EXT);
fp@2685: ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
fp@2685:
fp@2685: wrfl();
fp@2685:
fp@2685: /* Read SFP module data */
fp@2685: while (timeout) {
fp@2685: ret_val = igb_read_sfp_data_byte(hw,
fp@2685: E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
fp@2685: &tranceiver_type);
fp@2685: if (ret_val == 0)
fp@2685: break;
fp@2685: msleep(100);
fp@2685: timeout--;
fp@2685: }
fp@2685: if (ret_val != 0)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_read_sfp_data_byte(hw,
fp@2685: E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
fp@2685: (u8 *)eth_flags);
fp@2685: if (ret_val != 0)
fp@2685: goto out;
fp@2685:
fp@2685: /* Check if there is some SFP module plugged and powered */
fp@2685: if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
fp@2685: (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
fp@2685: dev_spec->module_plugged = true;
fp@2685: if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
fp@2685: hw->phy.media_type = e1000_media_type_internal_serdes;
fp@2685: } else if (eth_flags->e100_base_fx) {
fp@2685: dev_spec->sgmii_active = true;
fp@2685: hw->phy.media_type = e1000_media_type_internal_serdes;
fp@2685: } else if (eth_flags->e1000_base_t) {
fp@2685: dev_spec->sgmii_active = true;
fp@2685: hw->phy.media_type = e1000_media_type_copper;
fp@2685: } else {
fp@2685: hw->phy.media_type = e1000_media_type_unknown;
fp@2685: hw_dbg("PHY module has not been recognized\n");
fp@2685: goto out;
fp@2685: }
fp@2685: } else {
fp@2685: hw->phy.media_type = e1000_media_type_unknown;
fp@2685: }
fp@2685: ret_val = 0;
fp@2685: out:
fp@2685: /* Restore I2C interface setting */
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext);
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: static s32 igb_get_invariants_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
fp@2685: s32 ret_val;
fp@2685: u32 ctrl_ext = 0;
fp@2685: u32 link_mode = 0;
fp@2685:
fp@2685: switch (hw->device_id) {
fp@2685: case E1000_DEV_ID_82575EB_COPPER:
fp@2685: case E1000_DEV_ID_82575EB_FIBER_SERDES:
fp@2685: case E1000_DEV_ID_82575GB_QUAD_COPPER:
fp@2685: mac->type = e1000_82575;
fp@2685: break;
fp@2685: case E1000_DEV_ID_82576:
fp@2685: case E1000_DEV_ID_82576_NS:
fp@2685: case E1000_DEV_ID_82576_NS_SERDES:
fp@2685: case E1000_DEV_ID_82576_FIBER:
fp@2685: case E1000_DEV_ID_82576_SERDES:
fp@2685: case E1000_DEV_ID_82576_QUAD_COPPER:
fp@2685: case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
fp@2685: case E1000_DEV_ID_82576_SERDES_QUAD:
fp@2685: mac->type = e1000_82576;
fp@2685: break;
fp@2685: case E1000_DEV_ID_82580_COPPER:
fp@2685: case E1000_DEV_ID_82580_FIBER:
fp@2685: case E1000_DEV_ID_82580_QUAD_FIBER:
fp@2685: case E1000_DEV_ID_82580_SERDES:
fp@2685: case E1000_DEV_ID_82580_SGMII:
fp@2685: case E1000_DEV_ID_82580_COPPER_DUAL:
fp@2685: case E1000_DEV_ID_DH89XXCC_SGMII:
fp@2685: case E1000_DEV_ID_DH89XXCC_SERDES:
fp@2685: case E1000_DEV_ID_DH89XXCC_BACKPLANE:
fp@2685: case E1000_DEV_ID_DH89XXCC_SFP:
fp@2685: mac->type = e1000_82580;
fp@2685: break;
fp@2685: case E1000_DEV_ID_I350_COPPER:
fp@2685: case E1000_DEV_ID_I350_FIBER:
fp@2685: case E1000_DEV_ID_I350_SERDES:
fp@2685: case E1000_DEV_ID_I350_SGMII:
fp@2685: mac->type = e1000_i350;
fp@2685: break;
fp@2685: case E1000_DEV_ID_I210_COPPER:
fp@2685: case E1000_DEV_ID_I210_FIBER:
fp@2685: case E1000_DEV_ID_I210_SERDES:
fp@2685: case E1000_DEV_ID_I210_SGMII:
fp@2685: case E1000_DEV_ID_I210_COPPER_FLASHLESS:
fp@2685: case E1000_DEV_ID_I210_SERDES_FLASHLESS:
fp@2685: mac->type = e1000_i210;
fp@2685: break;
fp@2685: case E1000_DEV_ID_I211_COPPER:
fp@2685: mac->type = e1000_i211;
fp@2685: break;
fp@2685: case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
fp@2685: case E1000_DEV_ID_I354_SGMII:
fp@2685: case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
fp@2685: mac->type = e1000_i354;
fp@2685: break;
fp@2685: default:
fp@2685: return -E1000_ERR_MAC_INIT;
fp@2685: }
fp@2685:
fp@2685: /* Set media type */
fp@2685: /* The 82575 uses bits 22:23 for link mode. The mode can be changed
fp@2685: * based on the EEPROM. We cannot rely upon device ID. There
fp@2685: * is no distinguishable difference between fiber and internal
fp@2685: * SerDes mode on the 82575. There can be an external PHY attached
fp@2685: * on the SGMII interface. For this, we'll set sgmii_active to true.
fp@2685: */
fp@2685: hw->phy.media_type = e1000_media_type_copper;
fp@2685: dev_spec->sgmii_active = false;
fp@2685: dev_spec->module_plugged = false;
fp@2685:
fp@2685: ctrl_ext = rd32(E1000_CTRL_EXT);
fp@2685:
fp@2685: link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
fp@2685: switch (link_mode) {
fp@2685: case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
fp@2685: hw->phy.media_type = e1000_media_type_internal_serdes;
fp@2685: break;
fp@2685: case E1000_CTRL_EXT_LINK_MODE_SGMII:
fp@2685: /* Get phy control interface type set (MDIO vs. I2C)*/
fp@2685: if (igb_sgmii_uses_mdio_82575(hw)) {
fp@2685: hw->phy.media_type = e1000_media_type_copper;
fp@2685: dev_spec->sgmii_active = true;
fp@2685: break;
fp@2685: }
fp@2685: /* fall through for I2C based SGMII */
fp@2685: case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
fp@2685: /* read media type from SFP EEPROM */
fp@2685: ret_val = igb_set_sfp_media_type_82575(hw);
fp@2685: if ((ret_val != 0) ||
fp@2685: (hw->phy.media_type == e1000_media_type_unknown)) {
fp@2685: /* If media type was not identified then return media
fp@2685: * type defined by the CTRL_EXT settings.
fp@2685: */
fp@2685: hw->phy.media_type = e1000_media_type_internal_serdes;
fp@2685:
fp@2685: if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
fp@2685: hw->phy.media_type = e1000_media_type_copper;
fp@2685: dev_spec->sgmii_active = true;
fp@2685: }
fp@2685:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: /* do not change link mode for 100BaseFX */
fp@2685: if (dev_spec->eth_flags.e100_base_fx)
fp@2685: break;
fp@2685:
fp@2685: /* change current link mode setting */
fp@2685: ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
fp@2685:
fp@2685: if (hw->phy.media_type == e1000_media_type_copper)
fp@2685: ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
fp@2685: else
fp@2685: ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
fp@2685:
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext);
fp@2685:
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: /* mac initialization and operations */
fp@2685: ret_val = igb_init_mac_params_82575(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* NVM initialization */
fp@2685: ret_val = igb_init_nvm_params_82575(hw);
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_i210:
fp@2685: case e1000_i211:
fp@2685: ret_val = igb_init_nvm_params_i210(hw);
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* if part supports SR-IOV then initialize mailbox parameters */
fp@2685: switch (mac->type) {
fp@2685: case e1000_82576:
fp@2685: case e1000_i350:
fp@2685: igb_init_mbx_params_pf(hw);
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: /* setup PHY parameters */
fp@2685: ret_val = igb_init_phy_params_82575(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_acquire_phy_82575 - Acquire rights to access PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Acquire access rights to the correct PHY. This is a
fp@2685: * function pointer entry point called by the api module.
fp@2685: **/
fp@2685: static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u16 mask = E1000_SWFW_PHY0_SM;
fp@2685:
fp@2685: if (hw->bus.func == E1000_FUNC_1)
fp@2685: mask = E1000_SWFW_PHY1_SM;
fp@2685: else if (hw->bus.func == E1000_FUNC_2)
fp@2685: mask = E1000_SWFW_PHY2_SM;
fp@2685: else if (hw->bus.func == E1000_FUNC_3)
fp@2685: mask = E1000_SWFW_PHY3_SM;
fp@2685:
fp@2685: return hw->mac.ops.acquire_swfw_sync(hw, mask);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_release_phy_82575 - Release rights to access PHY
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * A wrapper to release access rights to the correct PHY. This is a
fp@2685: * function pointer entry point called by the api module.
fp@2685: **/
fp@2685: static void igb_release_phy_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u16 mask = E1000_SWFW_PHY0_SM;
fp@2685:
fp@2685: if (hw->bus.func == E1000_FUNC_1)
fp@2685: mask = E1000_SWFW_PHY1_SM;
fp@2685: else if (hw->bus.func == E1000_FUNC_2)
fp@2685: mask = E1000_SWFW_PHY2_SM;
fp@2685: else if (hw->bus.func == E1000_FUNC_3)
fp@2685: mask = E1000_SWFW_PHY3_SM;
fp@2685:
fp@2685: hw->mac.ops.release_swfw_sync(hw, mask);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to be read
fp@2685: * @data: pointer to the read data
fp@2685: *
fp@2685: * Reads the PHY register at offset using the serial gigabit media independent
fp@2685: * interface and stores the retrieved information in data.
fp@2685: **/
fp@2685: static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
fp@2685: u16 *data)
fp@2685: {
fp@2685: s32 ret_val = -E1000_ERR_PARAM;
fp@2685:
fp@2685: if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
fp@2685: hw_dbg("PHY Address %u is out of range\n", offset);
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_read_phy_reg_i2c(hw, offset, data);
fp@2685:
fp@2685: hw->phy.ops.release(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to write to
fp@2685: * @data: data to write at register offset
fp@2685: *
fp@2685: * Writes the data to PHY register at the offset using the serial gigabit
fp@2685: * media independent interface.
fp@2685: **/
fp@2685: static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
fp@2685: u16 data)
fp@2685: {
fp@2685: s32 ret_val = -E1000_ERR_PARAM;
fp@2685:
fp@2685:
fp@2685: if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
fp@2685: hw_dbg("PHY Address %d is out of range\n", offset);
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_write_phy_reg_i2c(hw, offset, data);
fp@2685:
fp@2685: hw->phy.ops.release(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_phy_id_82575 - Retrieve PHY addr and id
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Retrieves the PHY address and ID for both PHY's which do and do not use
fp@2685: * sgmi interface.
fp@2685: **/
fp@2685: static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u16 phy_id;
fp@2685: u32 ctrl_ext;
fp@2685: u32 mdic;
fp@2685:
fp@2685: /* Extra read required for some PHY's on i354 */
fp@2685: if (hw->mac.type == e1000_i354)
fp@2685: igb_get_phy_id(hw);
fp@2685:
fp@2685: /* For SGMII PHYs, we try the list of possible addresses until
fp@2685: * we find one that works. For non-SGMII PHYs
fp@2685: * (e.g. integrated copper PHYs), an address of 1 should
fp@2685: * work. The result of this function should mean phy->phy_addr
fp@2685: * and phy->id are set correctly.
fp@2685: */
fp@2685: if (!(igb_sgmii_active_82575(hw))) {
fp@2685: phy->addr = 1;
fp@2685: ret_val = igb_get_phy_id(hw);
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if (igb_sgmii_uses_mdio_82575(hw)) {
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82575:
fp@2685: case e1000_82576:
fp@2685: mdic = rd32(E1000_MDIC);
fp@2685: mdic &= E1000_MDIC_PHY_MASK;
fp@2685: phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
fp@2685: break;
fp@2685: case e1000_82580:
fp@2685: case e1000_i350:
fp@2685: case e1000_i354:
fp@2685: case e1000_i210:
fp@2685: case e1000_i211:
fp@2685: mdic = rd32(E1000_MDICNFG);
fp@2685: mdic &= E1000_MDICNFG_PHY_MASK;
fp@2685: phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
fp@2685: break;
fp@2685: default:
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685: ret_val = igb_get_phy_id(hw);
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Power on sgmii phy if it is disabled */
fp@2685: ctrl_ext = rd32(E1000_CTRL_EXT);
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
fp@2685: wrfl();
fp@2685: msleep(300);
fp@2685:
fp@2685: /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
fp@2685: * Therefore, we need to test 1-7
fp@2685: */
fp@2685: for (phy->addr = 1; phy->addr < 8; phy->addr++) {
fp@2685: ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
fp@2685: if (ret_val == 0) {
fp@2685: hw_dbg("Vendor ID 0x%08X read at address %u\n",
fp@2685: phy_id, phy->addr);
fp@2685: /* At the time of this writing, The M88 part is
fp@2685: * the only supported SGMII PHY product.
fp@2685: */
fp@2685: if (phy_id == M88_VENDOR)
fp@2685: break;
fp@2685: } else {
fp@2685: hw_dbg("PHY address %u was unreadable\n", phy->addr);
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /* A valid PHY type couldn't be found. */
fp@2685: if (phy->addr == 8) {
fp@2685: phy->addr = 0;
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: } else {
fp@2685: ret_val = igb_get_phy_id(hw);
fp@2685: }
fp@2685:
fp@2685: /* restore previous sfp cage power state */
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Resets the PHY using the serial gigabit media independent interface.
fp@2685: **/
fp@2685: static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685:
fp@2685: /* This isn't a true "hard" reset, but is the only reset
fp@2685: * available to us at this time.
fp@2685: */
fp@2685:
fp@2685: hw_dbg("Soft resetting SGMII attached PHY...\n");
fp@2685:
fp@2685: /* SFP documentation requires the following to configure the SPF module
fp@2685: * to work on SGMII. No further documentation is given.
fp@2685: */
fp@2685: ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_phy_sw_reset(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @active: true to enable LPLU, false to disable
fp@2685: *
fp@2685: * Sets the LPLU D0 state according to the active flag. When
fp@2685: * activating LPLU this function also disables smart speed
fp@2685: * and vice versa. LPLU will not be activated unless the
fp@2685: * device autonegotiation advertisement meets standards of
fp@2685: * either 10 or 10/100 or 10/100/1000 at all duplexes.
fp@2685: * This is a function pointer entry point only called by
fp@2685: * PHY setup routines.
fp@2685: **/
fp@2685: static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val;
fp@2685: u16 data;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (active) {
fp@2685: data |= IGP02E1000_PM_D0_LPLU;
fp@2685: ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* When LPLU is enabled, we should disable SmartSpeed */
fp@2685: ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2685: &data);
fp@2685: data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2685: data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: } else {
fp@2685: data &= ~IGP02E1000_PM_D0_LPLU;
fp@2685: ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
fp@2685: data);
fp@2685: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
fp@2685: * during Dx states where the power conservation is most
fp@2685: * important. During driver activity we should enable
fp@2685: * SmartSpeed, so performance is maintained.
fp@2685: */
fp@2685: if (phy->smart_speed == e1000_smart_speed_on) {
fp@2685: ret_val = phy->ops.read_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data |= IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG, data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: } else if (phy->smart_speed == e1000_smart_speed_off) {
fp@2685: ret_val = phy->ops.read_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG, &data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2685: ret_val = phy->ops.write_reg(hw,
fp@2685: IGP01E1000_PHY_PORT_CONFIG, data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @active: true to enable LPLU, false to disable
fp@2685: *
fp@2685: * Sets the LPLU D0 state according to the active flag. When
fp@2685: * activating LPLU this function also disables smart speed
fp@2685: * and vice versa. LPLU will not be activated unless the
fp@2685: * device autonegotiation advertisement meets standards of
fp@2685: * either 10 or 10/100 or 10/100/1000 at all duplexes.
fp@2685: * This is a function pointer entry point only called by
fp@2685: * PHY setup routines.
fp@2685: **/
fp@2685: static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: u16 data;
fp@2685:
fp@2685: data = rd32(E1000_82580_PHY_POWER_MGMT);
fp@2685:
fp@2685: if (active) {
fp@2685: data |= E1000_82580_PM_D0_LPLU;
fp@2685:
fp@2685: /* When LPLU is enabled, we should disable SmartSpeed */
fp@2685: data &= ~E1000_82580_PM_SPD;
fp@2685: } else {
fp@2685: data &= ~E1000_82580_PM_D0_LPLU;
fp@2685:
fp@2685: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
fp@2685: * during Dx states where the power conservation is most
fp@2685: * important. During driver activity we should enable
fp@2685: * SmartSpeed, so performance is maintained.
fp@2685: */
fp@2685: if (phy->smart_speed == e1000_smart_speed_on)
fp@2685: data |= E1000_82580_PM_SPD;
fp@2685: else if (phy->smart_speed == e1000_smart_speed_off)
fp@2685: data &= ~E1000_82580_PM_SPD; }
fp@2685:
fp@2685: wr32(E1000_82580_PHY_POWER_MGMT, data);
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @active: boolean used to enable/disable lplu
fp@2685: *
fp@2685: * Success returns 0, Failure returns 1
fp@2685: *
fp@2685: * The low power link up (lplu) state is set to the power management level D3
fp@2685: * and SmartSpeed is disabled when active is true, else clear lplu for D3
fp@2685: * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
fp@2685: * is used during Dx states where the power conservation is most important.
fp@2685: * During driver activity, SmartSpeed should be enabled so performance is
fp@2685: * maintained.
fp@2685: **/
fp@2685: static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: u16 data;
fp@2685:
fp@2685: data = rd32(E1000_82580_PHY_POWER_MGMT);
fp@2685:
fp@2685: if (!active) {
fp@2685: data &= ~E1000_82580_PM_D3_LPLU;
fp@2685: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
fp@2685: * during Dx states where the power conservation is most
fp@2685: * important. During driver activity we should enable
fp@2685: * SmartSpeed, so performance is maintained.
fp@2685: */
fp@2685: if (phy->smart_speed == e1000_smart_speed_on)
fp@2685: data |= E1000_82580_PM_SPD;
fp@2685: else if (phy->smart_speed == e1000_smart_speed_off)
fp@2685: data &= ~E1000_82580_PM_SPD;
fp@2685: } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
fp@2685: (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
fp@2685: (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
fp@2685: data |= E1000_82580_PM_D3_LPLU;
fp@2685: /* When LPLU is enabled, we should disable SmartSpeed */
fp@2685: data &= ~E1000_82580_PM_SPD;
fp@2685: }
fp@2685:
fp@2685: wr32(E1000_82580_PHY_POWER_MGMT, data);
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_acquire_nvm_82575 - Request for access to EEPROM
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Acquire the necessary semaphores for exclusive access to the EEPROM.
fp@2685: * Set the EEPROM access request bit and wait for EEPROM access grant bit.
fp@2685: * Return successful if access grant bit set, else clear the request for
fp@2685: * EEPROM access and return -E1000_ERR_NVM (-1).
fp@2685: **/
fp@2685: static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685:
fp@2685: ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_acquire_nvm(hw);
fp@2685:
fp@2685: if (ret_val)
fp@2685: hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_release_nvm_82575 - Release exclusive access to EEPROM
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Stop any current commands to the EEPROM and clear the EEPROM request bit,
fp@2685: * then release the semaphores acquired.
fp@2685: **/
fp@2685: static void igb_release_nvm_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: igb_release_nvm(hw);
fp@2685: hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @mask: specifies which semaphore to acquire
fp@2685: *
fp@2685: * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
fp@2685: * will also specify which port we're acquiring the lock for.
fp@2685: **/
fp@2685: static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
fp@2685: {
fp@2685: u32 swfw_sync;
fp@2685: u32 swmask = mask;
fp@2685: u32 fwmask = mask << 16;
fp@2685: s32 ret_val = 0;
fp@2685: s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
fp@2685:
fp@2685: while (i < timeout) {
fp@2685: if (igb_get_hw_semaphore(hw)) {
fp@2685: ret_val = -E1000_ERR_SWFW_SYNC;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: swfw_sync = rd32(E1000_SW_FW_SYNC);
fp@2685: if (!(swfw_sync & (fwmask | swmask)))
fp@2685: break;
fp@2685:
fp@2685: /* Firmware currently using resource (fwmask)
fp@2685: * or other software thread using resource (swmask)
fp@2685: */
fp@2685: igb_put_hw_semaphore(hw);
fp@2685: mdelay(5);
fp@2685: i++;
fp@2685: }
fp@2685:
fp@2685: if (i == timeout) {
fp@2685: hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
fp@2685: ret_val = -E1000_ERR_SWFW_SYNC;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: swfw_sync |= swmask;
fp@2685: wr32(E1000_SW_FW_SYNC, swfw_sync);
fp@2685:
fp@2685: igb_put_hw_semaphore(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_release_swfw_sync_82575 - Release SW/FW semaphore
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @mask: specifies which semaphore to acquire
fp@2685: *
fp@2685: * Release the SW/FW semaphore used to access the PHY or NVM. The mask
fp@2685: * will also specify which port we're releasing the lock for.
fp@2685: **/
fp@2685: static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
fp@2685: {
fp@2685: u32 swfw_sync;
fp@2685:
fp@2685: while (igb_get_hw_semaphore(hw) != 0)
fp@2685: ; /* Empty */
fp@2685:
fp@2685: swfw_sync = rd32(E1000_SW_FW_SYNC);
fp@2685: swfw_sync &= ~mask;
fp@2685: wr32(E1000_SW_FW_SYNC, swfw_sync);
fp@2685:
fp@2685: igb_put_hw_semaphore(hw);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_cfg_done_82575 - Read config done bit
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Read the management control register for the config done bit for
fp@2685: * completion status. NOTE: silicon which is EEPROM-less will fail trying
fp@2685: * to read the config done bit, so an error is *ONLY* logged and returns
fp@2685: * 0. If we were to return with error, EEPROM-less silicon
fp@2685: * would not be able to be reset or change link.
fp@2685: **/
fp@2685: static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 timeout = PHY_CFG_TIMEOUT;
fp@2685: u32 mask = E1000_NVM_CFG_DONE_PORT_0;
fp@2685:
fp@2685: if (hw->bus.func == 1)
fp@2685: mask = E1000_NVM_CFG_DONE_PORT_1;
fp@2685: else if (hw->bus.func == E1000_FUNC_2)
fp@2685: mask = E1000_NVM_CFG_DONE_PORT_2;
fp@2685: else if (hw->bus.func == E1000_FUNC_3)
fp@2685: mask = E1000_NVM_CFG_DONE_PORT_3;
fp@2685:
fp@2685: while (timeout) {
fp@2685: if (rd32(E1000_EEMNGCTL) & mask)
fp@2685: break;
fp@2685: usleep_range(1000, 2000);
fp@2685: timeout--;
fp@2685: }
fp@2685: if (!timeout)
fp@2685: hw_dbg("MNG configuration cycle has not completed.\n");
fp@2685:
fp@2685: /* If EEPROM is not marked present, init the PHY manually */
fp@2685: if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
fp@2685: (hw->phy.type == e1000_phy_igp_3))
fp@2685: igb_phy_init_script_igp3(hw);
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_link_up_info_82575 - Get link speed/duplex info
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @speed: stores the current speed
fp@2685: * @duplex: stores the current duplex
fp@2685: *
fp@2685: * This is a wrapper function, if using the serial gigabit media independent
fp@2685: * interface, use PCS to retrieve the link speed and duplex information.
fp@2685: * Otherwise, use the generic function to get the link speed and duplex info.
fp@2685: **/
fp@2685: static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
fp@2685: u16 *duplex)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685:
fp@2685: if (hw->phy.media_type != e1000_media_type_copper)
fp@2685: ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
fp@2685: duplex);
fp@2685: else
fp@2685: ret_val = igb_get_speed_and_duplex_copper(hw, speed,
fp@2685: duplex);
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_for_link_82575 - Check for link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * If sgmii is enabled, then use the pcs register to determine link, otherwise
fp@2685: * use the generic interface for determining link.
fp@2685: **/
fp@2685: static s32 igb_check_for_link_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: u16 speed, duplex;
fp@2685:
fp@2685: if (hw->phy.media_type != e1000_media_type_copper) {
fp@2685: ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
fp@2685: &duplex);
fp@2685: /* Use this flag to determine if link needs to be checked or
fp@2685: * not. If we have link clear the flag so that we do not
fp@2685: * continue to check for link.
fp@2685: */
fp@2685: hw->mac.get_link_status = !hw->mac.serdes_has_link;
fp@2685:
fp@2685: /* Configure Flow Control now that Auto-Neg has completed.
fp@2685: * First, we need to restore the desired flow control
fp@2685: * settings because we may have had to re-autoneg with a
fp@2685: * different link partner.
fp@2685: */
fp@2685: ret_val = igb_config_fc_after_link_up(hw);
fp@2685: if (ret_val)
fp@2685: hw_dbg("Error configuring flow control\n");
fp@2685: } else {
fp@2685: ret_val = igb_check_for_copper_link(hw);
fp@2685: }
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
fp@2685: * @hw: pointer to the HW structure
fp@2685: **/
fp@2685: void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 reg;
fp@2685:
fp@2685:
fp@2685: if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
fp@2685: !igb_sgmii_active_82575(hw))
fp@2685: return;
fp@2685:
fp@2685: /* Enable PCS to turn on link */
fp@2685: reg = rd32(E1000_PCS_CFG0);
fp@2685: reg |= E1000_PCS_CFG_PCS_EN;
fp@2685: wr32(E1000_PCS_CFG0, reg);
fp@2685:
fp@2685: /* Power up the laser */
fp@2685: reg = rd32(E1000_CTRL_EXT);
fp@2685: reg &= ~E1000_CTRL_EXT_SDP3_DATA;
fp@2685: wr32(E1000_CTRL_EXT, reg);
fp@2685:
fp@2685: /* flush the write to verify completion */
fp@2685: wrfl();
fp@2685: usleep_range(1000, 2000);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @speed: stores the current speed
fp@2685: * @duplex: stores the current duplex
fp@2685: *
fp@2685: * Using the physical coding sub-layer (PCS), retrieve the current speed and
fp@2685: * duplex, then store the values in the pointers provided.
fp@2685: **/
fp@2685: static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
fp@2685: u16 *duplex)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: u32 pcs, status;
fp@2685:
fp@2685: /* Set up defaults for the return values of this function */
fp@2685: mac->serdes_has_link = false;
fp@2685: *speed = 0;
fp@2685: *duplex = 0;
fp@2685:
fp@2685: /* Read the PCS Status register for link state. For non-copper mode,
fp@2685: * the status register is not accurate. The PCS status register is
fp@2685: * used instead.
fp@2685: */
fp@2685: pcs = rd32(E1000_PCS_LSTAT);
fp@2685:
fp@2685: /* The link up bit determines when link is up on autoneg. The sync ok
fp@2685: * gets set once both sides sync up and agree upon link. Stable link
fp@2685: * can be determined by checking for both link up and link sync ok
fp@2685: */
fp@2685: if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
fp@2685: mac->serdes_has_link = true;
fp@2685:
fp@2685: /* Detect and store PCS speed */
fp@2685: if (pcs & E1000_PCS_LSTS_SPEED_1000)
fp@2685: *speed = SPEED_1000;
fp@2685: else if (pcs & E1000_PCS_LSTS_SPEED_100)
fp@2685: *speed = SPEED_100;
fp@2685: else
fp@2685: *speed = SPEED_10;
fp@2685:
fp@2685: /* Detect and store PCS duplex */
fp@2685: if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
fp@2685: *duplex = FULL_DUPLEX;
fp@2685: else
fp@2685: *duplex = HALF_DUPLEX;
fp@2685:
fp@2685: /* Check if it is an I354 2.5Gb backplane connection. */
fp@2685: if (mac->type == e1000_i354) {
fp@2685: status = rd32(E1000_STATUS);
fp@2685: if ((status & E1000_STATUS_2P5_SKU) &&
fp@2685: !(status & E1000_STATUS_2P5_SKU_OVER)) {
fp@2685: *speed = SPEED_2500;
fp@2685: *duplex = FULL_DUPLEX;
fp@2685: hw_dbg("2500 Mbs, ");
fp@2685: hw_dbg("Full Duplex\n");
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_shutdown_serdes_link_82575 - Remove link during power down
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * In the case of fiber serdes, shut down optics and PCS on driver unload
fp@2685: * when management pass thru is not enabled.
fp@2685: **/
fp@2685: void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 reg;
fp@2685:
fp@2685: if (hw->phy.media_type != e1000_media_type_internal_serdes &&
fp@2685: igb_sgmii_active_82575(hw))
fp@2685: return;
fp@2685:
fp@2685: if (!igb_enable_mng_pass_thru(hw)) {
fp@2685: /* Disable PCS to turn off link */
fp@2685: reg = rd32(E1000_PCS_CFG0);
fp@2685: reg &= ~E1000_PCS_CFG_PCS_EN;
fp@2685: wr32(E1000_PCS_CFG0, reg);
fp@2685:
fp@2685: /* shutdown the laser */
fp@2685: reg = rd32(E1000_CTRL_EXT);
fp@2685: reg |= E1000_CTRL_EXT_SDP3_DATA;
fp@2685: wr32(E1000_CTRL_EXT, reg);
fp@2685:
fp@2685: /* flush the write to verify completion */
fp@2685: wrfl();
fp@2685: usleep_range(1000, 2000);
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_reset_hw_82575 - Reset hardware
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * This resets the hardware into a known state. This is a
fp@2685: * function pointer entry point called by the api module.
fp@2685: **/
fp@2685: static s32 igb_reset_hw_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 ctrl;
fp@2685: s32 ret_val;
fp@2685:
fp@2685: /* Prevent the PCI-E bus from sticking if there is no TLP connection
fp@2685: * on the last TLP read/write transaction when MAC is reset.
fp@2685: */
fp@2685: ret_val = igb_disable_pcie_master(hw);
fp@2685: if (ret_val)
fp@2685: hw_dbg("PCI-E Master disable polling has failed.\n");
fp@2685:
fp@2685: /* set the completion timeout for interface */
fp@2685: ret_val = igb_set_pcie_completion_timeout(hw);
fp@2685: if (ret_val)
fp@2685: hw_dbg("PCI-E Set completion timeout has failed.\n");
fp@2685:
fp@2685: hw_dbg("Masking off all interrupts\n");
fp@2685: wr32(E1000_IMC, 0xffffffff);
fp@2685:
fp@2685: wr32(E1000_RCTL, 0);
fp@2685: wr32(E1000_TCTL, E1000_TCTL_PSP);
fp@2685: wrfl();
fp@2685:
fp@2685: usleep_range(10000, 20000);
fp@2685:
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685:
fp@2685: hw_dbg("Issuing a global reset to MAC\n");
fp@2685: wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
fp@2685:
fp@2685: ret_val = igb_get_auto_rd_done(hw);
fp@2685: if (ret_val) {
fp@2685: /* When auto config read does not complete, do not
fp@2685: * return with an error. This can happen in situations
fp@2685: * where there is no eeprom and prevents getting link.
fp@2685: */
fp@2685: hw_dbg("Auto Read Done did not complete\n");
fp@2685: }
fp@2685:
fp@2685: /* If EEPROM is not present, run manual init scripts */
fp@2685: if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
fp@2685: igb_reset_init_script_82575(hw);
fp@2685:
fp@2685: /* Clear any pending interrupt events. */
fp@2685: wr32(E1000_IMC, 0xffffffff);
fp@2685: rd32(E1000_ICR);
fp@2685:
fp@2685: /* Install any alternate MAC address into RAR0 */
fp@2685: ret_val = igb_check_alt_mac_addr(hw);
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_init_hw_82575 - Initialize hardware
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * This inits the hardware readying it for operation.
fp@2685: **/
fp@2685: static s32 igb_init_hw_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: s32 ret_val;
fp@2685: u16 i, rar_count = mac->rar_entry_count;
fp@2685:
fp@2685: if ((hw->mac.type >= e1000_i210) &&
fp@2685: !(igb_get_flash_presence_i210(hw))) {
fp@2685: ret_val = igb_pll_workaround_i210(hw);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /* Initialize identification LED */
fp@2685: ret_val = igb_id_led_init(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error initializing identification LED\n");
fp@2685: /* This is not fatal and we should not stop init due to this */
fp@2685: }
fp@2685:
fp@2685: /* Disabling VLAN filtering */
fp@2685: hw_dbg("Initializing the IEEE VLAN\n");
fp@2685: if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
fp@2685: igb_clear_vfta_i350(hw);
fp@2685: else
fp@2685: igb_clear_vfta(hw);
fp@2685:
fp@2685: /* Setup the receive address */
fp@2685: igb_init_rx_addrs(hw, rar_count);
fp@2685:
fp@2685: /* Zero out the Multicast HASH table */
fp@2685: hw_dbg("Zeroing the MTA\n");
fp@2685: for (i = 0; i < mac->mta_reg_count; i++)
fp@2685: array_wr32(E1000_MTA, i, 0);
fp@2685:
fp@2685: /* Zero out the Unicast HASH table */
fp@2685: hw_dbg("Zeroing the UTA\n");
fp@2685: for (i = 0; i < mac->uta_reg_count; i++)
fp@2685: array_wr32(E1000_UTA, i, 0);
fp@2685:
fp@2685: /* Setup link and flow control */
fp@2685: ret_val = igb_setup_link(hw);
fp@2685:
fp@2685: /* Clear all of the statistics registers (clear on read). It is
fp@2685: * important that we do this after we have tried to establish link
fp@2685: * because the symbol error count will increment wildly if there
fp@2685: * is no link.
fp@2685: */
fp@2685: igb_clear_hw_cntrs_82575(hw);
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_setup_copper_link_82575 - Configure copper link settings
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Configures the link for auto-neg or forced speed and duplex. Then we check
fp@2685: * for link, once link is established calls to configure collision distance
fp@2685: * and flow control are called.
fp@2685: **/
fp@2685: static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 ctrl;
fp@2685: s32 ret_val;
fp@2685: u32 phpm_reg;
fp@2685:
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685: ctrl |= E1000_CTRL_SLU;
fp@2685: ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
fp@2685: wr32(E1000_CTRL, ctrl);
fp@2685:
fp@2685: /* Clear Go Link Disconnect bit on supported devices */
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82580:
fp@2685: case e1000_i350:
fp@2685: case e1000_i210:
fp@2685: case e1000_i211:
fp@2685: phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
fp@2685: phpm_reg &= ~E1000_82580_PM_GO_LINKD;
fp@2685: wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: ret_val = igb_setup_serdes_link_82575(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
fp@2685: /* allow time for SFP cage time to power up phy */
fp@2685: msleep(300);
fp@2685:
fp@2685: ret_val = hw->phy.ops.reset(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error resetting the PHY.\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685: switch (hw->phy.type) {
fp@2685: case e1000_phy_i210:
fp@2685: case e1000_phy_m88:
fp@2685: switch (hw->phy.id) {
fp@2685: case I347AT4_E_PHY_ID:
fp@2685: case M88E1112_E_PHY_ID:
fp@2685: case M88E1543_E_PHY_ID:
fp@2685: case I210_I_PHY_ID:
fp@2685: ret_val = igb_copper_link_setup_m88_gen2(hw);
fp@2685: break;
fp@2685: default:
fp@2685: ret_val = igb_copper_link_setup_m88(hw);
fp@2685: break;
fp@2685: }
fp@2685: break;
fp@2685: case e1000_phy_igp_3:
fp@2685: ret_val = igb_copper_link_setup_igp(hw);
fp@2685: break;
fp@2685: case e1000_phy_82580:
fp@2685: ret_val = igb_copper_link_setup_82580(hw);
fp@2685: break;
fp@2685: default:
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_setup_copper_link(hw);
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_setup_serdes_link_82575 - Setup link for serdes
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Configure the physical coding sub-layer (PCS) link. The PCS link is
fp@2685: * used on copper connections where the serialized gigabit media independent
fp@2685: * interface (sgmii), or serdes fiber is being used. Configures the link
fp@2685: * for auto-negotiation or forces speed/duplex.
fp@2685: **/
fp@2685: static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
fp@2685: bool pcs_autoneg;
fp@2685: s32 ret_val = 0;
fp@2685: u16 data;
fp@2685:
fp@2685: if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
fp@2685: !igb_sgmii_active_82575(hw))
fp@2685: return ret_val;
fp@2685:
fp@2685:
fp@2685: /* On the 82575, SerDes loopback mode persists until it is
fp@2685: * explicitly turned off or a power cycle is performed. A read to
fp@2685: * the register does not indicate its status. Therefore, we ensure
fp@2685: * loopback mode is disabled during initialization.
fp@2685: */
fp@2685: wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
fp@2685:
fp@2685: /* power on the sfp cage if present and turn on I2C */
fp@2685: ctrl_ext = rd32(E1000_CTRL_EXT);
fp@2685: ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
fp@2685: ctrl_ext |= E1000_CTRL_I2C_ENA;
fp@2685: wr32(E1000_CTRL_EXT, ctrl_ext);
fp@2685:
fp@2685: ctrl_reg = rd32(E1000_CTRL);
fp@2685: ctrl_reg |= E1000_CTRL_SLU;
fp@2685:
fp@2685: if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
fp@2685: /* set both sw defined pins */
fp@2685: ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
fp@2685:
fp@2685: /* Set switch control to serdes energy detect */
fp@2685: reg = rd32(E1000_CONNSW);
fp@2685: reg |= E1000_CONNSW_ENRGSRC;
fp@2685: wr32(E1000_CONNSW, reg);
fp@2685: }
fp@2685:
fp@2685: reg = rd32(E1000_PCS_LCTL);
fp@2685:
fp@2685: /* default pcs_autoneg to the same setting as mac autoneg */
fp@2685: pcs_autoneg = hw->mac.autoneg;
fp@2685:
fp@2685: switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
fp@2685: case E1000_CTRL_EXT_LINK_MODE_SGMII:
fp@2685: /* sgmii mode lets the phy handle forcing speed/duplex */
fp@2685: pcs_autoneg = true;
fp@2685: /* autoneg time out should be disabled for SGMII mode */
fp@2685: reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
fp@2685: break;
fp@2685: case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
fp@2685: /* disable PCS autoneg and support parallel detect only */
fp@2685: pcs_autoneg = false;
fp@2685: default:
fp@2685: if (hw->mac.type == e1000_82575 ||
fp@2685: hw->mac.type == e1000_82576) {
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
fp@2685: pcs_autoneg = false;
fp@2685: }
fp@2685:
fp@2685: /* non-SGMII modes only supports a speed of 1000/Full for the
fp@2685: * link so it is best to just force the MAC and let the pcs
fp@2685: * link either autoneg or be forced to 1000/Full
fp@2685: */
fp@2685: ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
fp@2685: E1000_CTRL_FD | E1000_CTRL_FRCDPX;
fp@2685:
fp@2685: /* set speed of 1000/Full if speed/duplex is forced */
fp@2685: reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: wr32(E1000_CTRL, ctrl_reg);
fp@2685:
fp@2685: /* New SerDes mode allows for forcing speed or autonegotiating speed
fp@2685: * at 1gb. Autoneg should be default set by most drivers. This is the
fp@2685: * mode that will be compatible with older link partners and switches.
fp@2685: * However, both are supported by the hardware and some drivers/tools.
fp@2685: */
fp@2685: reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
fp@2685: E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
fp@2685:
fp@2685: if (pcs_autoneg) {
fp@2685: /* Set PCS register for autoneg */
fp@2685: reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
fp@2685: E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
fp@2685:
fp@2685: /* Disable force flow control for autoneg */
fp@2685: reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
fp@2685:
fp@2685: /* Configure flow control advertisement for autoneg */
fp@2685: anadv_reg = rd32(E1000_PCS_ANADV);
fp@2685: anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
fp@2685: switch (hw->fc.requested_mode) {
fp@2685: case e1000_fc_full:
fp@2685: case e1000_fc_rx_pause:
fp@2685: anadv_reg |= E1000_TXCW_ASM_DIR;
fp@2685: anadv_reg |= E1000_TXCW_PAUSE;
fp@2685: break;
fp@2685: case e1000_fc_tx_pause:
fp@2685: anadv_reg |= E1000_TXCW_ASM_DIR;
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685: wr32(E1000_PCS_ANADV, anadv_reg);
fp@2685:
fp@2685: hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
fp@2685: } else {
fp@2685: /* Set PCS register for forced link */
fp@2685: reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
fp@2685:
fp@2685: /* Force flow control for forced link */
fp@2685: reg |= E1000_PCS_LCTL_FORCE_FCTRL;
fp@2685:
fp@2685: hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
fp@2685: }
fp@2685:
fp@2685: wr32(E1000_PCS_LCTL, reg);
fp@2685:
fp@2685: if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
fp@2685: igb_force_mac_fc(hw);
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_sgmii_active_82575 - Return sgmii state
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * 82575 silicon has a serialized gigabit media independent interface (sgmii)
fp@2685: * which can be enabled for use in the embedded applications. Simply
fp@2685: * return the current state of the sgmii interface.
fp@2685: **/
fp@2685: static bool igb_sgmii_active_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
fp@2685: return dev_spec->sgmii_active;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_reset_init_script_82575 - Inits HW defaults after reset
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Inits recommended HW defaults after a reset when there is no EEPROM
fp@2685: * detected. This is only for the 82575.
fp@2685: **/
fp@2685: static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: if (hw->mac.type == e1000_82575) {
fp@2685: hw_dbg("Running reset init script for 82575\n");
fp@2685: /* SerDes configuration via SERDESCTRL */
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
fp@2685:
fp@2685: /* CCM configuration via CCMCTL register */
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
fp@2685:
fp@2685: /* PCIe lanes configuration */
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
fp@2685:
fp@2685: /* PCIe PLL Configuration */
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
fp@2685: igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_mac_addr_82575 - Read device MAC address
fp@2685: * @hw: pointer to the HW structure
fp@2685: **/
fp@2685: static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: /* If there's an alternate MAC address place it in RAR0
fp@2685: * so that it will override the Si installed default perm
fp@2685: * address.
fp@2685: */
fp@2685: ret_val = igb_check_alt_mac_addr(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_read_mac_addr(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_power_down_phy_copper_82575 - Remove link during PHY power down
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * In the case of a PHY power down to save power, or to turn off link during a
fp@2685: * driver unload, or wake on lan is not enabled, remove the link.
fp@2685: **/
fp@2685: void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: /* If the management interface is not enabled, then power down */
fp@2685: if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
fp@2685: igb_power_down_phy_copper(hw);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Clears the hardware counters by reading the counter registers.
fp@2685: **/
fp@2685: static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: igb_clear_hw_cntrs_base(hw);
fp@2685:
fp@2685: rd32(E1000_PRC64);
fp@2685: rd32(E1000_PRC127);
fp@2685: rd32(E1000_PRC255);
fp@2685: rd32(E1000_PRC511);
fp@2685: rd32(E1000_PRC1023);
fp@2685: rd32(E1000_PRC1522);
fp@2685: rd32(E1000_PTC64);
fp@2685: rd32(E1000_PTC127);
fp@2685: rd32(E1000_PTC255);
fp@2685: rd32(E1000_PTC511);
fp@2685: rd32(E1000_PTC1023);
fp@2685: rd32(E1000_PTC1522);
fp@2685:
fp@2685: rd32(E1000_ALGNERRC);
fp@2685: rd32(E1000_RXERRC);
fp@2685: rd32(E1000_TNCRS);
fp@2685: rd32(E1000_CEXTERR);
fp@2685: rd32(E1000_TSCTC);
fp@2685: rd32(E1000_TSCTFC);
fp@2685:
fp@2685: rd32(E1000_MGTPRC);
fp@2685: rd32(E1000_MGTPDC);
fp@2685: rd32(E1000_MGTPTC);
fp@2685:
fp@2685: rd32(E1000_IAC);
fp@2685: rd32(E1000_ICRXOC);
fp@2685:
fp@2685: rd32(E1000_ICRXPTC);
fp@2685: rd32(E1000_ICRXATC);
fp@2685: rd32(E1000_ICTXPTC);
fp@2685: rd32(E1000_ICTXATC);
fp@2685: rd32(E1000_ICTXQEC);
fp@2685: rd32(E1000_ICTXQMTC);
fp@2685: rd32(E1000_ICRXDMTC);
fp@2685:
fp@2685: rd32(E1000_CBTMPC);
fp@2685: rd32(E1000_HTDPMC);
fp@2685: rd32(E1000_CBRMPC);
fp@2685: rd32(E1000_RPTHC);
fp@2685: rd32(E1000_HGPTC);
fp@2685: rd32(E1000_HTCBDPC);
fp@2685: rd32(E1000_HGORCL);
fp@2685: rd32(E1000_HGORCH);
fp@2685: rd32(E1000_HGOTCL);
fp@2685: rd32(E1000_HGOTCH);
fp@2685: rd32(E1000_LENERRS);
fp@2685:
fp@2685: /* This register should not be read in copper configurations */
fp@2685: if (hw->phy.media_type == e1000_media_type_internal_serdes ||
fp@2685: igb_sgmii_active_82575(hw))
fp@2685: rd32(E1000_SCVPC);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * After rx enable if managability is enabled then there is likely some
fp@2685: * bad data at the start of the fifo and possibly in the DMA fifo. This
fp@2685: * function clears the fifos and flushes any packets that came in as rx was
fp@2685: * being enabled.
fp@2685: **/
fp@2685: void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
fp@2685: int i, ms_wait;
fp@2685:
fp@2685: if (hw->mac.type != e1000_82575 ||
fp@2685: !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
fp@2685: return;
fp@2685:
fp@2685: /* Disable all RX queues */
fp@2685: for (i = 0; i < 4; i++) {
fp@2685: rxdctl[i] = rd32(E1000_RXDCTL(i));
fp@2685: wr32(E1000_RXDCTL(i),
fp@2685: rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
fp@2685: }
fp@2685: /* Poll all queues to verify they have shut down */
fp@2685: for (ms_wait = 0; ms_wait < 10; ms_wait++) {
fp@2685: usleep_range(1000, 2000);
fp@2685: rx_enabled = 0;
fp@2685: for (i = 0; i < 4; i++)
fp@2685: rx_enabled |= rd32(E1000_RXDCTL(i));
fp@2685: if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: if (ms_wait == 10)
fp@2685: hw_dbg("Queue disable timed out after 10ms\n");
fp@2685:
fp@2685: /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
fp@2685: * incoming packets are rejected. Set enable and wait 2ms so that
fp@2685: * any packet that was coming in as RCTL.EN was set is flushed
fp@2685: */
fp@2685: rfctl = rd32(E1000_RFCTL);
fp@2685: wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
fp@2685:
fp@2685: rlpml = rd32(E1000_RLPML);
fp@2685: wr32(E1000_RLPML, 0);
fp@2685:
fp@2685: rctl = rd32(E1000_RCTL);
fp@2685: temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
fp@2685: temp_rctl |= E1000_RCTL_LPE;
fp@2685:
fp@2685: wr32(E1000_RCTL, temp_rctl);
fp@2685: wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
fp@2685: wrfl();
fp@2685: usleep_range(2000, 3000);
fp@2685:
fp@2685: /* Enable RX queues that were previously enabled and restore our
fp@2685: * previous state
fp@2685: */
fp@2685: for (i = 0; i < 4; i++)
fp@2685: wr32(E1000_RXDCTL(i), rxdctl[i]);
fp@2685: wr32(E1000_RCTL, rctl);
fp@2685: wrfl();
fp@2685:
fp@2685: wr32(E1000_RLPML, rlpml);
fp@2685: wr32(E1000_RFCTL, rfctl);
fp@2685:
fp@2685: /* Flush receive errors generated by workaround */
fp@2685: rd32(E1000_ROC);
fp@2685: rd32(E1000_RNBC);
fp@2685: rd32(E1000_MPC);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_pcie_completion_timeout - set pci-e completion timeout
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
fp@2685: * however the hardware default for these parts is 500us to 1ms which is less
fp@2685: * than the 10ms recommended by the pci-e spec. To address this we need to
fp@2685: * increase the value to either 10ms to 200ms for capability version 1 config,
fp@2685: * or 16ms to 55ms for version 2.
fp@2685: **/
fp@2685: static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 gcr = rd32(E1000_GCR);
fp@2685: s32 ret_val = 0;
fp@2685: u16 pcie_devctl2;
fp@2685:
fp@2685: /* only take action if timeout value is defaulted to 0 */
fp@2685: if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
fp@2685: goto out;
fp@2685:
fp@2685: /* if capabilities version is type 1 we can write the
fp@2685: * timeout of 10ms to 200ms through the GCR register
fp@2685: */
fp@2685: if (!(gcr & E1000_GCR_CAP_VER2)) {
fp@2685: gcr |= E1000_GCR_CMPL_TMOUT_10ms;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* for version 2 capabilities we need to write the config space
fp@2685: * directly in order to set the completion timeout value for
fp@2685: * 16ms to 55ms
fp@2685: */
fp@2685: ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
fp@2685: &pcie_devctl2);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
fp@2685:
fp@2685: ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
fp@2685: &pcie_devctl2);
fp@2685: out:
fp@2685: /* disable completion timeout resend */
fp@2685: gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
fp@2685:
fp@2685: wr32(E1000_GCR, gcr);
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
fp@2685: * @hw: pointer to the hardware struct
fp@2685: * @enable: state to enter, either enabled or disabled
fp@2685: * @pf: Physical Function pool - do not set anti-spoofing for the PF
fp@2685: *
fp@2685: * enables/disables L2 switch anti-spoofing functionality.
fp@2685: **/
fp@2685: void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
fp@2685: {
fp@2685: u32 reg_val, reg_offset;
fp@2685:
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82576:
fp@2685: reg_offset = E1000_DTXSWC;
fp@2685: break;
fp@2685: case e1000_i350:
fp@2685: case e1000_i354:
fp@2685: reg_offset = E1000_TXSWC;
fp@2685: break;
fp@2685: default:
fp@2685: return;
fp@2685: }
fp@2685:
fp@2685: reg_val = rd32(reg_offset);
fp@2685: if (enable) {
fp@2685: reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
fp@2685: E1000_DTXSWC_VLAN_SPOOF_MASK);
fp@2685: /* The PF can spoof - it has to in order to
fp@2685: * support emulation mode NICs
fp@2685: */
fp@2685: reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
fp@2685: } else {
fp@2685: reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
fp@2685: E1000_DTXSWC_VLAN_SPOOF_MASK);
fp@2685: }
fp@2685: wr32(reg_offset, reg_val);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
fp@2685: * @hw: pointer to the hardware struct
fp@2685: * @enable: state to enter, either enabled or disabled
fp@2685: *
fp@2685: * enables/disables L2 switch loopback functionality.
fp@2685: **/
fp@2685: void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
fp@2685: {
fp@2685: u32 dtxswc;
fp@2685:
fp@2685: switch (hw->mac.type) {
fp@2685: case e1000_82576:
fp@2685: dtxswc = rd32(E1000_DTXSWC);
fp@2685: if (enable)
fp@2685: dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
fp@2685: else
fp@2685: dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
fp@2685: wr32(E1000_DTXSWC, dtxswc);
fp@2685: break;
fp@2685: case e1000_i354:
fp@2685: case e1000_i350:
fp@2685: dtxswc = rd32(E1000_TXSWC);
fp@2685: if (enable)
fp@2685: dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
fp@2685: else
fp@2685: dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
fp@2685: wr32(E1000_TXSWC, dtxswc);
fp@2685: break;
fp@2685: default:
fp@2685: /* Currently no other hardware supports loopback */
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_vmdq_set_replication_pf - enable or disable vmdq replication
fp@2685: * @hw: pointer to the hardware struct
fp@2685: * @enable: state to enter, either enabled or disabled
fp@2685: *
fp@2685: * enables/disables replication of packets across multiple pools.
fp@2685: **/
fp@2685: void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
fp@2685: {
fp@2685: u32 vt_ctl = rd32(E1000_VT_CTL);
fp@2685:
fp@2685: if (enable)
fp@2685: vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
fp@2685: else
fp@2685: vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
fp@2685:
fp@2685: wr32(E1000_VT_CTL, vt_ctl);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_phy_reg_82580 - Read 82580 MDI control register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to be read
fp@2685: * @data: pointer to the read data
fp@2685: *
fp@2685: * Reads the MDI control register in the PHY at offset and stores the
fp@2685: * information read to data.
fp@2685: **/
fp@2685: static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685:
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_read_phy_reg_mdic(hw, offset, data);
fp@2685:
fp@2685: hw->phy.ops.release(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_phy_reg_82580 - Write 82580 MDI control register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset to write to
fp@2685: * @data: data to write to register at offset
fp@2685: *
fp@2685: * Writes data to MDI control register in the PHY at offset.
fp@2685: **/
fp@2685: static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685:
fp@2685:
fp@2685: ret_val = hw->phy.ops.acquire(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_write_phy_reg_mdic(hw, offset, data);
fp@2685:
fp@2685: hw->phy.ops.release(hw);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
fp@2685: * the values found in the EEPROM. This addresses an issue in which these
fp@2685: * bits are not restored from EEPROM after reset.
fp@2685: **/
fp@2685: static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u32 mdicnfg;
fp@2685: u16 nvm_data = 0;
fp@2685:
fp@2685: if (hw->mac.type != e1000_82580)
fp@2685: goto out;
fp@2685: if (!igb_sgmii_active_82575(hw))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
fp@2685: NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
fp@2685: &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: mdicnfg = rd32(E1000_MDICNFG);
fp@2685: if (nvm_data & NVM_WORD24_EXT_MDIO)
fp@2685: mdicnfg |= E1000_MDICNFG_EXT_MDIO;
fp@2685: if (nvm_data & NVM_WORD24_COM_MDIO)
fp@2685: mdicnfg |= E1000_MDICNFG_COM_MDIO;
fp@2685: wr32(E1000_MDICNFG, mdicnfg);
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_reset_hw_82580 - Reset hardware
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * This resets function or entire device (all ports, etc.)
fp@2685: * to a known state.
fp@2685: **/
fp@2685: static s32 igb_reset_hw_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: /* BH SW mailbox bit in SW_FW_SYNC */
fp@2685: u16 swmbsw_mask = E1000_SW_SYNCH_MB;
fp@2685: u32 ctrl;
fp@2685: bool global_device_reset = hw->dev_spec._82575.global_device_reset;
fp@2685:
fp@2685: hw->dev_spec._82575.global_device_reset = false;
fp@2685:
fp@2685: /* due to hw errata, global device reset doesn't always
fp@2685: * work on 82580
fp@2685: */
fp@2685: if (hw->mac.type == e1000_82580)
fp@2685: global_device_reset = false;
fp@2685:
fp@2685: /* Get current control state. */
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685:
fp@2685: /* Prevent the PCI-E bus from sticking if there is no TLP connection
fp@2685: * on the last TLP read/write transaction when MAC is reset.
fp@2685: */
fp@2685: ret_val = igb_disable_pcie_master(hw);
fp@2685: if (ret_val)
fp@2685: hw_dbg("PCI-E Master disable polling has failed.\n");
fp@2685:
fp@2685: hw_dbg("Masking off all interrupts\n");
fp@2685: wr32(E1000_IMC, 0xffffffff);
fp@2685: wr32(E1000_RCTL, 0);
fp@2685: wr32(E1000_TCTL, E1000_TCTL_PSP);
fp@2685: wrfl();
fp@2685:
fp@2685: usleep_range(10000, 11000);
fp@2685:
fp@2685: /* Determine whether or not a global dev reset is requested */
fp@2685: if (global_device_reset &&
fp@2685: hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
fp@2685: global_device_reset = false;
fp@2685:
fp@2685: if (global_device_reset &&
fp@2685: !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
fp@2685: ctrl |= E1000_CTRL_DEV_RST;
fp@2685: else
fp@2685: ctrl |= E1000_CTRL_RST;
fp@2685:
fp@2685: wr32(E1000_CTRL, ctrl);
fp@2685: wrfl();
fp@2685:
fp@2685: /* Add delay to insure DEV_RST has time to complete */
fp@2685: if (global_device_reset)
fp@2685: usleep_range(5000, 6000);
fp@2685:
fp@2685: ret_val = igb_get_auto_rd_done(hw);
fp@2685: if (ret_val) {
fp@2685: /* When auto config read does not complete, do not
fp@2685: * return with an error. This can happen in situations
fp@2685: * where there is no eeprom and prevents getting link.
fp@2685: */
fp@2685: hw_dbg("Auto Read Done did not complete\n");
fp@2685: }
fp@2685:
fp@2685: /* clear global device reset status bit */
fp@2685: wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
fp@2685:
fp@2685: /* Clear any pending interrupt events. */
fp@2685: wr32(E1000_IMC, 0xffffffff);
fp@2685: rd32(E1000_ICR);
fp@2685:
fp@2685: ret_val = igb_reset_mdicnfg_82580(hw);
fp@2685: if (ret_val)
fp@2685: hw_dbg("Could not reset MDICNFG based on EEPROM\n");
fp@2685:
fp@2685: /* Install any alternate MAC address into RAR0 */
fp@2685: ret_val = igb_check_alt_mac_addr(hw);
fp@2685:
fp@2685: /* Release semaphore */
fp@2685: if (global_device_reset)
fp@2685: hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
fp@2685: * @data: data received by reading RXPBS register
fp@2685: *
fp@2685: * The 82580 uses a table based approach for packet buffer allocation sizes.
fp@2685: * This function converts the retrieved value into the correct table value
fp@2685: * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
fp@2685: * 0x0 36 72 144 1 2 4 8 16
fp@2685: * 0x8 35 70 140 rsv rsv rsv rsv rsv
fp@2685: */
fp@2685: u16 igb_rxpbs_adjust_82580(u32 data)
fp@2685: {
fp@2685: u16 ret_val = 0;
fp@2685:
fp@2685: if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
fp@2685: ret_val = e1000_82580_rxpbs_table[data];
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_validate_nvm_checksum_with_offset - Validate EEPROM
fp@2685: * checksum
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: offset in words of the checksum protected region
fp@2685: *
fp@2685: * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2685: * and then verifies that the sum of the EEPROM is equal to 0xBABA.
fp@2685: **/
fp@2685: static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
fp@2685: u16 offset)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 checksum = 0;
fp@2685: u16 i, nvm_data;
fp@2685:
fp@2685: for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
fp@2685: ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685: checksum += nvm_data;
fp@2685: }
fp@2685:
fp@2685: if (checksum != (u16) NVM_SUM) {
fp@2685: hw_dbg("NVM Checksum Invalid\n");
fp@2685: ret_val = -E1000_ERR_NVM;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_update_nvm_checksum_with_offset - Update EEPROM
fp@2685: * checksum
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: offset in words of the checksum protected region
fp@2685: *
fp@2685: * Updates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2685: * up to the checksum. Then calculates the EEPROM checksum and writes the
fp@2685: * value to the EEPROM.
fp@2685: **/
fp@2685: static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: u16 checksum = 0;
fp@2685: u16 i, nvm_data;
fp@2685:
fp@2685: for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
fp@2685: ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error while updating checksum.\n");
fp@2685: goto out;
fp@2685: }
fp@2685: checksum += nvm_data;
fp@2685: }
fp@2685: checksum = (u16) NVM_SUM - checksum;
fp@2685: ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
fp@2685: &checksum);
fp@2685: if (ret_val)
fp@2685: hw_dbg("NVM Write Error while updating checksum.\n");
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Calculates the EEPROM section checksum by reading/adding each word of
fp@2685: * the EEPROM and then verifies that the sum of the EEPROM is
fp@2685: * equal to 0xBABA.
fp@2685: **/
fp@2685: static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 eeprom_regions_count = 1;
fp@2685: u16 j, nvm_data;
fp@2685: u16 nvm_offset;
fp@2685:
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
fp@2685: /* if checksums compatibility bit is set validate checksums
fp@2685: * for all 4 ports.
fp@2685: */
fp@2685: eeprom_regions_count = 4;
fp@2685: }
fp@2685:
fp@2685: for (j = 0; j < eeprom_regions_count; j++) {
fp@2685: nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
fp@2685: ret_val = igb_validate_nvm_checksum_with_offset(hw,
fp@2685: nvm_offset);
fp@2685: if (ret_val != 0)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_update_nvm_checksum_82580 - Update EEPROM checksum
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Updates the EEPROM section checksums for all 4 ports by reading/adding
fp@2685: * each word of the EEPROM up to the checksum. Then calculates the EEPROM
fp@2685: * checksum and writes the value to the EEPROM.
fp@2685: **/
fp@2685: static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685: u16 j, nvm_data;
fp@2685: u16 nvm_offset;
fp@2685:
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
fp@2685: /* set compatibility bit to validate checksums appropriately */
fp@2685: nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
fp@2685: ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
fp@2685: &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: for (j = 0; j < 4; j++) {
fp@2685: nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
fp@2685: ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Calculates the EEPROM section checksum by reading/adding each word of
fp@2685: * the EEPROM and then verifies that the sum of the EEPROM is
fp@2685: * equal to 0xBABA.
fp@2685: **/
fp@2685: static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 j;
fp@2685: u16 nvm_offset;
fp@2685:
fp@2685: for (j = 0; j < 4; j++) {
fp@2685: nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
fp@2685: ret_val = igb_validate_nvm_checksum_with_offset(hw,
fp@2685: nvm_offset);
fp@2685: if (ret_val != 0)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_update_nvm_checksum_i350 - Update EEPROM checksum
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Updates the EEPROM section checksums for all 4 ports by reading/adding
fp@2685: * each word of the EEPROM up to the checksum. Then calculates the EEPROM
fp@2685: * checksum and writes the value to the EEPROM.
fp@2685: **/
fp@2685: static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 j;
fp@2685: u16 nvm_offset;
fp@2685:
fp@2685: for (j = 0; j < 4; j++) {
fp@2685: nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
fp@2685: ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
fp@2685: if (ret_val != 0)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * __igb_access_emi_reg - Read/write EMI register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @addr: EMI address to program
fp@2685: * @data: pointer to value to read/write from/to the EMI address
fp@2685: * @read: boolean flag to indicate read or write
fp@2685: **/
fp@2685: static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
fp@2685: u16 *data, bool read)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
fp@2685: if (ret_val)
fp@2685: return ret_val;
fp@2685:
fp@2685: if (read)
fp@2685: ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
fp@2685: else
fp@2685: ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_read_emi_reg - Read Extended Management Interface register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @addr: EMI address to program
fp@2685: * @data: value to be read from the EMI address
fp@2685: **/
fp@2685: s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
fp@2685: {
fp@2685: return __igb_access_emi_reg(hw, addr, data, true);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_eee_i350 - Enable/disable EEE support
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @adv1G: boolean flag enabling 1G EEE advertisement
fp@2685: * @adv100m: boolean flag enabling 100M EEE advertisement
fp@2685: *
fp@2685: * Enable/disable EEE based on setting in dev_spec structure.
fp@2685: *
fp@2685: **/
fp@2685: s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
fp@2685: {
fp@2685: u32 ipcnfg, eeer;
fp@2685:
fp@2685: if ((hw->mac.type < e1000_i350) ||
fp@2685: (hw->phy.media_type != e1000_media_type_copper))
fp@2685: goto out;
fp@2685: ipcnfg = rd32(E1000_IPCNFG);
fp@2685: eeer = rd32(E1000_EEER);
fp@2685:
fp@2685: /* enable or disable per user setting */
fp@2685: if (!(hw->dev_spec._82575.eee_disable)) {
fp@2685: u32 eee_su = rd32(E1000_EEE_SU);
fp@2685:
fp@2685: if (adv100M)
fp@2685: ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
fp@2685: else
fp@2685: ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
fp@2685:
fp@2685: if (adv1G)
fp@2685: ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
fp@2685: else
fp@2685: ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
fp@2685:
fp@2685: eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
fp@2685: E1000_EEER_LPI_FC);
fp@2685:
fp@2685: /* This bit should not be set in normal operation. */
fp@2685: if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
fp@2685: hw_dbg("LPI Clock Stop Bit should not be set!\n");
fp@2685:
fp@2685: } else {
fp@2685: ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
fp@2685: E1000_IPCNFG_EEE_100M_AN);
fp@2685: eeer &= ~(E1000_EEER_TX_LPI_EN |
fp@2685: E1000_EEER_RX_LPI_EN |
fp@2685: E1000_EEER_LPI_FC);
fp@2685: }
fp@2685: wr32(E1000_IPCNFG, ipcnfg);
fp@2685: wr32(E1000_EEER, eeer);
fp@2685: rd32(E1000_IPCNFG);
fp@2685: rd32(E1000_EEER);
fp@2685: out:
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_eee_i354 - Enable/disable EEE support
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @adv1G: boolean flag enabling 1G EEE advertisement
fp@2685: * @adv100m: boolean flag enabling 100M EEE advertisement
fp@2685: *
fp@2685: * Enable/disable EEE legacy mode based on setting in dev_spec structure.
fp@2685: *
fp@2685: **/
fp@2685: s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u16 phy_data;
fp@2685:
fp@2685: if ((hw->phy.media_type != e1000_media_type_copper) ||
fp@2685: (phy->id != M88E1543_E_PHY_ID))
fp@2685: goto out;
fp@2685:
fp@2685: if (!hw->dev_spec._82575.eee_disable) {
fp@2685: /* Switch to PHY page 18. */
fp@2685: ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
fp@2685: ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
fp@2685: phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Return the PHY to page 0. */
fp@2685: ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Turn on EEE advertisement. */
fp@2685: ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
fp@2685: E1000_EEE_ADV_DEV_I354,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (adv100M)
fp@2685: phy_data |= E1000_EEE_ADV_100_SUPPORTED;
fp@2685: else
fp@2685: phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
fp@2685:
fp@2685: if (adv1G)
fp@2685: phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
fp@2685: else
fp@2685: phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
fp@2685:
fp@2685: ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
fp@2685: E1000_EEE_ADV_DEV_I354,
fp@2685: phy_data);
fp@2685: } else {
fp@2685: /* Turn off EEE advertisement. */
fp@2685: ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
fp@2685: E1000_EEE_ADV_DEV_I354,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
fp@2685: E1000_EEE_ADV_1000_SUPPORTED);
fp@2685: ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
fp@2685: E1000_EEE_ADV_DEV_I354,
fp@2685: phy_data);
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_eee_status_i354 - Get EEE status
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @status: EEE status
fp@2685: *
fp@2685: * Get EEE status by guessing based on whether Tx or Rx LPI indications have
fp@2685: * been received.
fp@2685: **/
fp@2685: s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
fp@2685: {
fp@2685: struct e1000_phy_info *phy = &hw->phy;
fp@2685: s32 ret_val = 0;
fp@2685: u16 phy_data;
fp@2685:
fp@2685: /* Check if EEE is supported on this device. */
fp@2685: if ((hw->phy.media_type != e1000_media_type_copper) ||
fp@2685: (phy->id != M88E1543_E_PHY_ID))
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
fp@2685: E1000_PCS_STATUS_DEV_I354,
fp@2685: &phy_data);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
fp@2685: E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: static const u8 e1000_emc_temp_data[4] = {
fp@2685: E1000_EMC_INTERNAL_DATA,
fp@2685: E1000_EMC_DIODE1_DATA,
fp@2685: E1000_EMC_DIODE2_DATA,
fp@2685: E1000_EMC_DIODE3_DATA
fp@2685: };
fp@2685: static const u8 e1000_emc_therm_limit[4] = {
fp@2685: E1000_EMC_INTERNAL_THERM_LIMIT,
fp@2685: E1000_EMC_DIODE1_THERM_LIMIT,
fp@2685: E1000_EMC_DIODE2_THERM_LIMIT,
fp@2685: E1000_EMC_DIODE3_THERM_LIMIT
fp@2685: };
fp@2685:
fp@2685: #ifdef CONFIG_IGB_HWMON
fp@2685: /**
fp@2685: * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
fp@2685: * @hw: pointer to hardware structure
fp@2685: *
fp@2685: * Updates the temperatures in mac.thermal_sensor_data
fp@2685: **/
fp@2685: static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
fp@2685: {
fp@2685: u16 ets_offset;
fp@2685: u16 ets_cfg;
fp@2685: u16 ets_sensor;
fp@2685: u8 num_sensors;
fp@2685: u8 sensor_index;
fp@2685: u8 sensor_location;
fp@2685: u8 i;
fp@2685: struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
fp@2685:
fp@2685: if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
fp@2685: return E1000_NOT_IMPLEMENTED;
fp@2685:
fp@2685: data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
fp@2685:
fp@2685: /* Return the internal sensor only if ETS is unsupported */
fp@2685: hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
fp@2685: if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
fp@2685: return 0;
fp@2685:
fp@2685: hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
fp@2685: if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
fp@2685: != NVM_ETS_TYPE_EMC)
fp@2685: return E1000_NOT_IMPLEMENTED;
fp@2685:
fp@2685: num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
fp@2685: if (num_sensors > E1000_MAX_SENSORS)
fp@2685: num_sensors = E1000_MAX_SENSORS;
fp@2685:
fp@2685: for (i = 1; i < num_sensors; i++) {
fp@2685: hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
fp@2685: sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
fp@2685: NVM_ETS_DATA_INDEX_SHIFT);
fp@2685: sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
fp@2685: NVM_ETS_DATA_LOC_SHIFT);
fp@2685:
fp@2685: if (sensor_location != 0)
fp@2685: hw->phy.ops.read_i2c_byte(hw,
fp@2685: e1000_emc_temp_data[sensor_index],
fp@2685: E1000_I2C_THERMAL_SENSOR_ADDR,
fp@2685: &data->sensor[i].temp);
fp@2685: }
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
fp@2685: * @hw: pointer to hardware structure
fp@2685: *
fp@2685: * Sets the thermal sensor thresholds according to the NVM map
fp@2685: * and save off the threshold and location values into mac.thermal_sensor_data
fp@2685: **/
fp@2685: static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
fp@2685: {
fp@2685: u16 ets_offset;
fp@2685: u16 ets_cfg;
fp@2685: u16 ets_sensor;
fp@2685: u8 low_thresh_delta;
fp@2685: u8 num_sensors;
fp@2685: u8 sensor_index;
fp@2685: u8 sensor_location;
fp@2685: u8 therm_limit;
fp@2685: u8 i;
fp@2685: struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
fp@2685:
fp@2685: if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
fp@2685: return E1000_NOT_IMPLEMENTED;
fp@2685:
fp@2685: memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
fp@2685:
fp@2685: data->sensor[0].location = 0x1;
fp@2685: data->sensor[0].caution_thresh =
fp@2685: (rd32(E1000_THHIGHTC) & 0xFF);
fp@2685: data->sensor[0].max_op_thresh =
fp@2685: (rd32(E1000_THLOWTC) & 0xFF);
fp@2685:
fp@2685: /* Return the internal sensor only if ETS is unsupported */
fp@2685: hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
fp@2685: if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
fp@2685: return 0;
fp@2685:
fp@2685: hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
fp@2685: if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
fp@2685: != NVM_ETS_TYPE_EMC)
fp@2685: return E1000_NOT_IMPLEMENTED;
fp@2685:
fp@2685: low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
fp@2685: NVM_ETS_LTHRES_DELTA_SHIFT);
fp@2685: num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
fp@2685:
fp@2685: for (i = 1; i <= num_sensors; i++) {
fp@2685: hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
fp@2685: sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
fp@2685: NVM_ETS_DATA_INDEX_SHIFT);
fp@2685: sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
fp@2685: NVM_ETS_DATA_LOC_SHIFT);
fp@2685: therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
fp@2685:
fp@2685: hw->phy.ops.write_i2c_byte(hw,
fp@2685: e1000_emc_therm_limit[sensor_index],
fp@2685: E1000_I2C_THERMAL_SENSOR_ADDR,
fp@2685: therm_limit);
fp@2685:
fp@2685: if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
fp@2685: data->sensor[i].location = sensor_location;
fp@2685: data->sensor[i].caution_thresh = therm_limit;
fp@2685: data->sensor[i].max_op_thresh = therm_limit -
fp@2685: low_thresh_delta;
fp@2685: }
fp@2685: }
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: #endif
fp@2685: static struct e1000_mac_operations e1000_mac_ops_82575 = {
fp@2685: .init_hw = igb_init_hw_82575,
fp@2685: .check_for_link = igb_check_for_link_82575,
fp@2685: .rar_set = igb_rar_set,
fp@2685: .read_mac_addr = igb_read_mac_addr_82575,
fp@2685: .get_speed_and_duplex = igb_get_link_up_info_82575,
fp@2685: #ifdef CONFIG_IGB_HWMON
fp@2685: .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
fp@2685: .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
fp@2685: #endif
fp@2685: };
fp@2685:
fp@2685: static struct e1000_phy_operations e1000_phy_ops_82575 = {
fp@2685: .acquire = igb_acquire_phy_82575,
fp@2685: .get_cfg_done = igb_get_cfg_done_82575,
fp@2685: .release = igb_release_phy_82575,
fp@2685: .write_i2c_byte = igb_write_i2c_byte,
fp@2685: .read_i2c_byte = igb_read_i2c_byte,
fp@2685: };
fp@2685:
fp@2685: static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
fp@2685: .acquire = igb_acquire_nvm_82575,
fp@2685: .read = igb_read_nvm_eerd,
fp@2685: .release = igb_release_nvm_82575,
fp@2685: .write = igb_write_nvm_spi,
fp@2685: };
fp@2685:
fp@2685: const struct e1000_info e1000_82575_info = {
fp@2685: .get_invariants = igb_get_invariants_82575,
fp@2685: .mac_ops = &e1000_mac_ops_82575,
fp@2685: .phy_ops = &e1000_phy_ops_82575,
fp@2685: .nvm_ops = &e1000_nvm_ops_82575,
fp@2685: };
fp@2685: