fp@2587: /*******************************************************************************
fp@2587: 
fp@2587:   Intel PRO/1000 Linux driver
fp@2587:   Copyright(c) 1999 - 2013 Intel Corporation.
fp@2587: 
fp@2587:   This program is free software; you can redistribute it and/or modify it
fp@2587:   under the terms and conditions of the GNU General Public License,
fp@2587:   version 2, as published by the Free Software Foundation.
fp@2587: 
fp@2587:   This program is distributed in the hope it will be useful, but WITHOUT
fp@2587:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2587:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2587:   more details.
fp@2587: 
fp@2587:   You should have received a copy of the GNU General Public License along with
fp@2587:   this program; if not, write to the Free Software Foundation, Inc.,
fp@2587:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
fp@2587: 
fp@2587:   The full GNU General Public License is included in this distribution in
fp@2587:   the file called "COPYING".
fp@2587: 
fp@2587:   Contact Information:
fp@2587:   Linux NICS <linux.nics@intel.com>
fp@2587:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2587:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2587: 
fp@2587: *******************************************************************************/
fp@2587: 
fp@2587: /* 82562G 10/100 Network Connection
fp@2587:  * 82562G-2 10/100 Network Connection
fp@2587:  * 82562GT 10/100 Network Connection
fp@2587:  * 82562GT-2 10/100 Network Connection
fp@2587:  * 82562V 10/100 Network Connection
fp@2587:  * 82562V-2 10/100 Network Connection
fp@2587:  * 82566DC-2 Gigabit Network Connection
fp@2587:  * 82566DC Gigabit Network Connection
fp@2587:  * 82566DM-2 Gigabit Network Connection
fp@2587:  * 82566DM Gigabit Network Connection
fp@2587:  * 82566MC Gigabit Network Connection
fp@2587:  * 82566MM Gigabit Network Connection
fp@2587:  * 82567LM Gigabit Network Connection
fp@2587:  * 82567LF Gigabit Network Connection
fp@2587:  * 82567V Gigabit Network Connection
fp@2587:  * 82567LM-2 Gigabit Network Connection
fp@2587:  * 82567LF-2 Gigabit Network Connection
fp@2587:  * 82567V-2 Gigabit Network Connection
fp@2587:  * 82567LF-3 Gigabit Network Connection
fp@2587:  * 82567LM-3 Gigabit Network Connection
fp@2587:  * 82567LM-4 Gigabit Network Connection
fp@2587:  * 82577LM Gigabit Network Connection
fp@2587:  * 82577LC Gigabit Network Connection
fp@2587:  * 82578DM Gigabit Network Connection
fp@2587:  * 82578DC Gigabit Network Connection
fp@2587:  * 82579LM Gigabit Network Connection
fp@2587:  * 82579V Gigabit Network Connection
fp@2587:  */
fp@2587: 
fp@2587: #include "e1000-3.14-ethercat.h"
fp@2587: 
fp@2587: /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
fp@2587: /* Offset 04h HSFSTS */
fp@2587: union ich8_hws_flash_status {
fp@2587: 	struct ich8_hsfsts {
fp@2587: 		u16 flcdone:1;	/* bit 0 Flash Cycle Done */
fp@2587: 		u16 flcerr:1;	/* bit 1 Flash Cycle Error */
fp@2587: 		u16 dael:1;	/* bit 2 Direct Access error Log */
fp@2587: 		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */
fp@2587: 		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */
fp@2587: 		u16 reserved1:2;	/* bit 13:6 Reserved */
fp@2587: 		u16 reserved2:6;	/* bit 13:6 Reserved */
fp@2587: 		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */
fp@2587: 		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */
fp@2587: 	} hsf_status;
fp@2587: 	u16 regval;
fp@2587: };
fp@2587: 
fp@2587: /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
fp@2587: /* Offset 06h FLCTL */
fp@2587: union ich8_hws_flash_ctrl {
fp@2587: 	struct ich8_hsflctl {
fp@2587: 		u16 flcgo:1;	/* 0 Flash Cycle Go */
fp@2587: 		u16 flcycle:2;	/* 2:1 Flash Cycle */
fp@2587: 		u16 reserved:5;	/* 7:3 Reserved  */
fp@2587: 		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */
fp@2587: 		u16 flockdn:6;	/* 15:10 Reserved */
fp@2587: 	} hsf_ctrl;
fp@2587: 	u16 regval;
fp@2587: };
fp@2587: 
fp@2587: /* ICH Flash Region Access Permissions */
fp@2587: union ich8_hws_flash_regacc {
fp@2587: 	struct ich8_flracc {
fp@2587: 		u32 grra:8;	/* 0:7 GbE region Read Access */
fp@2587: 		u32 grwa:8;	/* 8:15 GbE region Write Access */
fp@2587: 		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */
fp@2587: 		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */
fp@2587: 	} hsf_flregacc;
fp@2587: 	u16 regval;
fp@2587: };
fp@2587: 
fp@2587: /* ICH Flash Protected Region */
fp@2587: union ich8_flash_protected_range {
fp@2587: 	struct ich8_pr {
fp@2587: 		u32 base:13;	/* 0:12 Protected Range Base */
fp@2587: 		u32 reserved1:2;	/* 13:14 Reserved */
fp@2587: 		u32 rpe:1;	/* 15 Read Protection Enable */
fp@2587: 		u32 limit:13;	/* 16:28 Protected Range Limit */
fp@2587: 		u32 reserved2:2;	/* 29:30 Reserved */
fp@2587: 		u32 wpe:1;	/* 31 Write Protection Enable */
fp@2587: 	} range;
fp@2587: 	u32 regval;
fp@2587: };
fp@2587: 
fp@2587: static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
fp@2587: static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
fp@2587: static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
fp@2587: static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
fp@2587: 						u32 offset, u8 byte);
fp@2587: static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					 u8 *data);
fp@2587: static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					 u16 *data);
fp@2587: static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					 u8 size, u16 *data);
fp@2587: static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
fp@2587: static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
fp@2587: static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
fp@2587: static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
fp@2587: static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
fp@2587: static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
fp@2587: static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
fp@2587: static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
fp@2587: static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fp@2587: static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
fp@2587: static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
fp@2587: static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
fp@2587: static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fp@2587: static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
fp@2587: static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
fp@2587: static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
fp@2587: static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
fp@2587: static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
fp@2587: static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
fp@2587: static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
fp@2587: static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
fp@2587: 
fp@2587: static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
fp@2587: {
fp@2587: 	return readw(hw->flash_address + reg);
fp@2587: }
fp@2587: 
fp@2587: static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
fp@2587: {
fp@2587: 	return readl(hw->flash_address + reg);
fp@2587: }
fp@2587: 
fp@2587: static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
fp@2587: {
fp@2587: 	writew(val, hw->flash_address + reg);
fp@2587: }
fp@2587: 
fp@2587: static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
fp@2587: {
fp@2587: 	writel(val, hw->flash_address + reg);
fp@2587: }
fp@2587: 
fp@2587: #define er16flash(reg)		__er16flash(hw, (reg))
fp@2587: #define er32flash(reg)		__er32flash(hw, (reg))
fp@2587: #define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
fp@2587: #define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Test access to the PHY registers by reading the PHY ID registers.  If
fp@2587:  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
fp@2587:  *  otherwise assume the read PHY ID is correct if it is valid.
fp@2587:  *
fp@2587:  *  Assumes the sw/fw/hw semaphore is already acquired.
fp@2587:  **/
fp@2587: static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u16 phy_reg = 0;
fp@2587: 	u32 phy_id = 0;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 retry_count;
fp@2587: 	u32 mac_reg = 0;
fp@2587: 
fp@2587: 	for (retry_count = 0; retry_count < 2; retry_count++) {
fp@2587: 		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
fp@2587: 		if (ret_val || (phy_reg == 0xFFFF))
fp@2587: 			continue;
fp@2587: 		phy_id = (u32)(phy_reg << 16);
fp@2587: 
fp@2587: 		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
fp@2587: 		if (ret_val || (phy_reg == 0xFFFF)) {
fp@2587: 			phy_id = 0;
fp@2587: 			continue;
fp@2587: 		}
fp@2587: 		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (hw->phy.id) {
fp@2587: 		if (hw->phy.id == phy_id)
fp@2587: 			goto out;
fp@2587: 	} else if (phy_id) {
fp@2587: 		hw->phy.id = phy_id;
fp@2587: 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
fp@2587: 		goto out;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* In case the PHY needs to be in mdio slow mode,
fp@2587: 	 * set slow mode and try to get the PHY id again.
fp@2587: 	 */
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
fp@2587: 	if (!ret_val)
fp@2587: 		ret_val = e1000e_get_phy_id(hw);
fp@2587: 	hw->phy.ops.acquire(hw);
fp@2587: 
fp@2587: 	if (ret_val)
fp@2587: 		return false;
fp@2587: out:
fp@2587: 	if (hw->mac.type == e1000_pch_lpt) {
fp@2587: 		/* Unforce SMBus mode in PHY */
fp@2587: 		e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
fp@2587: 		phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
fp@2587: 		e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
fp@2587: 
fp@2587: 		/* Unforce SMBus mode in MAC */
fp@2587: 		mac_reg = er32(CTRL_EXT);
fp@2587: 		mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
fp@2587: 		ew32(CTRL_EXT, mac_reg);
fp@2587: 	}
fp@2587: 
fp@2587: 	return true;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Workarounds/flow necessary for PHY initialization during driver load
fp@2587:  *  and resume paths.
fp@2587:  **/
fp@2587: static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 mac_reg, fwsm = er32(FWSM);
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	/* Gate automatic PHY configuration by hardware on managed and
fp@2587: 	 * non-managed 82579 and newer adapters.
fp@2587: 	 */
fp@2587: 	e1000_gate_hw_phy_config_ich8lan(hw, true);
fp@2587: 
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val) {
fp@2587: 		e_dbg("Failed to initialize PHY flow\n");
fp@2587: 		goto out;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
fp@2587: 	 * inaccessible and resetting the PHY is not blocked, toggle the
fp@2587: 	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
fp@2587: 	 */
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_pch_lpt:
fp@2587: 		if (e1000_phy_is_accessible_pchlan(hw))
fp@2587: 			break;
fp@2587: 
fp@2587: 		/* Before toggling LANPHYPC, see if PHY is accessible by
fp@2587: 		 * forcing MAC to SMBus mode first.
fp@2587: 		 */
fp@2587: 		mac_reg = er32(CTRL_EXT);
fp@2587: 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
fp@2587: 		ew32(CTRL_EXT, mac_reg);
fp@2587: 
fp@2587: 		/* Wait 50 milliseconds for MAC to finish any retries
fp@2587: 		 * that it might be trying to perform from previous
fp@2587: 		 * attempts to acknowledge any phy read requests.
fp@2587: 		 */
fp@2587: 		msleep(50);
fp@2587: 
fp@2587: 		/* fall-through */
fp@2587: 	case e1000_pch2lan:
fp@2587: 		if (e1000_phy_is_accessible_pchlan(hw))
fp@2587: 			break;
fp@2587: 
fp@2587: 		/* fall-through */
fp@2587: 	case e1000_pchlan:
fp@2587: 		if ((hw->mac.type == e1000_pchlan) &&
fp@2587: 		    (fwsm & E1000_ICH_FWSM_FW_VALID))
fp@2587: 			break;
fp@2587: 
fp@2587: 		if (hw->phy.ops.check_reset_block(hw)) {
fp@2587: 			e_dbg("Required LANPHYPC toggle blocked by ME\n");
fp@2587: 			ret_val = -E1000_ERR_PHY;
fp@2587: 			break;
fp@2587: 		}
fp@2587: 
fp@2587: 		e_dbg("Toggling LANPHYPC\n");
fp@2587: 
fp@2587: 		/* Set Phy Config Counter to 50msec */
fp@2587: 		mac_reg = er32(FEXTNVM3);
fp@2587: 		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
fp@2587: 		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
fp@2587: 		ew32(FEXTNVM3, mac_reg);
fp@2587: 
fp@2587: 		/* Toggle LANPHYPC Value bit */
fp@2587: 		mac_reg = er32(CTRL);
fp@2587: 		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
fp@2587: 		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
fp@2587: 		ew32(CTRL, mac_reg);
fp@2587: 		e1e_flush();
fp@2587: 		usleep_range(10, 20);
fp@2587: 		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
fp@2587: 		ew32(CTRL, mac_reg);
fp@2587: 		e1e_flush();
fp@2587: 		if (hw->mac.type < e1000_pch_lpt) {
fp@2587: 			msleep(50);
fp@2587: 		} else {
fp@2587: 			u16 count = 20;
fp@2587: 			do {
fp@2587: 				usleep_range(5000, 10000);
fp@2587: 			} while (!(er32(CTRL_EXT) &
fp@2587: 				   E1000_CTRL_EXT_LPCD) && count--);
fp@2587: 			usleep_range(30000, 60000);
fp@2587: 			if (e1000_phy_is_accessible_pchlan(hw))
fp@2587: 				break;
fp@2587: 
fp@2587: 			/* Toggling LANPHYPC brings the PHY out of SMBus mode
fp@2587: 			 * so ensure that the MAC is also out of SMBus mode
fp@2587: 			 */
fp@2587: 			mac_reg = er32(CTRL_EXT);
fp@2587: 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
fp@2587: 			ew32(CTRL_EXT, mac_reg);
fp@2587: 
fp@2587: 			if (e1000_phy_is_accessible_pchlan(hw))
fp@2587: 				break;
fp@2587: 
fp@2587: 			ret_val = -E1000_ERR_PHY;
fp@2587: 		}
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 	if (!ret_val) {
fp@2587: 		/* Reset the PHY before any access to it.  Doing so, ensures
fp@2587: 		 * that the PHY is in a known good state before we read/write
fp@2587: 		 * PHY registers.  The generic reset is sufficient here,
fp@2587: 		 * because we haven't determined the PHY type yet.
fp@2587: 		 */
fp@2587: 		ret_val = e1000e_phy_hw_reset_generic(hw);
fp@2587: 	}
fp@2587: 
fp@2587: out:
fp@2587: 	/* Ungate automatic PHY configuration on non-managed 82579 */
fp@2587: 	if ((hw->mac.type == e1000_pch2lan) &&
fp@2587: 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
fp@2587: 		usleep_range(10000, 20000);
fp@2587: 		e1000_gate_hw_phy_config_ich8lan(hw, false);
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Initialize family-specific PHY parameters and function pointers.
fp@2587:  **/
fp@2587: static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_phy_info *phy = &hw->phy;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	phy->addr = 1;
fp@2587: 	phy->reset_delay_us = 100;
fp@2587: 
fp@2587: 	phy->ops.set_page = e1000_set_page_igp;
fp@2587: 	phy->ops.read_reg = e1000_read_phy_reg_hv;
fp@2587: 	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fp@2587: 	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
fp@2587: 	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
fp@2587: 	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
fp@2587: 	phy->ops.write_reg = e1000_write_phy_reg_hv;
fp@2587: 	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
fp@2587: 	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
fp@2587: 	phy->ops.power_up = e1000_power_up_phy_copper;
fp@2587: 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
fp@2587: 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
fp@2587: 
fp@2587: 	phy->id = e1000_phy_unknown;
fp@2587: 
fp@2587: 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (phy->id == e1000_phy_unknown)
fp@2587: 		switch (hw->mac.type) {
fp@2587: 		default:
fp@2587: 			ret_val = e1000e_get_phy_id(hw);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
fp@2587: 				break;
fp@2587: 			/* fall-through */
fp@2587: 		case e1000_pch2lan:
fp@2587: 		case e1000_pch_lpt:
fp@2587: 			/* In case the PHY needs to be in mdio slow mode,
fp@2587: 			 * set slow mode and try to get the PHY id again.
fp@2587: 			 */
fp@2587: 			ret_val = e1000_set_mdio_slow_mode_hv(hw);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 			ret_val = e1000e_get_phy_id(hw);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 			break;
fp@2587: 		}
fp@2587: 	phy->type = e1000e_get_phy_type_from_id(phy->id);
fp@2587: 
fp@2587: 	switch (phy->type) {
fp@2587: 	case e1000_phy_82577:
fp@2587: 	case e1000_phy_82579:
fp@2587: 	case e1000_phy_i217:
fp@2587: 		phy->ops.check_polarity = e1000_check_polarity_82577;
fp@2587: 		phy->ops.force_speed_duplex =
fp@2587: 		    e1000_phy_force_speed_duplex_82577;
fp@2587: 		phy->ops.get_cable_length = e1000_get_cable_length_82577;
fp@2587: 		phy->ops.get_info = e1000_get_phy_info_82577;
fp@2587: 		phy->ops.commit = e1000e_phy_sw_reset;
fp@2587: 		break;
fp@2587: 	case e1000_phy_82578:
fp@2587: 		phy->ops.check_polarity = e1000_check_polarity_m88;
fp@2587: 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
fp@2587: 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;
fp@2587: 		phy->ops.get_info = e1000e_get_phy_info_m88;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		ret_val = -E1000_ERR_PHY;
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Initialize family-specific PHY parameters and function pointers.
fp@2587:  **/
fp@2587: static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_phy_info *phy = &hw->phy;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 i = 0;
fp@2587: 
fp@2587: 	phy->addr = 1;
fp@2587: 	phy->reset_delay_us = 100;
fp@2587: 
fp@2587: 	phy->ops.power_up = e1000_power_up_phy_copper;
fp@2587: 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
fp@2587: 
fp@2587: 	/* We may need to do this twice - once for IGP and if that fails,
fp@2587: 	 * we'll set BM func pointers and try again
fp@2587: 	 */
fp@2587: 	ret_val = e1000e_determine_phy_address(hw);
fp@2587: 	if (ret_val) {
fp@2587: 		phy->ops.write_reg = e1000e_write_phy_reg_bm;
fp@2587: 		phy->ops.read_reg = e1000e_read_phy_reg_bm;
fp@2587: 		ret_val = e1000e_determine_phy_address(hw);
fp@2587: 		if (ret_val) {
fp@2587: 			e_dbg("Cannot determine PHY addr. Erroring out\n");
fp@2587: 			return ret_val;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	phy->id = 0;
fp@2587: 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
fp@2587: 	       (i++ < 100)) {
fp@2587: 		usleep_range(1000, 2000);
fp@2587: 		ret_val = e1000e_get_phy_id(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Verify phy id */
fp@2587: 	switch (phy->id) {
fp@2587: 	case IGP03E1000_E_PHY_ID:
fp@2587: 		phy->type = e1000_phy_igp_3;
fp@2587: 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
fp@2587: 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
fp@2587: 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
fp@2587: 		phy->ops.get_info = e1000e_get_phy_info_igp;
fp@2587: 		phy->ops.check_polarity = e1000_check_polarity_igp;
fp@2587: 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
fp@2587: 		break;
fp@2587: 	case IFE_E_PHY_ID:
fp@2587: 	case IFE_PLUS_E_PHY_ID:
fp@2587: 	case IFE_C_E_PHY_ID:
fp@2587: 		phy->type = e1000_phy_ife;
fp@2587: 		phy->autoneg_mask = E1000_ALL_NOT_GIG;
fp@2587: 		phy->ops.get_info = e1000_get_phy_info_ife;
fp@2587: 		phy->ops.check_polarity = e1000_check_polarity_ife;
fp@2587: 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
fp@2587: 		break;
fp@2587: 	case BME1000_E_PHY_ID:
fp@2587: 		phy->type = e1000_phy_bm;
fp@2587: 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
fp@2587: 		phy->ops.read_reg = e1000e_read_phy_reg_bm;
fp@2587: 		phy->ops.write_reg = e1000e_write_phy_reg_bm;
fp@2587: 		phy->ops.commit = e1000e_phy_sw_reset;
fp@2587: 		phy->ops.get_info = e1000e_get_phy_info_m88;
fp@2587: 		phy->ops.check_polarity = e1000_check_polarity_m88;
fp@2587: 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		return -E1000_ERR_PHY;
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Initialize family-specific NVM parameters and function
fp@2587:  *  pointers.
fp@2587:  **/
fp@2587: static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u32 gfpreg, sector_base_addr, sector_end_addr;
fp@2587: 	u16 i;
fp@2587: 
fp@2587: 	/* Can't read flash registers if the register set isn't mapped. */
fp@2587: 	if (!hw->flash_address) {
fp@2587: 		e_dbg("ERROR: Flash registers not mapped\n");
fp@2587: 		return -E1000_ERR_CONFIG;
fp@2587: 	}
fp@2587: 
fp@2587: 	nvm->type = e1000_nvm_flash_sw;
fp@2587: 
fp@2587: 	gfpreg = er32flash(ICH_FLASH_GFPREG);
fp@2587: 
fp@2587: 	/* sector_X_addr is a "sector"-aligned address (4096 bytes)
fp@2587: 	 * Add 1 to sector_end_addr since this sector is included in
fp@2587: 	 * the overall size.
fp@2587: 	 */
fp@2587: 	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
fp@2587: 	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
fp@2587: 
fp@2587: 	/* flash_base_addr is byte-aligned */
fp@2587: 	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
fp@2587: 
fp@2587: 	/* find total size of the NVM, then cut in half since the total
fp@2587: 	 * size represents two separate NVM banks.
fp@2587: 	 */
fp@2587: 	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
fp@2587: 				<< FLASH_SECTOR_ADDR_SHIFT);
fp@2587: 	nvm->flash_bank_size /= 2;
fp@2587: 	/* Adjust to word count */
fp@2587: 	nvm->flash_bank_size /= sizeof(u16);
fp@2587: 
fp@2587: 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
fp@2587: 
fp@2587: 	/* Clear shadow ram */
fp@2587: 	for (i = 0; i < nvm->word_size; i++) {
fp@2587: 		dev_spec->shadow_ram[i].modified = false;
fp@2587: 		dev_spec->shadow_ram[i].value = 0xFFFF;
fp@2587: 	}
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Initialize family-specific MAC parameters and function
fp@2587:  *  pointers.
fp@2587:  **/
fp@2587: static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_mac_info *mac = &hw->mac;
fp@2587: 
fp@2587: 	/* Set media type function pointer */
fp@2587: 	hw->phy.media_type = e1000_media_type_copper;
fp@2587: 
fp@2587: 	/* Set mta register count */
fp@2587: 	mac->mta_reg_count = 32;
fp@2587: 	/* Set rar entry count */
fp@2587: 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
fp@2587: 	if (mac->type == e1000_ich8lan)
fp@2587: 		mac->rar_entry_count--;
fp@2587: 	/* FWSM register */
fp@2587: 	mac->has_fwsm = true;
fp@2587: 	/* ARC subsystem not supported */
fp@2587: 	mac->arc_subsystem_valid = false;
fp@2587: 	/* Adaptive IFS supported */
fp@2587: 	mac->adaptive_ifs = true;
fp@2587: 
fp@2587: 	/* LED and other operations */
fp@2587: 	switch (mac->type) {
fp@2587: 	case e1000_ich8lan:
fp@2587: 	case e1000_ich9lan:
fp@2587: 	case e1000_ich10lan:
fp@2587: 		/* check management mode */
fp@2587: 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
fp@2587: 		/* ID LED init */
fp@2587: 		mac->ops.id_led_init = e1000e_id_led_init_generic;
fp@2587: 		/* blink LED */
fp@2587: 		mac->ops.blink_led = e1000e_blink_led_generic;
fp@2587: 		/* setup LED */
fp@2587: 		mac->ops.setup_led = e1000e_setup_led_generic;
fp@2587: 		/* cleanup LED */
fp@2587: 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
fp@2587: 		/* turn on/off LED */
fp@2587: 		mac->ops.led_on = e1000_led_on_ich8lan;
fp@2587: 		mac->ops.led_off = e1000_led_off_ich8lan;
fp@2587: 		break;
fp@2587: 	case e1000_pch2lan:
fp@2587: 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
fp@2587: 		mac->ops.rar_set = e1000_rar_set_pch2lan;
fp@2587: 		/* fall-through */
fp@2587: 	case e1000_pch_lpt:
fp@2587: 	case e1000_pchlan:
fp@2587: 		/* check management mode */
fp@2587: 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
fp@2587: 		/* ID LED init */
fp@2587: 		mac->ops.id_led_init = e1000_id_led_init_pchlan;
fp@2587: 		/* setup LED */
fp@2587: 		mac->ops.setup_led = e1000_setup_led_pchlan;
fp@2587: 		/* cleanup LED */
fp@2587: 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
fp@2587: 		/* turn on/off LED */
fp@2587: 		mac->ops.led_on = e1000_led_on_pchlan;
fp@2587: 		mac->ops.led_off = e1000_led_off_pchlan;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (mac->type == e1000_pch_lpt) {
fp@2587: 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
fp@2587: 		mac->ops.rar_set = e1000_rar_set_pch_lpt;
fp@2587: 		mac->ops.setup_physical_interface =
fp@2587: 		    e1000_setup_copper_link_pch_lpt;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Enable PCS Lock-loss workaround for ICH8 */
fp@2587: 	if (mac->type == e1000_ich8lan)
fp@2587: 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  __e1000_access_emi_reg_locked - Read/write EMI register
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @addr: EMI address to program
fp@2587:  *  @data: pointer to value to read/write from/to the EMI address
fp@2587:  *  @read: boolean flag to indicate read or write
fp@2587:  *
fp@2587:  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
fp@2587:  **/
fp@2587: static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
fp@2587: 					 u16 *data, bool read)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (read)
fp@2587: 		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
fp@2587: 	else
fp@2587: 		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @addr: EMI address to program
fp@2587:  *  @data: value to be read from the EMI address
fp@2587:  *
fp@2587:  *  Assumes the SW/FW/HW Semaphore is already acquired.
fp@2587:  **/
fp@2587: s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
fp@2587: {
fp@2587: 	return __e1000_access_emi_reg_locked(hw, addr, data, true);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @addr: EMI address to program
fp@2587:  *  @data: value to be written to the EMI address
fp@2587:  *
fp@2587:  *  Assumes the SW/FW/HW Semaphore is already acquired.
fp@2587:  **/
fp@2587: s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
fp@2587: {
fp@2587: 	return __e1000_access_emi_reg_locked(hw, addr, &data, false);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_set_eee_pchlan - Enable/disable EEE support
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
fp@2587:  *  the link and the EEE capabilities of the link partner.  The LPI Control
fp@2587:  *  register bits will remain set only if/when link is up.
fp@2587:  **/
fp@2587: static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
fp@2587: 
fp@2587: 	switch (hw->phy.type) {
fp@2587: 	case e1000_phy_82579:
fp@2587: 		lpa = I82579_EEE_LP_ABILITY;
fp@2587: 		pcs_status = I82579_EEE_PCS_STATUS;
fp@2587: 		adv_addr = I82579_EEE_ADVERTISEMENT;
fp@2587: 		break;
fp@2587: 	case e1000_phy_i217:
fp@2587: 		lpa = I217_EEE_LP_ABILITY;
fp@2587: 		pcs_status = I217_EEE_PCS_STATUS;
fp@2587: 		adv_addr = I217_EEE_ADVERTISEMENT;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		return 0;
fp@2587: 	}
fp@2587: 
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	/* Clear bits that enable EEE in various speeds */
fp@2587: 	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
fp@2587: 
fp@2587: 	/* Enable EEE if not disabled by user */
fp@2587: 	if (!dev_spec->eee_disable) {
fp@2587: 		/* Save off link partner's EEE ability */
fp@2587: 		ret_val = e1000_read_emi_reg_locked(hw, lpa,
fp@2587: 						    &dev_spec->eee_lp_ability);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		/* Read EEE advertisement */
fp@2587: 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		/* Enable EEE only for speeds in which the link partner is
fp@2587: 		 * EEE capable and for which we advertise EEE.
fp@2587: 		 */
fp@2587: 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
fp@2587: 			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
fp@2587: 
fp@2587: 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
fp@2587: 			e1e_rphy_locked(hw, MII_LPA, &data);
fp@2587: 			if (data & LPA_100FULL)
fp@2587: 				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
fp@2587: 			else
fp@2587: 				/* EEE is not supported in 100Half, so ignore
fp@2587: 				 * partner's EEE in 100 ability if full-duplex
fp@2587: 				 * is not advertised.
fp@2587: 				 */
fp@2587: 				dev_spec->eee_lp_ability &=
fp@2587: 				    ~I82579_EEE_100_SUPPORTED;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
fp@2587: 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  *  @link: link up bool flag
fp@2587:  *
fp@2587:  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
fp@2587:  *  preventing further DMA write requests.  Workaround the issue by disabling
fp@2587:  *  the de-assertion of the clock request when in 1Gpbs mode.
fp@2587:  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
fp@2587:  *  speeds in order to avoid Tx hangs.
fp@2587:  **/
fp@2587: static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
fp@2587: {
fp@2587: 	u32 fextnvm6 = er32(FEXTNVM6);
fp@2587: 	u32 status = er32(STATUS);
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 reg;
fp@2587: 
fp@2587: 	if (link && (status & E1000_STATUS_SPEED_1000)) {
fp@2587: 		ret_val = hw->phy.ops.acquire(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		ret_val =
fp@2587: 		    e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
fp@2587: 						&reg);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		ret_val =
fp@2587: 		    e1000e_write_kmrn_reg_locked(hw,
fp@2587: 						 E1000_KMRNCTRLSTA_K1_CONFIG,
fp@2587: 						 reg &
fp@2587: 						 ~E1000_KMRNCTRLSTA_K1_ENABLE);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		usleep_range(10, 20);
fp@2587: 
fp@2587: 		ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
fp@2587: 
fp@2587: 		ret_val =
fp@2587: 		    e1000e_write_kmrn_reg_locked(hw,
fp@2587: 						 E1000_KMRNCTRLSTA_K1_CONFIG,
fp@2587: 						 reg);
fp@2587: release:
fp@2587: 		hw->phy.ops.release(hw);
fp@2587: 	} else {
fp@2587: 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
fp@2587: 		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
fp@2587: 
fp@2587: 		if (!link || ((status & E1000_STATUS_SPEED_100) &&
fp@2587: 			      (status & E1000_STATUS_FD)))
fp@2587: 			goto update_fextnvm6;
fp@2587: 
fp@2587: 		ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		/* Clear link status transmit timeout */
fp@2587: 		reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
fp@2587: 
fp@2587: 		if (status & E1000_STATUS_SPEED_100) {
fp@2587: 			/* Set inband Tx timeout to 5x10us for 100Half */
fp@2587: 			reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
fp@2587: 
fp@2587: 			/* Do not extend the K1 entry latency for 100Half */
fp@2587: 			fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
fp@2587: 		} else {
fp@2587: 			/* Set inband Tx timeout to 50x10us for 10Full/Half */
fp@2587: 			reg |= 50 <<
fp@2587: 			    I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
fp@2587: 
fp@2587: 			/* Extend the K1 entry latency for 10 Mbps */
fp@2587: 			fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
fp@2587: 		}
fp@2587: 
fp@2587: 		ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: update_fextnvm6:
fp@2587: 		ew32(FEXTNVM6, fextnvm6);
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_platform_pm_pch_lpt - Set platform power management values
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @link: bool indicating link status
fp@2587:  *
fp@2587:  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
fp@2587:  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
fp@2587:  *  when link is up (which must not exceed the maximum latency supported
fp@2587:  *  by the platform), otherwise specify there is no LTR requirement.
fp@2587:  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
fp@2587:  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
fp@2587:  *  Capability register set, on this device LTR is set by writing the
fp@2587:  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
fp@2587:  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
fp@2587:  *  message to the PMC.
fp@2587:  **/
fp@2587: static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
fp@2587: {
fp@2587: 	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
fp@2587: 	    link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
fp@2587: 	u16 lat_enc = 0;	/* latency encoded */
fp@2587: 
fp@2587: 	if (link) {
fp@2587: 		u16 speed, duplex, scale = 0;
fp@2587: 		u16 max_snoop, max_nosnoop;
fp@2587: 		u16 max_ltr_enc;	/* max LTR latency encoded */
fp@2587: 		s64 lat_ns;	/* latency (ns) */
fp@2587: 		s64 value;
fp@2587: 		u32 rxa;
fp@2587: 
fp@2587: 		if (!hw->adapter->max_frame_size) {
fp@2587: 			e_dbg("max_frame_size not set.\n");
fp@2587: 			return -E1000_ERR_CONFIG;
fp@2587: 		}
fp@2587: 
fp@2587: 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
fp@2587: 		if (!speed) {
fp@2587: 			e_dbg("Speed not set.\n");
fp@2587: 			return -E1000_ERR_CONFIG;
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Rx Packet Buffer Allocation size (KB) */
fp@2587: 		rxa = er32(PBA) & E1000_PBA_RXA_MASK;
fp@2587: 
fp@2587: 		/* Determine the maximum latency tolerated by the device.
fp@2587: 		 *
fp@2587: 		 * Per the PCIe spec, the tolerated latencies are encoded as
fp@2587: 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
fp@2587: 		 * a 10-bit value (0-1023) to provide a range from 1 ns to
fp@2587: 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
fp@2587: 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
fp@2587: 		 */
fp@2587: 		lat_ns = ((s64)rxa * 1024 -
fp@2587: 			  (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
fp@2587: 		if (lat_ns < 0)
fp@2587: 			lat_ns = 0;
fp@2587: 		else
fp@2587: 			do_div(lat_ns, speed);
fp@2587: 
fp@2587: 		value = lat_ns;
fp@2587: 		while (value > PCI_LTR_VALUE_MASK) {
fp@2587: 			scale++;
fp@2587: 			value = DIV_ROUND_UP(value, (1 << 5));
fp@2587: 		}
fp@2587: 		if (scale > E1000_LTRV_SCALE_MAX) {
fp@2587: 			e_dbg("Invalid LTR latency scale %d\n", scale);
fp@2587: 			return -E1000_ERR_CONFIG;
fp@2587: 		}
fp@2587: 		lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
fp@2587: 
fp@2587: 		/* Determine the maximum latency tolerated by the platform */
fp@2587: 		pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
fp@2587: 				     &max_snoop);
fp@2587: 		pci_read_config_word(hw->adapter->pdev,
fp@2587: 				     E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
fp@2587: 		max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
fp@2587: 
fp@2587: 		if (lat_enc > max_ltr_enc)
fp@2587: 			lat_enc = max_ltr_enc;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Set Snoop and No-Snoop latencies the same */
fp@2587: 	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
fp@2587: 	ew32(LTRV, reg);
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Checks to see of the link status of the hardware has changed.  If a
fp@2587:  *  change in link status has been detected, then we read the PHY registers
fp@2587:  *  to get the current speed/duplex if link exists.
fp@2587:  **/
fp@2587: static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_mac_info *mac = &hw->mac;
fp@2587: 	s32 ret_val;
fp@2587: 	bool link;
fp@2587: 	u16 phy_reg;
fp@2587: 
fp@2587: 	/* We only want to go out to the PHY registers to see if Auto-Neg
fp@2587: 	 * has completed and/or if our link status has changed.  The
fp@2587: 	 * get_link_status flag is set upon receiving a Link Status
fp@2587: 	 * Change or Rx Sequence Error interrupt.
fp@2587: 	 */
fp@2587: 	if (!mac->get_link_status)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* First we want to see if the MII Status Register reports
fp@2587: 	 * link.  If so, then we want to get the current speed/duplex
fp@2587: 	 * of the PHY.
fp@2587: 	 */
fp@2587: 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (hw->mac.type == e1000_pchlan) {
fp@2587: 		ret_val = e1000_k1_gig_workaround_hv(hw, link);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* When connected at 10Mbps half-duplex, 82579 parts are excessively
fp@2587: 	 * aggressive resulting in many collisions. To avoid this, increase
fp@2587: 	 * the IPG and reduce Rx latency in the PHY.
fp@2587: 	 */
fp@2587: 	if ((hw->mac.type == e1000_pch2lan) && link) {
fp@2587: 		u32 reg;
fp@2587: 		reg = er32(STATUS);
fp@2587: 		if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
fp@2587: 			reg = er32(TIPG);
fp@2587: 			reg &= ~E1000_TIPG_IPGT_MASK;
fp@2587: 			reg |= 0xFF;
fp@2587: 			ew32(TIPG, reg);
fp@2587: 
fp@2587: 			/* Reduce Rx latency in analog PHY */
fp@2587: 			ret_val = hw->phy.ops.acquire(hw);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 
fp@2587: 			ret_val =
fp@2587: 			    e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
fp@2587: 
fp@2587: 			hw->phy.ops.release(hw);
fp@2587: 
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Work-around I218 hang issue */
fp@2587: 	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
fp@2587: 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
fp@2587: 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
fp@2587: 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
fp@2587: 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (hw->mac.type == e1000_pch_lpt) {
fp@2587: 		/* Set platform power management values for
fp@2587: 		 * Latency Tolerance Reporting (LTR)
fp@2587: 		 */
fp@2587: 		ret_val = e1000_platform_pm_pch_lpt(hw, link);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Clear link partner's EEE ability */
fp@2587: 	hw->dev_spec.ich8lan.eee_lp_ability = 0;
fp@2587: 
fp@2587: 	if (!link)
fp@2587: 		return 0;	/* No link detected */
fp@2587: 
fp@2587: 	mac->get_link_status = false;
fp@2587: 
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_pch2lan:
fp@2587: 		ret_val = e1000_k1_workaround_lv(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		/* fall-thru */
fp@2587: 	case e1000_pchlan:
fp@2587: 		if (hw->phy.type == e1000_phy_82578) {
fp@2587: 			ret_val = e1000_link_stall_workaround_hv(hw);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Workaround for PCHx parts in half-duplex:
fp@2587: 		 * Set the number of preambles removed from the packet
fp@2587: 		 * when it is passed from the PHY to the MAC to prevent
fp@2587: 		 * the MAC from misinterpreting the packet type.
fp@2587: 		 */
fp@2587: 		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
fp@2587: 		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
fp@2587: 
fp@2587: 		if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
fp@2587: 			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
fp@2587: 
fp@2587: 		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Check if there was DownShift, must be checked
fp@2587: 	 * immediately after link-up
fp@2587: 	 */
fp@2587: 	e1000e_check_downshift(hw);
fp@2587: 
fp@2587: 	/* Enable/Disable EEE after link up */
fp@2587: 	ret_val = e1000_set_eee_pchlan(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	/* If we are forcing speed/duplex, then we simply return since
fp@2587: 	 * we have already determined whether we have link or not.
fp@2587: 	 */
fp@2587: 	if (!mac->autoneg)
fp@2587: 		return -E1000_ERR_CONFIG;
fp@2587: 
fp@2587: 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
fp@2587: 	 * of MAC speed/duplex configuration.  So we only need to
fp@2587: 	 * configure Collision Distance in the MAC.
fp@2587: 	 */
fp@2587: 	mac->ops.config_collision_dist(hw);
fp@2587: 
fp@2587: 	/* Configure Flow Control now that Auto-Neg has completed.
fp@2587: 	 * First, we need to restore the desired flow control
fp@2587: 	 * settings because we may have had to re-autoneg with a
fp@2587: 	 * different link partner.
fp@2587: 	 */
fp@2587: 	ret_val = e1000e_config_fc_after_link_up(hw);
fp@2587: 	if (ret_val)
fp@2587: 		e_dbg("Error configuring flow control\n");
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
fp@2587: {
fp@2587: 	struct e1000_hw *hw = &adapter->hw;
fp@2587: 	s32 rc;
fp@2587: 
fp@2587: 	rc = e1000_init_mac_params_ich8lan(hw);
fp@2587: 	if (rc)
fp@2587: 		return rc;
fp@2587: 
fp@2587: 	rc = e1000_init_nvm_params_ich8lan(hw);
fp@2587: 	if (rc)
fp@2587: 		return rc;
fp@2587: 
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_ich8lan:
fp@2587: 	case e1000_ich9lan:
fp@2587: 	case e1000_ich10lan:
fp@2587: 		rc = e1000_init_phy_params_ich8lan(hw);
fp@2587: 		break;
fp@2587: 	case e1000_pchlan:
fp@2587: 	case e1000_pch2lan:
fp@2587: 	case e1000_pch_lpt:
fp@2587: 		rc = e1000_init_phy_params_pchlan(hw);
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		break;
fp@2587: 	}
fp@2587: 	if (rc)
fp@2587: 		return rc;
fp@2587: 
fp@2587: 	/* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
fp@2587: 	 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
fp@2587: 	 */
fp@2587: 	if ((adapter->hw.phy.type == e1000_phy_ife) ||
fp@2587: 	    ((adapter->hw.mac.type >= e1000_pch2lan) &&
fp@2587: 	     (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
fp@2587: 		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
fp@2587: 		adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
fp@2587: 
fp@2587: 		hw->mac.ops.blink_led = NULL;
fp@2587: 	}
fp@2587: 
fp@2587: 	if ((adapter->hw.mac.type == e1000_ich8lan) &&
fp@2587: 	    (adapter->hw.phy.type != e1000_phy_ife))
fp@2587: 		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
fp@2587: 
fp@2587: 	/* Enable workaround for 82579 w/ ME enabled */
fp@2587: 	if ((adapter->hw.mac.type == e1000_pch2lan) &&
fp@2587: 	    (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
fp@2587: 		adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: static DEFINE_MUTEX(nvm_mutex);
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Acquires the mutex for performing NVM operations.
fp@2587:  **/
fp@2587: static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
fp@2587: {
fp@2587: 	mutex_lock(&nvm_mutex);
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_release_nvm_ich8lan - Release NVM mutex
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Releases the mutex used while performing NVM operations.
fp@2587:  **/
fp@2587: static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
fp@2587: {
fp@2587: 	mutex_unlock(&nvm_mutex);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Acquires the software control flag for performing PHY and select
fp@2587:  *  MAC CSR accesses.
fp@2587:  **/
fp@2587: static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
fp@2587: 	s32 ret_val = 0;
fp@2587: 
fp@2587: 	if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
fp@2587: 			     &hw->adapter->state)) {
fp@2587: 		e_dbg("contention for Phy access\n");
fp@2587: 		return -E1000_ERR_PHY;
fp@2587: 	}
fp@2587: 
fp@2587: 	while (timeout) {
fp@2587: 		extcnf_ctrl = er32(EXTCNF_CTRL);
fp@2587: 		if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
fp@2587: 			break;
fp@2587: 
fp@2587: 		mdelay(1);
fp@2587: 		timeout--;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (!timeout) {
fp@2587: 		e_dbg("SW has already locked the resource.\n");
fp@2587: 		ret_val = -E1000_ERR_CONFIG;
fp@2587: 		goto out;
fp@2587: 	}
fp@2587: 
fp@2587: 	timeout = SW_FLAG_TIMEOUT;
fp@2587: 
fp@2587: 	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
fp@2587: 	ew32(EXTCNF_CTRL, extcnf_ctrl);
fp@2587: 
fp@2587: 	while (timeout) {
fp@2587: 		extcnf_ctrl = er32(EXTCNF_CTRL);
fp@2587: 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
fp@2587: 			break;
fp@2587: 
fp@2587: 		mdelay(1);
fp@2587: 		timeout--;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (!timeout) {
fp@2587: 		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
fp@2587: 		      er32(FWSM), extcnf_ctrl);
fp@2587: 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
fp@2587: 		ew32(EXTCNF_CTRL, extcnf_ctrl);
fp@2587: 		ret_val = -E1000_ERR_CONFIG;
fp@2587: 		goto out;
fp@2587: 	}
fp@2587: 
fp@2587: out:
fp@2587: 	if (ret_val)
fp@2587: 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_release_swflag_ich8lan - Release software control flag
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Releases the software control flag for performing PHY and select
fp@2587:  *  MAC CSR accesses.
fp@2587:  **/
fp@2587: static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 extcnf_ctrl;
fp@2587: 
fp@2587: 	extcnf_ctrl = er32(EXTCNF_CTRL);
fp@2587: 
fp@2587: 	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
fp@2587: 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
fp@2587: 		ew32(EXTCNF_CTRL, extcnf_ctrl);
fp@2587: 	} else {
fp@2587: 		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
fp@2587: 	}
fp@2587: 
fp@2587: 	clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_check_mng_mode_ich8lan - Checks management mode
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  This checks if the adapter has any manageability enabled.
fp@2587:  *  This is a function pointer entry point only called by read/write
fp@2587:  *  routines for the PHY and NVM parts.
fp@2587:  **/
fp@2587: static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 fwsm;
fp@2587: 
fp@2587: 	fwsm = er32(FWSM);
fp@2587: 	return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
fp@2587: 		((fwsm & E1000_FWSM_MODE_MASK) ==
fp@2587: 		 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_check_mng_mode_pchlan - Checks management mode
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  This checks if the adapter has iAMT enabled.
fp@2587:  *  This is a function pointer entry point only called by read/write
fp@2587:  *  routines for the PHY and NVM parts.
fp@2587:  **/
fp@2587: static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 fwsm;
fp@2587: 
fp@2587: 	fwsm = er32(FWSM);
fp@2587: 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
fp@2587: 	    (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_rar_set_pch2lan - Set receive address register
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @addr: pointer to the receive address
fp@2587:  *  @index: receive address array register
fp@2587:  *
fp@2587:  *  Sets the receive address array register at index to the address passed
fp@2587:  *  in by addr.  For 82579, RAR[0] is the base address register that is to
fp@2587:  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
fp@2587:  *  Use SHRA[0-3] in place of those reserved for ME.
fp@2587:  **/
fp@2587: static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
fp@2587: {
fp@2587: 	u32 rar_low, rar_high;
fp@2587: 
fp@2587: 	/* HW expects these in little endian so we reverse the byte order
fp@2587: 	 * from network order (big endian) to little endian
fp@2587: 	 */
fp@2587: 	rar_low = ((u32)addr[0] |
fp@2587: 		   ((u32)addr[1] << 8) |
fp@2587: 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
fp@2587: 
fp@2587: 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
fp@2587: 
fp@2587: 	/* If MAC address zero, no need to set the AV bit */
fp@2587: 	if (rar_low || rar_high)
fp@2587: 		rar_high |= E1000_RAH_AV;
fp@2587: 
fp@2587: 	if (index == 0) {
fp@2587: 		ew32(RAL(index), rar_low);
fp@2587: 		e1e_flush();
fp@2587: 		ew32(RAH(index), rar_high);
fp@2587: 		e1e_flush();
fp@2587: 		return;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* RAR[1-6] are owned by manageability.  Skip those and program the
fp@2587: 	 * next address into the SHRA register array.
fp@2587: 	 */
fp@2587: 	if (index < (u32)(hw->mac.rar_entry_count - 6)) {
fp@2587: 		s32 ret_val;
fp@2587: 
fp@2587: 		ret_val = e1000_acquire_swflag_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			goto out;
fp@2587: 
fp@2587: 		ew32(SHRAL(index - 1), rar_low);
fp@2587: 		e1e_flush();
fp@2587: 		ew32(SHRAH(index - 1), rar_high);
fp@2587: 		e1e_flush();
fp@2587: 
fp@2587: 		e1000_release_swflag_ich8lan(hw);
fp@2587: 
fp@2587: 		/* verify the register updates */
fp@2587: 		if ((er32(SHRAL(index - 1)) == rar_low) &&
fp@2587: 		    (er32(SHRAH(index - 1)) == rar_high))
fp@2587: 			return;
fp@2587: 
fp@2587: 		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
fp@2587: 		      (index - 1), er32(FWSM));
fp@2587: 	}
fp@2587: 
fp@2587: out:
fp@2587: 	e_dbg("Failed to write receive address at index %d\n", index);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_rar_set_pch_lpt - Set receive address registers
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @addr: pointer to the receive address
fp@2587:  *  @index: receive address array register
fp@2587:  *
fp@2587:  *  Sets the receive address register array at index to the address passed
fp@2587:  *  in by addr. For LPT, RAR[0] is the base address register that is to
fp@2587:  *  contain the MAC address. SHRA[0-10] are the shared receive address
fp@2587:  *  registers that are shared between the Host and manageability engine (ME).
fp@2587:  **/
fp@2587: static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
fp@2587: {
fp@2587: 	u32 rar_low, rar_high;
fp@2587: 	u32 wlock_mac;
fp@2587: 
fp@2587: 	/* HW expects these in little endian so we reverse the byte order
fp@2587: 	 * from network order (big endian) to little endian
fp@2587: 	 */
fp@2587: 	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
fp@2587: 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
fp@2587: 
fp@2587: 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
fp@2587: 
fp@2587: 	/* If MAC address zero, no need to set the AV bit */
fp@2587: 	if (rar_low || rar_high)
fp@2587: 		rar_high |= E1000_RAH_AV;
fp@2587: 
fp@2587: 	if (index == 0) {
fp@2587: 		ew32(RAL(index), rar_low);
fp@2587: 		e1e_flush();
fp@2587: 		ew32(RAH(index), rar_high);
fp@2587: 		e1e_flush();
fp@2587: 		return;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* The manageability engine (ME) can lock certain SHRAR registers that
fp@2587: 	 * it is using - those registers are unavailable for use.
fp@2587: 	 */
fp@2587: 	if (index < hw->mac.rar_entry_count) {
fp@2587: 		wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
fp@2587: 		wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
fp@2587: 
fp@2587: 		/* Check if all SHRAR registers are locked */
fp@2587: 		if (wlock_mac == 1)
fp@2587: 			goto out;
fp@2587: 
fp@2587: 		if ((wlock_mac == 0) || (index <= wlock_mac)) {
fp@2587: 			s32 ret_val;
fp@2587: 
fp@2587: 			ret_val = e1000_acquire_swflag_ich8lan(hw);
fp@2587: 
fp@2587: 			if (ret_val)
fp@2587: 				goto out;
fp@2587: 
fp@2587: 			ew32(SHRAL_PCH_LPT(index - 1), rar_low);
fp@2587: 			e1e_flush();
fp@2587: 			ew32(SHRAH_PCH_LPT(index - 1), rar_high);
fp@2587: 			e1e_flush();
fp@2587: 
fp@2587: 			e1000_release_swflag_ich8lan(hw);
fp@2587: 
fp@2587: 			/* verify the register updates */
fp@2587: 			if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
fp@2587: 			    (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
fp@2587: 				return;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: out:
fp@2587: 	e_dbg("Failed to write receive address at index %d\n", index);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Checks if firmware is blocking the reset of the PHY.
fp@2587:  *  This is a function pointer entry point only called by
fp@2587:  *  reset routines.
fp@2587:  **/
fp@2587: static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 fwsm;
fp@2587: 
fp@2587: 	fwsm = er32(FWSM);
fp@2587: 
fp@2587: 	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Assumes semaphore already acquired.
fp@2587:  *
fp@2587:  **/
fp@2587: static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u16 phy_data;
fp@2587: 	u32 strap = er32(STRAP);
fp@2587: 	u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
fp@2587: 	    E1000_STRAP_SMT_FREQ_SHIFT;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
fp@2587: 
fp@2587: 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	phy_data &= ~HV_SMB_ADDR_MASK;
fp@2587: 	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
fp@2587: 	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
fp@2587: 
fp@2587: 	if (hw->phy.type == e1000_phy_i217) {
fp@2587: 		/* Restore SMBus frequency */
fp@2587: 		if (freq--) {
fp@2587: 			phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
fp@2587: 			phy_data |= (freq & (1 << 0)) <<
fp@2587: 			    HV_SMB_ADDR_FREQ_LOW_SHIFT;
fp@2587: 			phy_data |= (freq & (1 << 1)) <<
fp@2587: 			    (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
fp@2587: 		} else {
fp@2587: 			e_dbg("Unsupported SMB frequency in PHY\n");
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  *
fp@2587:  *  SW should configure the LCD from the NVM extended configuration region
fp@2587:  *  as a workaround for certain parts.
fp@2587:  **/
fp@2587: static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_phy_info *phy = &hw->phy;
fp@2587: 	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 word_addr, reg_data, reg_addr, phy_page = 0;
fp@2587: 
fp@2587: 	/* Initialize the PHY from the NVM on ICH platforms.  This
fp@2587: 	 * is needed due to an issue where the NVM configuration is
fp@2587: 	 * not properly autoloaded after power transitions.
fp@2587: 	 * Therefore, after each PHY reset, we will load the
fp@2587: 	 * configuration data out of the NVM manually.
fp@2587: 	 */
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_ich8lan:
fp@2587: 		if (phy->type != e1000_phy_igp_3)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
fp@2587: 		    (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
fp@2587: 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
fp@2587: 			break;
fp@2587: 		}
fp@2587: 		/* Fall-thru */
fp@2587: 	case e1000_pchlan:
fp@2587: 	case e1000_pch2lan:
fp@2587: 	case e1000_pch_lpt:
fp@2587: 		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	data = er32(FEXTNVM);
fp@2587: 	if (!(data & sw_cfg_mask))
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	/* Make sure HW does not configure LCD from PHY
fp@2587: 	 * extended configuration before SW configuration
fp@2587: 	 */
fp@2587: 	data = er32(EXTCNF_CTRL);
fp@2587: 	if ((hw->mac.type < e1000_pch2lan) &&
fp@2587: 	    (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	cnf_size = er32(EXTCNF_SIZE);
fp@2587: 	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
fp@2587: 	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
fp@2587: 	if (!cnf_size)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
fp@2587: 	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
fp@2587: 
fp@2587: 	if (((hw->mac.type == e1000_pchlan) &&
fp@2587: 	     !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
fp@2587: 	    (hw->mac.type > e1000_pchlan)) {
fp@2587: 		/* HW configures the SMBus address and LEDs when the
fp@2587: 		 * OEM and LCD Write Enable bits are set in the NVM.
fp@2587: 		 * When both NVM bits are cleared, SW will configure
fp@2587: 		 * them instead.
fp@2587: 		 */
fp@2587: 		ret_val = e1000_write_smbus_addr(hw);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		data = er32(LEDCTL);
fp@2587: 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
fp@2587: 							(u16)data);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Configure LCD from extended configuration region. */
fp@2587: 
fp@2587: 	/* cnf_base_addr is in DWORD */
fp@2587: 	word_addr = (u16)(cnf_base_addr << 1);
fp@2587: 
fp@2587: 	for (i = 0; i < cnf_size; i++) {
fp@2587: 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
fp@2587: 					 1, &reg_addr);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 		/* Save off the PHY page for future writes. */
fp@2587: 		if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
fp@2587: 			phy_page = reg_data;
fp@2587: 			continue;
fp@2587: 		}
fp@2587: 
fp@2587: 		reg_addr &= PHY_REG_MASK;
fp@2587: 		reg_addr |= phy_page;
fp@2587: 
fp@2587: 		ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 	}
fp@2587: 
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_k1_gig_workaround_hv - K1 Si workaround
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  *  @link: link up bool flag
fp@2587:  *
fp@2587:  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
fp@2587:  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
fp@2587:  *  If link is down, the function will restore the default K1 setting located
fp@2587:  *  in the NVM.
fp@2587:  **/
fp@2587: static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 status_reg = 0;
fp@2587: 	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
fp@2587: 
fp@2587: 	if (hw->mac.type != e1000_pchlan)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* Wrap the whole flow with the sw flag */
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
fp@2587: 	if (link) {
fp@2587: 		if (hw->phy.type == e1000_phy_82578) {
fp@2587: 			ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
fp@2587: 						  &status_reg);
fp@2587: 			if (ret_val)
fp@2587: 				goto release;
fp@2587: 
fp@2587: 			status_reg &= (BM_CS_STATUS_LINK_UP |
fp@2587: 				       BM_CS_STATUS_RESOLVED |
fp@2587: 				       BM_CS_STATUS_SPEED_MASK);
fp@2587: 
fp@2587: 			if (status_reg == (BM_CS_STATUS_LINK_UP |
fp@2587: 					   BM_CS_STATUS_RESOLVED |
fp@2587: 					   BM_CS_STATUS_SPEED_1000))
fp@2587: 				k1_enable = false;
fp@2587: 		}
fp@2587: 
fp@2587: 		if (hw->phy.type == e1000_phy_82577) {
fp@2587: 			ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
fp@2587: 			if (ret_val)
fp@2587: 				goto release;
fp@2587: 
fp@2587: 			status_reg &= (HV_M_STATUS_LINK_UP |
fp@2587: 				       HV_M_STATUS_AUTONEG_COMPLETE |
fp@2587: 				       HV_M_STATUS_SPEED_MASK);
fp@2587: 
fp@2587: 			if (status_reg == (HV_M_STATUS_LINK_UP |
fp@2587: 					   HV_M_STATUS_AUTONEG_COMPLETE |
fp@2587: 					   HV_M_STATUS_SPEED_1000))
fp@2587: 				k1_enable = false;
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Link stall fix for link up */
fp@2587: 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 
fp@2587: 	} else {
fp@2587: 		/* Link stall fix for link down */
fp@2587: 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 	}
fp@2587: 
fp@2587: 	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
fp@2587: 
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_configure_k1_ich8lan - Configure K1 power state
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @enable: K1 state to configure
fp@2587:  *
fp@2587:  *  Configure the K1 power state based on the provided parameter.
fp@2587:  *  Assumes semaphore already acquired.
fp@2587:  *
fp@2587:  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2587:  **/
fp@2587: s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u32 ctrl_reg = 0;
fp@2587: 	u32 ctrl_ext = 0;
fp@2587: 	u32 reg = 0;
fp@2587: 	u16 kmrn_reg = 0;
fp@2587: 
fp@2587: 	ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
fp@2587: 					      &kmrn_reg);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (k1_enable)
fp@2587: 		kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
fp@2587: 	else
fp@2587: 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
fp@2587: 
fp@2587: 	ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
fp@2587: 					       kmrn_reg);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	usleep_range(20, 40);
fp@2587: 	ctrl_ext = er32(CTRL_EXT);
fp@2587: 	ctrl_reg = er32(CTRL);
fp@2587: 
fp@2587: 	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
fp@2587: 	reg |= E1000_CTRL_FRCSPD;
fp@2587: 	ew32(CTRL, reg);
fp@2587: 
fp@2587: 	ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
fp@2587: 	e1e_flush();
fp@2587: 	usleep_range(20, 40);
fp@2587: 	ew32(CTRL, ctrl_reg);
fp@2587: 	ew32(CTRL_EXT, ctrl_ext);
fp@2587: 	e1e_flush();
fp@2587: 	usleep_range(20, 40);
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
fp@2587:  *  @hw:       pointer to the HW structure
fp@2587:  *  @d0_state: boolean if entering d0 or d3 device state
fp@2587:  *
fp@2587:  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
fp@2587:  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
fp@2587:  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
fp@2587:  **/
fp@2587: static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u32 mac_reg;
fp@2587: 	u16 oem_reg;
fp@2587: 
fp@2587: 	if (hw->mac.type < e1000_pchlan)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (hw->mac.type == e1000_pchlan) {
fp@2587: 		mac_reg = er32(EXTCNF_CTRL);
fp@2587: 		if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
fp@2587: 			goto release;
fp@2587: 	}
fp@2587: 
fp@2587: 	mac_reg = er32(FEXTNVM);
fp@2587: 	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	mac_reg = er32(PHY_CTRL);
fp@2587: 
fp@2587: 	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
fp@2587: 
fp@2587: 	if (d0_state) {
fp@2587: 		if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
fp@2587: 			oem_reg |= HV_OEM_BITS_GBE_DIS;
fp@2587: 
fp@2587: 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
fp@2587: 			oem_reg |= HV_OEM_BITS_LPLU;
fp@2587: 	} else {
fp@2587: 		if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
fp@2587: 			       E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
fp@2587: 			oem_reg |= HV_OEM_BITS_GBE_DIS;
fp@2587: 
fp@2587: 		if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
fp@2587: 			       E1000_PHY_CTRL_NOND0A_LPLU))
fp@2587: 			oem_reg |= HV_OEM_BITS_LPLU;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Set Restart auto-neg to activate the bits */
fp@2587: 	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
fp@2587: 	    !hw->phy.ops.check_reset_block(hw))
fp@2587: 		oem_reg |= HV_OEM_BITS_RESTART_AN;
fp@2587: 
fp@2587: 	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
fp@2587: 
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  **/
fp@2587: static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u16 data;
fp@2587: 
fp@2587: 	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	data |= HV_KMRN_MDIO_SLOW;
fp@2587: 
fp@2587: 	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
fp@2587:  *  done after every PHY reset.
fp@2587:  **/
fp@2587: static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 phy_data;
fp@2587: 
fp@2587: 	if (hw->mac.type != e1000_pchlan)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* Set MDIO slow mode before any other MDIO access */
fp@2587: 	if (hw->phy.type == e1000_phy_82577) {
fp@2587: 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (((hw->phy.type == e1000_phy_82577) &&
fp@2587: 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
fp@2587: 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
fp@2587: 		/* Disable generation of early preamble */
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		/* Preamble tuning for SSC */
fp@2587: 		ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (hw->phy.type == e1000_phy_82578) {
fp@2587: 		/* Return registers to default by doing a soft reset then
fp@2587: 		 * writing 0x3140 to the control register.
fp@2587: 		 */
fp@2587: 		if (hw->phy.revision < 2) {
fp@2587: 			e1000e_phy_sw_reset(hw);
fp@2587: 			ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Select page 0 */
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	hw->phy.addr = 1;
fp@2587: 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	/* Configure the K1 Si workaround during phy reset assuming there is
fp@2587: 	 * link so that it disables K1 if link is in 1Gbps.
fp@2587: 	 */
fp@2587: 	ret_val = e1000_k1_gig_workaround_hv(hw, true);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	/* Workaround for link disconnects on a busy hub in half duplex */
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	/* set MSE higher to enable link to stay up when noise is high */
fp@2587: 	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  **/
fp@2587: void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 mac_reg;
fp@2587: 	u16 i, phy_reg = 0;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return;
fp@2587: 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
fp@2587: 	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
fp@2587: 		mac_reg = er32(RAL(i));
fp@2587: 		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
fp@2587: 					   (u16)(mac_reg & 0xFFFF));
fp@2587: 		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
fp@2587: 					   (u16)((mac_reg >> 16) & 0xFFFF));
fp@2587: 
fp@2587: 		mac_reg = er32(RAH(i));
fp@2587: 		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
fp@2587: 					   (u16)(mac_reg & 0xFFFF));
fp@2587: 		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
fp@2587: 					   (u16)((mac_reg & E1000_RAH_AV)
fp@2587: 						 >> 16));
fp@2587: 	}
fp@2587: 
fp@2587: 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
fp@2587: 
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
fp@2587:  *  with 82579 PHY
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
fp@2587:  **/
fp@2587: s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 phy_reg, data;
fp@2587: 	u32 mac_reg;
fp@2587: 	u16 i;
fp@2587: 
fp@2587: 	if (hw->mac.type < e1000_pch2lan)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* disable Rx path while enabling/disabling workaround */
fp@2587: 	e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
fp@2587: 	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (enable) {
fp@2587: 		/* Write Rx addresses (rar_entry_count for RAL/H, and
fp@2587: 		 * SHRAL/H) and initial CRC values to the MAC
fp@2587: 		 */
fp@2587: 		for (i = 0; i < hw->mac.rar_entry_count; i++) {
fp@2587: 			u8 mac_addr[ETH_ALEN] = { 0 };
fp@2587: 			u32 addr_high, addr_low;
fp@2587: 
fp@2587: 			addr_high = er32(RAH(i));
fp@2587: 			if (!(addr_high & E1000_RAH_AV))
fp@2587: 				continue;
fp@2587: 			addr_low = er32(RAL(i));
fp@2587: 			mac_addr[0] = (addr_low & 0xFF);
fp@2587: 			mac_addr[1] = ((addr_low >> 8) & 0xFF);
fp@2587: 			mac_addr[2] = ((addr_low >> 16) & 0xFF);
fp@2587: 			mac_addr[3] = ((addr_low >> 24) & 0xFF);
fp@2587: 			mac_addr[4] = (addr_high & 0xFF);
fp@2587: 			mac_addr[5] = ((addr_high >> 8) & 0xFF);
fp@2587: 
fp@2587: 			ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Write Rx addresses to the PHY */
fp@2587: 		e1000_copy_rx_addrs_to_phy_ich8lan(hw);
fp@2587: 
fp@2587: 		/* Enable jumbo frame workaround in the MAC */
fp@2587: 		mac_reg = er32(FFLT_DBG);
fp@2587: 		mac_reg &= ~(1 << 14);
fp@2587: 		mac_reg |= (7 << 15);
fp@2587: 		ew32(FFLT_DBG, mac_reg);
fp@2587: 
fp@2587: 		mac_reg = er32(RCTL);
fp@2587: 		mac_reg |= E1000_RCTL_SECRC;
fp@2587: 		ew32(RCTL, mac_reg);
fp@2587: 
fp@2587: 		ret_val = e1000e_read_kmrn_reg(hw,
fp@2587: 					       E1000_KMRNCTRLSTA_CTRL_OFFSET,
fp@2587: 					       &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1000e_write_kmrn_reg(hw,
fp@2587: 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
fp@2587: 						data | (1 << 0));
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1000e_read_kmrn_reg(hw,
fp@2587: 					       E1000_KMRNCTRLSTA_HD_CTRL,
fp@2587: 					       &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		data &= ~(0xF << 8);
fp@2587: 		data |= (0xB << 8);
fp@2587: 		ret_val = e1000e_write_kmrn_reg(hw,
fp@2587: 						E1000_KMRNCTRLSTA_HD_CTRL,
fp@2587: 						data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		/* Enable jumbo frame workaround in the PHY */
fp@2587: 		e1e_rphy(hw, PHY_REG(769, 23), &data);
fp@2587: 		data &= ~(0x7F << 5);
fp@2587: 		data |= (0x37 << 5);
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		e1e_rphy(hw, PHY_REG(769, 16), &data);
fp@2587: 		data &= ~(1 << 13);
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		e1e_rphy(hw, PHY_REG(776, 20), &data);
fp@2587: 		data &= ~(0x3FF << 2);
fp@2587: 		data |= (0x1A << 2);
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		e1e_rphy(hw, HV_PM_CTRL, &data);
fp@2587: 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	} else {
fp@2587: 		/* Write MAC register values back to h/w defaults */
fp@2587: 		mac_reg = er32(FFLT_DBG);
fp@2587: 		mac_reg &= ~(0xF << 14);
fp@2587: 		ew32(FFLT_DBG, mac_reg);
fp@2587: 
fp@2587: 		mac_reg = er32(RCTL);
fp@2587: 		mac_reg &= ~E1000_RCTL_SECRC;
fp@2587: 		ew32(RCTL, mac_reg);
fp@2587: 
fp@2587: 		ret_val = e1000e_read_kmrn_reg(hw,
fp@2587: 					       E1000_KMRNCTRLSTA_CTRL_OFFSET,
fp@2587: 					       &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1000e_write_kmrn_reg(hw,
fp@2587: 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
fp@2587: 						data & ~(1 << 0));
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1000e_read_kmrn_reg(hw,
fp@2587: 					       E1000_KMRNCTRLSTA_HD_CTRL,
fp@2587: 					       &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		data &= ~(0xF << 8);
fp@2587: 		data |= (0xB << 8);
fp@2587: 		ret_val = e1000e_write_kmrn_reg(hw,
fp@2587: 						E1000_KMRNCTRLSTA_HD_CTRL,
fp@2587: 						data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		/* Write PHY register values back to h/w defaults */
fp@2587: 		e1e_rphy(hw, PHY_REG(769, 23), &data);
fp@2587: 		data &= ~(0x7F << 5);
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		e1e_rphy(hw, PHY_REG(769, 16), &data);
fp@2587: 		data |= (1 << 13);
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		e1e_rphy(hw, PHY_REG(776, 20), &data);
fp@2587: 		data &= ~(0x3FF << 2);
fp@2587: 		data |= (0x8 << 2);
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		e1e_rphy(hw, HV_PM_CTRL, &data);
fp@2587: 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* re-enable Rx path after enabling/disabling workaround */
fp@2587: 	return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
fp@2587:  *  done after every PHY reset.
fp@2587:  **/
fp@2587: static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 
fp@2587: 	if (hw->mac.type != e1000_pch2lan)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* Set MDIO slow mode before any other MDIO access */
fp@2587: 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	ret_val = hw->phy.ops.acquire(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 	/* set MSE higher to enable link to stay up when noise is high */
fp@2587: 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 	/* drop link after 5 times MSE threshold was reached */
fp@2587: 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
fp@2587: release:
fp@2587: 	hw->phy.ops.release(hw);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_k1_gig_workaround_lv - K1 Si workaround
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  *
fp@2587:  *  Workaround to set the K1 beacon duration for 82579 parts
fp@2587:  **/
fp@2587: static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 status_reg = 0;
fp@2587: 	u32 mac_reg;
fp@2587: 	u16 phy_reg;
fp@2587: 
fp@2587: 	if (hw->mac.type != e1000_pch2lan)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* Set K1 beacon duration based on 1Gbps speed or otherwise */
fp@2587: 	ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
fp@2587: 	    == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
fp@2587: 		mac_reg = er32(FEXTNVM4);
fp@2587: 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
fp@2587: 
fp@2587: 		ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		if (status_reg & HV_M_STATUS_SPEED_1000) {
fp@2587: 			u16 pm_phy_reg;
fp@2587: 
fp@2587: 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
fp@2587: 			phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
fp@2587: 			/* LV 1G Packet drop issue wa  */
fp@2587: 			ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 			pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
fp@2587: 			ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		} else {
fp@2587: 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
fp@2587: 			phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
fp@2587: 		}
fp@2587: 		ew32(FEXTNVM4, mac_reg);
fp@2587: 		ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
fp@2587:  *  @hw:   pointer to the HW structure
fp@2587:  *  @gate: boolean set to true to gate, false to ungate
fp@2587:  *
fp@2587:  *  Gate/ungate the automatic PHY configuration via hardware; perform
fp@2587:  *  the configuration via software instead.
fp@2587:  **/
fp@2587: static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
fp@2587: {
fp@2587: 	u32 extcnf_ctrl;
fp@2587: 
fp@2587: 	if (hw->mac.type < e1000_pch2lan)
fp@2587: 		return;
fp@2587: 
fp@2587: 	extcnf_ctrl = er32(EXTCNF_CTRL);
fp@2587: 
fp@2587: 	if (gate)
fp@2587: 		extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
fp@2587: 	else
fp@2587: 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
fp@2587: 
fp@2587: 	ew32(EXTCNF_CTRL, extcnf_ctrl);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Check the appropriate indication the MAC has finished configuring the
fp@2587:  *  PHY after a software reset.
fp@2587:  **/
fp@2587: static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
fp@2587: 
fp@2587: 	/* Wait for basic configuration completes before proceeding */
fp@2587: 	do {
fp@2587: 		data = er32(STATUS);
fp@2587: 		data &= E1000_STATUS_LAN_INIT_DONE;
fp@2587: 		usleep_range(100, 200);
fp@2587: 	} while ((!data) && --loop);
fp@2587: 
fp@2587: 	/* If basic configuration is incomplete before the above loop
fp@2587: 	 * count reaches 0, loading the configuration from NVM will
fp@2587: 	 * leave the PHY in a bad state possibly resulting in no link.
fp@2587: 	 */
fp@2587: 	if (loop == 0)
fp@2587: 		e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fp@2587: 
fp@2587: 	/* Clear the Init Done bit for the next init event */
fp@2587: 	data = er32(STATUS);
fp@2587: 	data &= ~E1000_STATUS_LAN_INIT_DONE;
fp@2587: 	ew32(STATUS, data);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  **/
fp@2587: static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 reg;
fp@2587: 
fp@2587: 	if (hw->phy.ops.check_reset_block(hw))
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* Allow time for h/w to get to quiescent state after reset */
fp@2587: 	usleep_range(10000, 20000);
fp@2587: 
fp@2587: 	/* Perform any necessary post-reset workarounds */
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_pchlan:
fp@2587: 		ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		break;
fp@2587: 	case e1000_pch2lan:
fp@2587: 		ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Clear the host wakeup bit after lcd reset */
fp@2587: 	if (hw->mac.type >= e1000_pchlan) {
fp@2587: 		e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
fp@2587: 		reg &= ~BM_WUC_HOST_WU_BIT;
fp@2587: 		e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Configure the LCD with the extended configuration region in NVM */
fp@2587: 	ret_val = e1000_sw_lcd_config_ich8lan(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	/* Configure the LCD with the OEM bits in NVM */
fp@2587: 	ret_val = e1000_oem_bits_config_ich8lan(hw, true);
fp@2587: 
fp@2587: 	if (hw->mac.type == e1000_pch2lan) {
fp@2587: 		/* Ungate automatic PHY configuration on non-managed 82579 */
fp@2587: 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
fp@2587: 			usleep_range(10000, 20000);
fp@2587: 			e1000_gate_hw_phy_config_ich8lan(hw, false);
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Set EEE LPI Update Timer to 200usec */
fp@2587: 		ret_val = hw->phy.ops.acquire(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1000_write_emi_reg_locked(hw,
fp@2587: 						     I82579_LPI_UPDATE_TIMER,
fp@2587: 						     0x1387);
fp@2587: 		hw->phy.ops.release(hw);
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Resets the PHY
fp@2587:  *  This is a function pointer entry point called by drivers
fp@2587:  *  or other shared routines.
fp@2587:  **/
fp@2587: static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 
fp@2587: 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
fp@2587: 	if ((hw->mac.type == e1000_pch2lan) &&
fp@2587: 	    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
fp@2587: 		e1000_gate_hw_phy_config_ich8lan(hw, true);
fp@2587: 
fp@2587: 	ret_val = e1000e_phy_hw_reset_generic(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	return e1000_post_phy_reset_ich8lan(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @active: true to enable LPLU, false to disable
fp@2587:  *
fp@2587:  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
fp@2587:  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
fp@2587:  *  the phy speed. This function will manually set the LPLU bit and restart
fp@2587:  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
fp@2587:  *  since it configures the same bit.
fp@2587:  **/
fp@2587: static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u16 oem_reg;
fp@2587: 
fp@2587: 	ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (active)
fp@2587: 		oem_reg |= HV_OEM_BITS_LPLU;
fp@2587: 	else
fp@2587: 		oem_reg &= ~HV_OEM_BITS_LPLU;
fp@2587: 
fp@2587: 	if (!hw->phy.ops.check_reset_block(hw))
fp@2587: 		oem_reg |= HV_OEM_BITS_RESTART_AN;
fp@2587: 
fp@2587: 	return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @active: true to enable LPLU, false to disable
fp@2587:  *
fp@2587:  *  Sets the LPLU D0 state according to the active flag.  When
fp@2587:  *  activating LPLU this function also disables smart speed
fp@2587:  *  and vice versa.  LPLU will not be activated unless the
fp@2587:  *  device autonegotiation advertisement meets standards of
fp@2587:  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
fp@2587:  *  This is a function pointer entry point only called by
fp@2587:  *  PHY setup routines.
fp@2587:  **/
fp@2587: static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
fp@2587: {
fp@2587: 	struct e1000_phy_info *phy = &hw->phy;
fp@2587: 	u32 phy_ctrl;
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 data;
fp@2587: 
fp@2587: 	if (phy->type == e1000_phy_ife)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	phy_ctrl = er32(PHY_CTRL);
fp@2587: 
fp@2587: 	if (active) {
fp@2587: 		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
fp@2587: 		ew32(PHY_CTRL, phy_ctrl);
fp@2587: 
fp@2587: 		if (phy->type != e1000_phy_igp_3)
fp@2587: 			return 0;
fp@2587: 
fp@2587: 		/* Call gig speed drop workaround on LPLU before accessing
fp@2587: 		 * any PHY registers
fp@2587: 		 */
fp@2587: 		if (hw->mac.type == e1000_ich8lan)
fp@2587: 			e1000e_gig_downshift_workaround_ich8lan(hw);
fp@2587: 
fp@2587: 		/* When LPLU is enabled, we should disable SmartSpeed */
fp@2587: 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2587: 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	} else {
fp@2587: 		phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
fp@2587: 		ew32(PHY_CTRL, phy_ctrl);
fp@2587: 
fp@2587: 		if (phy->type != e1000_phy_igp_3)
fp@2587: 			return 0;
fp@2587: 
fp@2587: 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
fp@2587: 		 * during Dx states where the power conservation is most
fp@2587: 		 * important.  During driver activity we should enable
fp@2587: 		 * SmartSpeed, so performance is maintained.
fp@2587: 		 */
fp@2587: 		if (phy->smart_speed == e1000_smart_speed_on) {
fp@2587: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   &data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 
fp@2587: 			data |= IGP01E1000_PSCFR_SMART_SPEED;
fp@2587: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		} else if (phy->smart_speed == e1000_smart_speed_off) {
fp@2587: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   &data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 
fp@2587: 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2587: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @active: true to enable LPLU, false to disable
fp@2587:  *
fp@2587:  *  Sets the LPLU D3 state according to the active flag.  When
fp@2587:  *  activating LPLU this function also disables smart speed
fp@2587:  *  and vice versa.  LPLU will not be activated unless the
fp@2587:  *  device autonegotiation advertisement meets standards of
fp@2587:  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
fp@2587:  *  This is a function pointer entry point only called by
fp@2587:  *  PHY setup routines.
fp@2587:  **/
fp@2587: static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
fp@2587: {
fp@2587: 	struct e1000_phy_info *phy = &hw->phy;
fp@2587: 	u32 phy_ctrl;
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u16 data;
fp@2587: 
fp@2587: 	phy_ctrl = er32(PHY_CTRL);
fp@2587: 
fp@2587: 	if (!active) {
fp@2587: 		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
fp@2587: 		ew32(PHY_CTRL, phy_ctrl);
fp@2587: 
fp@2587: 		if (phy->type != e1000_phy_igp_3)
fp@2587: 			return 0;
fp@2587: 
fp@2587: 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
fp@2587: 		 * during Dx states where the power conservation is most
fp@2587: 		 * important.  During driver activity we should enable
fp@2587: 		 * SmartSpeed, so performance is maintained.
fp@2587: 		 */
fp@2587: 		if (phy->smart_speed == e1000_smart_speed_on) {
fp@2587: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   &data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 
fp@2587: 			data |= IGP01E1000_PSCFR_SMART_SPEED;
fp@2587: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		} else if (phy->smart_speed == e1000_smart_speed_off) {
fp@2587: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   &data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 
fp@2587: 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2587: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2587: 					   data);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 		}
fp@2587: 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
fp@2587: 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
fp@2587: 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
fp@2587: 		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
fp@2587: 		ew32(PHY_CTRL, phy_ctrl);
fp@2587: 
fp@2587: 		if (phy->type != e1000_phy_igp_3)
fp@2587: 			return 0;
fp@2587: 
fp@2587: 		/* Call gig speed drop workaround on LPLU before accessing
fp@2587: 		 * any PHY registers
fp@2587: 		 */
fp@2587: 		if (hw->mac.type == e1000_ich8lan)
fp@2587: 			e1000e_gig_downshift_workaround_ich8lan(hw);
fp@2587: 
fp@2587: 		/* When LPLU is enabled, we should disable SmartSpeed */
fp@2587: 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2587: 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @bank:  pointer to the variable that returns the active bank
fp@2587:  *
fp@2587:  *  Reads signature byte from the NVM using the flash access registers.
fp@2587:  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
fp@2587:  **/
fp@2587: static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
fp@2587: {
fp@2587: 	u32 eecd;
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
fp@2587: 	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
fp@2587: 	u8 sig_byte = 0;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_ich8lan:
fp@2587: 	case e1000_ich9lan:
fp@2587: 		eecd = er32(EECD);
fp@2587: 		if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
fp@2587: 		    E1000_EECD_SEC1VAL_VALID_MASK) {
fp@2587: 			if (eecd & E1000_EECD_SEC1VAL)
fp@2587: 				*bank = 1;
fp@2587: 			else
fp@2587: 				*bank = 0;
fp@2587: 
fp@2587: 			return 0;
fp@2587: 		}
fp@2587: 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
fp@2587: 		/* fall-thru */
fp@2587: 	default:
fp@2587: 		/* set bank to 0 in case flash read fails */
fp@2587: 		*bank = 0;
fp@2587: 
fp@2587: 		/* Check bank 0 */
fp@2587: 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
fp@2587: 							&sig_byte);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
fp@2587: 		    E1000_ICH_NVM_SIG_VALUE) {
fp@2587: 			*bank = 0;
fp@2587: 			return 0;
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Check bank 1 */
fp@2587: 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
fp@2587: 							bank1_offset,
fp@2587: 							&sig_byte);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
fp@2587: 		    E1000_ICH_NVM_SIG_VALUE) {
fp@2587: 			*bank = 1;
fp@2587: 			return 0;
fp@2587: 		}
fp@2587: 
fp@2587: 		e_dbg("ERROR: No valid NVM bank present\n");
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 	}
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The offset (in bytes) of the word(s) to read.
fp@2587:  *  @words: Size of data to read in words
fp@2587:  *  @data: Pointer to the word(s) to read at offset.
fp@2587:  *
fp@2587:  *  Reads a word(s) from the NVM using the flash access registers.
fp@2587:  **/
fp@2587: static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
fp@2587: 				  u16 *data)
fp@2587: {
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u32 act_offset;
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u32 bank = 0;
fp@2587: 	u16 i, word;
fp@2587: 
fp@2587: 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
fp@2587: 	    (words == 0)) {
fp@2587: 		e_dbg("nvm parameter(s) out of bounds\n");
fp@2587: 		ret_val = -E1000_ERR_NVM;
fp@2587: 		goto out;
fp@2587: 	}
fp@2587: 
fp@2587: 	nvm->ops.acquire(hw);
fp@2587: 
fp@2587: 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
fp@2587: 	if (ret_val) {
fp@2587: 		e_dbg("Could not detect valid bank, assuming bank 0\n");
fp@2587: 		bank = 0;
fp@2587: 	}
fp@2587: 
fp@2587: 	act_offset = (bank) ? nvm->flash_bank_size : 0;
fp@2587: 	act_offset += offset;
fp@2587: 
fp@2587: 	ret_val = 0;
fp@2587: 	for (i = 0; i < words; i++) {
fp@2587: 		if (dev_spec->shadow_ram[offset + i].modified) {
fp@2587: 			data[i] = dev_spec->shadow_ram[offset + i].value;
fp@2587: 		} else {
fp@2587: 			ret_val = e1000_read_flash_word_ich8lan(hw,
fp@2587: 								act_offset + i,
fp@2587: 								&word);
fp@2587: 			if (ret_val)
fp@2587: 				break;
fp@2587: 			data[i] = word;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	nvm->ops.release(hw);
fp@2587: 
fp@2587: out:
fp@2587: 	if (ret_val)
fp@2587: 		e_dbg("NVM read error: %d\n", ret_val);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_flash_cycle_init_ich8lan - Initialize flash
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  This function does initial flash setup so that a new read/write/erase cycle
fp@2587:  *  can be started.
fp@2587:  **/
fp@2587: static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	union ich8_hws_flash_status hsfsts;
fp@2587: 	s32 ret_val = -E1000_ERR_NVM;
fp@2587: 
fp@2587: 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 
fp@2587: 	/* Check if the flash descriptor is valid */
fp@2587: 	if (!hsfsts.hsf_status.fldesvalid) {
fp@2587: 		e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Clear FCERR and DAEL in hw status by writing 1 */
fp@2587: 	hsfsts.hsf_status.flcerr = 1;
fp@2587: 	hsfsts.hsf_status.dael = 1;
fp@2587: 
fp@2587: 	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
fp@2587: 
fp@2587: 	/* Either we should have a hardware SPI cycle in progress
fp@2587: 	 * bit to check against, in order to start a new cycle or
fp@2587: 	 * FDONE bit should be changed in the hardware so that it
fp@2587: 	 * is 1 after hardware reset, which can then be used as an
fp@2587: 	 * indication whether a cycle is in progress or has been
fp@2587: 	 * completed.
fp@2587: 	 */
fp@2587: 
fp@2587: 	if (!hsfsts.hsf_status.flcinprog) {
fp@2587: 		/* There is no cycle running at present,
fp@2587: 		 * so we can start a cycle.
fp@2587: 		 * Begin by setting Flash Cycle Done.
fp@2587: 		 */
fp@2587: 		hsfsts.hsf_status.flcdone = 1;
fp@2587: 		ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
fp@2587: 		ret_val = 0;
fp@2587: 	} else {
fp@2587: 		s32 i;
fp@2587: 
fp@2587: 		/* Otherwise poll for sometime so the current
fp@2587: 		 * cycle has a chance to end before giving up.
fp@2587: 		 */
fp@2587: 		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
fp@2587: 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 			if (!hsfsts.hsf_status.flcinprog) {
fp@2587: 				ret_val = 0;
fp@2587: 				break;
fp@2587: 			}
fp@2587: 			udelay(1);
fp@2587: 		}
fp@2587: 		if (!ret_val) {
fp@2587: 			/* Successful in waiting for previous cycle to timeout,
fp@2587: 			 * now set the Flash Cycle Done.
fp@2587: 			 */
fp@2587: 			hsfsts.hsf_status.flcdone = 1;
fp@2587: 			ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
fp@2587: 		} else {
fp@2587: 			e_dbg("Flash controller busy, cannot get access\n");
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @timeout: maximum time to wait for completion
fp@2587:  *
fp@2587:  *  This function starts a flash cycle and waits for its completion.
fp@2587:  **/
fp@2587: static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
fp@2587: {
fp@2587: 	union ich8_hws_flash_ctrl hsflctl;
fp@2587: 	union ich8_hws_flash_status hsfsts;
fp@2587: 	u32 i = 0;
fp@2587: 
fp@2587: 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
fp@2587: 	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
fp@2587: 	hsflctl.hsf_ctrl.flcgo = 1;
fp@2587: 	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
fp@2587: 
fp@2587: 	/* wait till FDONE bit is set to 1 */
fp@2587: 	do {
fp@2587: 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 		if (hsfsts.hsf_status.flcdone)
fp@2587: 			break;
fp@2587: 		udelay(1);
fp@2587: 	} while (i++ < timeout);
fp@2587: 
fp@2587: 	if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	return -E1000_ERR_NVM;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_read_flash_word_ich8lan - Read word from flash
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: offset to data location
fp@2587:  *  @data: pointer to the location for storing the data
fp@2587:  *
fp@2587:  *  Reads the flash word at offset into data.  Offset is converted
fp@2587:  *  to bytes before read.
fp@2587:  **/
fp@2587: static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					 u16 *data)
fp@2587: {
fp@2587: 	/* Must convert offset into bytes. */
fp@2587: 	offset <<= 1;
fp@2587: 
fp@2587: 	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_read_flash_byte_ich8lan - Read byte from flash
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The offset of the byte to read.
fp@2587:  *  @data: Pointer to a byte to store the value read.
fp@2587:  *
fp@2587:  *  Reads a single byte from the NVM using the flash access registers.
fp@2587:  **/
fp@2587: static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					 u8 *data)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u16 word = 0;
fp@2587: 
fp@2587: 	ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	*data = (u8)word;
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The offset (in bytes) of the byte or word to read.
fp@2587:  *  @size: Size of data to read, 1=byte 2=word
fp@2587:  *  @data: Pointer to the word to store the value read.
fp@2587:  *
fp@2587:  *  Reads a byte or word from the NVM using the flash access registers.
fp@2587:  **/
fp@2587: static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					 u8 size, u16 *data)
fp@2587: {
fp@2587: 	union ich8_hws_flash_status hsfsts;
fp@2587: 	union ich8_hws_flash_ctrl hsflctl;
fp@2587: 	u32 flash_linear_addr;
fp@2587: 	u32 flash_data = 0;
fp@2587: 	s32 ret_val = -E1000_ERR_NVM;
fp@2587: 	u8 count = 0;
fp@2587: 
fp@2587: 	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 
fp@2587: 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
fp@2587: 			     hw->nvm.flash_base_addr);
fp@2587: 
fp@2587: 	do {
fp@2587: 		udelay(1);
fp@2587: 		/* Steps */
fp@2587: 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			break;
fp@2587: 
fp@2587: 		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
fp@2587: 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
fp@2587: 		hsflctl.hsf_ctrl.fldbcount = size - 1;
fp@2587: 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
fp@2587: 		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
fp@2587: 
fp@2587: 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
fp@2587: 
fp@2587: 		ret_val =
fp@2587: 		    e1000_flash_cycle_ich8lan(hw,
fp@2587: 					      ICH_FLASH_READ_COMMAND_TIMEOUT);
fp@2587: 
fp@2587: 		/* Check if FCERR is set to 1, if set to 1, clear it
fp@2587: 		 * and try the whole sequence a few more times, else
fp@2587: 		 * read in (shift in) the Flash Data0, the order is
fp@2587: 		 * least significant byte first msb to lsb
fp@2587: 		 */
fp@2587: 		if (!ret_val) {
fp@2587: 			flash_data = er32flash(ICH_FLASH_FDATA0);
fp@2587: 			if (size == 1)
fp@2587: 				*data = (u8)(flash_data & 0x000000FF);
fp@2587: 			else if (size == 2)
fp@2587: 				*data = (u16)(flash_data & 0x0000FFFF);
fp@2587: 			break;
fp@2587: 		} else {
fp@2587: 			/* If we've gotten here, then things are probably
fp@2587: 			 * completely hosed, but if the error condition is
fp@2587: 			 * detected, it won't hurt to give it another try...
fp@2587: 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
fp@2587: 			 */
fp@2587: 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 			if (hsfsts.hsf_status.flcerr) {
fp@2587: 				/* Repeat for some time before giving up. */
fp@2587: 				continue;
fp@2587: 			} else if (!hsfsts.hsf_status.flcdone) {
fp@2587: 				e_dbg("Timeout error - flash cycle did not complete.\n");
fp@2587: 				break;
fp@2587: 			}
fp@2587: 		}
fp@2587: 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The offset (in bytes) of the word(s) to write.
fp@2587:  *  @words: Size of data to write in words
fp@2587:  *  @data: Pointer to the word(s) to write at offset.
fp@2587:  *
fp@2587:  *  Writes a byte or word to the NVM using the flash access registers.
fp@2587:  **/
fp@2587: static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
fp@2587: 				   u16 *data)
fp@2587: {
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u16 i;
fp@2587: 
fp@2587: 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
fp@2587: 	    (words == 0)) {
fp@2587: 		e_dbg("nvm parameter(s) out of bounds\n");
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 	}
fp@2587: 
fp@2587: 	nvm->ops.acquire(hw);
fp@2587: 
fp@2587: 	for (i = 0; i < words; i++) {
fp@2587: 		dev_spec->shadow_ram[offset + i].modified = true;
fp@2587: 		dev_spec->shadow_ram[offset + i].value = data[i];
fp@2587: 	}
fp@2587: 
fp@2587: 	nvm->ops.release(hw);
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
fp@2587:  *  which writes the checksum to the shadow ram.  The changes in the shadow
fp@2587:  *  ram are then committed to the EEPROM by processing each bank at a time
fp@2587:  *  checking for the modified bit and writing only the pending changes.
fp@2587:  *  After a successful commit, the shadow ram is cleared and is ready for
fp@2587:  *  future writes.
fp@2587:  **/
fp@2587: static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 data;
fp@2587: 
fp@2587: 	ret_val = e1000e_update_nvm_checksum_generic(hw);
fp@2587: 	if (ret_val)
fp@2587: 		goto out;
fp@2587: 
fp@2587: 	if (nvm->type != e1000_nvm_flash_sw)
fp@2587: 		goto out;
fp@2587: 
fp@2587: 	nvm->ops.acquire(hw);
fp@2587: 
fp@2587: 	/* We're writing to the opposite bank so if we're on bank 1,
fp@2587: 	 * write to bank 0 etc.  We also need to erase the segment that
fp@2587: 	 * is going to be written
fp@2587: 	 */
fp@2587: 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
fp@2587: 	if (ret_val) {
fp@2587: 		e_dbg("Could not detect valid bank, assuming bank 0\n");
fp@2587: 		bank = 0;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (bank == 0) {
fp@2587: 		new_bank_offset = nvm->flash_bank_size;
fp@2587: 		old_bank_offset = 0;
fp@2587: 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 	} else {
fp@2587: 		old_bank_offset = nvm->flash_bank_size;
fp@2587: 		new_bank_offset = 0;
fp@2587: 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 	}
fp@2587: 
fp@2587: 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
fp@2587: 		/* Determine whether to write the value stored
fp@2587: 		 * in the other NVM bank or a modified value stored
fp@2587: 		 * in the shadow RAM
fp@2587: 		 */
fp@2587: 		if (dev_spec->shadow_ram[i].modified) {
fp@2587: 			data = dev_spec->shadow_ram[i].value;
fp@2587: 		} else {
fp@2587: 			ret_val = e1000_read_flash_word_ich8lan(hw, i +
fp@2587: 								old_bank_offset,
fp@2587: 								&data);
fp@2587: 			if (ret_val)
fp@2587: 				break;
fp@2587: 		}
fp@2587: 
fp@2587: 		/* If the word is 0x13, then make sure the signature bits
fp@2587: 		 * (15:14) are 11b until the commit has completed.
fp@2587: 		 * This will allow us to write 10b which indicates the
fp@2587: 		 * signature is valid.  We want to do this after the write
fp@2587: 		 * has completed so that we don't mark the segment valid
fp@2587: 		 * while the write is still in progress
fp@2587: 		 */
fp@2587: 		if (i == E1000_ICH_NVM_SIG_WORD)
fp@2587: 			data |= E1000_ICH_NVM_SIG_MASK;
fp@2587: 
fp@2587: 		/* Convert offset to bytes. */
fp@2587: 		act_offset = (i + new_bank_offset) << 1;
fp@2587: 
fp@2587: 		usleep_range(100, 200);
fp@2587: 		/* Write the bytes to the new bank. */
fp@2587: 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
fp@2587: 							       act_offset,
fp@2587: 							       (u8)data);
fp@2587: 		if (ret_val)
fp@2587: 			break;
fp@2587: 
fp@2587: 		usleep_range(100, 200);
fp@2587: 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
fp@2587: 							       act_offset + 1,
fp@2587: 							       (u8)(data >> 8));
fp@2587: 		if (ret_val)
fp@2587: 			break;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Don't bother writing the segment valid bits if sector
fp@2587: 	 * programming failed.
fp@2587: 	 */
fp@2587: 	if (ret_val) {
fp@2587: 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
fp@2587: 		e_dbg("Flash commit failed.\n");
fp@2587: 		goto release;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Finally validate the new segment by setting bit 15:14
fp@2587: 	 * to 10b in word 0x13 , this can be done without an
fp@2587: 	 * erase as well since these bits are 11 to start with
fp@2587: 	 * and we need to change bit 14 to 0b
fp@2587: 	 */
fp@2587: 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
fp@2587: 	ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	data &= 0xBFFF;
fp@2587: 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
fp@2587: 						       act_offset * 2 + 1,
fp@2587: 						       (u8)(data >> 8));
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	/* And invalidate the previously valid segment by setting
fp@2587: 	 * its signature word (0x13) high_byte to 0b. This can be
fp@2587: 	 * done without an erase because flash erase sets all bits
fp@2587: 	 * to 1's. We can write 1's to 0's without an erase
fp@2587: 	 */
fp@2587: 	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
fp@2587: 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
fp@2587: 	if (ret_val)
fp@2587: 		goto release;
fp@2587: 
fp@2587: 	/* Great!  Everything worked, we can now clear the cached entries. */
fp@2587: 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
fp@2587: 		dev_spec->shadow_ram[i].modified = false;
fp@2587: 		dev_spec->shadow_ram[i].value = 0xFFFF;
fp@2587: 	}
fp@2587: 
fp@2587: release:
fp@2587: 	nvm->ops.release(hw);
fp@2587: 
fp@2587: 	/* Reload the EEPROM, or else modifications will not appear
fp@2587: 	 * until after the next adapter reset.
fp@2587: 	 */
fp@2587: 	if (!ret_val) {
fp@2587: 		nvm->ops.reload(hw);
fp@2587: 		usleep_range(10000, 20000);
fp@2587: 	}
fp@2587: 
fp@2587: out:
fp@2587: 	if (ret_val)
fp@2587: 		e_dbg("NVM update error: %d\n", ret_val);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
fp@2587:  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
fp@2587:  *  calculated, in which case we need to calculate the checksum and set bit 6.
fp@2587:  **/
fp@2587: static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u16 data;
fp@2587: 	u16 word;
fp@2587: 	u16 valid_csum_mask;
fp@2587: 
fp@2587: 	/* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
fp@2587: 	 * the checksum needs to be fixed.  This bit is an indication that
fp@2587: 	 * the NVM was prepared by OEM software and did not calculate
fp@2587: 	 * the checksum...a likely scenario.
fp@2587: 	 */
fp@2587: 	switch (hw->mac.type) {
fp@2587: 	case e1000_pch_lpt:
fp@2587: 		word = NVM_COMPAT;
fp@2587: 		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		word = NVM_FUTURE_INIT_WORD1;
fp@2587: 		valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	ret_val = e1000_read_nvm(hw, word, 1, &data);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if (!(data & valid_csum_mask)) {
fp@2587: 		data |= valid_csum_mask;
fp@2587: 		ret_val = e1000_write_nvm(hw, word, 1, &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		ret_val = e1000e_update_nvm_checksum(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	return e1000e_validate_nvm_checksum_generic(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  To prevent malicious write/erase of the NVM, set it to be read-only
fp@2587:  *  so that the hardware ignores all write/erase cycles of the NVM via
fp@2587:  *  the flash control registers.  The shadow-ram copy of the NVM will
fp@2587:  *  still be updated, however any updates to this copy will not stick
fp@2587:  *  across driver reloads.
fp@2587:  **/
fp@2587: void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	union ich8_flash_protected_range pr0;
fp@2587: 	union ich8_hws_flash_status hsfsts;
fp@2587: 	u32 gfpreg;
fp@2587: 
fp@2587: 	nvm->ops.acquire(hw);
fp@2587: 
fp@2587: 	gfpreg = er32flash(ICH_FLASH_GFPREG);
fp@2587: 
fp@2587: 	/* Write-protect GbE Sector of NVM */
fp@2587: 	pr0.regval = er32flash(ICH_FLASH_PR0);
fp@2587: 	pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
fp@2587: 	pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
fp@2587: 	pr0.range.wpe = true;
fp@2587: 	ew32flash(ICH_FLASH_PR0, pr0.regval);
fp@2587: 
fp@2587: 	/* Lock down a subset of GbE Flash Control Registers, e.g.
fp@2587: 	 * PR0 to prevent the write-protection from being lifted.
fp@2587: 	 * Once FLOCKDN is set, the registers protected by it cannot
fp@2587: 	 * be written until FLOCKDN is cleared by a hardware reset.
fp@2587: 	 */
fp@2587: 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 	hsfsts.hsf_status.flockdn = true;
fp@2587: 	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
fp@2587: 
fp@2587: 	nvm->ops.release(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The offset (in bytes) of the byte/word to read.
fp@2587:  *  @size: Size of data to read, 1=byte 2=word
fp@2587:  *  @data: The byte(s) to write to the NVM.
fp@2587:  *
fp@2587:  *  Writes one/two bytes to the NVM using the flash access registers.
fp@2587:  **/
fp@2587: static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					  u8 size, u16 data)
fp@2587: {
fp@2587: 	union ich8_hws_flash_status hsfsts;
fp@2587: 	union ich8_hws_flash_ctrl hsflctl;
fp@2587: 	u32 flash_linear_addr;
fp@2587: 	u32 flash_data = 0;
fp@2587: 	s32 ret_val;
fp@2587: 	u8 count = 0;
fp@2587: 
fp@2587: 	if (size < 1 || size > 2 || data > size * 0xff ||
fp@2587: 	    offset > ICH_FLASH_LINEAR_ADDR_MASK)
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 
fp@2587: 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
fp@2587: 			     hw->nvm.flash_base_addr);
fp@2587: 
fp@2587: 	do {
fp@2587: 		udelay(1);
fp@2587: 		/* Steps */
fp@2587: 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			break;
fp@2587: 
fp@2587: 		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
fp@2587: 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
fp@2587: 		hsflctl.hsf_ctrl.fldbcount = size - 1;
fp@2587: 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
fp@2587: 		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
fp@2587: 
fp@2587: 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
fp@2587: 
fp@2587: 		if (size == 1)
fp@2587: 			flash_data = (u32)data & 0x00FF;
fp@2587: 		else
fp@2587: 			flash_data = (u32)data;
fp@2587: 
fp@2587: 		ew32flash(ICH_FLASH_FDATA0, flash_data);
fp@2587: 
fp@2587: 		/* check if FCERR is set to 1 , if set to 1, clear it
fp@2587: 		 * and try the whole sequence a few more times else done
fp@2587: 		 */
fp@2587: 		ret_val =
fp@2587: 		    e1000_flash_cycle_ich8lan(hw,
fp@2587: 					      ICH_FLASH_WRITE_COMMAND_TIMEOUT);
fp@2587: 		if (!ret_val)
fp@2587: 			break;
fp@2587: 
fp@2587: 		/* If we're here, then things are most likely
fp@2587: 		 * completely hosed, but if the error condition
fp@2587: 		 * is detected, it won't hurt to give it another
fp@2587: 		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
fp@2587: 		 */
fp@2587: 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 		if (hsfsts.hsf_status.flcerr)
fp@2587: 			/* Repeat for some time before giving up. */
fp@2587: 			continue;
fp@2587: 		if (!hsfsts.hsf_status.flcdone) {
fp@2587: 			e_dbg("Timeout error - flash cycle did not complete.\n");
fp@2587: 			break;
fp@2587: 		}
fp@2587: 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The index of the byte to read.
fp@2587:  *  @data: The byte to write to the NVM.
fp@2587:  *
fp@2587:  *  Writes a single byte to the NVM using the flash access registers.
fp@2587:  **/
fp@2587: static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
fp@2587: 					  u8 data)
fp@2587: {
fp@2587: 	u16 word = (u16)data;
fp@2587: 
fp@2587: 	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @offset: The offset of the byte to write.
fp@2587:  *  @byte: The byte to write to the NVM.
fp@2587:  *
fp@2587:  *  Writes a single byte to the NVM using the flash access registers.
fp@2587:  *  Goes through a retry algorithm before giving up.
fp@2587:  **/
fp@2587: static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
fp@2587: 						u32 offset, u8 byte)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u16 program_retries;
fp@2587: 
fp@2587: 	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
fp@2587: 	if (!ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	for (program_retries = 0; program_retries < 100; program_retries++) {
fp@2587: 		e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
fp@2587: 		usleep_range(100, 200);
fp@2587: 		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
fp@2587: 		if (!ret_val)
fp@2587: 			break;
fp@2587: 	}
fp@2587: 	if (program_retries == 100)
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @bank: 0 for first bank, 1 for second bank, etc.
fp@2587:  *
fp@2587:  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
fp@2587:  *  bank N is 4096 * N + flash_reg_addr.
fp@2587:  **/
fp@2587: static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
fp@2587: {
fp@2587: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2587: 	union ich8_hws_flash_status hsfsts;
fp@2587: 	union ich8_hws_flash_ctrl hsflctl;
fp@2587: 	u32 flash_linear_addr;
fp@2587: 	/* bank size is in 16bit words - adjust to bytes */
fp@2587: 	u32 flash_bank_size = nvm->flash_bank_size * 2;
fp@2587: 	s32 ret_val;
fp@2587: 	s32 count = 0;
fp@2587: 	s32 j, iteration, sector_size;
fp@2587: 
fp@2587: 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 
fp@2587: 	/* Determine HW Sector size: Read BERASE bits of hw flash status
fp@2587: 	 * register
fp@2587: 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16
fp@2587: 	 *     consecutive sectors.  The start index for the nth Hw sector
fp@2587: 	 *     can be calculated as = bank * 4096 + n * 256
fp@2587: 	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
fp@2587: 	 *     The start index for the nth Hw sector can be calculated
fp@2587: 	 *     as = bank * 4096
fp@2587: 	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
fp@2587: 	 *     (ich9 only, otherwise error condition)
fp@2587: 	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
fp@2587: 	 */
fp@2587: 	switch (hsfsts.hsf_status.berasesz) {
fp@2587: 	case 0:
fp@2587: 		/* Hw sector size 256 */
fp@2587: 		sector_size = ICH_FLASH_SEG_SIZE_256;
fp@2587: 		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
fp@2587: 		break;
fp@2587: 	case 1:
fp@2587: 		sector_size = ICH_FLASH_SEG_SIZE_4K;
fp@2587: 		iteration = 1;
fp@2587: 		break;
fp@2587: 	case 2:
fp@2587: 		sector_size = ICH_FLASH_SEG_SIZE_8K;
fp@2587: 		iteration = 1;
fp@2587: 		break;
fp@2587: 	case 3:
fp@2587: 		sector_size = ICH_FLASH_SEG_SIZE_64K;
fp@2587: 		iteration = 1;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		return -E1000_ERR_NVM;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Start with the base address, then add the sector offset. */
fp@2587: 	flash_linear_addr = hw->nvm.flash_base_addr;
fp@2587: 	flash_linear_addr += (bank) ? flash_bank_size : 0;
fp@2587: 
fp@2587: 	for (j = 0; j < iteration; j++) {
fp@2587: 		do {
fp@2587: 			u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
fp@2587: 
fp@2587: 			/* Steps */
fp@2587: 			ret_val = e1000_flash_cycle_init_ich8lan(hw);
fp@2587: 			if (ret_val)
fp@2587: 				return ret_val;
fp@2587: 
fp@2587: 			/* Write a value 11 (block Erase) in Flash
fp@2587: 			 * Cycle field in hw flash control
fp@2587: 			 */
fp@2587: 			hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
fp@2587: 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
fp@2587: 			ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
fp@2587: 
fp@2587: 			/* Write the last 24 bits of an index within the
fp@2587: 			 * block into Flash Linear address field in Flash
fp@2587: 			 * Address.
fp@2587: 			 */
fp@2587: 			flash_linear_addr += (j * sector_size);
fp@2587: 			ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
fp@2587: 
fp@2587: 			ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
fp@2587: 			if (!ret_val)
fp@2587: 				break;
fp@2587: 
fp@2587: 			/* Check if FCERR is set to 1.  If 1,
fp@2587: 			 * clear it and try the whole sequence
fp@2587: 			 * a few more times else Done
fp@2587: 			 */
fp@2587: 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
fp@2587: 			if (hsfsts.hsf_status.flcerr)
fp@2587: 				/* repeat for some time before giving up */
fp@2587: 				continue;
fp@2587: 			else if (!hsfsts.hsf_status.flcdone)
fp@2587: 				return ret_val;
fp@2587: 		} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
fp@2587: 	}
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_valid_led_default_ich8lan - Set the default LED settings
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @data: Pointer to the LED settings
fp@2587:  *
fp@2587:  *  Reads the LED default settings from the NVM to data.  If the NVM LED
fp@2587:  *  settings is all 0's or F's, set the LED default to a valid LED default
fp@2587:  *  setting.
fp@2587:  **/
fp@2587: static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
fp@2587: 	if (ret_val) {
fp@2587: 		e_dbg("NVM Read Error\n");
fp@2587: 		return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
fp@2587: 		*data = ID_LED_DEFAULT_ICH8LAN;
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_id_led_init_pchlan - store LED configurations
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  PCH does not control LEDs via the LEDCTL register, rather it uses
fp@2587:  *  the PHY LED configuration register.
fp@2587:  *
fp@2587:  *  PCH also does not have an "always on" or "always off" mode which
fp@2587:  *  complicates the ID feature.  Instead of using the "on" mode to indicate
fp@2587:  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
fp@2587:  *  use "link_up" mode.  The LEDs will still ID on request if there is no
fp@2587:  *  link based on logic in e1000_led_[on|off]_pchlan().
fp@2587:  **/
fp@2587: static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_mac_info *mac = &hw->mac;
fp@2587: 	s32 ret_val;
fp@2587: 	const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
fp@2587: 	const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
fp@2587: 	u16 data, i, temp, shift;
fp@2587: 
fp@2587: 	/* Get default ID LED modes */
fp@2587: 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	mac->ledctl_default = er32(LEDCTL);
fp@2587: 	mac->ledctl_mode1 = mac->ledctl_default;
fp@2587: 	mac->ledctl_mode2 = mac->ledctl_default;
fp@2587: 
fp@2587: 	for (i = 0; i < 4; i++) {
fp@2587: 		temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
fp@2587: 		shift = (i * 5);
fp@2587: 		switch (temp) {
fp@2587: 		case ID_LED_ON1_DEF2:
fp@2587: 		case ID_LED_ON1_ON2:
fp@2587: 		case ID_LED_ON1_OFF2:
fp@2587: 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
fp@2587: 			mac->ledctl_mode1 |= (ledctl_on << shift);
fp@2587: 			break;
fp@2587: 		case ID_LED_OFF1_DEF2:
fp@2587: 		case ID_LED_OFF1_ON2:
fp@2587: 		case ID_LED_OFF1_OFF2:
fp@2587: 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
fp@2587: 			mac->ledctl_mode1 |= (ledctl_off << shift);
fp@2587: 			break;
fp@2587: 		default:
fp@2587: 			/* Do nothing */
fp@2587: 			break;
fp@2587: 		}
fp@2587: 		switch (temp) {
fp@2587: 		case ID_LED_DEF1_ON2:
fp@2587: 		case ID_LED_ON1_ON2:
fp@2587: 		case ID_LED_OFF1_ON2:
fp@2587: 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
fp@2587: 			mac->ledctl_mode2 |= (ledctl_on << shift);
fp@2587: 			break;
fp@2587: 		case ID_LED_DEF1_OFF2:
fp@2587: 		case ID_LED_ON1_OFF2:
fp@2587: 		case ID_LED_OFF1_OFF2:
fp@2587: 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
fp@2587: 			mac->ledctl_mode2 |= (ledctl_off << shift);
fp@2587: 			break;
fp@2587: 		default:
fp@2587: 			/* Do nothing */
fp@2587: 			break;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
fp@2587:  *  register, so the the bus width is hard coded.
fp@2587:  **/
fp@2587: static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_bus_info *bus = &hw->bus;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	ret_val = e1000e_get_bus_info_pcie(hw);
fp@2587: 
fp@2587: 	/* ICH devices are "PCI Express"-ish.  They have
fp@2587: 	 * a configuration space, but do not contain
fp@2587: 	 * PCI Express Capability registers, so bus width
fp@2587: 	 * must be hardcoded.
fp@2587: 	 */
fp@2587: 	if (bus->width == e1000_bus_width_unknown)
fp@2587: 		bus->width = e1000_bus_width_pcie_x1;
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_reset_hw_ich8lan - Reset the hardware
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Does a full reset of the hardware which includes a reset of the PHY and
fp@2587:  *  MAC.
fp@2587:  **/
fp@2587: static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u16 kum_cfg;
fp@2587: 	u32 ctrl, reg;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
fp@2587: 	 * on the last TLP read/write transaction when MAC is reset.
fp@2587: 	 */
fp@2587: 	ret_val = e1000e_disable_pcie_master(hw);
fp@2587: 	if (ret_val)
fp@2587: 		e_dbg("PCI-E Master disable polling has failed.\n");
fp@2587: 
fp@2587: 	e_dbg("Masking off all interrupts\n");
fp@2587: 	ew32(IMC, 0xffffffff);
fp@2587: 
fp@2587: 	/* Disable the Transmit and Receive units.  Then delay to allow
fp@2587: 	 * any pending transactions to complete before we hit the MAC
fp@2587: 	 * with the global reset.
fp@2587: 	 */
fp@2587: 	ew32(RCTL, 0);
fp@2587: 	ew32(TCTL, E1000_TCTL_PSP);
fp@2587: 	e1e_flush();
fp@2587: 
fp@2587: 	usleep_range(10000, 20000);
fp@2587: 
fp@2587: 	/* Workaround for ICH8 bit corruption issue in FIFO memory */
fp@2587: 	if (hw->mac.type == e1000_ich8lan) {
fp@2587: 		/* Set Tx and Rx buffer allocation to 8k apiece. */
fp@2587: 		ew32(PBA, E1000_PBA_8K);
fp@2587: 		/* Set Packet Buffer Size to 16k. */
fp@2587: 		ew32(PBS, E1000_PBS_16K);
fp@2587: 	}
fp@2587: 
fp@2587: 	if (hw->mac.type == e1000_pchlan) {
fp@2587: 		/* Save the NVM K1 bit setting */
fp@2587: 		ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		if (kum_cfg & E1000_NVM_K1_ENABLE)
fp@2587: 			dev_spec->nvm_k1_enabled = true;
fp@2587: 		else
fp@2587: 			dev_spec->nvm_k1_enabled = false;
fp@2587: 	}
fp@2587: 
fp@2587: 	ctrl = er32(CTRL);
fp@2587: 
fp@2587: 	if (!hw->phy.ops.check_reset_block(hw)) {
fp@2587: 		/* Full-chip reset requires MAC and PHY reset at the same
fp@2587: 		 * time to make sure the interface between MAC and the
fp@2587: 		 * external PHY is reset.
fp@2587: 		 */
fp@2587: 		ctrl |= E1000_CTRL_PHY_RST;
fp@2587: 
fp@2587: 		/* Gate automatic PHY configuration by hardware on
fp@2587: 		 * non-managed 82579
fp@2587: 		 */
fp@2587: 		if ((hw->mac.type == e1000_pch2lan) &&
fp@2587: 		    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
fp@2587: 			e1000_gate_hw_phy_config_ich8lan(hw, true);
fp@2587: 	}
fp@2587: 	ret_val = e1000_acquire_swflag_ich8lan(hw);
fp@2587: 	e_dbg("Issuing a global reset to ich8lan\n");
fp@2587: 	ew32(CTRL, (ctrl | E1000_CTRL_RST));
fp@2587: 	/* cannot issue a flush here because it hangs the hardware */
fp@2587: 	msleep(20);
fp@2587: 
fp@2587: 	/* Set Phy Config Counter to 50msec */
fp@2587: 	if (hw->mac.type == e1000_pch2lan) {
fp@2587: 		reg = er32(FEXTNVM3);
fp@2587: 		reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
fp@2587: 		reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
fp@2587: 		ew32(FEXTNVM3, reg);
fp@2587: 	}
fp@2587: 
fp@2587: 	if (!ret_val)
fp@2587: 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
fp@2587: 
fp@2587: 	if (ctrl & E1000_CTRL_PHY_RST) {
fp@2587: 		ret_val = hw->phy.ops.get_cfg_done(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		ret_val = e1000_post_phy_reset_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* For PCH, this write will make sure that any noise
fp@2587: 	 * will be detected as a CRC error and be dropped rather than show up
fp@2587: 	 * as a bad packet to the DMA engine.
fp@2587: 	 */
fp@2587: 	if (hw->mac.type == e1000_pchlan)
fp@2587: 		ew32(CRC_OFFSET, 0x65656565);
fp@2587: 
fp@2587: 	ew32(IMC, 0xffffffff);
fp@2587: 	er32(ICR);
fp@2587: 
fp@2587: 	reg = er32(KABGTXD);
fp@2587: 	reg |= E1000_KABGTXD_BGSQLBIAS;
fp@2587: 	ew32(KABGTXD, reg);
fp@2587: 
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_init_hw_ich8lan - Initialize the hardware
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Prepares the hardware for transmit and receive by doing the following:
fp@2587:  *   - initialize hardware bits
fp@2587:  *   - initialize LED identification
fp@2587:  *   - setup receive address registers
fp@2587:  *   - setup flow control
fp@2587:  *   - setup transmit descriptors
fp@2587:  *   - clear statistics
fp@2587:  **/
fp@2587: static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_mac_info *mac = &hw->mac;
fp@2587: 	u32 ctrl_ext, txdctl, snoop;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 i;
fp@2587: 
fp@2587: 	e1000_initialize_hw_bits_ich8lan(hw);
fp@2587: 
fp@2587: 	/* Initialize identification LED */
fp@2587: 	ret_val = mac->ops.id_led_init(hw);
fp@2587: 	/* An error is not fatal and we should not stop init due to this */
fp@2587: 	if (ret_val)
fp@2587: 		e_dbg("Error initializing identification LED\n");
fp@2587: 
fp@2587: 	/* Setup the receive address. */
fp@2587: 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
fp@2587: 
fp@2587: 	/* Zero out the Multicast HASH table */
fp@2587: 	e_dbg("Zeroing the MTA\n");
fp@2587: 	for (i = 0; i < mac->mta_reg_count; i++)
fp@2587: 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
fp@2587: 
fp@2587: 	/* The 82578 Rx buffer will stall if wakeup is enabled in host and
fp@2587: 	 * the ME.  Disable wakeup by clearing the host wakeup bit.
fp@2587: 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
fp@2587: 	 */
fp@2587: 	if (hw->phy.type == e1000_phy_82578) {
fp@2587: 		e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
fp@2587: 		i &= ~BM_WUC_HOST_WU_BIT;
fp@2587: 		e1e_wphy(hw, BM_PORT_GEN_CFG, i);
fp@2587: 		ret_val = e1000_phy_hw_reset_ich8lan(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Setup link and flow control */
fp@2587: 	ret_val = mac->ops.setup_link(hw);
fp@2587: 
fp@2587: 	/* Set the transmit descriptor write-back policy for both queues */
fp@2587: 	txdctl = er32(TXDCTL(0));
fp@2587: 	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
fp@2587: 		  E1000_TXDCTL_FULL_TX_DESC_WB);
fp@2587: 	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
fp@2587: 		  E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
fp@2587: 	ew32(TXDCTL(0), txdctl);
fp@2587: 	txdctl = er32(TXDCTL(1));
fp@2587: 	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
fp@2587: 		  E1000_TXDCTL_FULL_TX_DESC_WB);
fp@2587: 	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
fp@2587: 		  E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
fp@2587: 	ew32(TXDCTL(1), txdctl);
fp@2587: 
fp@2587: 	/* ICH8 has opposite polarity of no_snoop bits.
fp@2587: 	 * By default, we should use snoop behavior.
fp@2587: 	 */
fp@2587: 	if (mac->type == e1000_ich8lan)
fp@2587: 		snoop = PCIE_ICH8_SNOOP_ALL;
fp@2587: 	else
fp@2587: 		snoop = (u32)~(PCIE_NO_SNOOP_ALL);
fp@2587: 	e1000e_set_pcie_no_snoop(hw, snoop);
fp@2587: 
fp@2587: 	ctrl_ext = er32(CTRL_EXT);
fp@2587: 	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
fp@2587: 	ew32(CTRL_EXT, ctrl_ext);
fp@2587: 
fp@2587: 	/* Clear all of the statistics registers (clear on read).  It is
fp@2587: 	 * important that we do this after we have tried to establish link
fp@2587: 	 * because the symbol error count will increment wildly if there
fp@2587: 	 * is no link.
fp@2587: 	 */
fp@2587: 	e1000_clear_hw_cntrs_ich8lan(hw);
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Sets/Clears required hardware bits necessary for correctly setting up the
fp@2587:  *  hardware for transmit and receive.
fp@2587:  **/
fp@2587: static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 reg;
fp@2587: 
fp@2587: 	/* Extended Device Control */
fp@2587: 	reg = er32(CTRL_EXT);
fp@2587: 	reg |= (1 << 22);
fp@2587: 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
fp@2587: 	if (hw->mac.type >= e1000_pchlan)
fp@2587: 		reg |= E1000_CTRL_EXT_PHYPDEN;
fp@2587: 	ew32(CTRL_EXT, reg);
fp@2587: 
fp@2587: 	/* Transmit Descriptor Control 0 */
fp@2587: 	reg = er32(TXDCTL(0));
fp@2587: 	reg |= (1 << 22);
fp@2587: 	ew32(TXDCTL(0), reg);
fp@2587: 
fp@2587: 	/* Transmit Descriptor Control 1 */
fp@2587: 	reg = er32(TXDCTL(1));
fp@2587: 	reg |= (1 << 22);
fp@2587: 	ew32(TXDCTL(1), reg);
fp@2587: 
fp@2587: 	/* Transmit Arbitration Control 0 */
fp@2587: 	reg = er32(TARC(0));
fp@2587: 	if (hw->mac.type == e1000_ich8lan)
fp@2587: 		reg |= (1 << 28) | (1 << 29);
fp@2587: 	reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
fp@2587: 	ew32(TARC(0), reg);
fp@2587: 
fp@2587: 	/* Transmit Arbitration Control 1 */
fp@2587: 	reg = er32(TARC(1));
fp@2587: 	if (er32(TCTL) & E1000_TCTL_MULR)
fp@2587: 		reg &= ~(1 << 28);
fp@2587: 	else
fp@2587: 		reg |= (1 << 28);
fp@2587: 	reg |= (1 << 24) | (1 << 26) | (1 << 30);
fp@2587: 	ew32(TARC(1), reg);
fp@2587: 
fp@2587: 	/* Device Status */
fp@2587: 	if (hw->mac.type == e1000_ich8lan) {
fp@2587: 		reg = er32(STATUS);
fp@2587: 		reg &= ~(1 << 31);
fp@2587: 		ew32(STATUS, reg);
fp@2587: 	}
fp@2587: 
fp@2587: 	/* work-around descriptor data corruption issue during nfs v2 udp
fp@2587: 	 * traffic, just disable the nfs filtering capability
fp@2587: 	 */
fp@2587: 	reg = er32(RFCTL);
fp@2587: 	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
fp@2587: 
fp@2587: 	/* Disable IPv6 extension header parsing because some malformed
fp@2587: 	 * IPv6 headers can hang the Rx.
fp@2587: 	 */
fp@2587: 	if (hw->mac.type == e1000_ich8lan)
fp@2587: 		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
fp@2587: 	ew32(RFCTL, reg);
fp@2587: 
fp@2587: 	/* Enable ECC on Lynxpoint */
fp@2587: 	if (hw->mac.type == e1000_pch_lpt) {
fp@2587: 		reg = er32(PBECCSTS);
fp@2587: 		reg |= E1000_PBECCSTS_ECC_ENABLE;
fp@2587: 		ew32(PBECCSTS, reg);
fp@2587: 
fp@2587: 		reg = er32(CTRL);
fp@2587: 		reg |= E1000_CTRL_MEHE;
fp@2587: 		ew32(CTRL, reg);
fp@2587: 	}
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_setup_link_ich8lan - Setup flow control and link settings
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Determines which flow control settings to use, then configures flow
fp@2587:  *  control.  Calls the appropriate media-specific link configuration
fp@2587:  *  function.  Assuming the adapter has a valid link partner, a valid link
fp@2587:  *  should be established.  Assumes the hardware has previously been reset
fp@2587:  *  and the transmitter and receiver are not enabled.
fp@2587:  **/
fp@2587: static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	if (hw->phy.ops.check_reset_block(hw))
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* ICH parts do not have a word in the NVM to determine
fp@2587: 	 * the default flow control setting, so we explicitly
fp@2587: 	 * set it to full.
fp@2587: 	 */
fp@2587: 	if (hw->fc.requested_mode == e1000_fc_default) {
fp@2587: 		/* Workaround h/w hang when Tx flow control enabled */
fp@2587: 		if (hw->mac.type == e1000_pchlan)
fp@2587: 			hw->fc.requested_mode = e1000_fc_rx_pause;
fp@2587: 		else
fp@2587: 			hw->fc.requested_mode = e1000_fc_full;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Save off the requested flow control mode for use later.  Depending
fp@2587: 	 * on the link partner's capabilities, we may or may not use this mode.
fp@2587: 	 */
fp@2587: 	hw->fc.current_mode = hw->fc.requested_mode;
fp@2587: 
fp@2587: 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
fp@2587: 
fp@2587: 	/* Continue to configure the copper link. */
fp@2587: 	ret_val = hw->mac.ops.setup_physical_interface(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	ew32(FCTTV, hw->fc.pause_time);
fp@2587: 	if ((hw->phy.type == e1000_phy_82578) ||
fp@2587: 	    (hw->phy.type == e1000_phy_82579) ||
fp@2587: 	    (hw->phy.type == e1000_phy_i217) ||
fp@2587: 	    (hw->phy.type == e1000_phy_82577)) {
fp@2587: 		ew32(FCRTV_PCH, hw->fc.refresh_time);
fp@2587: 
fp@2587: 		ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
fp@2587: 				   hw->fc.pause_time);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 	}
fp@2587: 
fp@2587: 	return e1000e_set_fc_watermarks(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Configures the kumeran interface to the PHY to wait the appropriate time
fp@2587:  *  when polling the PHY, then call the generic setup_copper_link to finish
fp@2587:  *  configuring the copper link.
fp@2587:  **/
fp@2587: static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 ctrl;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 reg_data;
fp@2587: 
fp@2587: 	ctrl = er32(CTRL);
fp@2587: 	ctrl |= E1000_CTRL_SLU;
fp@2587: 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
fp@2587: 	ew32(CTRL, ctrl);
fp@2587: 
fp@2587: 	/* Set the mac to wait the maximum time between each iteration
fp@2587: 	 * and increase the max iterations when polling the phy;
fp@2587: 	 * this fixes erroneous timeouts at 10Mbps.
fp@2587: 	 */
fp@2587: 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
fp@2587: 				       &reg_data);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 	reg_data |= 0x3F;
fp@2587: 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
fp@2587: 					reg_data);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	switch (hw->phy.type) {
fp@2587: 	case e1000_phy_igp_3:
fp@2587: 		ret_val = e1000e_copper_link_setup_igp(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		break;
fp@2587: 	case e1000_phy_bm:
fp@2587: 	case e1000_phy_82578:
fp@2587: 		ret_val = e1000e_copper_link_setup_m88(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		break;
fp@2587: 	case e1000_phy_82577:
fp@2587: 	case e1000_phy_82579:
fp@2587: 		ret_val = e1000_copper_link_setup_82577(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		break;
fp@2587: 	case e1000_phy_ife:
fp@2587: 		ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		reg_data &= ~IFE_PMC_AUTO_MDIX;
fp@2587: 
fp@2587: 		switch (hw->phy.mdix) {
fp@2587: 		case 1:
fp@2587: 			reg_data &= ~IFE_PMC_FORCE_MDIX;
fp@2587: 			break;
fp@2587: 		case 2:
fp@2587: 			reg_data |= IFE_PMC_FORCE_MDIX;
fp@2587: 			break;
fp@2587: 		case 0:
fp@2587: 		default:
fp@2587: 			reg_data |= IFE_PMC_AUTO_MDIX;
fp@2587: 			break;
fp@2587: 		}
fp@2587: 		ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		break;
fp@2587: 	default:
fp@2587: 		break;
fp@2587: 	}
fp@2587: 
fp@2587: 	return e1000e_setup_copper_link(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Calls the PHY specific link setup function and then calls the
fp@2587:  *  generic setup_copper_link to finish configuring the link for
fp@2587:  *  Lynxpoint PCH devices
fp@2587:  **/
fp@2587: static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 ctrl;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	ctrl = er32(CTRL);
fp@2587: 	ctrl |= E1000_CTRL_SLU;
fp@2587: 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
fp@2587: 	ew32(CTRL, ctrl);
fp@2587: 
fp@2587: 	ret_val = e1000_copper_link_setup_82577(hw);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	return e1000e_setup_copper_link(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @speed: pointer to store current link speed
fp@2587:  *  @duplex: pointer to store the current link duplex
fp@2587:  *
fp@2587:  *  Calls the generic get_speed_and_duplex to retrieve the current link
fp@2587:  *  information and then calls the Kumeran lock loss workaround for links at
fp@2587:  *  gigabit speeds.
fp@2587:  **/
fp@2587: static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
fp@2587: 					  u16 *duplex)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
fp@2587: 	if (ret_val)
fp@2587: 		return ret_val;
fp@2587: 
fp@2587: 	if ((hw->mac.type == e1000_ich8lan) &&
fp@2587: 	    (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
fp@2587: 		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Work-around for 82566 Kumeran PCS lock loss:
fp@2587:  *  On link status change (i.e. PCI reset, speed change) and link is up and
fp@2587:  *  speed is gigabit-
fp@2587:  *    0) if workaround is optionally disabled do nothing
fp@2587:  *    1) wait 1ms for Kumeran link to come up
fp@2587:  *    2) check Kumeran Diagnostic register PCS lock loss bit
fp@2587:  *    3) if not set the link is locked (all is good), otherwise...
fp@2587:  *    4) reset the PHY
fp@2587:  *    5) repeat up to 10 times
fp@2587:  *  Note: this is only called for IGP3 copper when speed is 1gb.
fp@2587:  **/
fp@2587: static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u32 phy_ctrl;
fp@2587: 	s32 ret_val;
fp@2587: 	u16 i, data;
fp@2587: 	bool link;
fp@2587: 
fp@2587: 	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	/* Make sure link is up before proceeding.  If not just return.
fp@2587: 	 * Attempting this while link is negotiating fouled up link
fp@2587: 	 * stability
fp@2587: 	 */
fp@2587: 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
fp@2587: 	if (!link)
fp@2587: 		return 0;
fp@2587: 
fp@2587: 	for (i = 0; i < 10; i++) {
fp@2587: 		/* read once to clear */
fp@2587: 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 		/* and again to get new status */
fp@2587: 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
fp@2587: 		if (ret_val)
fp@2587: 			return ret_val;
fp@2587: 
fp@2587: 		/* check for PCS lock */
fp@2587: 		if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
fp@2587: 			return 0;
fp@2587: 
fp@2587: 		/* Issue PHY reset */
fp@2587: 		e1000_phy_hw_reset(hw);
fp@2587: 		mdelay(5);
fp@2587: 	}
fp@2587: 	/* Disable GigE link negotiation */
fp@2587: 	phy_ctrl = er32(PHY_CTRL);
fp@2587: 	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
fp@2587: 		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
fp@2587: 	ew32(PHY_CTRL, phy_ctrl);
fp@2587: 
fp@2587: 	/* Call gig speed drop workaround on Gig disable before accessing
fp@2587: 	 * any PHY registers
fp@2587: 	 */
fp@2587: 	e1000e_gig_downshift_workaround_ich8lan(hw);
fp@2587: 
fp@2587: 	/* unable to acquire PCS lock */
fp@2587: 	return -E1000_ERR_PHY;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *  @state: boolean value used to set the current Kumeran workaround state
fp@2587:  *
fp@2587:  *  If ICH8, set the current Kumeran workaround state (enabled - true
fp@2587:  *  /disabled - false).
fp@2587:  **/
fp@2587: void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
fp@2587: 						  bool state)
fp@2587: {
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 
fp@2587: 	if (hw->mac.type != e1000_ich8lan) {
fp@2587: 		e_dbg("Workaround applies to ICH8 only.\n");
fp@2587: 		return;
fp@2587: 	}
fp@2587: 
fp@2587: 	dev_spec->kmrn_lock_loss_workaround_enabled = state;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Workaround for 82566 power-down on D3 entry:
fp@2587:  *    1) disable gigabit link
fp@2587:  *    2) write VR power-down enable
fp@2587:  *    3) read it back
fp@2587:  *  Continue if successful, else issue LCD reset and repeat
fp@2587:  **/
fp@2587: void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u32 reg;
fp@2587: 	u16 data;
fp@2587: 	u8 retry = 0;
fp@2587: 
fp@2587: 	if (hw->phy.type != e1000_phy_igp_3)
fp@2587: 		return;
fp@2587: 
fp@2587: 	/* Try the workaround twice (if needed) */
fp@2587: 	do {
fp@2587: 		/* Disable link */
fp@2587: 		reg = er32(PHY_CTRL);
fp@2587: 		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
fp@2587: 			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
fp@2587: 		ew32(PHY_CTRL, reg);
fp@2587: 
fp@2587: 		/* Call gig speed drop workaround on Gig disable before
fp@2587: 		 * accessing any PHY registers
fp@2587: 		 */
fp@2587: 		if (hw->mac.type == e1000_ich8lan)
fp@2587: 			e1000e_gig_downshift_workaround_ich8lan(hw);
fp@2587: 
fp@2587: 		/* Write VR power-down enable */
fp@2587: 		e1e_rphy(hw, IGP3_VR_CTRL, &data);
fp@2587: 		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
fp@2587: 		e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
fp@2587: 
fp@2587: 		/* Read it back and test */
fp@2587: 		e1e_rphy(hw, IGP3_VR_CTRL, &data);
fp@2587: 		data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
fp@2587: 		if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
fp@2587: 			break;
fp@2587: 
fp@2587: 		/* Issue PHY reset and repeat at most one more time */
fp@2587: 		reg = er32(CTRL);
fp@2587: 		ew32(CTRL, reg | E1000_CTRL_PHY_RST);
fp@2587: 		retry++;
fp@2587: 	} while (retry);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
fp@2587:  *  LPLU, Gig disable, MDIC PHY reset):
fp@2587:  *    1) Set Kumeran Near-end loopback
fp@2587:  *    2) Clear Kumeran Near-end loopback
fp@2587:  *  Should only be called for ICH8[m] devices with any 1G Phy.
fp@2587:  **/
fp@2587: void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 	u16 reg_data;
fp@2587: 
fp@2587: 	if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
fp@2587: 		return;
fp@2587: 
fp@2587: 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
fp@2587: 				       &reg_data);
fp@2587: 	if (ret_val)
fp@2587: 		return;
fp@2587: 	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
fp@2587: 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
fp@2587: 					reg_data);
fp@2587: 	if (ret_val)
fp@2587: 		return;
fp@2587: 	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
fp@2587: 	e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  During S0 to Sx transition, it is possible the link remains at gig
fp@2587:  *  instead of negotiating to a lower speed.  Before going to Sx, set
fp@2587:  *  'Gig Disable' to force link speed negotiation to a lower speed based on
fp@2587:  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
fp@2587:  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
fp@2587:  *  needs to be written.
fp@2587:  *  Parts that support (and are linked to a partner which support) EEE in
fp@2587:  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
fp@2587:  *  than 10Mbps w/o EEE.
fp@2587:  **/
fp@2587: void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
fp@2587: 	u32 phy_ctrl;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	phy_ctrl = er32(PHY_CTRL);
fp@2587: 	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
fp@2587: 
fp@2587: 	if (hw->phy.type == e1000_phy_i217) {
fp@2587: 		u16 phy_reg, device_id = hw->adapter->pdev->device;
fp@2587: 
fp@2587: 		if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
fp@2587: 		    (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
fp@2587: 		    (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
fp@2587: 		    (device_id == E1000_DEV_ID_PCH_I218_V3)) {
fp@2587: 			u32 fextnvm6 = er32(FEXTNVM6);
fp@2587: 
fp@2587: 			ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
fp@2587: 		}
fp@2587: 
fp@2587: 		ret_val = hw->phy.ops.acquire(hw);
fp@2587: 		if (ret_val)
fp@2587: 			goto out;
fp@2587: 
fp@2587: 		if (!dev_spec->eee_disable) {
fp@2587: 			u16 eee_advert;
fp@2587: 
fp@2587: 			ret_val =
fp@2587: 			    e1000_read_emi_reg_locked(hw,
fp@2587: 						      I217_EEE_ADVERTISEMENT,
fp@2587: 						      &eee_advert);
fp@2587: 			if (ret_val)
fp@2587: 				goto release;
fp@2587: 
fp@2587: 			/* Disable LPLU if both link partners support 100BaseT
fp@2587: 			 * EEE and 100Full is advertised on both ends of the
fp@2587: 			 * link.
fp@2587: 			 */
fp@2587: 			if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
fp@2587: 			    (dev_spec->eee_lp_ability &
fp@2587: 			     I82579_EEE_100_SUPPORTED) &&
fp@2587: 			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
fp@2587: 				phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
fp@2587: 					      E1000_PHY_CTRL_NOND0A_LPLU);
fp@2587: 		}
fp@2587: 
fp@2587: 		/* For i217 Intel Rapid Start Technology support,
fp@2587: 		 * when the system is going into Sx and no manageability engine
fp@2587: 		 * is present, the driver must configure proxy to reset only on
fp@2587: 		 * power good.  LPI (Low Power Idle) state must also reset only
fp@2587: 		 * on power good, as well as the MTA (Multicast table array).
fp@2587: 		 * The SMBus release must also be disabled on LCD reset.
fp@2587: 		 */
fp@2587: 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
fp@2587: 			/* Enable proxy to reset only on power good. */
fp@2587: 			e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
fp@2587: 			phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
fp@2587: 			e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
fp@2587: 
fp@2587: 			/* Set bit enable LPI (EEE) to reset only on
fp@2587: 			 * power good.
fp@2587: 			 */
fp@2587: 			e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
fp@2587: 			phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
fp@2587: 			e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
fp@2587: 
fp@2587: 			/* Disable the SMB release on LCD reset. */
fp@2587: 			e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
fp@2587: 			phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
fp@2587: 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
fp@2587: 		}
fp@2587: 
fp@2587: 		/* Enable MTA to reset for Intel Rapid Start Technology
fp@2587: 		 * Support
fp@2587: 		 */
fp@2587: 		e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
fp@2587: 		phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
fp@2587: 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
fp@2587: 
fp@2587: release:
fp@2587: 		hw->phy.ops.release(hw);
fp@2587: 	}
fp@2587: out:
fp@2587: 	ew32(PHY_CTRL, phy_ctrl);
fp@2587: 
fp@2587: 	if (hw->mac.type == e1000_ich8lan)
fp@2587: 		e1000e_gig_downshift_workaround_ich8lan(hw);
fp@2587: 
fp@2587: 	if (hw->mac.type >= e1000_pchlan) {
fp@2587: 		e1000_oem_bits_config_ich8lan(hw, false);
fp@2587: 
fp@2587: 		/* Reset PHY to activate OEM bits on 82577/8 */
fp@2587: 		if (hw->mac.type == e1000_pchlan)
fp@2587: 			e1000e_phy_hw_reset_generic(hw);
fp@2587: 
fp@2587: 		ret_val = hw->phy.ops.acquire(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return;
fp@2587: 		e1000_write_smbus_addr(hw);
fp@2587: 		hw->phy.ops.release(hw);
fp@2587: 	}
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  During Sx to S0 transitions on non-managed devices or managed devices
fp@2587:  *  on which PHY resets are not blocked, if the PHY registers cannot be
fp@2587:  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
fp@2587:  *  the PHY.
fp@2587:  *  On i217, setup Intel Rapid Start Technology.
fp@2587:  **/
fp@2587: void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	if (hw->mac.type < e1000_pch2lan)
fp@2587: 		return;
fp@2587: 
fp@2587: 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
fp@2587: 	if (ret_val) {
fp@2587: 		e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
fp@2587: 		return;
fp@2587: 	}
fp@2587: 
fp@2587: 	/* For i217 Intel Rapid Start Technology support when the system
fp@2587: 	 * is transitioning from Sx and no manageability engine is present
fp@2587: 	 * configure SMBus to restore on reset, disable proxy, and enable
fp@2587: 	 * the reset on MTA (Multicast table array).
fp@2587: 	 */
fp@2587: 	if (hw->phy.type == e1000_phy_i217) {
fp@2587: 		u16 phy_reg;
fp@2587: 
fp@2587: 		ret_val = hw->phy.ops.acquire(hw);
fp@2587: 		if (ret_val) {
fp@2587: 			e_dbg("Failed to setup iRST\n");
fp@2587: 			return;
fp@2587: 		}
fp@2587: 
fp@2587: 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
fp@2587: 			/* Restore clear on SMB if no manageability engine
fp@2587: 			 * is present
fp@2587: 			 */
fp@2587: 			ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
fp@2587: 			if (ret_val)
fp@2587: 				goto release;
fp@2587: 			phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
fp@2587: 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
fp@2587: 
fp@2587: 			/* Disable Proxy */
fp@2587: 			e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
fp@2587: 		}
fp@2587: 		/* Enable reset on MTA */
fp@2587: 		ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 		phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
fp@2587: 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
fp@2587: release:
fp@2587: 		if (ret_val)
fp@2587: 			e_dbg("Error %d in resume workarounds\n", ret_val);
fp@2587: 		hw->phy.ops.release(hw);
fp@2587: 	}
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Return the LED back to the default configuration.
fp@2587:  **/
fp@2587: static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	if (hw->phy.type == e1000_phy_ife)
fp@2587: 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
fp@2587: 
fp@2587: 	ew32(LEDCTL, hw->mac.ledctl_default);
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_led_on_ich8lan - Turn LEDs on
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Turn on the LEDs.
fp@2587:  **/
fp@2587: static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	if (hw->phy.type == e1000_phy_ife)
fp@2587: 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
fp@2587: 				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
fp@2587: 
fp@2587: 	ew32(LEDCTL, hw->mac.ledctl_mode2);
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_led_off_ich8lan - Turn LEDs off
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Turn off the LEDs.
fp@2587:  **/
fp@2587: static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	if (hw->phy.type == e1000_phy_ife)
fp@2587: 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
fp@2587: 				(IFE_PSCL_PROBE_MODE |
fp@2587: 				 IFE_PSCL_PROBE_LEDS_OFF));
fp@2587: 
fp@2587: 	ew32(LEDCTL, hw->mac.ledctl_mode1);
fp@2587: 	return 0;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_setup_led_pchlan - Configures SW controllable LED
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  This prepares the SW controllable LED for use.
fp@2587:  **/
fp@2587: static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_cleanup_led_pchlan - Restore the default LED operation
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Return the LED back to the default configuration.
fp@2587:  **/
fp@2587: static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_led_on_pchlan - Turn LEDs on
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Turn on the LEDs.
fp@2587:  **/
fp@2587: static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u16 data = (u16)hw->mac.ledctl_mode2;
fp@2587: 	u32 i, led;
fp@2587: 
fp@2587: 	/* If no link, then turn LED on by setting the invert bit
fp@2587: 	 * for each LED that's mode is "link_up" in ledctl_mode2.
fp@2587: 	 */
fp@2587: 	if (!(er32(STATUS) & E1000_STATUS_LU)) {
fp@2587: 		for (i = 0; i < 3; i++) {
fp@2587: 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
fp@2587: 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
fp@2587: 			    E1000_LEDCTL_MODE_LINK_UP)
fp@2587: 				continue;
fp@2587: 			if (led & E1000_PHY_LED0_IVRT)
fp@2587: 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
fp@2587: 			else
fp@2587: 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return e1e_wphy(hw, HV_LED_CONFIG, data);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_led_off_pchlan - Turn LEDs off
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Turn off the LEDs.
fp@2587:  **/
fp@2587: static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u16 data = (u16)hw->mac.ledctl_mode1;
fp@2587: 	u32 i, led;
fp@2587: 
fp@2587: 	/* If no link, then turn LED off by clearing the invert bit
fp@2587: 	 * for each LED that's mode is "link_up" in ledctl_mode1.
fp@2587: 	 */
fp@2587: 	if (!(er32(STATUS) & E1000_STATUS_LU)) {
fp@2587: 		for (i = 0; i < 3; i++) {
fp@2587: 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
fp@2587: 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
fp@2587: 			    E1000_LEDCTL_MODE_LINK_UP)
fp@2587: 				continue;
fp@2587: 			if (led & E1000_PHY_LED0_IVRT)
fp@2587: 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
fp@2587: 			else
fp@2587: 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return e1e_wphy(hw, HV_LED_CONFIG, data);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Read appropriate register for the config done bit for completion status
fp@2587:  *  and configure the PHY through s/w for EEPROM-less parts.
fp@2587:  *
fp@2587:  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
fp@2587:  *  config done bit, so only an error is logged and continues.  If we were
fp@2587:  *  to return with error, EEPROM-less silicon would not be able to be reset
fp@2587:  *  or change link.
fp@2587:  **/
fp@2587: static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 ret_val = 0;
fp@2587: 	u32 bank = 0;
fp@2587: 	u32 status;
fp@2587: 
fp@2587: 	e1000e_get_cfg_done_generic(hw);
fp@2587: 
fp@2587: 	/* Wait for indication from h/w that it has completed basic config */
fp@2587: 	if (hw->mac.type >= e1000_ich10lan) {
fp@2587: 		e1000_lan_init_done_ich8lan(hw);
fp@2587: 	} else {
fp@2587: 		ret_val = e1000e_get_auto_rd_done(hw);
fp@2587: 		if (ret_val) {
fp@2587: 			/* When auto config read does not complete, do not
fp@2587: 			 * return with an error. This can happen in situations
fp@2587: 			 * where there is no eeprom and prevents getting link.
fp@2587: 			 */
fp@2587: 			e_dbg("Auto Read Done did not complete\n");
fp@2587: 			ret_val = 0;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	/* Clear PHY Reset Asserted bit */
fp@2587: 	status = er32(STATUS);
fp@2587: 	if (status & E1000_STATUS_PHYRA)
fp@2587: 		ew32(STATUS, status & ~E1000_STATUS_PHYRA);
fp@2587: 	else
fp@2587: 		e_dbg("PHY Reset Asserted not set - needs delay\n");
fp@2587: 
fp@2587: 	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
fp@2587: 	if (hw->mac.type <= e1000_ich9lan) {
fp@2587: 		if (!(er32(EECD) & E1000_EECD_PRES) &&
fp@2587: 		    (hw->phy.type == e1000_phy_igp_3)) {
fp@2587: 			e1000e_phy_init_script_igp3(hw);
fp@2587: 		}
fp@2587: 	} else {
fp@2587: 		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
fp@2587: 			/* Maybe we should do a basic PHY config */
fp@2587: 			e_dbg("EEPROM not present\n");
fp@2587: 			ret_val = -E1000_ERR_CONFIG;
fp@2587: 		}
fp@2587: 	}
fp@2587: 
fp@2587: 	return ret_val;
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
fp@2587:  * @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  * In the case of a PHY power down to save power, or to turn off link during a
fp@2587:  * driver unload, or wake on lan is not enabled, remove the link.
fp@2587:  **/
fp@2587: static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	/* If the management interface is not enabled, then power down */
fp@2587: 	if (!(hw->mac.ops.check_mng_mode(hw) ||
fp@2587: 	      hw->phy.ops.check_reset_block(hw)))
fp@2587: 		e1000_power_down_phy_copper(hw);
fp@2587: }
fp@2587: 
fp@2587: /**
fp@2587:  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
fp@2587:  *  @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  *  Clears hardware counters specific to the silicon family and calls
fp@2587:  *  clear_hw_cntrs_generic to clear all general purpose counters.
fp@2587:  **/
fp@2587: static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	u16 phy_data;
fp@2587: 	s32 ret_val;
fp@2587: 
fp@2587: 	e1000e_clear_hw_cntrs_base(hw);
fp@2587: 
fp@2587: 	er32(ALGNERRC);
fp@2587: 	er32(RXERRC);
fp@2587: 	er32(TNCRS);
fp@2587: 	er32(CEXTERR);
fp@2587: 	er32(TSCTC);
fp@2587: 	er32(TSCTFC);
fp@2587: 
fp@2587: 	er32(MGTPRC);
fp@2587: 	er32(MGTPDC);
fp@2587: 	er32(MGTPTC);
fp@2587: 
fp@2587: 	er32(IAC);
fp@2587: 	er32(ICRXOC);
fp@2587: 
fp@2587: 	/* Clear PHY statistics registers */
fp@2587: 	if ((hw->phy.type == e1000_phy_82578) ||
fp@2587: 	    (hw->phy.type == e1000_phy_82579) ||
fp@2587: 	    (hw->phy.type == e1000_phy_i217) ||
fp@2587: 	    (hw->phy.type == e1000_phy_82577)) {
fp@2587: 		ret_val = hw->phy.ops.acquire(hw);
fp@2587: 		if (ret_val)
fp@2587: 			return;
fp@2587: 		ret_val = hw->phy.ops.set_page(hw,
fp@2587: 					       HV_STATS_PAGE << IGP_PAGE_SHIFT);
fp@2587: 		if (ret_val)
fp@2587: 			goto release;
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
fp@2587: 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
fp@2587: release:
fp@2587: 		hw->phy.ops.release(hw);
fp@2587: 	}
fp@2587: }
fp@2587: 
fp@2587: static const struct e1000_mac_operations ich8_mac_ops = {
fp@2587: 	/* check_mng_mode dependent on mac type */
fp@2587: 	.check_for_link		= e1000_check_for_copper_link_ich8lan,
fp@2587: 	/* cleanup_led dependent on mac type */
fp@2587: 	.clear_hw_cntrs		= e1000_clear_hw_cntrs_ich8lan,
fp@2587: 	.get_bus_info		= e1000_get_bus_info_ich8lan,
fp@2587: 	.set_lan_id		= e1000_set_lan_id_single_port,
fp@2587: 	.get_link_up_info	= e1000_get_link_up_info_ich8lan,
fp@2587: 	/* led_on dependent on mac type */
fp@2587: 	/* led_off dependent on mac type */
fp@2587: 	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
fp@2587: 	.reset_hw		= e1000_reset_hw_ich8lan,
fp@2587: 	.init_hw		= e1000_init_hw_ich8lan,
fp@2587: 	.setup_link		= e1000_setup_link_ich8lan,
fp@2587: 	.setup_physical_interface = e1000_setup_copper_link_ich8lan,
fp@2587: 	/* id_led_init dependent on mac type */
fp@2587: 	.config_collision_dist	= e1000e_config_collision_dist_generic,
fp@2587: 	.rar_set		= e1000e_rar_set_generic,
fp@2587: };
fp@2587: 
fp@2587: static const struct e1000_phy_operations ich8_phy_ops = {
fp@2587: 	.acquire		= e1000_acquire_swflag_ich8lan,
fp@2587: 	.check_reset_block	= e1000_check_reset_block_ich8lan,
fp@2587: 	.commit			= NULL,
fp@2587: 	.get_cfg_done		= e1000_get_cfg_done_ich8lan,
fp@2587: 	.get_cable_length	= e1000e_get_cable_length_igp_2,
fp@2587: 	.read_reg		= e1000e_read_phy_reg_igp,
fp@2587: 	.release		= e1000_release_swflag_ich8lan,
fp@2587: 	.reset			= e1000_phy_hw_reset_ich8lan,
fp@2587: 	.set_d0_lplu_state	= e1000_set_d0_lplu_state_ich8lan,
fp@2587: 	.set_d3_lplu_state	= e1000_set_d3_lplu_state_ich8lan,
fp@2587: 	.write_reg		= e1000e_write_phy_reg_igp,
fp@2587: };
fp@2587: 
fp@2587: static const struct e1000_nvm_operations ich8_nvm_ops = {
fp@2587: 	.acquire		= e1000_acquire_nvm_ich8lan,
fp@2587: 	.read			= e1000_read_nvm_ich8lan,
fp@2587: 	.release		= e1000_release_nvm_ich8lan,
fp@2587: 	.reload			= e1000e_reload_nvm_generic,
fp@2587: 	.update			= e1000_update_nvm_checksum_ich8lan,
fp@2587: 	.valid_led_default	= e1000_valid_led_default_ich8lan,
fp@2587: 	.validate		= e1000_validate_nvm_checksum_ich8lan,
fp@2587: 	.write			= e1000_write_nvm_ich8lan,
fp@2587: };
fp@2587: 
fp@2587: const struct e1000_info e1000_ich8_info = {
fp@2587: 	.mac			= e1000_ich8lan,
fp@2587: 	.flags			= FLAG_HAS_WOL
fp@2587: 				  | FLAG_IS_ICH
fp@2587: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2587: 				  | FLAG_HAS_AMT
fp@2587: 				  | FLAG_HAS_FLASH
fp@2587: 				  | FLAG_APME_IN_WUC,
fp@2587: 	.pba			= 8,
fp@2587: 	.max_hw_frame_size	= ETH_FRAME_LEN + ETH_FCS_LEN,
fp@2587: 	.get_variants		= e1000_get_variants_ich8lan,
fp@2587: 	.mac_ops		= &ich8_mac_ops,
fp@2587: 	.phy_ops		= &ich8_phy_ops,
fp@2587: 	.nvm_ops		= &ich8_nvm_ops,
fp@2587: };
fp@2587: 
fp@2587: const struct e1000_info e1000_ich9_info = {
fp@2587: 	.mac			= e1000_ich9lan,
fp@2587: 	.flags			= FLAG_HAS_JUMBO_FRAMES
fp@2587: 				  | FLAG_IS_ICH
fp@2587: 				  | FLAG_HAS_WOL
fp@2587: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2587: 				  | FLAG_HAS_AMT
fp@2587: 				  | FLAG_HAS_FLASH
fp@2587: 				  | FLAG_APME_IN_WUC,
fp@2587: 	.pba			= 18,
fp@2587: 	.max_hw_frame_size	= DEFAULT_JUMBO,
fp@2587: 	.get_variants		= e1000_get_variants_ich8lan,
fp@2587: 	.mac_ops		= &ich8_mac_ops,
fp@2587: 	.phy_ops		= &ich8_phy_ops,
fp@2587: 	.nvm_ops		= &ich8_nvm_ops,
fp@2587: };
fp@2587: 
fp@2587: const struct e1000_info e1000_ich10_info = {
fp@2587: 	.mac			= e1000_ich10lan,
fp@2587: 	.flags			= FLAG_HAS_JUMBO_FRAMES
fp@2587: 				  | FLAG_IS_ICH
fp@2587: 				  | FLAG_HAS_WOL
fp@2587: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2587: 				  | FLAG_HAS_AMT
fp@2587: 				  | FLAG_HAS_FLASH
fp@2587: 				  | FLAG_APME_IN_WUC,
fp@2587: 	.pba			= 18,
fp@2587: 	.max_hw_frame_size	= DEFAULT_JUMBO,
fp@2587: 	.get_variants		= e1000_get_variants_ich8lan,
fp@2587: 	.mac_ops		= &ich8_mac_ops,
fp@2587: 	.phy_ops		= &ich8_phy_ops,
fp@2587: 	.nvm_ops		= &ich8_nvm_ops,
fp@2587: };
fp@2587: 
fp@2587: const struct e1000_info e1000_pch_info = {
fp@2587: 	.mac			= e1000_pchlan,
fp@2587: 	.flags			= FLAG_IS_ICH
fp@2587: 				  | FLAG_HAS_WOL
fp@2587: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2587: 				  | FLAG_HAS_AMT
fp@2587: 				  | FLAG_HAS_FLASH
fp@2587: 				  | FLAG_HAS_JUMBO_FRAMES
fp@2587: 				  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
fp@2587: 				  | FLAG_APME_IN_WUC,
fp@2587: 	.flags2			= FLAG2_HAS_PHY_STATS,
fp@2587: 	.pba			= 26,
fp@2587: 	.max_hw_frame_size	= 4096,
fp@2587: 	.get_variants		= e1000_get_variants_ich8lan,
fp@2587: 	.mac_ops		= &ich8_mac_ops,
fp@2587: 	.phy_ops		= &ich8_phy_ops,
fp@2587: 	.nvm_ops		= &ich8_nvm_ops,
fp@2587: };
fp@2587: 
fp@2587: const struct e1000_info e1000_pch2_info = {
fp@2587: 	.mac			= e1000_pch2lan,
fp@2587: 	.flags			= FLAG_IS_ICH
fp@2587: 				  | FLAG_HAS_WOL
fp@2587: 				  | FLAG_HAS_HW_TIMESTAMP
fp@2587: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2587: 				  | FLAG_HAS_AMT
fp@2587: 				  | FLAG_HAS_FLASH
fp@2587: 				  | FLAG_HAS_JUMBO_FRAMES
fp@2587: 				  | FLAG_APME_IN_WUC,
fp@2587: 	.flags2			= FLAG2_HAS_PHY_STATS
fp@2587: 				  | FLAG2_HAS_EEE,
fp@2587: 	.pba			= 26,
fp@2587: 	.max_hw_frame_size	= 9018,
fp@2587: 	.get_variants		= e1000_get_variants_ich8lan,
fp@2587: 	.mac_ops		= &ich8_mac_ops,
fp@2587: 	.phy_ops		= &ich8_phy_ops,
fp@2587: 	.nvm_ops		= &ich8_nvm_ops,
fp@2587: };
fp@2587: 
fp@2587: const struct e1000_info e1000_pch_lpt_info = {
fp@2587: 	.mac			= e1000_pch_lpt,
fp@2587: 	.flags			= FLAG_IS_ICH
fp@2587: 				  | FLAG_HAS_WOL
fp@2587: 				  | FLAG_HAS_HW_TIMESTAMP
fp@2587: 				  | FLAG_HAS_CTRLEXT_ON_LOAD
fp@2587: 				  | FLAG_HAS_AMT
fp@2587: 				  | FLAG_HAS_FLASH
fp@2587: 				  | FLAG_HAS_JUMBO_FRAMES
fp@2587: 				  | FLAG_APME_IN_WUC,
fp@2587: 	.flags2			= FLAG2_HAS_PHY_STATS
fp@2587: 				  | FLAG2_HAS_EEE,
fp@2587: 	.pba			= 26,
fp@2587: 	.max_hw_frame_size	= 9018,
fp@2587: 	.get_variants		= e1000_get_variants_ich8lan,
fp@2587: 	.mac_ops		= &ich8_mac_ops,
fp@2587: 	.phy_ops		= &ich8_phy_ops,
fp@2587: 	.nvm_ops		= &ich8_nvm_ops,
fp@2587: };