ch1010832@2198: /******************************************************************************* ch1010832@2198: ch1010832@2198: Intel PRO/1000 Linux driver ch1010832@2198: Copyright(c) 1999 - 2006 Intel Corporation. ch1010832@2198: ch1010832@2198: This program is free software; you can redistribute it and/or modify it ch1010832@2198: under the terms and conditions of the GNU General Public License, ch1010832@2198: version 2, as published by the Free Software Foundation. ch1010832@2198: ch1010832@2198: This program is distributed in the hope it will be useful, but WITHOUT ch1010832@2198: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ch1010832@2198: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ch1010832@2198: more details. ch1010832@2198: ch1010832@2198: You should have received a copy of the GNU General Public License along with ch1010832@2198: this program; if not, write to the Free Software Foundation, Inc., ch1010832@2198: 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ch1010832@2198: ch1010832@2198: The full GNU General Public License is included in this distribution in ch1010832@2198: the file called "COPYING". ch1010832@2198: ch1010832@2198: Contact Information: ch1010832@2198: Linux NICS ch1010832@2198: e1000-devel Mailing List ch1010832@2198: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ch1010832@2198: ch1010832@2198: *******************************************************************************/ ch1010832@2198: ch1010832@2198: /* e1000_hw.c ch1010832@2198: * Shared functions for accessing and configuring the MAC ch1010832@2198: */ ch1010832@2198: ch1010832@2198: ch1010832@2198: #include "e1000_hw.h" ch1010832@2198: ch1010832@2198: static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask); ch1010832@2198: static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask); ch1010832@2198: static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data); ch1010832@2198: static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); ch1010832@2198: static s32 e1000_get_software_semaphore(struct e1000_hw *hw); ch1010832@2198: static void e1000_release_software_semaphore(struct e1000_hw *hw); ch1010832@2198: ch1010832@2198: static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_check_downshift(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_check_polarity(struct e1000_hw *hw, ch1010832@2198: e1000_rev_polarity *polarity); ch1010832@2198: static void e1000_clear_hw_cntrs(struct e1000_hw *hw); ch1010832@2198: static void e1000_clear_vfta(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_commit_shadow_ram(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, ch1010832@2198: bool link_up); ch1010832@2198: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_detect_gig_phy(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank); ch1010832@2198: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, ch1010832@2198: u16 *max_length); ch1010832@2198: static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_get_software_flag(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_ich8_cycle_init(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout); ch1010832@2198: static s32 e1000_id_led_init(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, ch1010832@2198: u32 cnf_base_addr, ch1010832@2198: u32 cnf_size); ch1010832@2198: static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw); ch1010832@2198: static void e1000_init_rx_addrs(struct e1000_hw *hw); ch1010832@2198: static void e1000_initialize_hardware_bits(struct e1000_hw *hw); ch1010832@2198: static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_mng_enable_host_if(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, ch1010832@2198: u16 offset, u8 *sum); ch1010832@2198: static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, ch1010832@2198: struct e1000_host_mng_command_header ch1010832@2198: *hdr); ch1010832@2198: static s32 e1000_mng_write_commit(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, ch1010832@2198: struct e1000_phy_info *phy_info); ch1010832@2198: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, ch1010832@2198: struct e1000_phy_info *phy_info); ch1010832@2198: static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data); ch1010832@2198: static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data); ch1010832@2198: static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); ch1010832@2198: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, ch1010832@2198: struct e1000_phy_info *phy_info); ch1010832@2198: static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data); ch1010832@2198: static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, ch1010832@2198: u8 byte); ch1010832@2198: static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); ch1010832@2198: static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data); ch1010832@2198: static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, ch1010832@2198: u16 *data); ch1010832@2198: static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, ch1010832@2198: u16 data); ch1010832@2198: static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data); ch1010832@2198: static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data); ch1010832@2198: static void e1000_release_software_flag(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); ch1010832@2198: static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); ch1010832@2198: static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop); ch1010832@2198: static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_wait_autoneg(struct e1000_hw *hw); ch1010832@2198: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); ch1010832@2198: static s32 e1000_set_phy_type(struct e1000_hw *hw); ch1010832@2198: static void e1000_phy_init_script(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_setup_copper_link(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); ch1010832@2198: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); ch1010832@2198: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); ch1010832@2198: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, ch1010832@2198: u16 count); ch1010832@2198: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, ch1010832@2198: u16 words, u16 *data); ch1010832@2198: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, ch1010832@2198: u16 words, u16 *data); ch1010832@2198: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); ch1010832@2198: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); ch1010832@2198: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); ch1010832@2198: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); ch1010832@2198: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@2198: u16 phy_data); ch1010832@2198: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, ch1010832@2198: u16 *phy_data); ch1010832@2198: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); ch1010832@2198: static s32 e1000_acquire_eeprom(struct e1000_hw *hw); ch1010832@2198: static void e1000_release_eeprom(struct e1000_hw *hw); ch1010832@2198: static void e1000_standby_eeprom(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_set_vco_speed(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_set_phy_mode(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer); ch1010832@2198: static u8 e1000_calculate_mng_checksum(char *buffer, u32 length); ch1010832@2198: static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex); ch1010832@2198: static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw); ch1010832@2198: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ch1010832@2198: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); ch1010832@2198: ch1010832@2198: /* IGP cable length table */ ch1010832@2198: static const ch1010832@2198: u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = ch1010832@2198: { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ch1010832@2198: 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, ch1010832@2198: 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, ch1010832@2198: 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, ch1010832@2198: 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, ch1010832@2198: 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, ch1010832@2198: 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, ch1010832@2198: 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; ch1010832@2198: ch1010832@2198: static const ch1010832@2198: u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = ch1010832@2198: { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, ch1010832@2198: 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, ch1010832@2198: 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, ch1010832@2198: 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, ch1010832@2198: 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, ch1010832@2198: 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, ch1010832@2198: 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, ch1010832@2198: 104, 109, 114, 118, 121, 124}; ch1010832@2198: ch1010832@2198: static DEFINE_SPINLOCK(e1000_eeprom_lock); ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Set the phy type member in the hw struct. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_set_phy_type(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: DEBUGFUNC("e1000_set_phy_type"); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_undefined) ch1010832@2198: return -E1000_ERR_PHY_TYPE; ch1010832@2198: ch1010832@2198: switch (hw->phy_id) { ch1010832@2198: case M88E1000_E_PHY_ID: ch1010832@2198: case M88E1000_I_PHY_ID: ch1010832@2198: case M88E1011_I_PHY_ID: ch1010832@2198: case M88E1111_I_PHY_ID: ch1010832@2198: hw->phy_type = e1000_phy_m88; ch1010832@2198: break; ch1010832@2198: case IGP01E1000_I_PHY_ID: ch1010832@2198: if (hw->mac_type == e1000_82541 || ch1010832@2198: hw->mac_type == e1000_82541_rev_2 || ch1010832@2198: hw->mac_type == e1000_82547 || ch1010832@2198: hw->mac_type == e1000_82547_rev_2) { ch1010832@2198: hw->phy_type = e1000_phy_igp; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: case IGP03E1000_E_PHY_ID: ch1010832@2198: hw->phy_type = e1000_phy_igp_3; ch1010832@2198: break; ch1010832@2198: case IFE_E_PHY_ID: ch1010832@2198: case IFE_PLUS_E_PHY_ID: ch1010832@2198: case IFE_C_E_PHY_ID: ch1010832@2198: hw->phy_type = e1000_phy_ife; ch1010832@2198: break; ch1010832@2198: case GG82563_E_PHY_ID: ch1010832@2198: if (hw->mac_type == e1000_80003es2lan) { ch1010832@2198: hw->phy_type = e1000_phy_gg82563; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: /* Fall Through */ ch1010832@2198: default: ch1010832@2198: /* Should never have loaded on this device */ ch1010832@2198: hw->phy_type = e1000_phy_undefined; ch1010832@2198: return -E1000_ERR_PHY_TYPE; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * IGP phy init script - initializes the GbE PHY ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_phy_init_script(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ret_val; ch1010832@2198: u16 phy_saved_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_init_script"); ch1010832@2198: ch1010832@2198: if (hw->phy_init_script) { ch1010832@2198: msleep(20); ch1010832@2198: ch1010832@2198: /* Save off the current value of register 0x2F5B to be restored at ch1010832@2198: * the end of this routine. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); ch1010832@2198: ch1010832@2198: /* Disabled the PHY transmitter */ ch1010832@2198: e1000_write_phy_reg(hw, 0x2F5B, 0x0003); ch1010832@2198: ch1010832@2198: msleep(20); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw,0x0000,0x0140); ch1010832@2198: ch1010832@2198: msleep(5); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82547: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F95, 0x0001); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F71, 0xBD21); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F79, 0x0018); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F30, 0x1600); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F31, 0x0014); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F32, 0x161C); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F94, 0x0003); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F96, 0x003F); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x2010, 0x0008); ch1010832@2198: break; ch1010832@2198: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: e1000_write_phy_reg(hw, 0x1F73, 0x0099); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, 0x0000, 0x3300); ch1010832@2198: ch1010832@2198: msleep(20); ch1010832@2198: ch1010832@2198: /* Now enable the transmitter */ ch1010832@2198: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82547) { ch1010832@2198: u16 fused, fine, coarse; ch1010832@2198: ch1010832@2198: /* Move to analog registers page */ ch1010832@2198: e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); ch1010832@2198: ch1010832@2198: if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { ch1010832@2198: e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); ch1010832@2198: ch1010832@2198: fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; ch1010832@2198: coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; ch1010832@2198: ch1010832@2198: if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { ch1010832@2198: coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; ch1010832@2198: fine -= IGP01E1000_ANALOG_FUSE_FINE_1; ch1010832@2198: } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) ch1010832@2198: fine -= IGP01E1000_ANALOG_FUSE_FINE_10; ch1010832@2198: ch1010832@2198: fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | ch1010832@2198: (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | ch1010832@2198: (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); ch1010832@2198: ch1010832@2198: e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); ch1010832@2198: e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, ch1010832@2198: IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Set the mac type member in the hw struct. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_set_mac_type(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: DEBUGFUNC("e1000_set_mac_type"); ch1010832@2198: ch1010832@2198: switch (hw->device_id) { ch1010832@2198: case E1000_DEV_ID_82542: ch1010832@2198: switch (hw->revision_id) { ch1010832@2198: case E1000_82542_2_0_REV_ID: ch1010832@2198: hw->mac_type = e1000_82542_rev2_0; ch1010832@2198: break; ch1010832@2198: case E1000_82542_2_1_REV_ID: ch1010832@2198: hw->mac_type = e1000_82542_rev2_1; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: /* Invalid 82542 revision ID */ ch1010832@2198: return -E1000_ERR_MAC_TYPE; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82543GC_FIBER: ch1010832@2198: case E1000_DEV_ID_82543GC_COPPER: ch1010832@2198: hw->mac_type = e1000_82543; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82544EI_COPPER: ch1010832@2198: case E1000_DEV_ID_82544EI_FIBER: ch1010832@2198: case E1000_DEV_ID_82544GC_COPPER: ch1010832@2198: case E1000_DEV_ID_82544GC_LOM: ch1010832@2198: hw->mac_type = e1000_82544; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82540EM: ch1010832@2198: case E1000_DEV_ID_82540EM_LOM: ch1010832@2198: case E1000_DEV_ID_82540EP: ch1010832@2198: case E1000_DEV_ID_82540EP_LOM: ch1010832@2198: case E1000_DEV_ID_82540EP_LP: ch1010832@2198: hw->mac_type = e1000_82540; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82545EM_COPPER: ch1010832@2198: case E1000_DEV_ID_82545EM_FIBER: ch1010832@2198: hw->mac_type = e1000_82545; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82545GM_COPPER: ch1010832@2198: case E1000_DEV_ID_82545GM_FIBER: ch1010832@2198: case E1000_DEV_ID_82545GM_SERDES: ch1010832@2198: hw->mac_type = e1000_82545_rev_3; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82546EB_COPPER: ch1010832@2198: case E1000_DEV_ID_82546EB_FIBER: ch1010832@2198: case E1000_DEV_ID_82546EB_QUAD_COPPER: ch1010832@2198: hw->mac_type = e1000_82546; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82546GB_COPPER: ch1010832@2198: case E1000_DEV_ID_82546GB_FIBER: ch1010832@2198: case E1000_DEV_ID_82546GB_SERDES: ch1010832@2198: case E1000_DEV_ID_82546GB_PCIE: ch1010832@2198: case E1000_DEV_ID_82546GB_QUAD_COPPER: ch1010832@2198: case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: ch1010832@2198: hw->mac_type = e1000_82546_rev_3; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82541EI: ch1010832@2198: case E1000_DEV_ID_82541EI_MOBILE: ch1010832@2198: case E1000_DEV_ID_82541ER_LOM: ch1010832@2198: hw->mac_type = e1000_82541; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82541ER: ch1010832@2198: case E1000_DEV_ID_82541GI: ch1010832@2198: case E1000_DEV_ID_82541GI_LF: ch1010832@2198: case E1000_DEV_ID_82541GI_MOBILE: ch1010832@2198: hw->mac_type = e1000_82541_rev_2; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82547EI: ch1010832@2198: case E1000_DEV_ID_82547EI_MOBILE: ch1010832@2198: hw->mac_type = e1000_82547; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82547GI: ch1010832@2198: hw->mac_type = e1000_82547_rev_2; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82571EB_COPPER: ch1010832@2198: case E1000_DEV_ID_82571EB_FIBER: ch1010832@2198: case E1000_DEV_ID_82571EB_SERDES: ch1010832@2198: case E1000_DEV_ID_82571EB_SERDES_DUAL: ch1010832@2198: case E1000_DEV_ID_82571EB_SERDES_QUAD: ch1010832@2198: case E1000_DEV_ID_82571EB_QUAD_COPPER: ch1010832@2198: case E1000_DEV_ID_82571PT_QUAD_COPPER: ch1010832@2198: case E1000_DEV_ID_82571EB_QUAD_FIBER: ch1010832@2198: case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: ch1010832@2198: hw->mac_type = e1000_82571; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82572EI_COPPER: ch1010832@2198: case E1000_DEV_ID_82572EI_FIBER: ch1010832@2198: case E1000_DEV_ID_82572EI_SERDES: ch1010832@2198: case E1000_DEV_ID_82572EI: ch1010832@2198: hw->mac_type = e1000_82572; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_82573E: ch1010832@2198: case E1000_DEV_ID_82573E_IAMT: ch1010832@2198: case E1000_DEV_ID_82573L: ch1010832@2198: hw->mac_type = e1000_82573; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: ch1010832@2198: case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: ch1010832@2198: case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: ch1010832@2198: case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: ch1010832@2198: hw->mac_type = e1000_80003es2lan; ch1010832@2198: break; ch1010832@2198: case E1000_DEV_ID_ICH8_IGP_M_AMT: ch1010832@2198: case E1000_DEV_ID_ICH8_IGP_AMT: ch1010832@2198: case E1000_DEV_ID_ICH8_IGP_C: ch1010832@2198: case E1000_DEV_ID_ICH8_IFE: ch1010832@2198: case E1000_DEV_ID_ICH8_IFE_GT: ch1010832@2198: case E1000_DEV_ID_ICH8_IFE_G: ch1010832@2198: case E1000_DEV_ID_ICH8_IGP_M: ch1010832@2198: hw->mac_type = e1000_ich8lan; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: /* Should never have loaded on this device */ ch1010832@2198: return -E1000_ERR_MAC_TYPE; ch1010832@2198: } ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_ich8lan: ch1010832@2198: hw->swfwhw_semaphore_present = true; ch1010832@2198: hw->asf_firmware_present = true; ch1010832@2198: break; ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: hw->swfw_sync_present = true; ch1010832@2198: /* fall through */ ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: case e1000_82573: ch1010832@2198: hw->eeprom_semaphore_present = true; ch1010832@2198: /* fall through */ ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82547: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: hw->asf_firmware_present = true; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* The 82543 chip does not count tx_carrier_errors properly in ch1010832@2198: * FD mode ch1010832@2198: */ ch1010832@2198: if (hw->mac_type == e1000_82543) ch1010832@2198: hw->bad_tx_carr_stats_fd = true; ch1010832@2198: ch1010832@2198: /* capable of receiving management packets to the host */ ch1010832@2198: if (hw->mac_type >= e1000_82571) ch1010832@2198: hw->has_manc2h = true; ch1010832@2198: ch1010832@2198: /* In rare occasions, ESB2 systems would end up started without ch1010832@2198: * the RX unit being turned on. ch1010832@2198: */ ch1010832@2198: if (hw->mac_type == e1000_80003es2lan) ch1010832@2198: hw->rx_needs_kicking = true; ch1010832@2198: ch1010832@2198: if (hw->mac_type > e1000_82544) ch1010832@2198: hw->has_smbus = true; ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * Set media type and TBI compatibility. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * **************************************************************************/ ch1010832@2198: void e1000_set_media_type(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 status; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_set_media_type"); ch1010832@2198: ch1010832@2198: if (hw->mac_type != e1000_82543) { ch1010832@2198: /* tbi_compatibility is only valid on 82543 */ ch1010832@2198: hw->tbi_compatibility_en = false; ch1010832@2198: } ch1010832@2198: ch1010832@2198: switch (hw->device_id) { ch1010832@2198: case E1000_DEV_ID_82545GM_SERDES: ch1010832@2198: case E1000_DEV_ID_82546GB_SERDES: ch1010832@2198: case E1000_DEV_ID_82571EB_SERDES: ch1010832@2198: case E1000_DEV_ID_82571EB_SERDES_DUAL: ch1010832@2198: case E1000_DEV_ID_82571EB_SERDES_QUAD: ch1010832@2198: case E1000_DEV_ID_82572EI_SERDES: ch1010832@2198: case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: ch1010832@2198: hw->media_type = e1000_media_type_internal_serdes; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: hw->media_type = e1000_media_type_fiber; ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: case e1000_82573: ch1010832@2198: /* The STATUS_TBIMODE bit is reserved or reused for the this ch1010832@2198: * device. ch1010832@2198: */ ch1010832@2198: hw->media_type = e1000_media_type_copper; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: status = er32(STATUS); ch1010832@2198: if (status & E1000_STATUS_TBIMODE) { ch1010832@2198: hw->media_type = e1000_media_type_fiber; ch1010832@2198: /* tbi_compatibility not valid on fiber */ ch1010832@2198: hw->tbi_compatibility_en = false; ch1010832@2198: } else { ch1010832@2198: hw->media_type = e1000_media_type_copper; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reset the transmit and receive units; mask and clear all interrupts. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_reset_hw(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: u32 ctrl_ext; ch1010832@2198: u32 icr; ch1010832@2198: u32 manc; ch1010832@2198: u32 led_ctrl; ch1010832@2198: u32 timeout; ch1010832@2198: u32 extcnf_ctrl; ch1010832@2198: s32 ret_val; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_reset_hw"); ch1010832@2198: ch1010832@2198: /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ ch1010832@2198: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@2198: DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); ch1010832@2198: e1000_pci_clear_mwi(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->bus_type == e1000_bus_type_pci_express) { ch1010832@2198: /* Prevent the PCI-E bus from sticking if there is no TLP connection ch1010832@2198: * on the last TLP read/write transaction when MAC is reset. ch1010832@2198: */ ch1010832@2198: if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { ch1010832@2198: DEBUGOUT("PCI-E Master disable polling has failed.\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Clear interrupt mask to stop board from generating interrupts */ ch1010832@2198: DEBUGOUT("Masking off all interrupts\n"); ch1010832@2198: ew32(IMC, 0xffffffff); ch1010832@2198: ch1010832@2198: /* Disable the Transmit and Receive units. Then delay to allow ch1010832@2198: * any pending transactions to complete before we hit the MAC with ch1010832@2198: * the global reset. ch1010832@2198: */ ch1010832@2198: ew32(RCTL, 0); ch1010832@2198: ew32(TCTL, E1000_TCTL_PSP); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ ch1010832@2198: hw->tbi_compatibility_on = false; ch1010832@2198: ch1010832@2198: /* Delay to allow any outstanding PCI transactions to complete before ch1010832@2198: * resetting the device ch1010832@2198: */ ch1010832@2198: msleep(10); ch1010832@2198: ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: /* Must reset the PHY before resetting the MAC */ ch1010832@2198: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@2198: ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); ch1010832@2198: msleep(5); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Must acquire the MDIO ownership before MAC reset. ch1010832@2198: * Ownership defaults to firmware after a reset. */ ch1010832@2198: if (hw->mac_type == e1000_82573) { ch1010832@2198: timeout = 10; ch1010832@2198: ch1010832@2198: extcnf_ctrl = er32(EXTCNF_CTRL); ch1010832@2198: extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; ch1010832@2198: ch1010832@2198: do { ch1010832@2198: ew32(EXTCNF_CTRL, extcnf_ctrl); ch1010832@2198: extcnf_ctrl = er32(EXTCNF_CTRL); ch1010832@2198: ch1010832@2198: if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) ch1010832@2198: break; ch1010832@2198: else ch1010832@2198: extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; ch1010832@2198: ch1010832@2198: msleep(2); ch1010832@2198: timeout--; ch1010832@2198: } while (timeout); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Workaround for ICH8 bit corruption issue in FIFO memory */ ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /* Set Tx and Rx buffer allocation to 8k apiece. */ ch1010832@2198: ew32(PBA, E1000_PBA_8K); ch1010832@2198: /* Set Packet Buffer Size to 16k. */ ch1010832@2198: ew32(PBS, E1000_PBS_16K); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Issue a global reset to the MAC. This will reset the chip's ch1010832@2198: * transmit, receive, DMA, and link units. It will not effect ch1010832@2198: * the current PCI configuration. The global reset bit is self- ch1010832@2198: * clearing, and should clear within a microsecond. ch1010832@2198: */ ch1010832@2198: DEBUGOUT("Issuing a global reset to MAC\n"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82544: ch1010832@2198: case e1000_82540: ch1010832@2198: case e1000_82545: ch1010832@2198: case e1000_82546: ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: /* These controllers can't ack the 64-bit write when issuing the ch1010832@2198: * reset, so use IO-mapping as a workaround to issue the reset */ ch1010832@2198: E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); ch1010832@2198: break; ch1010832@2198: case e1000_82545_rev_3: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: /* Reset is performed on a shadow of the control register */ ch1010832@2198: ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: if (!hw->phy_reset_disable && ch1010832@2198: e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { ch1010832@2198: /* e1000_ich8lan PHY HW reset requires MAC CORE reset ch1010832@2198: * at the same time to make sure the interface between ch1010832@2198: * MAC and the external PHY is reset. ch1010832@2198: */ ch1010832@2198: ctrl |= E1000_CTRL_PHY_RST; ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_get_software_flag(hw); ch1010832@2198: ew32(CTRL, (ctrl | E1000_CTRL_RST)); ch1010832@2198: msleep(5); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: ew32(CTRL, (ctrl | E1000_CTRL_RST)); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* After MAC reset, force reload of EEPROM to restore power-on settings to ch1010832@2198: * device. Later controllers reload the EEPROM automatically, so just wait ch1010832@2198: * for reload to complete. ch1010832@2198: */ ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: case e1000_82543: ch1010832@2198: case e1000_82544: ch1010832@2198: /* Wait for reset to complete */ ch1010832@2198: udelay(10); ch1010832@2198: ctrl_ext = er32(CTRL_EXT); ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_EE_RST; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: /* Wait for EEPROM reload */ ch1010832@2198: msleep(2); ch1010832@2198: break; ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: /* Wait for EEPROM reload */ ch1010832@2198: msleep(20); ch1010832@2198: break; ch1010832@2198: case e1000_82573: ch1010832@2198: if (!e1000_is_onboard_nvm_eeprom(hw)) { ch1010832@2198: udelay(10); ch1010832@2198: ctrl_ext = er32(CTRL_EXT); ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_EE_RST; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: /* fall through */ ch1010832@2198: default: ch1010832@2198: /* Auto read done will delay 5ms or poll based on mac type */ ch1010832@2198: ret_val = e1000_get_auto_rd_done(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Disable HW ARPs on ASF enabled adapters */ ch1010832@2198: if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { ch1010832@2198: manc = er32(MANC); ch1010832@2198: manc &= ~(E1000_MANC_ARP_EN); ch1010832@2198: ew32(MANC, manc); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@2198: e1000_phy_init_script(hw); ch1010832@2198: ch1010832@2198: /* Configure activity LED after PHY reset */ ch1010832@2198: led_ctrl = er32(LEDCTL); ch1010832@2198: led_ctrl &= IGP_ACTIVITY_LED_MASK; ch1010832@2198: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ch1010832@2198: ew32(LEDCTL, led_ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Clear interrupt mask to stop board from generating interrupts */ ch1010832@2198: DEBUGOUT("Masking off all interrupts\n"); ch1010832@2198: ew32(IMC, 0xffffffff); ch1010832@2198: ch1010832@2198: /* Clear any pending interrupt events. */ ch1010832@2198: icr = er32(ICR); ch1010832@2198: ch1010832@2198: /* If MWI was previously enabled, reenable it. */ ch1010832@2198: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@2198: if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) ch1010832@2198: e1000_pci_set_mwi(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: u32 kab = er32(KABGTXD); ch1010832@2198: kab |= E1000_KABGTXD_BGSQLBIAS; ch1010832@2198: ew32(KABGTXD, kab); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * ch1010832@2198: * Initialize a number of hardware-dependent bits ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * This function contains hardware limitation workarounds for PCI-E adapters ch1010832@2198: * ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_initialize_hardware_bits(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { ch1010832@2198: /* Settings common to all PCI-express silicon */ ch1010832@2198: u32 reg_ctrl, reg_ctrl_ext; ch1010832@2198: u32 reg_tarc0, reg_tarc1; ch1010832@2198: u32 reg_tctl; ch1010832@2198: u32 reg_txdctl, reg_txdctl1; ch1010832@2198: ch1010832@2198: /* link autonegotiation/sync workarounds */ ch1010832@2198: reg_tarc0 = er32(TARC0); ch1010832@2198: reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); ch1010832@2198: ch1010832@2198: /* Enable not-done TX descriptor counting */ ch1010832@2198: reg_txdctl = er32(TXDCTL); ch1010832@2198: reg_txdctl |= E1000_TXDCTL_COUNT_DESC; ch1010832@2198: ew32(TXDCTL, reg_txdctl); ch1010832@2198: reg_txdctl1 = er32(TXDCTL1); ch1010832@2198: reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; ch1010832@2198: ew32(TXDCTL1, reg_txdctl1); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: /* Clear PHY TX compatible mode bits */ ch1010832@2198: reg_tarc1 = er32(TARC1); ch1010832@2198: reg_tarc1 &= ~((1 << 30)|(1 << 29)); ch1010832@2198: ch1010832@2198: /* link autonegotiation/sync workarounds */ ch1010832@2198: reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); ch1010832@2198: ch1010832@2198: /* TX ring control fixes */ ch1010832@2198: reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); ch1010832@2198: ch1010832@2198: /* Multiple read bit is reversed polarity */ ch1010832@2198: reg_tctl = er32(TCTL); ch1010832@2198: if (reg_tctl & E1000_TCTL_MULR) ch1010832@2198: reg_tarc1 &= ~(1 << 28); ch1010832@2198: else ch1010832@2198: reg_tarc1 |= (1 << 28); ch1010832@2198: ch1010832@2198: ew32(TARC1, reg_tarc1); ch1010832@2198: break; ch1010832@2198: case e1000_82573: ch1010832@2198: reg_ctrl_ext = er32(CTRL_EXT); ch1010832@2198: reg_ctrl_ext &= ~(1 << 23); ch1010832@2198: reg_ctrl_ext |= (1 << 22); ch1010832@2198: ch1010832@2198: /* TX byte count fix */ ch1010832@2198: reg_ctrl = er32(CTRL); ch1010832@2198: reg_ctrl &= ~(1 << 29); ch1010832@2198: ch1010832@2198: ew32(CTRL_EXT, reg_ctrl_ext); ch1010832@2198: ew32(CTRL, reg_ctrl); ch1010832@2198: break; ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: /* improve small packet performace for fiber/serdes */ ch1010832@2198: if ((hw->media_type == e1000_media_type_fiber) || ch1010832@2198: (hw->media_type == e1000_media_type_internal_serdes)) { ch1010832@2198: reg_tarc0 &= ~(1 << 20); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Multiple read bit is reversed polarity */ ch1010832@2198: reg_tctl = er32(TCTL); ch1010832@2198: reg_tarc1 = er32(TARC1); ch1010832@2198: if (reg_tctl & E1000_TCTL_MULR) ch1010832@2198: reg_tarc1 &= ~(1 << 28); ch1010832@2198: else ch1010832@2198: reg_tarc1 |= (1 << 28); ch1010832@2198: ch1010832@2198: ew32(TARC1, reg_tarc1); ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: /* Reduce concurrent DMA requests to 3 from 4 */ ch1010832@2198: if ((hw->revision_id < 3) || ch1010832@2198: ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && ch1010832@2198: (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) ch1010832@2198: reg_tarc0 |= ((1 << 29)|(1 << 28)); ch1010832@2198: ch1010832@2198: reg_ctrl_ext = er32(CTRL_EXT); ch1010832@2198: reg_ctrl_ext |= (1 << 22); ch1010832@2198: ew32(CTRL_EXT, reg_ctrl_ext); ch1010832@2198: ch1010832@2198: /* workaround TX hang with TSO=on */ ch1010832@2198: reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); ch1010832@2198: ch1010832@2198: /* Multiple read bit is reversed polarity */ ch1010832@2198: reg_tctl = er32(TCTL); ch1010832@2198: reg_tarc1 = er32(TARC1); ch1010832@2198: if (reg_tctl & E1000_TCTL_MULR) ch1010832@2198: reg_tarc1 &= ~(1 << 28); ch1010832@2198: else ch1010832@2198: reg_tarc1 |= (1 << 28); ch1010832@2198: ch1010832@2198: /* workaround TX hang with TSO=on */ ch1010832@2198: reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); ch1010832@2198: ch1010832@2198: ew32(TARC1, reg_tarc1); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ew32(TARC0, reg_tarc0); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Performs basic configuration of the adapter. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Assumes that the controller has previously been reset and is in a ch1010832@2198: * post-reset uninitialized state. Initializes the receive address registers, ch1010832@2198: * multicast table, and VLAN filter table. Calls routines to setup link ch1010832@2198: * configuration and flow control settings. Clears all on-chip counters. Leaves ch1010832@2198: * the transmit and receive units disabled and uninitialized. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_init_hw(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: u32 i; ch1010832@2198: s32 ret_val; ch1010832@2198: u32 mta_size; ch1010832@2198: u32 reg_data; ch1010832@2198: u32 ctrl_ext; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_init_hw"); ch1010832@2198: ch1010832@2198: /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ ch1010832@2198: if ((hw->mac_type == e1000_ich8lan) && ch1010832@2198: ((hw->revision_id < 3) || ch1010832@2198: ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && ch1010832@2198: (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { ch1010832@2198: reg_data = er32(STATUS); ch1010832@2198: reg_data &= ~0x80000000; ch1010832@2198: ew32(STATUS, reg_data); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Initialize Identification LED */ ch1010832@2198: ret_val = e1000_id_led_init(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Initializing Identification LED\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Set the media type and TBI compatibility */ ch1010832@2198: e1000_set_media_type(hw); ch1010832@2198: ch1010832@2198: /* Must be called after e1000_set_media_type because media_type is used */ ch1010832@2198: e1000_initialize_hardware_bits(hw); ch1010832@2198: ch1010832@2198: /* Disabling VLAN filtering. */ ch1010832@2198: DEBUGOUT("Initializing the IEEE VLAN\n"); ch1010832@2198: /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ ch1010832@2198: if (hw->mac_type != e1000_ich8lan) { ch1010832@2198: if (hw->mac_type < e1000_82545_rev_3) ch1010832@2198: ew32(VET, 0); ch1010832@2198: e1000_clear_vfta(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ ch1010832@2198: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@2198: DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); ch1010832@2198: e1000_pci_clear_mwi(hw); ch1010832@2198: ew32(RCTL, E1000_RCTL_RST); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: msleep(5); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Setup the receive address. This involves initializing all of the Receive ch1010832@2198: * Address Registers (RARs 0 - 15). ch1010832@2198: */ ch1010832@2198: e1000_init_rx_addrs(hw); ch1010832@2198: ch1010832@2198: /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ ch1010832@2198: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@2198: ew32(RCTL, 0); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: msleep(1); ch1010832@2198: if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) ch1010832@2198: e1000_pci_set_mwi(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Zero out the Multicast HASH table */ ch1010832@2198: DEBUGOUT("Zeroing the MTA\n"); ch1010832@2198: mta_size = E1000_MC_TBL_SIZE; ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: mta_size = E1000_MC_TBL_SIZE_ICH8LAN; ch1010832@2198: for (i = 0; i < mta_size; i++) { ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); ch1010832@2198: /* use write flush to prevent Memory Write Block (MWB) from ch1010832@2198: * occuring when accessing our register space */ ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Set the PCI priority bit correctly in the CTRL register. This ch1010832@2198: * determines if the adapter gives priority to receives, or if it ch1010832@2198: * gives equal priority to transmits and receives. Valid only on ch1010832@2198: * 82542 and 82543 silicon. ch1010832@2198: */ ch1010832@2198: if (hw->dma_fairness && hw->mac_type <= e1000_82543) { ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ew32(CTRL, ctrl | E1000_CTRL_PRIOR); ch1010832@2198: } ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82545_rev_3: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ ch1010832@2198: if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048) ch1010832@2198: e1000_pcix_set_mmrbc(hw, 2048); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* More time needed for PHY to initialize */ ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: msleep(15); ch1010832@2198: ch1010832@2198: /* Call a subroutine to configure the link and setup flow control. */ ch1010832@2198: ret_val = e1000_setup_link(hw); ch1010832@2198: ch1010832@2198: /* Set the transmit descriptor write-back policy */ ch1010832@2198: if (hw->mac_type > e1000_82544) { ch1010832@2198: ctrl = er32(TXDCTL); ch1010832@2198: ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; ch1010832@2198: ew32(TXDCTL, ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82573) { ch1010832@2198: e1000_enable_tx_pkt_filtering(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: /* Enable retransmit on late collisions */ ch1010832@2198: reg_data = er32(TCTL); ch1010832@2198: reg_data |= E1000_TCTL_RTLC; ch1010832@2198: ew32(TCTL, reg_data); ch1010832@2198: ch1010832@2198: /* Configure Gigabit Carry Extend Padding */ ch1010832@2198: reg_data = er32(TCTL_EXT); ch1010832@2198: reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; ch1010832@2198: reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; ch1010832@2198: ew32(TCTL_EXT, reg_data); ch1010832@2198: ch1010832@2198: /* Configure Transmit Inter-Packet Gap */ ch1010832@2198: reg_data = er32(TIPG); ch1010832@2198: reg_data &= ~E1000_TIPG_IPGT_MASK; ch1010832@2198: reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; ch1010832@2198: ew32(TIPG, reg_data); ch1010832@2198: ch1010832@2198: reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); ch1010832@2198: reg_data &= ~0x00100000; ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); ch1010832@2198: /* Fall through */ ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: case e1000_ich8lan: ch1010832@2198: ctrl = er32(TXDCTL1); ch1010832@2198: ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; ch1010832@2198: ew32(TXDCTL1, ctrl); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82573) { ch1010832@2198: u32 gcr = er32(GCR); ch1010832@2198: gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; ch1010832@2198: ew32(GCR, gcr); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Clear all of the statistics registers (clear on read). It is ch1010832@2198: * important that we do this after we have tried to establish link ch1010832@2198: * because the symbol error count will increment wildly if there ch1010832@2198: * is no link. ch1010832@2198: */ ch1010832@2198: e1000_clear_hw_cntrs(hw); ch1010832@2198: ch1010832@2198: /* ICH8 No-snoop bits are opposite polarity. ch1010832@2198: * Set to snoop by default after reset. */ ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); ch1010832@2198: ch1010832@2198: if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || ch1010832@2198: hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { ch1010832@2198: ctrl_ext = er32(CTRL_EXT); ch1010832@2198: /* Relaxed ordering must be disabled to avoid a parity ch1010832@2198: * error crash in a PCI slot. */ ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Adjust SERDES output amplitude based on EEPROM setting. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u16 eeprom_data; ch1010832@2198: s32 ret_val; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_adjust_serdes_amplitude"); ch1010832@2198: ch1010832@2198: if (hw->media_type != e1000_media_type_internal_serdes) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82545_rev_3: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); ch1010832@2198: if (ret_val) { ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (eeprom_data != EEPROM_RESERVED_WORD) { ch1010832@2198: /* Adjust SERDES output amplitude only. */ ch1010832@2198: eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Configures flow control and link settings. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Determines which flow control settings to use. Calls the apropriate media- ch1010832@2198: * specific link configuration function. Configures the flow control settings. ch1010832@2198: * Assuming the adapter has a valid link partner, a valid link should be ch1010832@2198: * established. Assumes the hardware has previously been reset and the ch1010832@2198: * transmitter and receiver are not enabled. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_setup_link(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl_ext; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 eeprom_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_setup_link"); ch1010832@2198: ch1010832@2198: /* In the case of the phy reset being blocked, we already have a link. ch1010832@2198: * We do not have to set it up again. */ ch1010832@2198: if (e1000_check_phy_reset_block(hw)) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Read and store word 0x0F of the EEPROM. This word contains bits ch1010832@2198: * that determine the hardware's default PAUSE (flow control) mode, ch1010832@2198: * a bit that determines whether the HW defaults to enabling or ch1010832@2198: * disabling auto-negotiation, and the direction of the ch1010832@2198: * SW defined pins. If there is no SW over-ride of the flow ch1010832@2198: * control setting, then the variable hw->fc will ch1010832@2198: * be initialized based on a value in the EEPROM. ch1010832@2198: */ ch1010832@2198: if (hw->fc == E1000_FC_DEFAULT) { ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_ich8lan: ch1010832@2198: case e1000_82573: ch1010832@2198: hw->fc = E1000_FC_FULL; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, ch1010832@2198: 1, &eeprom_data); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("EEPROM Read Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) ch1010832@2198: hw->fc = E1000_FC_NONE; ch1010832@2198: else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == ch1010832@2198: EEPROM_WORD0F_ASM_DIR) ch1010832@2198: hw->fc = E1000_FC_TX_PAUSE; ch1010832@2198: else ch1010832@2198: hw->fc = E1000_FC_FULL; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* We want to save off the original Flow Control configuration just ch1010832@2198: * in case we get disconnected and then reconnected into a different ch1010832@2198: * hub or switch with different Flow Control capabilities. ch1010832@2198: */ ch1010832@2198: if (hw->mac_type == e1000_82542_rev2_0) ch1010832@2198: hw->fc &= (~E1000_FC_TX_PAUSE); ch1010832@2198: ch1010832@2198: if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) ch1010832@2198: hw->fc &= (~E1000_FC_RX_PAUSE); ch1010832@2198: ch1010832@2198: hw->original_fc = hw->fc; ch1010832@2198: ch1010832@2198: DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); ch1010832@2198: ch1010832@2198: /* Take the 4 bits from EEPROM word 0x0F that determine the initial ch1010832@2198: * polarity value for the SW controlled pins, and setup the ch1010832@2198: * Extended Device Control reg with that info. ch1010832@2198: * This is needed because one of the SW controlled pins is used for ch1010832@2198: * signal detection. So this should be done before e1000_setup_pcs_link() ch1010832@2198: * or e1000_phy_setup() is called. ch1010832@2198: */ ch1010832@2198: if (hw->mac_type == e1000_82543) { ch1010832@2198: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, ch1010832@2198: 1, &eeprom_data); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("EEPROM Read Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << ch1010832@2198: SWDPIO__EXT_SHIFT); ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Call the necessary subroutine to configure the link. */ ch1010832@2198: ret_val = (hw->media_type == e1000_media_type_copper) ? ch1010832@2198: e1000_setup_copper_link(hw) : ch1010832@2198: e1000_setup_fiber_serdes_link(hw); ch1010832@2198: ch1010832@2198: /* Initialize the flow control address, type, and PAUSE timer ch1010832@2198: * registers to their default values. This is done even if flow ch1010832@2198: * control is disabled, because it does not hurt anything to ch1010832@2198: * initialize these registers. ch1010832@2198: */ ch1010832@2198: DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); ch1010832@2198: ch1010832@2198: /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ ch1010832@2198: if (hw->mac_type != e1000_ich8lan) { ch1010832@2198: ew32(FCT, FLOW_CONTROL_TYPE); ch1010832@2198: ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); ch1010832@2198: ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); ch1010832@2198: } ch1010832@2198: ch1010832@2198: ew32(FCTTV, hw->fc_pause_time); ch1010832@2198: ch1010832@2198: /* Set the flow control receive threshold registers. Normally, ch1010832@2198: * these registers will be set to a default threshold that may be ch1010832@2198: * adjusted later by the driver's runtime code. However, if the ch1010832@2198: * ability to transmit pause frames in not enabled, then these ch1010832@2198: * registers will be set to 0. ch1010832@2198: */ ch1010832@2198: if (!(hw->fc & E1000_FC_TX_PAUSE)) { ch1010832@2198: ew32(FCRTL, 0); ch1010832@2198: ew32(FCRTH, 0); ch1010832@2198: } else { ch1010832@2198: /* We need to set up the Receive Threshold high and low water marks ch1010832@2198: * as well as (optionally) enabling the transmission of XON frames. ch1010832@2198: */ ch1010832@2198: if (hw->fc_send_xon) { ch1010832@2198: ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); ch1010832@2198: ew32(FCRTH, hw->fc_high_water); ch1010832@2198: } else { ch1010832@2198: ew32(FCRTL, hw->fc_low_water); ch1010832@2198: ew32(FCRTH, hw->fc_high_water); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Sets up link for a fiber based or serdes based adapter ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Manipulates Physical Coding Sublayer functions in order to configure ch1010832@2198: * link. Assumes the hardware has been previously reset and the transmitter ch1010832@2198: * and receiver are not enabled. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: u32 status; ch1010832@2198: u32 txcw = 0; ch1010832@2198: u32 i; ch1010832@2198: u32 signal = 0; ch1010832@2198: s32 ret_val; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_setup_fiber_serdes_link"); ch1010832@2198: ch1010832@2198: /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists ch1010832@2198: * until explicitly turned off or a power cycle is performed. A read to ch1010832@2198: * the register does not indicate its status. Therefore, we ensure ch1010832@2198: * loopback mode is disabled during initialization. ch1010832@2198: */ ch1010832@2198: if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) ch1010832@2198: ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK); ch1010832@2198: ch1010832@2198: /* On adapters with a MAC newer than 82544, SWDP 1 will be ch1010832@2198: * set when the optics detect a signal. On older adapters, it will be ch1010832@2198: * cleared when there is a signal. This applies to fiber media only. ch1010832@2198: * If we're on serdes media, adjust the output amplitude to value ch1010832@2198: * set in the EEPROM. ch1010832@2198: */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) ch1010832@2198: signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; ch1010832@2198: ch1010832@2198: ret_val = e1000_adjust_serdes_amplitude(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Take the link out of reset */ ch1010832@2198: ctrl &= ~(E1000_CTRL_LRST); ch1010832@2198: ch1010832@2198: /* Adjust VCO speed to improve BER performance */ ch1010832@2198: ret_val = e1000_set_vco_speed(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: e1000_config_collision_dist(hw); ch1010832@2198: ch1010832@2198: /* Check for a software override of the flow control settings, and setup ch1010832@2198: * the device accordingly. If auto-negotiation is enabled, then software ch1010832@2198: * will have to set the "PAUSE" bits to the correct value in the Tranmsit ch1010832@2198: * Config Word Register (TXCW) and re-start auto-negotiation. However, if ch1010832@2198: * auto-negotiation is disabled, then software will have to manually ch1010832@2198: * configure the two flow control enable bits in the CTRL register. ch1010832@2198: * ch1010832@2198: * The possible values of the "fc" parameter are: ch1010832@2198: * 0: Flow control is completely disabled ch1010832@2198: * 1: Rx flow control is enabled (we can receive pause frames, but ch1010832@2198: * not send pause frames). ch1010832@2198: * 2: Tx flow control is enabled (we can send pause frames but we do ch1010832@2198: * not support receiving pause frames). ch1010832@2198: * 3: Both Rx and TX flow control (symmetric) are enabled. ch1010832@2198: */ ch1010832@2198: switch (hw->fc) { ch1010832@2198: case E1000_FC_NONE: ch1010832@2198: /* Flow control is completely disabled by a software over-ride. */ ch1010832@2198: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); ch1010832@2198: break; ch1010832@2198: case E1000_FC_RX_PAUSE: ch1010832@2198: /* RX Flow control is enabled and TX Flow control is disabled by a ch1010832@2198: * software over-ride. Since there really isn't a way to advertise ch1010832@2198: * that we are capable of RX Pause ONLY, we will advertise that we ch1010832@2198: * support both symmetric and asymmetric RX PAUSE. Later, we will ch1010832@2198: * disable the adapter's ability to send PAUSE frames. ch1010832@2198: */ ch1010832@2198: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ch1010832@2198: break; ch1010832@2198: case E1000_FC_TX_PAUSE: ch1010832@2198: /* TX Flow control is enabled, and RX Flow control is disabled, by a ch1010832@2198: * software over-ride. ch1010832@2198: */ ch1010832@2198: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); ch1010832@2198: break; ch1010832@2198: case E1000_FC_FULL: ch1010832@2198: /* Flow control (both RX and TX) is enabled by a software over-ride. */ ch1010832@2198: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: DEBUGOUT("Flow control param set incorrectly\n"); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Since auto-negotiation is enabled, take the link out of reset (the link ch1010832@2198: * will be in reset, because we previously reset the chip). This will ch1010832@2198: * restart auto-negotiation. If auto-neogtiation is successful then the ch1010832@2198: * link-up status bit will be set and the flow control enable bits (RFCE ch1010832@2198: * and TFCE) will be set according to their negotiated value. ch1010832@2198: */ ch1010832@2198: DEBUGOUT("Auto-negotiation enabled\n"); ch1010832@2198: ch1010832@2198: ew32(TXCW, txcw); ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: hw->txcw = txcw; ch1010832@2198: msleep(1); ch1010832@2198: ch1010832@2198: /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" ch1010832@2198: * indication in the Device Status Register. Time-out if a link isn't ch1010832@2198: * seen in 500 milliseconds seconds (Auto-negotiation should complete in ch1010832@2198: * less than 500 milliseconds even if the other end is doing it in SW). ch1010832@2198: * For internal serdes, we just assume a signal is present, then poll. ch1010832@2198: */ ch1010832@2198: if (hw->media_type == e1000_media_type_internal_serdes || ch1010832@2198: (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { ch1010832@2198: DEBUGOUT("Looking for Link\n"); ch1010832@2198: for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { ch1010832@2198: msleep(10); ch1010832@2198: status = er32(STATUS); ch1010832@2198: if (status & E1000_STATUS_LU) break; ch1010832@2198: } ch1010832@2198: if (i == (LINK_UP_TIMEOUT / 10)) { ch1010832@2198: DEBUGOUT("Never got a valid link from auto-neg!!!\n"); ch1010832@2198: hw->autoneg_failed = 1; ch1010832@2198: /* AutoNeg failed to achieve a link, so we'll call ch1010832@2198: * e1000_check_for_link. This routine will force the link up if ch1010832@2198: * we detect a signal. This will allow us to communicate with ch1010832@2198: * non-autonegotiating link partners. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_check_for_link(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error while checking for link\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: hw->autoneg_failed = 0; ch1010832@2198: } else { ch1010832@2198: hw->autoneg_failed = 0; ch1010832@2198: DEBUGOUT("Valid Link Found\n"); ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: DEBUGOUT("No Signal Detected\n"); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Make sure we have a valid PHY and change PHY mode before link setup. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_copper_link_preconfig"); ch1010832@2198: ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: /* With 82543, we need to force speed and duplex on the MAC equal to what ch1010832@2198: * the PHY speed and duplex configuration is. In addition, we need to ch1010832@2198: * perform a hardware reset on the PHY to take it out of reset. ch1010832@2198: */ ch1010832@2198: if (hw->mac_type > e1000_82543) { ch1010832@2198: ctrl |= E1000_CTRL_SLU; ch1010832@2198: ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: } else { ch1010832@2198: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: ret_val = e1000_phy_hw_reset(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Make sure we have a valid PHY */ ch1010832@2198: ret_val = e1000_detect_gig_phy(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error, did not detect valid phy.\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: DEBUGOUT1("Phy ID = %x \n", hw->phy_id); ch1010832@2198: ch1010832@2198: /* Set PHY to class A mode (if necessary) */ ch1010832@2198: ret_val = e1000_set_phy_mode(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82545_rev_3) || ch1010832@2198: (hw->mac_type == e1000_82546_rev_3)) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: phy_data |= 0x00000008; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type <= e1000_82543 || ch1010832@2198: hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || ch1010832@2198: hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) ch1010832@2198: hw->phy_reset_disable = false; ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /******************************************************************** ch1010832@2198: * Copper link setup for e1000_phy_igp series. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *********************************************************************/ ch1010832@2198: static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 led_ctrl; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_copper_link_igp_setup"); ch1010832@2198: ch1010832@2198: if (hw->phy_reset_disable) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: ret_val = e1000_phy_reset(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Resetting the PHY\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Wait 15ms for MAC to configure PHY from eeprom settings */ ch1010832@2198: msleep(15); ch1010832@2198: if (hw->mac_type != e1000_ich8lan) { ch1010832@2198: /* Configure activity LED after PHY reset */ ch1010832@2198: led_ctrl = er32(LEDCTL); ch1010832@2198: led_ctrl &= IGP_ACTIVITY_LED_MASK; ch1010832@2198: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ch1010832@2198: ew32(LEDCTL, led_ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ ch1010832@2198: if (hw->phy_type == e1000_phy_igp) { ch1010832@2198: /* disable lplu d3 during driver init */ ch1010832@2198: ret_val = e1000_set_d3_lplu_state(hw, false); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Disabling LPLU D3\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* disable lplu d0 during driver init */ ch1010832@2198: ret_val = e1000_set_d0_lplu_state(hw, false); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Disabling LPLU D0\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: /* Configure mdi-mdix settings */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@2198: hw->dsp_config_state = e1000_dsp_config_disabled; ch1010832@2198: /* Force MDI for earlier revs of the IGP PHY */ ch1010832@2198: phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); ch1010832@2198: hw->mdix = 1; ch1010832@2198: ch1010832@2198: } else { ch1010832@2198: hw->dsp_config_state = e1000_dsp_config_enabled; ch1010832@2198: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ch1010832@2198: ch1010832@2198: switch (hw->mdix) { ch1010832@2198: case 1: ch1010832@2198: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ch1010832@2198: break; ch1010832@2198: case 2: ch1010832@2198: phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; ch1010832@2198: break; ch1010832@2198: case 0: ch1010832@2198: default: ch1010832@2198: phy_data |= IGP01E1000_PSCR_AUTO_MDIX; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* set auto-master slave resolution settings */ ch1010832@2198: if (hw->autoneg) { ch1010832@2198: e1000_ms_type phy_ms_setting = hw->master_slave; ch1010832@2198: ch1010832@2198: if (hw->ffe_config_state == e1000_ffe_config_active) ch1010832@2198: hw->ffe_config_state = e1000_ffe_config_enabled; ch1010832@2198: ch1010832@2198: if (hw->dsp_config_state == e1000_dsp_config_activated) ch1010832@2198: hw->dsp_config_state = e1000_dsp_config_enabled; ch1010832@2198: ch1010832@2198: /* when autonegotiation advertisment is only 1000Mbps then we ch1010832@2198: * should disable SmartSpeed and enable Auto MasterSlave ch1010832@2198: * resolution as hardware default. */ ch1010832@2198: if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { ch1010832@2198: /* Disable SmartSpeed */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: /* Set auto Master/Slave resolution process */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: phy_data &= ~CR_1000T_MS_ENABLE; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* load defaults for future use */ ch1010832@2198: hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? ch1010832@2198: ((phy_data & CR_1000T_MS_VALUE) ? ch1010832@2198: e1000_ms_force_master : ch1010832@2198: e1000_ms_force_slave) : ch1010832@2198: e1000_ms_auto; ch1010832@2198: ch1010832@2198: switch (phy_ms_setting) { ch1010832@2198: case e1000_ms_force_master: ch1010832@2198: phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); ch1010832@2198: break; ch1010832@2198: case e1000_ms_force_slave: ch1010832@2198: phy_data |= CR_1000T_MS_ENABLE; ch1010832@2198: phy_data &= ~(CR_1000T_MS_VALUE); ch1010832@2198: break; ch1010832@2198: case e1000_ms_auto: ch1010832@2198: phy_data &= ~CR_1000T_MS_ENABLE; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /******************************************************************** ch1010832@2198: * Copper link setup for e1000_phy_gg82563 series. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *********************************************************************/ ch1010832@2198: static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: u32 reg_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_copper_link_ggp_setup"); ch1010832@2198: ch1010832@2198: if (!hw->phy_reset_disable) { ch1010832@2198: ch1010832@2198: /* Enable CRS on TX for half-duplex operation. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ch1010832@2198: /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ ch1010832@2198: phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Options: ch1010832@2198: * MDI/MDI-X = 0 (default) ch1010832@2198: * 0 - Auto for all speeds ch1010832@2198: * 1 - MDI mode ch1010832@2198: * 2 - MDI-X mode ch1010832@2198: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; ch1010832@2198: ch1010832@2198: switch (hw->mdix) { ch1010832@2198: case 1: ch1010832@2198: phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; ch1010832@2198: break; ch1010832@2198: case 2: ch1010832@2198: phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; ch1010832@2198: break; ch1010832@2198: case 0: ch1010832@2198: default: ch1010832@2198: phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Options: ch1010832@2198: * disable_polarity_correction = 0 (default) ch1010832@2198: * Automatic Correction for Reversed Cable Polarity ch1010832@2198: * 0 - Disabled ch1010832@2198: * 1 - Enabled ch1010832@2198: */ ch1010832@2198: phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ch1010832@2198: if (hw->disable_polarity_correction == 1) ch1010832@2198: phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* SW Reset the PHY so all changes take effect */ ch1010832@2198: ret_val = e1000_phy_reset(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Resetting the PHY\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } /* phy_reset_disable */ ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_80003es2lan) { ch1010832@2198: /* Bypass RX and TX FIFO's */ ch1010832@2198: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, ch1010832@2198: E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | ch1010832@2198: E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: reg_data = er32(CTRL_EXT); ch1010832@2198: reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); ch1010832@2198: ew32(CTRL_EXT, reg_data); ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Do not init these registers when the HW is in IAMT mode, since the ch1010832@2198: * firmware will have already initialized them. We only initialize ch1010832@2198: * them if the HW is not in IAMT mode. ch1010832@2198: */ ch1010832@2198: if (!e1000_check_mng_mode(hw)) { ch1010832@2198: /* Enable Electrical Idle on the PHY */ ch1010832@2198: phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ch1010832@2198: phy_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Workaround: Disable padding in Kumeran interface in the MAC ch1010832@2198: * and in the PHY to avoid CRC errors. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: phy_data |= GG82563_ICR_DIS_PADDING; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /******************************************************************** ch1010832@2198: * Copper link setup for e1000_phy_m88 series. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *********************************************************************/ ch1010832@2198: static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_copper_link_mgp_setup"); ch1010832@2198: ch1010832@2198: if (hw->phy_reset_disable) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Enable CRS on TX. This must be set for half-duplex operation. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ch1010832@2198: ch1010832@2198: /* Options: ch1010832@2198: * MDI/MDI-X = 0 (default) ch1010832@2198: * 0 - Auto for all speeds ch1010832@2198: * 1 - MDI mode ch1010832@2198: * 2 - MDI-X mode ch1010832@2198: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ch1010832@2198: */ ch1010832@2198: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ch1010832@2198: ch1010832@2198: switch (hw->mdix) { ch1010832@2198: case 1: ch1010832@2198: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; ch1010832@2198: break; ch1010832@2198: case 2: ch1010832@2198: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; ch1010832@2198: break; ch1010832@2198: case 3: ch1010832@2198: phy_data |= M88E1000_PSCR_AUTO_X_1000T; ch1010832@2198: break; ch1010832@2198: case 0: ch1010832@2198: default: ch1010832@2198: phy_data |= M88E1000_PSCR_AUTO_X_MODE; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Options: ch1010832@2198: * disable_polarity_correction = 0 (default) ch1010832@2198: * Automatic Correction for Reversed Cable Polarity ch1010832@2198: * 0 - Disabled ch1010832@2198: * 1 - Enabled ch1010832@2198: */ ch1010832@2198: phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; ch1010832@2198: if (hw->disable_polarity_correction == 1) ch1010832@2198: phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (hw->phy_revision < M88E1011_I_REV_4) { ch1010832@2198: /* Force TX_CLK in the Extended PHY Specific Control Register ch1010832@2198: * to 25MHz clock. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= M88E1000_EPSCR_TX_CLK_25; ch1010832@2198: ch1010832@2198: if ((hw->phy_revision == E1000_REVISION_2) && ch1010832@2198: (hw->phy_id == M88E1111_I_PHY_ID)) { ch1010832@2198: /* Vidalia Phy, set the downshift counter to 5x */ ch1010832@2198: phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); ch1010832@2198: phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, ch1010832@2198: M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else { ch1010832@2198: /* Configure Master and Slave downshift values */ ch1010832@2198: phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | ch1010832@2198: M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); ch1010832@2198: phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | ch1010832@2198: M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ch1010832@2198: ret_val = e1000_write_phy_reg(hw, ch1010832@2198: M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* SW Reset the PHY so all changes take effect */ ch1010832@2198: ret_val = e1000_phy_reset(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Resetting the PHY\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /******************************************************************** ch1010832@2198: * Setup auto-negotiation and flow control advertisements, ch1010832@2198: * and then perform auto-negotiation. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *********************************************************************/ ch1010832@2198: static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_copper_link_autoneg"); ch1010832@2198: ch1010832@2198: /* Perform some bounds checking on the hw->autoneg_advertised ch1010832@2198: * parameter. If this variable is zero, then set it to the default. ch1010832@2198: */ ch1010832@2198: hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; ch1010832@2198: ch1010832@2198: /* If autoneg_advertised is zero, we assume it was not defaulted ch1010832@2198: * by the calling code so we set to advertise full capability. ch1010832@2198: */ ch1010832@2198: if (hw->autoneg_advertised == 0) ch1010832@2198: hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; ch1010832@2198: ch1010832@2198: /* IFE phy only supports 10/100 */ ch1010832@2198: if (hw->phy_type == e1000_phy_ife) ch1010832@2198: hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; ch1010832@2198: ch1010832@2198: DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); ch1010832@2198: ret_val = e1000_phy_setup_autoneg(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Setting up Auto-Negotiation\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: DEBUGOUT("Restarting Auto-Neg\n"); ch1010832@2198: ch1010832@2198: /* Restart auto-negotiation by setting the Auto Neg Enable bit and ch1010832@2198: * the Auto Neg Restart bit in the PHY control register. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Does the user want to wait for Auto-Neg to complete here, or ch1010832@2198: * check at a later time (for example, callback routine). ch1010832@2198: */ ch1010832@2198: if (hw->wait_autoneg_complete) { ch1010832@2198: ret_val = e1000_wait_autoneg(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error while waiting for autoneg to complete\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: hw->get_link_status = true; ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Config the MAC and the PHY after link is up. ch1010832@2198: * 1) Set up the MAC to the current PHY speed/duplex ch1010832@2198: * if we are on 82543. If we ch1010832@2198: * are on newer silicon, we only need to configure ch1010832@2198: * collision distance in the Transmit Control Register. ch1010832@2198: * 2) Set up flow control on the MAC to that established with ch1010832@2198: * the link partner. ch1010832@2198: * 3) Config DSP to improve Gigabit link quality for some PHY revisions. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: DEBUGFUNC("e1000_copper_link_postconfig"); ch1010832@2198: ch1010832@2198: if (hw->mac_type >= e1000_82544) { ch1010832@2198: e1000_config_collision_dist(hw); ch1010832@2198: } else { ch1010832@2198: ret_val = e1000_config_mac_to_phy(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error configuring MAC to PHY settings\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ret_val = e1000_config_fc_after_link_up(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Configuring Flow Control\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Config DSP to improve Giga link quality */ ch1010832@2198: if (hw->phy_type == e1000_phy_igp) { ch1010832@2198: ret_val = e1000_config_dsp_after_link_change(hw, true); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Configuring DSP after link up\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Detects which PHY is present and setup the speed and duplex ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_setup_copper_link(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 i; ch1010832@2198: u16 phy_data; ch1010832@2198: u16 reg_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_setup_copper_link"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: case e1000_ich8lan: ch1010832@2198: /* Set the mac to wait the maximum time between each ch1010832@2198: * iteration and increase the max iterations when ch1010832@2198: * polling the phy; this fixes erroneous timeouts at 10Mbps. */ ch1010832@2198: ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: reg_data |= 0x3F; ch1010832@2198: ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Check if it is a valid PHY and set PHY mode if necessary. */ ch1010832@2198: ret_val = e1000_copper_link_preconfig(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: /* Kumeran registers are written-only */ ch1010832@2198: reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; ch1010832@2198: reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; ch1010832@2198: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, ch1010832@2198: reg_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->phy_type == e1000_phy_igp || ch1010832@2198: hw->phy_type == e1000_phy_igp_3 || ch1010832@2198: hw->phy_type == e1000_phy_igp_2) { ch1010832@2198: ret_val = e1000_copper_link_igp_setup(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else if (hw->phy_type == e1000_phy_m88) { ch1010832@2198: ret_val = e1000_copper_link_mgp_setup(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else if (hw->phy_type == e1000_phy_gg82563) { ch1010832@2198: ret_val = e1000_copper_link_ggp_setup(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->autoneg) { ch1010832@2198: /* Setup autoneg and flow control advertisement ch1010832@2198: * and perform autonegotiation */ ch1010832@2198: ret_val = e1000_copper_link_autoneg(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else { ch1010832@2198: /* PHY will be set to 10H, 10F, 100H,or 100F ch1010832@2198: * depending on value from forced_speed_duplex. */ ch1010832@2198: DEBUGOUT("Forcing speed and duplex\n"); ch1010832@2198: ret_val = e1000_phy_force_speed_duplex(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Forcing Speed and Duplex\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Check link status. Wait up to 100 microseconds for link to become ch1010832@2198: * valid. ch1010832@2198: */ ch1010832@2198: for (i = 0; i < 10; i++) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (phy_data & MII_SR_LINK_STATUS) { ch1010832@2198: /* Config the MAC and PHY after link is up */ ch1010832@2198: ret_val = e1000_copper_link_postconfig(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: DEBUGOUT("Valid link established!!!\n"); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: udelay(10); ch1010832@2198: } ch1010832@2198: ch1010832@2198: DEBUGOUT("Unable to establish link!!!\n"); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Configure the MAC-to-PHY interface for 10/100Mbps ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex) ch1010832@2198: { ch1010832@2198: s32 ret_val = E1000_SUCCESS; ch1010832@2198: u32 tipg; ch1010832@2198: u16 reg_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_configure_kmrn_for_10_100"); ch1010832@2198: ch1010832@2198: reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; ch1010832@2198: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, ch1010832@2198: reg_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Configure Transmit Inter-Packet Gap */ ch1010832@2198: tipg = er32(TIPG); ch1010832@2198: tipg &= ~E1000_TIPG_IPGT_MASK; ch1010832@2198: tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; ch1010832@2198: ew32(TIPG, tipg); ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (duplex == HALF_DUPLEX) ch1010832@2198: reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; ch1010832@2198: else ch1010832@2198: reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); ch1010832@2198: ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val = E1000_SUCCESS; ch1010832@2198: u16 reg_data; ch1010832@2198: u32 tipg; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_configure_kmrn_for_1000"); ch1010832@2198: ch1010832@2198: reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; ch1010832@2198: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, ch1010832@2198: reg_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Configure Transmit Inter-Packet Gap */ ch1010832@2198: tipg = er32(TIPG); ch1010832@2198: tipg &= ~E1000_TIPG_IPGT_MASK; ch1010832@2198: tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; ch1010832@2198: ew32(TIPG, tipg); ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); ch1010832@2198: ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Configures PHY autoneg and flow control advertisement settings ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 mii_autoneg_adv_reg; ch1010832@2198: u16 mii_1000t_ctrl_reg; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_setup_autoneg"); ch1010832@2198: ch1010832@2198: /* Read the MII Auto-Neg Advertisement Register (Address 4). */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (hw->phy_type != e1000_phy_ife) { ch1010832@2198: /* Read the MII 1000Base-T Control Register (Address 9). */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else ch1010832@2198: mii_1000t_ctrl_reg=0; ch1010832@2198: ch1010832@2198: /* Need to parse both autoneg_advertised and fc and set up ch1010832@2198: * the appropriate PHY registers. First we will parse for ch1010832@2198: * autoneg_advertised software override. Since we can advertise ch1010832@2198: * a plethora of combinations, we need to check each bit ch1010832@2198: * individually. ch1010832@2198: */ ch1010832@2198: ch1010832@2198: /* First we clear all the 10/100 mb speed bits in the Auto-Neg ch1010832@2198: * Advertisement Register (Address 4) and the 1000 mb speed bits in ch1010832@2198: * the 1000Base-T Control Register (Address 9). ch1010832@2198: */ ch1010832@2198: mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; ch1010832@2198: mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; ch1010832@2198: ch1010832@2198: DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); ch1010832@2198: ch1010832@2198: /* Do we want to advertise 10 Mb Half Duplex? */ ch1010832@2198: if (hw->autoneg_advertised & ADVERTISE_10_HALF) { ch1010832@2198: DEBUGOUT("Advertise 10mb Half duplex\n"); ch1010832@2198: mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Do we want to advertise 10 Mb Full Duplex? */ ch1010832@2198: if (hw->autoneg_advertised & ADVERTISE_10_FULL) { ch1010832@2198: DEBUGOUT("Advertise 10mb Full duplex\n"); ch1010832@2198: mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Do we want to advertise 100 Mb Half Duplex? */ ch1010832@2198: if (hw->autoneg_advertised & ADVERTISE_100_HALF) { ch1010832@2198: DEBUGOUT("Advertise 100mb Half duplex\n"); ch1010832@2198: mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Do we want to advertise 100 Mb Full Duplex? */ ch1010832@2198: if (hw->autoneg_advertised & ADVERTISE_100_FULL) { ch1010832@2198: DEBUGOUT("Advertise 100mb Full duplex\n"); ch1010832@2198: mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ ch1010832@2198: if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { ch1010832@2198: DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Do we want to advertise 1000 Mb Full Duplex? */ ch1010832@2198: if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { ch1010832@2198: DEBUGOUT("Advertise 1000mb Full duplex\n"); ch1010832@2198: mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; ch1010832@2198: if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Check for a software override of the flow control settings, and ch1010832@2198: * setup the PHY advertisement registers accordingly. If ch1010832@2198: * auto-negotiation is enabled, then software will have to set the ch1010832@2198: * "PAUSE" bits to the correct value in the Auto-Negotiation ch1010832@2198: * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. ch1010832@2198: * ch1010832@2198: * The possible values of the "fc" parameter are: ch1010832@2198: * 0: Flow control is completely disabled ch1010832@2198: * 1: Rx flow control is enabled (we can receive pause frames ch1010832@2198: * but not send pause frames). ch1010832@2198: * 2: Tx flow control is enabled (we can send pause frames ch1010832@2198: * but we do not support receiving pause frames). ch1010832@2198: * 3: Both Rx and TX flow control (symmetric) are enabled. ch1010832@2198: * other: No software override. The flow control configuration ch1010832@2198: * in the EEPROM is used. ch1010832@2198: */ ch1010832@2198: switch (hw->fc) { ch1010832@2198: case E1000_FC_NONE: /* 0 */ ch1010832@2198: /* Flow control (RX & TX) is completely disabled by a ch1010832@2198: * software over-ride. ch1010832@2198: */ ch1010832@2198: mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ch1010832@2198: break; ch1010832@2198: case E1000_FC_RX_PAUSE: /* 1 */ ch1010832@2198: /* RX Flow control is enabled, and TX Flow control is ch1010832@2198: * disabled, by a software over-ride. ch1010832@2198: */ ch1010832@2198: /* Since there really isn't a way to advertise that we are ch1010832@2198: * capable of RX Pause ONLY, we will advertise that we ch1010832@2198: * support both symmetric and asymmetric RX PAUSE. Later ch1010832@2198: * (in e1000_config_fc_after_link_up) we will disable the ch1010832@2198: *hw's ability to send PAUSE frames. ch1010832@2198: */ ch1010832@2198: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ch1010832@2198: break; ch1010832@2198: case E1000_FC_TX_PAUSE: /* 2 */ ch1010832@2198: /* TX Flow control is enabled, and RX Flow control is ch1010832@2198: * disabled, by a software over-ride. ch1010832@2198: */ ch1010832@2198: mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; ch1010832@2198: mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; ch1010832@2198: break; ch1010832@2198: case E1000_FC_FULL: /* 3 */ ch1010832@2198: /* Flow control (both RX and TX) is enabled by a software ch1010832@2198: * over-ride. ch1010832@2198: */ ch1010832@2198: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: DEBUGOUT("Flow control param set incorrectly\n"); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ch1010832@2198: ch1010832@2198: if (hw->phy_type != e1000_phy_ife) { ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Force PHY speed and duplex settings to hw->forced_speed_duplex ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 mii_ctrl_reg; ch1010832@2198: u16 mii_status_reg; ch1010832@2198: u16 phy_data; ch1010832@2198: u16 i; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_force_speed_duplex"); ch1010832@2198: ch1010832@2198: /* Turn off Flow control if we are forcing speed and duplex. */ ch1010832@2198: hw->fc = E1000_FC_NONE; ch1010832@2198: ch1010832@2198: DEBUGOUT1("hw->fc = %d\n", hw->fc); ch1010832@2198: ch1010832@2198: /* Read the Device Control Register. */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ ch1010832@2198: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ch1010832@2198: ctrl &= ~(DEVICE_SPEED_MASK); ch1010832@2198: ch1010832@2198: /* Clear the Auto Speed Detect Enable bit. */ ch1010832@2198: ctrl &= ~E1000_CTRL_ASDE; ch1010832@2198: ch1010832@2198: /* Read the MII Control Register. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* We need to disable autoneg in order to force link and duplex. */ ch1010832@2198: ch1010832@2198: mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; ch1010832@2198: ch1010832@2198: /* Are we forcing Full or Half Duplex? */ ch1010832@2198: if (hw->forced_speed_duplex == e1000_100_full || ch1010832@2198: hw->forced_speed_duplex == e1000_10_full) { ch1010832@2198: /* We want to force full duplex so we SET the full duplex bits in the ch1010832@2198: * Device and MII Control Registers. ch1010832@2198: */ ch1010832@2198: ctrl |= E1000_CTRL_FD; ch1010832@2198: mii_ctrl_reg |= MII_CR_FULL_DUPLEX; ch1010832@2198: DEBUGOUT("Full Duplex\n"); ch1010832@2198: } else { ch1010832@2198: /* We want to force half duplex so we CLEAR the full duplex bits in ch1010832@2198: * the Device and MII Control Registers. ch1010832@2198: */ ch1010832@2198: ctrl &= ~E1000_CTRL_FD; ch1010832@2198: mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; ch1010832@2198: DEBUGOUT("Half Duplex\n"); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Are we forcing 100Mbps??? */ ch1010832@2198: if (hw->forced_speed_duplex == e1000_100_full || ch1010832@2198: hw->forced_speed_duplex == e1000_100_half) { ch1010832@2198: /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ ch1010832@2198: ctrl |= E1000_CTRL_SPD_100; ch1010832@2198: mii_ctrl_reg |= MII_CR_SPEED_100; ch1010832@2198: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); ch1010832@2198: DEBUGOUT("Forcing 100mb "); ch1010832@2198: } else { ch1010832@2198: /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ ch1010832@2198: ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); ch1010832@2198: mii_ctrl_reg |= MII_CR_SPEED_10; ch1010832@2198: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); ch1010832@2198: DEBUGOUT("Forcing 10mb "); ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_config_collision_dist(hw); ch1010832@2198: ch1010832@2198: /* Write the configured values back to the Device Control Reg. */ ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: ch1010832@2198: if ((hw->phy_type == e1000_phy_m88) || ch1010832@2198: (hw->phy_type == e1000_phy_gg82563)) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ch1010832@2198: * forced whenever speed are duplex are forced. ch1010832@2198: */ ch1010832@2198: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); ch1010832@2198: ch1010832@2198: /* Need to reset the PHY or these changes will be ignored */ ch1010832@2198: mii_ctrl_reg |= MII_CR_RESET; ch1010832@2198: ch1010832@2198: /* Disable MDI-X support for 10/100 */ ch1010832@2198: } else if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IFE_PMC_AUTO_MDIX; ch1010832@2198: phy_data &= ~IFE_PMC_FORCE_MDIX; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: } else { ch1010832@2198: /* Clear Auto-Crossover to force MDI manually. IGP requires MDI ch1010832@2198: * forced whenever speed or duplex are forced. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ch1010832@2198: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Write back the modified PHY MII control register. */ ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: udelay(1); ch1010832@2198: ch1010832@2198: /* The wait_autoneg_complete flag may be a little misleading here. ch1010832@2198: * Since we are forcing speed and duplex, Auto-Neg is not enabled. ch1010832@2198: * But we do want to delay for a period while forcing only so we ch1010832@2198: * don't generate false No Link messages. So we will wait here ch1010832@2198: * only if the user has set wait_autoneg_complete to 1, which is ch1010832@2198: * the default. ch1010832@2198: */ ch1010832@2198: if (hw->wait_autoneg_complete) { ch1010832@2198: /* We will wait for autoneg to complete. */ ch1010832@2198: DEBUGOUT("Waiting for forced speed/duplex link.\n"); ch1010832@2198: mii_status_reg = 0; ch1010832@2198: ch1010832@2198: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ ch1010832@2198: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@2198: /* Read the MII Status Register and wait for Auto-Neg Complete bit ch1010832@2198: * to be set. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (mii_status_reg & MII_SR_LINK_STATUS) break; ch1010832@2198: msleep(100); ch1010832@2198: } ch1010832@2198: if ((i == 0) && ch1010832@2198: ((hw->phy_type == e1000_phy_m88) || ch1010832@2198: (hw->phy_type == e1000_phy_gg82563))) { ch1010832@2198: /* We didn't get link. Reset the DSP and wait again for link. */ ch1010832@2198: ret_val = e1000_phy_reset_dsp(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error Resetting PHY DSP\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: /* This loop will early-out if the link condition has been met. */ ch1010832@2198: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@2198: if (mii_status_reg & MII_SR_LINK_STATUS) break; ch1010832@2198: msleep(100); ch1010832@2198: /* Read the MII Status Register and wait for Auto-Neg Complete bit ch1010832@2198: * to be set. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->phy_type == e1000_phy_m88) { ch1010832@2198: /* Because we reset the PHY above, we need to re-force TX_CLK in the ch1010832@2198: * Extended PHY Specific Control Register to 25MHz clock. This value ch1010832@2198: * defaults back to a 2.5MHz clock when the PHY is reset. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= M88E1000_EPSCR_TX_CLK_25; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* In addition, because of the s/w reset above, we need to enable CRS on ch1010832@2198: * TX. This must be set for both full and half duplex operation. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && ch1010832@2198: (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || ch1010832@2198: hw->forced_speed_duplex == e1000_10_half)) { ch1010832@2198: ret_val = e1000_polarity_reversal_workaround(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } else if (hw->phy_type == e1000_phy_gg82563) { ch1010832@2198: /* The TX_CLK of the Extended PHY Specific Control Register defaults ch1010832@2198: * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if ch1010832@2198: * we're not in a forced 10/duplex configuration. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~GG82563_MSCR_TX_CLK_MASK; ch1010832@2198: if ((hw->forced_speed_duplex == e1000_10_full) || ch1010832@2198: (hw->forced_speed_duplex == e1000_10_half)) ch1010832@2198: phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; ch1010832@2198: else ch1010832@2198: phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; ch1010832@2198: ch1010832@2198: /* Also due to the reset, we need to enable CRS on Tx. */ ch1010832@2198: phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Sets the collision distance in the Transmit Control register ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Link should have been established previously. Reads the speed and duplex ch1010832@2198: * information from the Device Status register. ch1010832@2198: ******************************************************************************/ ch1010832@2198: void e1000_config_collision_dist(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 tctl, coll_dist; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_config_collision_dist"); ch1010832@2198: ch1010832@2198: if (hw->mac_type < e1000_82543) ch1010832@2198: coll_dist = E1000_COLLISION_DISTANCE_82542; ch1010832@2198: else ch1010832@2198: coll_dist = E1000_COLLISION_DISTANCE; ch1010832@2198: ch1010832@2198: tctl = er32(TCTL); ch1010832@2198: ch1010832@2198: tctl &= ~E1000_TCTL_COLD; ch1010832@2198: tctl |= coll_dist << E1000_COLD_SHIFT; ch1010832@2198: ch1010832@2198: ew32(TCTL, tctl); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Sets MAC speed and duplex settings to reflect the those in the PHY ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * mii_reg - data to write to the MII control register ch1010832@2198: * ch1010832@2198: * The contents of the PHY register containing the needed information need to ch1010832@2198: * be passed in. ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_config_mac_to_phy"); ch1010832@2198: ch1010832@2198: /* 82544 or newer MAC, Auto Speed Detection takes care of ch1010832@2198: * MAC speed/duplex configuration.*/ ch1010832@2198: if (hw->mac_type >= e1000_82544) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Read the Device Control Register and set the bits to Force Speed ch1010832@2198: * and Duplex. ch1010832@2198: */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ch1010832@2198: ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); ch1010832@2198: ch1010832@2198: /* Set up duplex in the Device Control and Transmit Control ch1010832@2198: * registers depending on negotiated values. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (phy_data & M88E1000_PSSR_DPLX) ch1010832@2198: ctrl |= E1000_CTRL_FD; ch1010832@2198: else ch1010832@2198: ctrl &= ~E1000_CTRL_FD; ch1010832@2198: ch1010832@2198: e1000_config_collision_dist(hw); ch1010832@2198: ch1010832@2198: /* Set up speed in the Device Control register depending on ch1010832@2198: * negotiated values. ch1010832@2198: */ ch1010832@2198: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) ch1010832@2198: ctrl |= E1000_CTRL_SPD_1000; ch1010832@2198: else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) ch1010832@2198: ctrl |= E1000_CTRL_SPD_100; ch1010832@2198: ch1010832@2198: /* Write the configured values back to the Device Control Reg. */ ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Forces the MAC's flow control settings. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Sets the TFCE and RFCE bits in the device control register to reflect ch1010832@2198: * the adapter settings. TFCE and RFCE need to be explicitly set by ch1010832@2198: * software when a Copper PHY is used because autonegotiation is managed ch1010832@2198: * by the PHY rather than the MAC. Software must also configure these ch1010832@2198: * bits when link is forced on a fiber connection. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_force_mac_fc(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_force_mac_fc"); ch1010832@2198: ch1010832@2198: /* Get the current configuration of the Device Control Register */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: /* Because we didn't get link via the internal auto-negotiation ch1010832@2198: * mechanism (we either forced link or we got link via PHY ch1010832@2198: * auto-neg), we have to manually enable/disable transmit an ch1010832@2198: * receive flow control. ch1010832@2198: * ch1010832@2198: * The "Case" statement below enables/disable flow control ch1010832@2198: * according to the "hw->fc" parameter. ch1010832@2198: * ch1010832@2198: * The possible values of the "fc" parameter are: ch1010832@2198: * 0: Flow control is completely disabled ch1010832@2198: * 1: Rx flow control is enabled (we can receive pause ch1010832@2198: * frames but not send pause frames). ch1010832@2198: * 2: Tx flow control is enabled (we can send pause frames ch1010832@2198: * frames but we do not receive pause frames). ch1010832@2198: * 3: Both Rx and TX flow control (symmetric) is enabled. ch1010832@2198: * other: No other values should be possible at this point. ch1010832@2198: */ ch1010832@2198: ch1010832@2198: switch (hw->fc) { ch1010832@2198: case E1000_FC_NONE: ch1010832@2198: ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); ch1010832@2198: break; ch1010832@2198: case E1000_FC_RX_PAUSE: ch1010832@2198: ctrl &= (~E1000_CTRL_TFCE); ch1010832@2198: ctrl |= E1000_CTRL_RFCE; ch1010832@2198: break; ch1010832@2198: case E1000_FC_TX_PAUSE: ch1010832@2198: ctrl &= (~E1000_CTRL_RFCE); ch1010832@2198: ctrl |= E1000_CTRL_TFCE; ch1010832@2198: break; ch1010832@2198: case E1000_FC_FULL: ch1010832@2198: ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: DEBUGOUT("Flow control param set incorrectly\n"); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Disable TX Flow Control for 82542 (rev 2.0) */ ch1010832@2198: if (hw->mac_type == e1000_82542_rev2_0) ch1010832@2198: ctrl &= (~E1000_CTRL_TFCE); ch1010832@2198: ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Configures flow control settings after link is established ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Should be called immediately after a valid link has been established. ch1010832@2198: * Forces MAC flow control settings if link was forced. When in MII/GMII mode ch1010832@2198: * and autonegotiation is enabled, the MAC flow control settings will be set ch1010832@2198: * based on the flow control negotiated by the PHY. In TBI mode, the TFCE ch1010832@2198: * and RFCE bits will be automaticaly set to the negotiated flow control mode. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 mii_status_reg; ch1010832@2198: u16 mii_nway_adv_reg; ch1010832@2198: u16 mii_nway_lp_ability_reg; ch1010832@2198: u16 speed; ch1010832@2198: u16 duplex; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_config_fc_after_link_up"); ch1010832@2198: ch1010832@2198: /* Check for the case where we have fiber media and auto-neg failed ch1010832@2198: * so we had to force link. In this case, we need to force the ch1010832@2198: * configuration of the MAC to match the "fc" parameter. ch1010832@2198: */ ch1010832@2198: if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || ch1010832@2198: ((hw->media_type == e1000_media_type_internal_serdes) && ch1010832@2198: (hw->autoneg_failed)) || ch1010832@2198: ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { ch1010832@2198: ret_val = e1000_force_mac_fc(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error forcing flow control settings\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Check for the case where we have copper media and auto-neg is ch1010832@2198: * enabled. In this case, we need to check and see if Auto-Neg ch1010832@2198: * has completed, and if so, how the PHY and link partner has ch1010832@2198: * flow control configured. ch1010832@2198: */ ch1010832@2198: if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { ch1010832@2198: /* Read the MII Status Register and check to see if AutoNeg ch1010832@2198: * has completed. We read this twice because this reg has ch1010832@2198: * some "sticky" (latched) bits. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { ch1010832@2198: /* The AutoNeg process has completed, so we now need to ch1010832@2198: * read both the Auto Negotiation Advertisement Register ch1010832@2198: * (Address 4) and the Auto_Negotiation Base Page Ability ch1010832@2198: * Register (Address 5) to determine how flow control was ch1010832@2198: * negotiated. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, ch1010832@2198: &mii_nway_adv_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, ch1010832@2198: &mii_nway_lp_ability_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Two bits in the Auto Negotiation Advertisement Register ch1010832@2198: * (Address 4) and two bits in the Auto Negotiation Base ch1010832@2198: * Page Ability Register (Address 5) determine flow control ch1010832@2198: * for both the PHY and the link partner. The following ch1010832@2198: * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, ch1010832@2198: * 1999, describes these PAUSE resolution bits and how flow ch1010832@2198: * control is determined based upon these settings. ch1010832@2198: * NOTE: DC = Don't Care ch1010832@2198: * ch1010832@2198: * LOCAL DEVICE | LINK PARTNER ch1010832@2198: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution ch1010832@2198: *-------|---------|-------|---------|-------------------- ch1010832@2198: * 0 | 0 | DC | DC | E1000_FC_NONE ch1010832@2198: * 0 | 1 | 0 | DC | E1000_FC_NONE ch1010832@2198: * 0 | 1 | 1 | 0 | E1000_FC_NONE ch1010832@2198: * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE ch1010832@2198: * 1 | 0 | 0 | DC | E1000_FC_NONE ch1010832@2198: * 1 | DC | 1 | DC | E1000_FC_FULL ch1010832@2198: * 1 | 1 | 0 | 0 | E1000_FC_NONE ch1010832@2198: * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE ch1010832@2198: * ch1010832@2198: */ ch1010832@2198: /* Are both PAUSE bits set to 1? If so, this implies ch1010832@2198: * Symmetric Flow Control is enabled at both ends. The ch1010832@2198: * ASM_DIR bits are irrelevant per the spec. ch1010832@2198: * ch1010832@2198: * For Symmetric Flow Control: ch1010832@2198: * ch1010832@2198: * LOCAL DEVICE | LINK PARTNER ch1010832@2198: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ch1010832@2198: *-------|---------|-------|---------|-------------------- ch1010832@2198: * 1 | DC | 1 | DC | E1000_FC_FULL ch1010832@2198: * ch1010832@2198: */ ch1010832@2198: if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ch1010832@2198: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { ch1010832@2198: /* Now we need to check if the user selected RX ONLY ch1010832@2198: * of pause frames. In this case, we had to advertise ch1010832@2198: * FULL flow control because we could not advertise RX ch1010832@2198: * ONLY. Hence, we must now check to see if we need to ch1010832@2198: * turn OFF the TRANSMISSION of PAUSE frames. ch1010832@2198: */ ch1010832@2198: if (hw->original_fc == E1000_FC_FULL) { ch1010832@2198: hw->fc = E1000_FC_FULL; ch1010832@2198: DEBUGOUT("Flow Control = FULL.\n"); ch1010832@2198: } else { ch1010832@2198: hw->fc = E1000_FC_RX_PAUSE; ch1010832@2198: DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: /* For receiving PAUSE frames ONLY. ch1010832@2198: * ch1010832@2198: * LOCAL DEVICE | LINK PARTNER ch1010832@2198: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ch1010832@2198: *-------|---------|-------|---------|-------------------- ch1010832@2198: * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE ch1010832@2198: * ch1010832@2198: */ ch1010832@2198: else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && ch1010832@2198: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ch1010832@2198: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ch1010832@2198: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ch1010832@2198: hw->fc = E1000_FC_TX_PAUSE; ch1010832@2198: DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); ch1010832@2198: } ch1010832@2198: /* For transmitting PAUSE frames ONLY. ch1010832@2198: * ch1010832@2198: * LOCAL DEVICE | LINK PARTNER ch1010832@2198: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ch1010832@2198: *-------|---------|-------|---------|-------------------- ch1010832@2198: * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE ch1010832@2198: * ch1010832@2198: */ ch1010832@2198: else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ch1010832@2198: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ch1010832@2198: !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ch1010832@2198: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { ch1010832@2198: hw->fc = E1000_FC_RX_PAUSE; ch1010832@2198: DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); ch1010832@2198: } ch1010832@2198: /* Per the IEEE spec, at this point flow control should be ch1010832@2198: * disabled. However, we want to consider that we could ch1010832@2198: * be connected to a legacy switch that doesn't advertise ch1010832@2198: * desired flow control, but can be forced on the link ch1010832@2198: * partner. So if we advertised no flow control, that is ch1010832@2198: * what we will resolve to. If we advertised some kind of ch1010832@2198: * receive capability (Rx Pause Only or Full Flow Control) ch1010832@2198: * and the link partner advertised none, we will configure ch1010832@2198: * ourselves to enable Rx Flow Control only. We can do ch1010832@2198: * this safely for two reasons: If the link partner really ch1010832@2198: * didn't want flow control enabled, and we enable Rx, no ch1010832@2198: * harm done since we won't be receiving any PAUSE frames ch1010832@2198: * anyway. If the intent on the link partner was to have ch1010832@2198: * flow control enabled, then by us enabling RX only, we ch1010832@2198: * can at least receive pause frames and process them. ch1010832@2198: * This is a good idea because in most cases, since we are ch1010832@2198: * predominantly a server NIC, more times than not we will ch1010832@2198: * be asked to delay transmission of packets than asking ch1010832@2198: * our link partner to pause transmission of frames. ch1010832@2198: */ ch1010832@2198: else if ((hw->original_fc == E1000_FC_NONE || ch1010832@2198: hw->original_fc == E1000_FC_TX_PAUSE) || ch1010832@2198: hw->fc_strict_ieee) { ch1010832@2198: hw->fc = E1000_FC_NONE; ch1010832@2198: DEBUGOUT("Flow Control = NONE.\n"); ch1010832@2198: } else { ch1010832@2198: hw->fc = E1000_FC_RX_PAUSE; ch1010832@2198: DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Now we need to do one last check... If we auto- ch1010832@2198: * negotiated to HALF DUPLEX, flow control should not be ch1010832@2198: * enabled per IEEE 802.3 spec. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error getting link speed and duplex\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (duplex == HALF_DUPLEX) ch1010832@2198: hw->fc = E1000_FC_NONE; ch1010832@2198: ch1010832@2198: /* Now we call a subroutine to actually force the MAC ch1010832@2198: * controller to use the correct flow control settings. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_force_mac_fc(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error forcing flow control settings\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Checks to see if the link status of the hardware has changed. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Called by any function that needs to check the link status of the adapter. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_check_for_link(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 rxcw = 0; ch1010832@2198: u32 ctrl; ch1010832@2198: u32 status; ch1010832@2198: u32 rctl; ch1010832@2198: u32 icr; ch1010832@2198: u32 signal = 0; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_check_for_link"); ch1010832@2198: ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: status = er32(STATUS); ch1010832@2198: ch1010832@2198: /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be ch1010832@2198: * set when the optics detect a signal. On older adapters, it will be ch1010832@2198: * cleared when there is a signal. This applies to fiber media only. ch1010832@2198: */ ch1010832@2198: if ((hw->media_type == e1000_media_type_fiber) || ch1010832@2198: (hw->media_type == e1000_media_type_internal_serdes)) { ch1010832@2198: rxcw = er32(RXCW); ch1010832@2198: ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; ch1010832@2198: if (status & E1000_STATUS_LU) ch1010832@2198: hw->get_link_status = false; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* If we have a copper PHY then we only want to go out to the PHY ch1010832@2198: * registers to see if Auto-Neg has completed and/or if our link ch1010832@2198: * status has changed. The get_link_status flag will be set if we ch1010832@2198: * receive a Link Status Change interrupt or we have Rx Sequence ch1010832@2198: * Errors. ch1010832@2198: */ ch1010832@2198: if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { ch1010832@2198: /* First we want to see if the MII Status Register reports ch1010832@2198: * link. If so, then we want to get the current speed/duplex ch1010832@2198: * of the PHY. ch1010832@2198: * Read the register twice since the link bit is sticky. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (phy_data & MII_SR_LINK_STATUS) { ch1010832@2198: hw->get_link_status = false; ch1010832@2198: /* Check if there was DownShift, must be checked immediately after ch1010832@2198: * link-up */ ch1010832@2198: e1000_check_downshift(hw); ch1010832@2198: ch1010832@2198: /* If we are on 82544 or 82543 silicon and speed/duplex ch1010832@2198: * are forced to 10H or 10F, then we will implement the polarity ch1010832@2198: * reversal workaround. We disable interrupts first, and upon ch1010832@2198: * returning, place the devices interrupt state to its previous ch1010832@2198: * value except for the link status change interrupt which will ch1010832@2198: * happen due to the execution of this workaround. ch1010832@2198: */ ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && ch1010832@2198: (!hw->autoneg) && ch1010832@2198: (hw->forced_speed_duplex == e1000_10_full || ch1010832@2198: hw->forced_speed_duplex == e1000_10_half)) { ch1010832@2198: ew32(IMC, 0xffffffff); ch1010832@2198: ret_val = e1000_polarity_reversal_workaround(hw); ch1010832@2198: icr = er32(ICR); ch1010832@2198: ew32(ICS, (icr & ~E1000_ICS_LSC)); ch1010832@2198: ew32(IMS, IMS_ENABLE_MASK); ch1010832@2198: } ch1010832@2198: ch1010832@2198: } else { ch1010832@2198: /* No link detected */ ch1010832@2198: e1000_config_dsp_after_link_change(hw, false); ch1010832@2198: return 0; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* If we are forcing speed/duplex, then we simply return since ch1010832@2198: * we have already determined whether we have link or not. ch1010832@2198: */ ch1010832@2198: if (!hw->autoneg) return -E1000_ERR_CONFIG; ch1010832@2198: ch1010832@2198: /* optimize the dsp settings for the igp phy */ ch1010832@2198: e1000_config_dsp_after_link_change(hw, true); ch1010832@2198: ch1010832@2198: /* We have a M88E1000 PHY and Auto-Neg is enabled. If we ch1010832@2198: * have Si on board that is 82544 or newer, Auto ch1010832@2198: * Speed Detection takes care of MAC speed/duplex ch1010832@2198: * configuration. So we only need to configure Collision ch1010832@2198: * Distance in the MAC. Otherwise, we need to force ch1010832@2198: * speed/duplex on the MAC to the current PHY speed/duplex ch1010832@2198: * settings. ch1010832@2198: */ ch1010832@2198: if (hw->mac_type >= e1000_82544) ch1010832@2198: e1000_config_collision_dist(hw); ch1010832@2198: else { ch1010832@2198: ret_val = e1000_config_mac_to_phy(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error configuring MAC to PHY settings\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Configure Flow Control now that Auto-Neg has completed. First, we ch1010832@2198: * need to restore the desired flow control settings because we may ch1010832@2198: * have had to re-autoneg with a different link partner. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_config_fc_after_link_up(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error configuring flow control\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* At this point we know that we are on copper and we have ch1010832@2198: * auto-negotiated link. These are conditions for checking the link ch1010832@2198: * partner capability register. We use the link speed to determine if ch1010832@2198: * TBI compatibility needs to be turned on or off. If the link is not ch1010832@2198: * at gigabit speed, then TBI compatibility is not needed. If we are ch1010832@2198: * at gigabit speed, we turn on TBI compatibility. ch1010832@2198: */ ch1010832@2198: if (hw->tbi_compatibility_en) { ch1010832@2198: u16 speed, duplex; ch1010832@2198: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error getting link speed and duplex\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: if (speed != SPEED_1000) { ch1010832@2198: /* If link speed is not set to gigabit speed, we do not need ch1010832@2198: * to enable TBI compatibility. ch1010832@2198: */ ch1010832@2198: if (hw->tbi_compatibility_on) { ch1010832@2198: /* If we previously were in the mode, turn it off. */ ch1010832@2198: rctl = er32(RCTL); ch1010832@2198: rctl &= ~E1000_RCTL_SBP; ch1010832@2198: ew32(RCTL, rctl); ch1010832@2198: hw->tbi_compatibility_on = false; ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: /* If TBI compatibility is was previously off, turn it on. For ch1010832@2198: * compatibility with a TBI link partner, we will store bad ch1010832@2198: * packets. Some frames have an additional byte on the end and ch1010832@2198: * will look like CRC errors to to the hardware. ch1010832@2198: */ ch1010832@2198: if (!hw->tbi_compatibility_on) { ch1010832@2198: hw->tbi_compatibility_on = true; ch1010832@2198: rctl = er32(RCTL); ch1010832@2198: rctl |= E1000_RCTL_SBP; ch1010832@2198: ew32(RCTL, rctl); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: /* If we don't have link (auto-negotiation failed or link partner cannot ch1010832@2198: * auto-negotiate), the cable is plugged in (we have signal), and our ch1010832@2198: * link partner is not trying to auto-negotiate with us (we are receiving ch1010832@2198: * idles or data), we need to force link up. We also need to give ch1010832@2198: * auto-negotiation time to complete, in case the cable was just plugged ch1010832@2198: * in. The autoneg_failed flag does this. ch1010832@2198: */ ch1010832@2198: else if ((((hw->media_type == e1000_media_type_fiber) && ch1010832@2198: ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || ch1010832@2198: (hw->media_type == e1000_media_type_internal_serdes)) && ch1010832@2198: (!(status & E1000_STATUS_LU)) && ch1010832@2198: (!(rxcw & E1000_RXCW_C))) { ch1010832@2198: if (hw->autoneg_failed == 0) { ch1010832@2198: hw->autoneg_failed = 1; ch1010832@2198: return 0; ch1010832@2198: } ch1010832@2198: DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ch1010832@2198: ch1010832@2198: /* Disable auto-negotiation in the TXCW register */ ch1010832@2198: ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); ch1010832@2198: ch1010832@2198: /* Force link-up and also force full-duplex. */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: ch1010832@2198: /* Configure Flow Control after forcing link up. */ ch1010832@2198: ret_val = e1000_config_fc_after_link_up(hw); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error configuring flow control\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: /* If we are forcing link and we are receiving /C/ ordered sets, re-enable ch1010832@2198: * auto-negotiation in the TXCW register and disable forced link in the ch1010832@2198: * Device Control register in an attempt to auto-negotiate with our link ch1010832@2198: * partner. ch1010832@2198: */ ch1010832@2198: else if (((hw->media_type == e1000_media_type_fiber) || ch1010832@2198: (hw->media_type == e1000_media_type_internal_serdes)) && ch1010832@2198: (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ch1010832@2198: DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ch1010832@2198: ew32(TXCW, hw->txcw); ch1010832@2198: ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); ch1010832@2198: ch1010832@2198: hw->serdes_link_down = false; ch1010832@2198: } ch1010832@2198: /* If we force link for non-auto-negotiation switch, check link status ch1010832@2198: * based on MAC synchronization for internal serdes media type. ch1010832@2198: */ ch1010832@2198: else if ((hw->media_type == e1000_media_type_internal_serdes) && ch1010832@2198: !(E1000_TXCW_ANE & er32(TXCW))) { ch1010832@2198: /* SYNCH bit and IV bit are sticky. */ ch1010832@2198: udelay(10); ch1010832@2198: if (E1000_RXCW_SYNCH & er32(RXCW)) { ch1010832@2198: if (!(rxcw & E1000_RXCW_IV)) { ch1010832@2198: hw->serdes_link_down = false; ch1010832@2198: DEBUGOUT("SERDES: Link is up.\n"); ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: hw->serdes_link_down = true; ch1010832@2198: DEBUGOUT("SERDES: Link is down.\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: if ((hw->media_type == e1000_media_type_internal_serdes) && ch1010832@2198: (E1000_TXCW_ANE & er32(TXCW))) { ch1010832@2198: hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS)); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Detects the current speed and duplex settings of the hardware. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * speed - Speed of the connection ch1010832@2198: * duplex - Duplex setting of the connection ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) ch1010832@2198: { ch1010832@2198: u32 status; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_speed_and_duplex"); ch1010832@2198: ch1010832@2198: if (hw->mac_type >= e1000_82543) { ch1010832@2198: status = er32(STATUS); ch1010832@2198: if (status & E1000_STATUS_SPEED_1000) { ch1010832@2198: *speed = SPEED_1000; ch1010832@2198: DEBUGOUT("1000 Mbs, "); ch1010832@2198: } else if (status & E1000_STATUS_SPEED_100) { ch1010832@2198: *speed = SPEED_100; ch1010832@2198: DEBUGOUT("100 Mbs, "); ch1010832@2198: } else { ch1010832@2198: *speed = SPEED_10; ch1010832@2198: DEBUGOUT("10 Mbs, "); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (status & E1000_STATUS_FD) { ch1010832@2198: *duplex = FULL_DUPLEX; ch1010832@2198: DEBUGOUT("Full Duplex\n"); ch1010832@2198: } else { ch1010832@2198: *duplex = HALF_DUPLEX; ch1010832@2198: DEBUGOUT(" Half Duplex\n"); ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: DEBUGOUT("1000 Mbs, Full Duplex\n"); ch1010832@2198: *speed = SPEED_1000; ch1010832@2198: *duplex = FULL_DUPLEX; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* IGP01 PHY may advertise full duplex operation after speed downgrade even ch1010832@2198: * if it is operating at half duplex. Here we set the duplex settings to ch1010832@2198: * match the duplex in the link partner's capabilities. ch1010832@2198: */ ch1010832@2198: if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) ch1010832@2198: *duplex = HALF_DUPLEX; ch1010832@2198: else { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || ch1010832@2198: (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) ch1010832@2198: *duplex = HALF_DUPLEX; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_80003es2lan) && ch1010832@2198: (hw->media_type == e1000_media_type_copper)) { ch1010832@2198: if (*speed == SPEED_1000) ch1010832@2198: ret_val = e1000_configure_kmrn_for_1000(hw); ch1010832@2198: else ch1010832@2198: ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { ch1010832@2198: ret_val = e1000_kumeran_lock_loss_workaround(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Blocks until autoneg completes or times out (~4.5 seconds) ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_wait_autoneg(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 i; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_wait_autoneg"); ch1010832@2198: DEBUGOUT("Waiting for Auto-Neg to complete.\n"); ch1010832@2198: ch1010832@2198: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ ch1010832@2198: for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { ch1010832@2198: /* Read the MII Status Register and wait for Auto-Neg ch1010832@2198: * Complete bit to be set. ch1010832@2198: */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: if (phy_data & MII_SR_AUTONEG_COMPLETE) { ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: msleep(100); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Raises the Management Data Clock ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ctrl - Device control register's current value ch1010832@2198: ******************************************************************************/ ch1010832@2198: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) ch1010832@2198: { ch1010832@2198: /* Raise the clock input to the Management Data Clock (by setting the MDC ch1010832@2198: * bit), and then delay 10 microseconds. ch1010832@2198: */ ch1010832@2198: ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(10); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Lowers the Management Data Clock ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ctrl - Device control register's current value ch1010832@2198: ******************************************************************************/ ch1010832@2198: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) ch1010832@2198: { ch1010832@2198: /* Lower the clock input to the Management Data Clock (by clearing the MDC ch1010832@2198: * bit), and then delay 10 microseconds. ch1010832@2198: */ ch1010832@2198: ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(10); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Shifts data bits out to the PHY ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * data - Data to send out to the PHY ch1010832@2198: * count - Number of bits to shift out ch1010832@2198: * ch1010832@2198: * Bits are shifted out in MSB to LSB order. ch1010832@2198: ******************************************************************************/ ch1010832@2198: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: u32 mask; ch1010832@2198: ch1010832@2198: /* We need to shift "count" number of bits out to the PHY. So, the value ch1010832@2198: * in the "data" parameter will be shifted out to the PHY one bit at a ch1010832@2198: * time. In order to do this, "data" must be broken down into bits. ch1010832@2198: */ ch1010832@2198: mask = 0x01; ch1010832@2198: mask <<= (count - 1); ch1010832@2198: ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ ch1010832@2198: ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); ch1010832@2198: ch1010832@2198: while (mask) { ch1010832@2198: /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and ch1010832@2198: * then raising and lowering the Management Data Clock. A "0" is ch1010832@2198: * shifted out to the PHY by setting the MDIO bit to "0" and then ch1010832@2198: * raising and lowering the clock. ch1010832@2198: */ ch1010832@2198: if (data & mask) ch1010832@2198: ctrl |= E1000_CTRL_MDIO; ch1010832@2198: else ch1010832@2198: ctrl &= ~E1000_CTRL_MDIO; ch1010832@2198: ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: udelay(10); ch1010832@2198: ch1010832@2198: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@2198: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@2198: ch1010832@2198: mask = mask >> 1; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Shifts data bits in from the PHY ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Bits are shifted in in MSB to LSB order. ch1010832@2198: ******************************************************************************/ ch1010832@2198: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: u16 data = 0; ch1010832@2198: u8 i; ch1010832@2198: ch1010832@2198: /* In order to read a register from the PHY, we need to shift in a total ch1010832@2198: * of 18 bits from the PHY. The first two bit (turnaround) times are used ch1010832@2198: * to avoid contention on the MDIO pin when a read operation is performed. ch1010832@2198: * These two bits are ignored by us and thrown away. Bits are "shifted in" ch1010832@2198: * by raising the input to the Management Data Clock (setting the MDC bit), ch1010832@2198: * and then reading the value of the MDIO bit. ch1010832@2198: */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ ch1010832@2198: ctrl &= ~E1000_CTRL_MDIO_DIR; ch1010832@2198: ctrl &= ~E1000_CTRL_MDIO; ch1010832@2198: ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: /* Raise and Lower the clock before reading in the data. This accounts for ch1010832@2198: * the turnaround bits. The first clock occurred when we clocked out the ch1010832@2198: * last bit of the Register Address. ch1010832@2198: */ ch1010832@2198: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@2198: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@2198: ch1010832@2198: for (data = 0, i = 0; i < 16; i++) { ch1010832@2198: data = data << 1; ch1010832@2198: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: /* Check to see if we shifted in a "1". */ ch1010832@2198: if (ctrl & E1000_CTRL_MDIO) ch1010832@2198: data |= 1; ch1010832@2198: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@2198: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@2198: ch1010832@2198: return data; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask) ch1010832@2198: { ch1010832@2198: u32 swfw_sync = 0; ch1010832@2198: u32 swmask = mask; ch1010832@2198: u32 fwmask = mask << 16; ch1010832@2198: s32 timeout = 200; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_swfw_sync_acquire"); ch1010832@2198: ch1010832@2198: if (hw->swfwhw_semaphore_present) ch1010832@2198: return e1000_get_software_flag(hw); ch1010832@2198: ch1010832@2198: if (!hw->swfw_sync_present) ch1010832@2198: return e1000_get_hw_eeprom_semaphore(hw); ch1010832@2198: ch1010832@2198: while (timeout) { ch1010832@2198: if (e1000_get_hw_eeprom_semaphore(hw)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: ch1010832@2198: swfw_sync = er32(SW_FW_SYNC); ch1010832@2198: if (!(swfw_sync & (fwmask | swmask))) { ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* firmware currently using resource (fwmask) */ ch1010832@2198: /* or other software thread currently using resource (swmask) */ ch1010832@2198: e1000_put_hw_eeprom_semaphore(hw); ch1010832@2198: mdelay(5); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!timeout) { ch1010832@2198: DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: } ch1010832@2198: ch1010832@2198: swfw_sync |= swmask; ch1010832@2198: ew32(SW_FW_SYNC, swfw_sync); ch1010832@2198: ch1010832@2198: e1000_put_hw_eeprom_semaphore(hw); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask) ch1010832@2198: { ch1010832@2198: u32 swfw_sync; ch1010832@2198: u32 swmask = mask; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_swfw_sync_release"); ch1010832@2198: ch1010832@2198: if (hw->swfwhw_semaphore_present) { ch1010832@2198: e1000_release_software_flag(hw); ch1010832@2198: return; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!hw->swfw_sync_present) { ch1010832@2198: e1000_put_hw_eeprom_semaphore(hw); ch1010832@2198: return; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* if (e1000_get_hw_eeprom_semaphore(hw)) ch1010832@2198: * return -E1000_ERR_SWFW_SYNC; */ ch1010832@2198: while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); ch1010832@2198: /* empty */ ch1010832@2198: ch1010832@2198: swfw_sync = er32(SW_FW_SYNC); ch1010832@2198: swfw_sync &= ~swmask; ch1010832@2198: ew32(SW_FW_SYNC, swfw_sync); ch1010832@2198: ch1010832@2198: e1000_put_hw_eeprom_semaphore(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * Reads the value from a PHY register, if the value is on a specific non zero ch1010832@2198: * page, sets the page first. ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * reg_addr - address of the PHY register to read ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) ch1010832@2198: { ch1010832@2198: u32 ret_val; ch1010832@2198: u16 swfw; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_read_phy_reg"); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_80003es2lan) && ch1010832@2198: (er32(STATUS) & E1000_STATUS_FUNC_1)) { ch1010832@2198: swfw = E1000_SWFW_PHY1_SM; ch1010832@2198: } else { ch1010832@2198: swfw = E1000_SWFW_PHY0_SM; ch1010832@2198: } ch1010832@2198: if (e1000_swfw_sync_acquire(hw, swfw)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: ch1010832@2198: if ((hw->phy_type == e1000_phy_igp || ch1010832@2198: hw->phy_type == e1000_phy_igp_3 || ch1010832@2198: hw->phy_type == e1000_phy_igp_2) && ch1010832@2198: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, ch1010832@2198: (u16)reg_addr); ch1010832@2198: if (ret_val) { ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } else if (hw->phy_type == e1000_phy_gg82563) { ch1010832@2198: if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || ch1010832@2198: (hw->mac_type == e1000_80003es2lan)) { ch1010832@2198: /* Select Configuration Page */ ch1010832@2198: if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, ch1010832@2198: (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); ch1010832@2198: } else { ch1010832@2198: /* Use Alternative Page Select register to access ch1010832@2198: * registers 30 and 31 ch1010832@2198: */ ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, ch1010832@2198: GG82563_PHY_PAGE_SELECT_ALT, ch1010832@2198: (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (ret_val) { ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, ch1010832@2198: phy_data); ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@2198: u16 *phy_data) ch1010832@2198: { ch1010832@2198: u32 i; ch1010832@2198: u32 mdic = 0; ch1010832@2198: const u32 phy_addr = 1; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_read_phy_reg_ex"); ch1010832@2198: ch1010832@2198: if (reg_addr > MAX_PHY_REG_ADDRESS) { ch1010832@2198: DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); ch1010832@2198: return -E1000_ERR_PARAM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type > e1000_82543) { ch1010832@2198: /* Set up Op-code, Phy Address, and register address in the MDI ch1010832@2198: * Control register. The MAC will take care of interfacing with the ch1010832@2198: * PHY to retrieve the desired data. ch1010832@2198: */ ch1010832@2198: mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | ch1010832@2198: (phy_addr << E1000_MDIC_PHY_SHIFT) | ch1010832@2198: (E1000_MDIC_OP_READ)); ch1010832@2198: ch1010832@2198: ew32(MDIC, mdic); ch1010832@2198: ch1010832@2198: /* Poll the ready bit to see if the MDI read completed */ ch1010832@2198: for (i = 0; i < 64; i++) { ch1010832@2198: udelay(50); ch1010832@2198: mdic = er32(MDIC); ch1010832@2198: if (mdic & E1000_MDIC_READY) break; ch1010832@2198: } ch1010832@2198: if (!(mdic & E1000_MDIC_READY)) { ch1010832@2198: DEBUGOUT("MDI Read did not complete\n"); ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: } ch1010832@2198: if (mdic & E1000_MDIC_ERROR) { ch1010832@2198: DEBUGOUT("MDI Error\n"); ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: } ch1010832@2198: *phy_data = (u16)mdic; ch1010832@2198: } else { ch1010832@2198: /* We must first send a preamble through the MDIO pin to signal the ch1010832@2198: * beginning of an MII instruction. This is done by sending 32 ch1010832@2198: * consecutive "1" bits. ch1010832@2198: */ ch1010832@2198: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); ch1010832@2198: ch1010832@2198: /* Now combine the next few fields that are required for a read ch1010832@2198: * operation. We use this method instead of calling the ch1010832@2198: * e1000_shift_out_mdi_bits routine five different times. The format of ch1010832@2198: * a MII read instruction consists of a shift out of 14 bits and is ch1010832@2198: * defined as follows: ch1010832@2198: * ch1010832@2198: * followed by a shift in of 18 bits. This first two bits shifted in ch1010832@2198: * are TurnAround bits used to avoid contention on the MDIO pin when a ch1010832@2198: * READ operation is performed. These two bits are thrown away ch1010832@2198: * followed by a shift in of 16 bits which contains the desired data. ch1010832@2198: */ ch1010832@2198: mdic = ((reg_addr) | (phy_addr << 5) | ch1010832@2198: (PHY_OP_READ << 10) | (PHY_SOF << 12)); ch1010832@2198: ch1010832@2198: e1000_shift_out_mdi_bits(hw, mdic, 14); ch1010832@2198: ch1010832@2198: /* Now that we've shifted out the read command to the MII, we need to ch1010832@2198: * "shift in" the 16-bit value (18 total bits) of the requested PHY ch1010832@2198: * register address. ch1010832@2198: */ ch1010832@2198: *phy_data = e1000_shift_in_mdi_bits(hw); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a value to a PHY register ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * reg_addr - address of the PHY register to write ch1010832@2198: * data - data to write to the PHY ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) ch1010832@2198: { ch1010832@2198: u32 ret_val; ch1010832@2198: u16 swfw; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_write_phy_reg"); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_80003es2lan) && ch1010832@2198: (er32(STATUS) & E1000_STATUS_FUNC_1)) { ch1010832@2198: swfw = E1000_SWFW_PHY1_SM; ch1010832@2198: } else { ch1010832@2198: swfw = E1000_SWFW_PHY0_SM; ch1010832@2198: } ch1010832@2198: if (e1000_swfw_sync_acquire(hw, swfw)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: ch1010832@2198: if ((hw->phy_type == e1000_phy_igp || ch1010832@2198: hw->phy_type == e1000_phy_igp_3 || ch1010832@2198: hw->phy_type == e1000_phy_igp_2) && ch1010832@2198: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, ch1010832@2198: (u16)reg_addr); ch1010832@2198: if (ret_val) { ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } else if (hw->phy_type == e1000_phy_gg82563) { ch1010832@2198: if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || ch1010832@2198: (hw->mac_type == e1000_80003es2lan)) { ch1010832@2198: /* Select Configuration Page */ ch1010832@2198: if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, ch1010832@2198: (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); ch1010832@2198: } else { ch1010832@2198: /* Use Alternative Page Select register to access ch1010832@2198: * registers 30 and 31 ch1010832@2198: */ ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, ch1010832@2198: GG82563_PHY_PAGE_SELECT_ALT, ch1010832@2198: (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (ret_val) { ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, ch1010832@2198: phy_data); ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@2198: u16 phy_data) ch1010832@2198: { ch1010832@2198: u32 i; ch1010832@2198: u32 mdic = 0; ch1010832@2198: const u32 phy_addr = 1; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_write_phy_reg_ex"); ch1010832@2198: ch1010832@2198: if (reg_addr > MAX_PHY_REG_ADDRESS) { ch1010832@2198: DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); ch1010832@2198: return -E1000_ERR_PARAM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type > e1000_82543) { ch1010832@2198: /* Set up Op-code, Phy Address, register address, and data intended ch1010832@2198: * for the PHY register in the MDI Control register. The MAC will take ch1010832@2198: * care of interfacing with the PHY to send the desired data. ch1010832@2198: */ ch1010832@2198: mdic = (((u32)phy_data) | ch1010832@2198: (reg_addr << E1000_MDIC_REG_SHIFT) | ch1010832@2198: (phy_addr << E1000_MDIC_PHY_SHIFT) | ch1010832@2198: (E1000_MDIC_OP_WRITE)); ch1010832@2198: ch1010832@2198: ew32(MDIC, mdic); ch1010832@2198: ch1010832@2198: /* Poll the ready bit to see if the MDI read completed */ ch1010832@2198: for (i = 0; i < 641; i++) { ch1010832@2198: udelay(5); ch1010832@2198: mdic = er32(MDIC); ch1010832@2198: if (mdic & E1000_MDIC_READY) break; ch1010832@2198: } ch1010832@2198: if (!(mdic & E1000_MDIC_READY)) { ch1010832@2198: DEBUGOUT("MDI Write did not complete\n"); ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: /* We'll need to use the SW defined pins to shift the write command ch1010832@2198: * out to the PHY. We first send a preamble to the PHY to signal the ch1010832@2198: * beginning of the MII instruction. This is done by sending 32 ch1010832@2198: * consecutive "1" bits. ch1010832@2198: */ ch1010832@2198: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); ch1010832@2198: ch1010832@2198: /* Now combine the remaining required fields that will indicate a ch1010832@2198: * write operation. We use this method instead of calling the ch1010832@2198: * e1000_shift_out_mdi_bits routine for each field in the command. The ch1010832@2198: * format of a MII write instruction is as follows: ch1010832@2198: * . ch1010832@2198: */ ch1010832@2198: mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | ch1010832@2198: (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); ch1010832@2198: mdic <<= 16; ch1010832@2198: mdic |= (u32)phy_data; ch1010832@2198: ch1010832@2198: e1000_shift_out_mdi_bits(hw, mdic, 32); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data) ch1010832@2198: { ch1010832@2198: u32 reg_val; ch1010832@2198: u16 swfw; ch1010832@2198: DEBUGFUNC("e1000_read_kmrn_reg"); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_80003es2lan) && ch1010832@2198: (er32(STATUS) & E1000_STATUS_FUNC_1)) { ch1010832@2198: swfw = E1000_SWFW_PHY1_SM; ch1010832@2198: } else { ch1010832@2198: swfw = E1000_SWFW_PHY0_SM; ch1010832@2198: } ch1010832@2198: if (e1000_swfw_sync_acquire(hw, swfw)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: ch1010832@2198: /* Write register address */ ch1010832@2198: reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & ch1010832@2198: E1000_KUMCTRLSTA_OFFSET) | ch1010832@2198: E1000_KUMCTRLSTA_REN; ch1010832@2198: ew32(KUMCTRLSTA, reg_val); ch1010832@2198: udelay(2); ch1010832@2198: ch1010832@2198: /* Read the data returned */ ch1010832@2198: reg_val = er32(KUMCTRLSTA); ch1010832@2198: *data = (u16)reg_val; ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data) ch1010832@2198: { ch1010832@2198: u32 reg_val; ch1010832@2198: u16 swfw; ch1010832@2198: DEBUGFUNC("e1000_write_kmrn_reg"); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_80003es2lan) && ch1010832@2198: (er32(STATUS) & E1000_STATUS_FUNC_1)) { ch1010832@2198: swfw = E1000_SWFW_PHY1_SM; ch1010832@2198: } else { ch1010832@2198: swfw = E1000_SWFW_PHY0_SM; ch1010832@2198: } ch1010832@2198: if (e1000_swfw_sync_acquire(hw, swfw)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: ch1010832@2198: reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & ch1010832@2198: E1000_KUMCTRLSTA_OFFSET) | data; ch1010832@2198: ew32(KUMCTRLSTA, reg_val); ch1010832@2198: udelay(2); ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Returns the PHY to the power-on reset state ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_phy_hw_reset(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl, ctrl_ext; ch1010832@2198: u32 led_ctrl; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 swfw; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_hw_reset"); ch1010832@2198: ch1010832@2198: /* In the case of the phy reset being blocked, it's not an error, we ch1010832@2198: * simply return success without performing the reset. */ ch1010832@2198: ret_val = e1000_check_phy_reset_block(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: DEBUGOUT("Resetting Phy...\n"); ch1010832@2198: ch1010832@2198: if (hw->mac_type > e1000_82543) { ch1010832@2198: if ((hw->mac_type == e1000_80003es2lan) && ch1010832@2198: (er32(STATUS) & E1000_STATUS_FUNC_1)) { ch1010832@2198: swfw = E1000_SWFW_PHY1_SM; ch1010832@2198: } else { ch1010832@2198: swfw = E1000_SWFW_PHY0_SM; ch1010832@2198: } ch1010832@2198: if (e1000_swfw_sync_acquire(hw, swfw)) { ch1010832@2198: DEBUGOUT("Unable to acquire swfw sync\n"); ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: } ch1010832@2198: /* Read the device control register and assert the E1000_CTRL_PHY_RST ch1010832@2198: * bit. Then, take it out of reset. ch1010832@2198: * For pre-e1000_82571 hardware, we delay for 10ms between the assert ch1010832@2198: * and deassert. For e1000_82571 hardware and later, we instead delay ch1010832@2198: * for 50us between and 10ms after the deassertion. ch1010832@2198: */ ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: if (hw->mac_type < e1000_82571) ch1010832@2198: msleep(10); ch1010832@2198: else ch1010832@2198: udelay(100); ch1010832@2198: ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: if (hw->mac_type >= e1000_82571) ch1010832@2198: mdelay(10); ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, swfw); ch1010832@2198: } else { ch1010832@2198: /* Read the Extended Device Control Register, assert the PHY_RESET_DIR ch1010832@2198: * bit to put the PHY into reset. Then, take it out of reset. ch1010832@2198: */ ch1010832@2198: ctrl_ext = er32(CTRL_EXT); ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; ch1010832@2198: ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: msleep(10); ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: udelay(150); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@2198: /* Configure activity LED after PHY reset */ ch1010832@2198: led_ctrl = er32(LEDCTL); ch1010832@2198: led_ctrl &= IGP_ACTIVITY_LED_MASK; ch1010832@2198: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ch1010832@2198: ew32(LEDCTL, led_ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Wait for FW to finish PHY configuration. */ ch1010832@2198: ret_val = e1000_get_phy_cfg_done(hw); ch1010832@2198: if (ret_val != E1000_SUCCESS) ch1010832@2198: return ret_val; ch1010832@2198: e1000_release_software_semaphore(hw); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) ch1010832@2198: ret_val = e1000_init_lcd_from_nvm(hw); ch1010832@2198: ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Resets the PHY ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Sets bit 15 of the MII Control register ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_phy_reset(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_reset"); ch1010832@2198: ch1010832@2198: /* In the case of the phy reset being blocked, it's not an error, we ch1010832@2198: * simply return success without performing the reset. */ ch1010832@2198: ret_val = e1000_check_phy_reset_block(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: switch (hw->phy_type) { ch1010832@2198: case e1000_phy_igp: ch1010832@2198: case e1000_phy_igp_2: ch1010832@2198: case e1000_phy_igp_3: ch1010832@2198: case e1000_phy_ife: ch1010832@2198: ret_val = e1000_phy_hw_reset(hw); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= MII_CR_RESET; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: udelay(1); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) ch1010832@2198: e1000_phy_init_script(hw); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Work-around for 82566 power-down: on D3 entry- ch1010832@2198: * 1) disable gigabit link ch1010832@2198: * 2) write VR power-down enable ch1010832@2198: * 3) read it back ch1010832@2198: * if successful continue, else issue LCD reset and repeat ch1010832@2198: * ch1010832@2198: * hw - struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: void e1000_phy_powerdown_workaround(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 reg; ch1010832@2198: u16 phy_data; ch1010832@2198: s32 retry = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_powerdown_workaround"); ch1010832@2198: ch1010832@2198: if (hw->phy_type != e1000_phy_igp_3) ch1010832@2198: return; ch1010832@2198: ch1010832@2198: do { ch1010832@2198: /* Disable link */ ch1010832@2198: reg = er32(PHY_CTRL); ch1010832@2198: ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | ch1010832@2198: E1000_PHY_CTRL_NOND0A_GBE_DISABLE); ch1010832@2198: ch1010832@2198: /* Write VR power-down enable - bits 9:8 should be 10b */ ch1010832@2198: e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); ch1010832@2198: phy_data |= (1 << 9); ch1010832@2198: phy_data &= ~(1 << 8); ch1010832@2198: e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); ch1010832@2198: ch1010832@2198: /* Read it back and test */ ch1010832@2198: e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); ch1010832@2198: if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) ch1010832@2198: break; ch1010832@2198: ch1010832@2198: /* Issue PHY reset and repeat at most one more time */ ch1010832@2198: reg = er32(CTRL); ch1010832@2198: ew32(CTRL, reg | E1000_CTRL_PHY_RST); ch1010832@2198: retry++; ch1010832@2198: } while (retry); ch1010832@2198: ch1010832@2198: return; ch1010832@2198: ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Work-around for 82566 Kumeran PCS lock loss: ch1010832@2198: * On link status change (i.e. PCI reset, speed change) and link is up and ch1010832@2198: * speed is gigabit- ch1010832@2198: * 0) if workaround is optionally disabled do nothing ch1010832@2198: * 1) wait 1ms for Kumeran link to come up ch1010832@2198: * 2) check Kumeran Diagnostic register PCS lock loss bit ch1010832@2198: * 3) if not set the link is locked (all is good), otherwise... ch1010832@2198: * 4) reset the PHY ch1010832@2198: * 5) repeat up to 10 times ch1010832@2198: * Note: this is only called for IGP3 copper when speed is 1gb. ch1010832@2198: * ch1010832@2198: * hw - struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: s32 reg; ch1010832@2198: s32 cnt; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: if (hw->kmrn_lock_loss_workaround_disabled) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Make sure link is up before proceeding. If not just return. ch1010832@2198: * Attempting this while link is negotiating fouled up link ch1010832@2198: * stability */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: ch1010832@2198: if (phy_data & MII_SR_LINK_STATUS) { ch1010832@2198: for (cnt = 0; cnt < 10; cnt++) { ch1010832@2198: /* read once to clear */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: /* and again to get new status */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* check for PCS lock */ ch1010832@2198: if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Issue PHY reset */ ch1010832@2198: e1000_phy_hw_reset(hw); ch1010832@2198: mdelay(5); ch1010832@2198: } ch1010832@2198: /* Disable GigE link negotiation */ ch1010832@2198: reg = er32(PHY_CTRL); ch1010832@2198: ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | ch1010832@2198: E1000_PHY_CTRL_NOND0A_GBE_DISABLE); ch1010832@2198: ch1010832@2198: /* unable to acquire PCS lock */ ch1010832@2198: return E1000_ERR_PHY; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Probes the expected PHY address for known PHY IDs ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_detect_gig_phy(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 phy_init_status, ret_val; ch1010832@2198: u16 phy_id_high, phy_id_low; ch1010832@2198: bool match = false; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_detect_gig_phy"); ch1010832@2198: ch1010832@2198: if (hw->phy_id != 0) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* The 82571 firmware may still be configuring the PHY. In this ch1010832@2198: * case, we cannot access the PHY until the configuration is done. So ch1010832@2198: * we explicitly set the PHY values. */ ch1010832@2198: if (hw->mac_type == e1000_82571 || ch1010832@2198: hw->mac_type == e1000_82572) { ch1010832@2198: hw->phy_id = IGP01E1000_I_PHY_ID; ch1010832@2198: hw->phy_type = e1000_phy_igp_2; ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- ch1010832@2198: * around that forces PHY page 0 to be set or the reads fail. The rest of ch1010832@2198: * the code in this routine uses e1000_read_phy_reg to read the PHY ID. ch1010832@2198: * So for ESB-2 we need to have this set so our reads won't fail. If the ch1010832@2198: * attached PHY is not a e1000_phy_gg82563, the routines below will figure ch1010832@2198: * this out as well. */ ch1010832@2198: if (hw->mac_type == e1000_80003es2lan) ch1010832@2198: hw->phy_type = e1000_phy_gg82563; ch1010832@2198: ch1010832@2198: /* Read the PHY ID Registers to identify which PHY is onboard. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->phy_id = (u32)(phy_id_high << 16); ch1010832@2198: udelay(20); ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK); ch1010832@2198: hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK; ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82543: ch1010832@2198: if (hw->phy_id == M88E1000_E_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: case e1000_82544: ch1010832@2198: if (hw->phy_id == M88E1000_I_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: case e1000_82540: ch1010832@2198: case e1000_82545: ch1010832@2198: case e1000_82545_rev_3: ch1010832@2198: case e1000_82546: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: if (hw->phy_id == M88E1011_I_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: case e1000_82573: ch1010832@2198: if (hw->phy_id == M88E1111_I_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: if (hw->phy_id == GG82563_E_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true; ch1010832@2198: if (hw->phy_id == IFE_E_PHY_ID) match = true; ch1010832@2198: if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true; ch1010832@2198: if (hw->phy_id == IFE_C_E_PHY_ID) match = true; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: phy_init_status = e1000_set_phy_type(hw); ch1010832@2198: ch1010832@2198: if ((match) && (phy_init_status == E1000_SUCCESS)) { ch1010832@2198: DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Resets the PHY's DSP ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: DEBUGFUNC("e1000_phy_reset_dsp"); ch1010832@2198: ch1010832@2198: do { ch1010832@2198: if (hw->phy_type != e1000_phy_gg82563) { ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 29, 0x001d); ch1010832@2198: if (ret_val) break; ch1010832@2198: } ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); ch1010832@2198: if (ret_val) break; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 30, 0x0000); ch1010832@2198: if (ret_val) break; ch1010832@2198: ret_val = E1000_SUCCESS; ch1010832@2198: } while (0); ch1010832@2198: ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Get PHY information from various PHY registers for igp PHY only. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * phy_info - PHY information structure ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, ch1010832@2198: struct e1000_phy_info *phy_info) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data, min_length, max_length, average; ch1010832@2198: e1000_rev_polarity polarity; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_igp_get_info"); ch1010832@2198: ch1010832@2198: /* The downshift status is checked only once, after link is established, ch1010832@2198: * and it stored in the hw->speed_downgraded parameter. */ ch1010832@2198: phy_info->downshift = (e1000_downshift)hw->speed_downgraded; ch1010832@2198: ch1010832@2198: /* IGP01E1000 does not need to support it. */ ch1010832@2198: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; ch1010832@2198: ch1010832@2198: /* IGP01E1000 always correct polarity reversal */ ch1010832@2198: phy_info->polarity_correction = e1000_polarity_reversal_enabled; ch1010832@2198: ch1010832@2198: /* Check polarity status */ ch1010832@2198: ret_val = e1000_check_polarity(hw, &polarity); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->cable_polarity = polarity; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> ch1010832@2198: IGP01E1000_PSSR_MDIX_SHIFT); ch1010832@2198: ch1010832@2198: if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == ch1010832@2198: IGP01E1000_PSSR_SPEED_1000MBPS) { ch1010832@2198: /* Local/Remote Receiver Information are only valid at 1000 Mbps */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> ch1010832@2198: SR_1000T_LOCAL_RX_STATUS_SHIFT) ? ch1010832@2198: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@2198: phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> ch1010832@2198: SR_1000T_REMOTE_RX_STATUS_SHIFT) ? ch1010832@2198: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@2198: ch1010832@2198: /* Get cable length */ ch1010832@2198: ret_val = e1000_get_cable_length(hw, &min_length, &max_length); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Translate to old method */ ch1010832@2198: average = (max_length + min_length) / 2; ch1010832@2198: ch1010832@2198: if (average <= e1000_igp_cable_length_50) ch1010832@2198: phy_info->cable_length = e1000_cable_length_50; ch1010832@2198: else if (average <= e1000_igp_cable_length_80) ch1010832@2198: phy_info->cable_length = e1000_cable_length_50_80; ch1010832@2198: else if (average <= e1000_igp_cable_length_110) ch1010832@2198: phy_info->cable_length = e1000_cable_length_80_110; ch1010832@2198: else if (average <= e1000_igp_cable_length_140) ch1010832@2198: phy_info->cable_length = e1000_cable_length_110_140; ch1010832@2198: else ch1010832@2198: phy_info->cable_length = e1000_cable_length_140; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Get PHY information from various PHY registers for ife PHY only. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * phy_info - PHY information structure ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, ch1010832@2198: struct e1000_phy_info *phy_info) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: e1000_rev_polarity polarity; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_ife_get_info"); ch1010832@2198: ch1010832@2198: phy_info->downshift = (e1000_downshift)hw->speed_downgraded; ch1010832@2198: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: phy_info->polarity_correction = ch1010832@2198: ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> ch1010832@2198: IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? ch1010832@2198: e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; ch1010832@2198: ch1010832@2198: if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { ch1010832@2198: ret_val = e1000_check_polarity(hw, &polarity); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else { ch1010832@2198: /* Polarity is forced. */ ch1010832@2198: polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> ch1010832@2198: IFE_PSC_FORCE_POLARITY_SHIFT) ? ch1010832@2198: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; ch1010832@2198: } ch1010832@2198: phy_info->cable_polarity = polarity; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->mdix_mode = (e1000_auto_x_mode) ch1010832@2198: ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> ch1010832@2198: IFE_PMC_MDIX_MODE_SHIFT); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Get PHY information from various PHY registers fot m88 PHY only. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * phy_info - PHY information structure ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, ch1010832@2198: struct e1000_phy_info *phy_info) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: e1000_rev_polarity polarity; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_m88_get_info"); ch1010832@2198: ch1010832@2198: /* The downshift status is checked only once, after link is established, ch1010832@2198: * and it stored in the hw->speed_downgraded parameter. */ ch1010832@2198: phy_info->downshift = (e1000_downshift)hw->speed_downgraded; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->extended_10bt_distance = ch1010832@2198: ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> ch1010832@2198: M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? ch1010832@2198: e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; ch1010832@2198: ch1010832@2198: phy_info->polarity_correction = ch1010832@2198: ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> ch1010832@2198: M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? ch1010832@2198: e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; ch1010832@2198: ch1010832@2198: /* Check polarity status */ ch1010832@2198: ret_val = e1000_check_polarity(hw, &polarity); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: phy_info->cable_polarity = polarity; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> ch1010832@2198: M88E1000_PSSR_MDIX_SHIFT); ch1010832@2198: ch1010832@2198: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { ch1010832@2198: /* Cable Length Estimation and Local/Remote Receiver Information ch1010832@2198: * are only valid at 1000 Mbps. ch1010832@2198: */ ch1010832@2198: if (hw->phy_type != e1000_phy_gg82563) { ch1010832@2198: phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> ch1010832@2198: M88E1000_PSSR_CABLE_LENGTH_SHIFT); ch1010832@2198: } else { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> ch1010832@2198: SR_1000T_LOCAL_RX_STATUS_SHIFT) ? ch1010832@2198: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@2198: phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> ch1010832@2198: SR_1000T_REMOTE_RX_STATUS_SHIFT) ? ch1010832@2198: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@2198: ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Get PHY information from various PHY registers ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * phy_info - PHY information structure ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_phy_get_info"); ch1010832@2198: ch1010832@2198: phy_info->cable_length = e1000_cable_length_undefined; ch1010832@2198: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; ch1010832@2198: phy_info->cable_polarity = e1000_rev_polarity_undefined; ch1010832@2198: phy_info->downshift = e1000_downshift_undefined; ch1010832@2198: phy_info->polarity_correction = e1000_polarity_reversal_undefined; ch1010832@2198: phy_info->mdix_mode = e1000_auto_x_mode_undefined; ch1010832@2198: phy_info->local_rx = e1000_1000t_rx_status_undefined; ch1010832@2198: phy_info->remote_rx = e1000_1000t_rx_status_undefined; ch1010832@2198: ch1010832@2198: if (hw->media_type != e1000_media_type_copper) { ch1010832@2198: DEBUGOUT("PHY info is only valid for copper media\n"); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { ch1010832@2198: DEBUGOUT("PHY info is only valid if link is up\n"); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->phy_type == e1000_phy_igp || ch1010832@2198: hw->phy_type == e1000_phy_igp_3 || ch1010832@2198: hw->phy_type == e1000_phy_igp_2) ch1010832@2198: return e1000_phy_igp_get_info(hw, phy_info); ch1010832@2198: else if (hw->phy_type == e1000_phy_ife) ch1010832@2198: return e1000_phy_ife_get_info(hw, phy_info); ch1010832@2198: else ch1010832@2198: return e1000_phy_m88_get_info(hw, phy_info); ch1010832@2198: } ch1010832@2198: ch1010832@2198: s32 e1000_validate_mdi_setting(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: DEBUGFUNC("e1000_validate_mdi_settings"); ch1010832@2198: ch1010832@2198: if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { ch1010832@2198: DEBUGOUT("Invalid MDI setting detected\n"); ch1010832@2198: hw->mdix = 1; ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Sets up eeprom variables in the hw struct. Must be called after mac_type ch1010832@2198: * is configured. Additionally, if this is ICH8, the flash controller GbE ch1010832@2198: * registers must be mapped, or this will crash. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_init_eeprom_params(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u32 eecd = er32(EECD); ch1010832@2198: s32 ret_val = E1000_SUCCESS; ch1010832@2198: u16 eeprom_size; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_init_eeprom_params"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: case e1000_82543: ch1010832@2198: case e1000_82544: ch1010832@2198: eeprom->type = e1000_eeprom_microwire; ch1010832@2198: eeprom->word_size = 64; ch1010832@2198: eeprom->opcode_bits = 3; ch1010832@2198: eeprom->address_bits = 6; ch1010832@2198: eeprom->delay_usec = 50; ch1010832@2198: eeprom->use_eerd = false; ch1010832@2198: eeprom->use_eewr = false; ch1010832@2198: break; ch1010832@2198: case e1000_82540: ch1010832@2198: case e1000_82545: ch1010832@2198: case e1000_82545_rev_3: ch1010832@2198: case e1000_82546: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: eeprom->type = e1000_eeprom_microwire; ch1010832@2198: eeprom->opcode_bits = 3; ch1010832@2198: eeprom->delay_usec = 50; ch1010832@2198: if (eecd & E1000_EECD_SIZE) { ch1010832@2198: eeprom->word_size = 256; ch1010832@2198: eeprom->address_bits = 8; ch1010832@2198: } else { ch1010832@2198: eeprom->word_size = 64; ch1010832@2198: eeprom->address_bits = 6; ch1010832@2198: } ch1010832@2198: eeprom->use_eerd = false; ch1010832@2198: eeprom->use_eewr = false; ch1010832@2198: break; ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: if (eecd & E1000_EECD_TYPE) { ch1010832@2198: eeprom->type = e1000_eeprom_spi; ch1010832@2198: eeprom->opcode_bits = 8; ch1010832@2198: eeprom->delay_usec = 1; ch1010832@2198: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@2198: eeprom->page_size = 32; ch1010832@2198: eeprom->address_bits = 16; ch1010832@2198: } else { ch1010832@2198: eeprom->page_size = 8; ch1010832@2198: eeprom->address_bits = 8; ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: eeprom->type = e1000_eeprom_microwire; ch1010832@2198: eeprom->opcode_bits = 3; ch1010832@2198: eeprom->delay_usec = 50; ch1010832@2198: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@2198: eeprom->word_size = 256; ch1010832@2198: eeprom->address_bits = 8; ch1010832@2198: } else { ch1010832@2198: eeprom->word_size = 64; ch1010832@2198: eeprom->address_bits = 6; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: eeprom->use_eerd = false; ch1010832@2198: eeprom->use_eewr = false; ch1010832@2198: break; ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: eeprom->type = e1000_eeprom_spi; ch1010832@2198: eeprom->opcode_bits = 8; ch1010832@2198: eeprom->delay_usec = 1; ch1010832@2198: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@2198: eeprom->page_size = 32; ch1010832@2198: eeprom->address_bits = 16; ch1010832@2198: } else { ch1010832@2198: eeprom->page_size = 8; ch1010832@2198: eeprom->address_bits = 8; ch1010832@2198: } ch1010832@2198: eeprom->use_eerd = false; ch1010832@2198: eeprom->use_eewr = false; ch1010832@2198: break; ch1010832@2198: case e1000_82573: ch1010832@2198: eeprom->type = e1000_eeprom_spi; ch1010832@2198: eeprom->opcode_bits = 8; ch1010832@2198: eeprom->delay_usec = 1; ch1010832@2198: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@2198: eeprom->page_size = 32; ch1010832@2198: eeprom->address_bits = 16; ch1010832@2198: } else { ch1010832@2198: eeprom->page_size = 8; ch1010832@2198: eeprom->address_bits = 8; ch1010832@2198: } ch1010832@2198: eeprom->use_eerd = true; ch1010832@2198: eeprom->use_eewr = true; ch1010832@2198: if (!e1000_is_onboard_nvm_eeprom(hw)) { ch1010832@2198: eeprom->type = e1000_eeprom_flash; ch1010832@2198: eeprom->word_size = 2048; ch1010832@2198: ch1010832@2198: /* Ensure that the Autonomous FLASH update bit is cleared due to ch1010832@2198: * Flash update issue on parts which use a FLASH for NVM. */ ch1010832@2198: eecd &= ~E1000_EECD_AUPDEN; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: eeprom->type = e1000_eeprom_spi; ch1010832@2198: eeprom->opcode_bits = 8; ch1010832@2198: eeprom->delay_usec = 1; ch1010832@2198: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@2198: eeprom->page_size = 32; ch1010832@2198: eeprom->address_bits = 16; ch1010832@2198: } else { ch1010832@2198: eeprom->page_size = 8; ch1010832@2198: eeprom->address_bits = 8; ch1010832@2198: } ch1010832@2198: eeprom->use_eerd = true; ch1010832@2198: eeprom->use_eewr = false; ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: { ch1010832@2198: s32 i = 0; ch1010832@2198: u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); ch1010832@2198: ch1010832@2198: eeprom->type = e1000_eeprom_ich8; ch1010832@2198: eeprom->use_eerd = false; ch1010832@2198: eeprom->use_eewr = false; ch1010832@2198: eeprom->word_size = E1000_SHADOW_RAM_WORDS; ch1010832@2198: ch1010832@2198: /* Zero the shadow RAM structure. But don't load it from NVM ch1010832@2198: * so as to save time for driver init */ ch1010832@2198: if (hw->eeprom_shadow_ram != NULL) { ch1010832@2198: for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { ch1010832@2198: hw->eeprom_shadow_ram[i].modified = false; ch1010832@2198: hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * ch1010832@2198: ICH_FLASH_SECTOR_SIZE; ch1010832@2198: ch1010832@2198: hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; ch1010832@2198: hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); ch1010832@2198: ch1010832@2198: hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; ch1010832@2198: ch1010832@2198: hw->flash_bank_size /= 2 * sizeof(u16); ch1010832@2198: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (eeprom->type == e1000_eeprom_spi) { ch1010832@2198: /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to ch1010832@2198: * 32KB (incremented by powers of 2). ch1010832@2198: */ ch1010832@2198: if (hw->mac_type <= e1000_82547_rev_2) { ch1010832@2198: /* Set to default value for initial eeprom read. */ ch1010832@2198: eeprom->word_size = 64; ch1010832@2198: ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; ch1010832@2198: /* 256B eeprom size was not supported in earlier hardware, so we ch1010832@2198: * bump eeprom_size up one to ensure that "1" (which maps to 256B) ch1010832@2198: * is never the result used in the shifting logic below. */ ch1010832@2198: if (eeprom_size) ch1010832@2198: eeprom_size++; ch1010832@2198: } else { ch1010832@2198: eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> ch1010832@2198: E1000_EECD_SIZE_EX_SHIFT); ch1010832@2198: } ch1010832@2198: ch1010832@2198: eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); ch1010832@2198: } ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Raises the EEPROM's clock input. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * eecd - EECD's current value ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) ch1010832@2198: { ch1010832@2198: /* Raise the clock input to the EEPROM (by setting the SK bit), and then ch1010832@2198: * wait microseconds. ch1010832@2198: */ ch1010832@2198: *eecd = *eecd | E1000_EECD_SK; ch1010832@2198: ew32(EECD, *eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(hw->eeprom.delay_usec); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Lowers the EEPROM's clock input. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * eecd - EECD's current value ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) ch1010832@2198: { ch1010832@2198: /* Lower the clock input to the EEPROM (by clearing the SK bit), and then ch1010832@2198: * wait 50 microseconds. ch1010832@2198: */ ch1010832@2198: *eecd = *eecd & ~E1000_EECD_SK; ch1010832@2198: ew32(EECD, *eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(hw->eeprom.delay_usec); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Shift data bits out to the EEPROM. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * data - data to send to the EEPROM ch1010832@2198: * count - number of bits to shift out ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u32 eecd; ch1010832@2198: u32 mask; ch1010832@2198: ch1010832@2198: /* We need to shift "count" bits out to the EEPROM. So, value in the ch1010832@2198: * "data" parameter will be shifted out to the EEPROM one bit at a time. ch1010832@2198: * In order to do this, "data" must be broken down into bits. ch1010832@2198: */ ch1010832@2198: mask = 0x01 << (count - 1); ch1010832@2198: eecd = er32(EECD); ch1010832@2198: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@2198: eecd &= ~E1000_EECD_DO; ch1010832@2198: } else if (eeprom->type == e1000_eeprom_spi) { ch1010832@2198: eecd |= E1000_EECD_DO; ch1010832@2198: } ch1010832@2198: do { ch1010832@2198: /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", ch1010832@2198: * and then raising and then lowering the clock (the SK bit controls ch1010832@2198: * the clock input to the EEPROM). A "0" is shifted out to the EEPROM ch1010832@2198: * by setting "DI" to "0" and then raising and then lowering the clock. ch1010832@2198: */ ch1010832@2198: eecd &= ~E1000_EECD_DI; ch1010832@2198: ch1010832@2198: if (data & mask) ch1010832@2198: eecd |= E1000_EECD_DI; ch1010832@2198: ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: ch1010832@2198: e1000_raise_ee_clk(hw, &eecd); ch1010832@2198: e1000_lower_ee_clk(hw, &eecd); ch1010832@2198: ch1010832@2198: mask = mask >> 1; ch1010832@2198: ch1010832@2198: } while (mask); ch1010832@2198: ch1010832@2198: /* We leave the "DI" bit set to "0" when we leave this routine. */ ch1010832@2198: eecd &= ~E1000_EECD_DI; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Shift data bits in from the EEPROM ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) ch1010832@2198: { ch1010832@2198: u32 eecd; ch1010832@2198: u32 i; ch1010832@2198: u16 data; ch1010832@2198: ch1010832@2198: /* In order to read a register from the EEPROM, we need to shift 'count' ch1010832@2198: * bits in from the EEPROM. Bits are "shifted in" by raising the clock ch1010832@2198: * input to the EEPROM (setting the SK bit), and then reading the value of ch1010832@2198: * the "DO" bit. During this "shifting in" process the "DI" bit should ch1010832@2198: * always be clear. ch1010832@2198: */ ch1010832@2198: ch1010832@2198: eecd = er32(EECD); ch1010832@2198: ch1010832@2198: eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); ch1010832@2198: data = 0; ch1010832@2198: ch1010832@2198: for (i = 0; i < count; i++) { ch1010832@2198: data = data << 1; ch1010832@2198: e1000_raise_ee_clk(hw, &eecd); ch1010832@2198: ch1010832@2198: eecd = er32(EECD); ch1010832@2198: ch1010832@2198: eecd &= ~(E1000_EECD_DI); ch1010832@2198: if (eecd & E1000_EECD_DO) ch1010832@2198: data |= 1; ch1010832@2198: ch1010832@2198: e1000_lower_ee_clk(hw, &eecd); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return data; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Prepares EEPROM for access ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This ch1010832@2198: * function should be called before issuing a command to the EEPROM. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_acquire_eeprom(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u32 eecd, i=0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_acquire_eeprom"); ch1010832@2198: ch1010832@2198: if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: eecd = er32(EECD); ch1010832@2198: ch1010832@2198: if (hw->mac_type != e1000_82573) { ch1010832@2198: /* Request EEPROM Access */ ch1010832@2198: if (hw->mac_type > e1000_82544) { ch1010832@2198: eecd |= E1000_EECD_REQ; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: eecd = er32(EECD); ch1010832@2198: while ((!(eecd & E1000_EECD_GNT)) && ch1010832@2198: (i < E1000_EEPROM_GRANT_ATTEMPTS)) { ch1010832@2198: i++; ch1010832@2198: udelay(5); ch1010832@2198: eecd = er32(EECD); ch1010832@2198: } ch1010832@2198: if (!(eecd & E1000_EECD_GNT)) { ch1010832@2198: eecd &= ~E1000_EECD_REQ; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: DEBUGOUT("Could not acquire EEPROM grant\n"); ch1010832@2198: e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Setup EEPROM for Read/Write */ ch1010832@2198: ch1010832@2198: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@2198: /* Clear SK and DI */ ch1010832@2198: eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: ch1010832@2198: /* Set CS */ ch1010832@2198: eecd |= E1000_EECD_CS; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: } else if (eeprom->type == e1000_eeprom_spi) { ch1010832@2198: /* Clear SK and CS */ ch1010832@2198: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: udelay(1); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Returns EEPROM to a "standby" state ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_standby_eeprom(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u32 eecd; ch1010832@2198: ch1010832@2198: eecd = er32(EECD); ch1010832@2198: ch1010832@2198: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@2198: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: ch1010832@2198: /* Clock high */ ch1010832@2198: eecd |= E1000_EECD_SK; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: ch1010832@2198: /* Select EEPROM */ ch1010832@2198: eecd |= E1000_EECD_CS; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: ch1010832@2198: /* Clock low */ ch1010832@2198: eecd &= ~E1000_EECD_SK; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: } else if (eeprom->type == e1000_eeprom_spi) { ch1010832@2198: /* Toggle CS to flush commands */ ch1010832@2198: eecd |= E1000_EECD_CS; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: eecd &= ~E1000_EECD_CS; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(eeprom->delay_usec); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Terminates a command by inverting the EEPROM's chip select pin ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_release_eeprom(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 eecd; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_release_eeprom"); ch1010832@2198: ch1010832@2198: eecd = er32(EECD); ch1010832@2198: ch1010832@2198: if (hw->eeprom.type == e1000_eeprom_spi) { ch1010832@2198: eecd |= E1000_EECD_CS; /* Pull CS high */ ch1010832@2198: eecd &= ~E1000_EECD_SK; /* Lower SCK */ ch1010832@2198: ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: ch1010832@2198: udelay(hw->eeprom.delay_usec); ch1010832@2198: } else if (hw->eeprom.type == e1000_eeprom_microwire) { ch1010832@2198: /* cleanup eeprom */ ch1010832@2198: ch1010832@2198: /* CS on Microwire is active-high */ ch1010832@2198: eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); ch1010832@2198: ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: ch1010832@2198: /* Rising edge of clock */ ch1010832@2198: eecd |= E1000_EECD_SK; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(hw->eeprom.delay_usec); ch1010832@2198: ch1010832@2198: /* Falling edge of clock */ ch1010832@2198: eecd &= ~E1000_EECD_SK; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: udelay(hw->eeprom.delay_usec); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Stop requesting EEPROM access */ ch1010832@2198: if (hw->mac_type > e1000_82544) { ch1010832@2198: eecd &= ~E1000_EECD_REQ; ch1010832@2198: ew32(EECD, eecd); ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a 16 bit word from the EEPROM. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u16 retry_count = 0; ch1010832@2198: u8 spi_stat_reg; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_spi_eeprom_ready"); ch1010832@2198: ch1010832@2198: /* Read "Status Register" repeatedly until the LSB is cleared. The ch1010832@2198: * EEPROM will signal that the command has been completed by clearing ch1010832@2198: * bit 0 of the internal status register. If it's not cleared within ch1010832@2198: * 5 milliseconds, then error out. ch1010832@2198: */ ch1010832@2198: retry_count = 0; ch1010832@2198: do { ch1010832@2198: e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, ch1010832@2198: hw->eeprom.opcode_bits); ch1010832@2198: spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8); ch1010832@2198: if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) ch1010832@2198: break; ch1010832@2198: ch1010832@2198: udelay(5); ch1010832@2198: retry_count += 5; ch1010832@2198: ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: } while (retry_count < EEPROM_MAX_RETRY_SPI); ch1010832@2198: ch1010832@2198: /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and ch1010832@2198: * only 0-5mSec on 5V devices) ch1010832@2198: */ ch1010832@2198: if (retry_count >= EEPROM_MAX_RETRY_SPI) { ch1010832@2198: DEBUGOUT("SPI EEPROM Status error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a 16 bit word from the EEPROM. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset of word in the EEPROM to read ch1010832@2198: * data - word read from the EEPROM ch1010832@2198: * words - number of words to read ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ch1010832@2198: { ch1010832@2198: s32 ret; ch1010832@2198: spin_lock(&e1000_eeprom_lock); ch1010832@2198: ret = e1000_do_read_eeprom(hw, offset, words, data); ch1010832@2198: spin_unlock(&e1000_eeprom_lock); ch1010832@2198: return ret; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u32 i = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_read_eeprom"); ch1010832@2198: ch1010832@2198: /* If eeprom is not yet detected, do so now */ ch1010832@2198: if (eeprom->word_size == 0) ch1010832@2198: e1000_init_eeprom_params(hw); ch1010832@2198: ch1010832@2198: /* A check for invalid values: offset too large, too many words, and not ch1010832@2198: * enough words. ch1010832@2198: */ ch1010832@2198: if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || ch1010832@2198: (words == 0)) { ch1010832@2198: DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* EEPROM's that don't use EERD to read require us to bit-bang the SPI ch1010832@2198: * directly. In this case, we need to acquire the EEPROM so that ch1010832@2198: * FW or other port software does not interrupt. ch1010832@2198: */ ch1010832@2198: if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) { ch1010832@2198: /* Prepare the EEPROM for bit-bang reading */ ch1010832@2198: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Eerd register EEPROM access requires no eeprom aquire/release */ ch1010832@2198: if (eeprom->use_eerd) ch1010832@2198: return e1000_read_eeprom_eerd(hw, offset, words, data); ch1010832@2198: ch1010832@2198: /* ICH EEPROM access is done via the ICH flash controller */ ch1010832@2198: if (eeprom->type == e1000_eeprom_ich8) ch1010832@2198: return e1000_read_eeprom_ich8(hw, offset, words, data); ch1010832@2198: ch1010832@2198: /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have ch1010832@2198: * acquired the EEPROM at this point, so any returns should relase it */ ch1010832@2198: if (eeprom->type == e1000_eeprom_spi) { ch1010832@2198: u16 word_in; ch1010832@2198: u8 read_opcode = EEPROM_READ_OPCODE_SPI; ch1010832@2198: ch1010832@2198: if (e1000_spi_eeprom_ready(hw)) { ch1010832@2198: e1000_release_eeprom(hw); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: ch1010832@2198: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ ch1010832@2198: if ((eeprom->address_bits == 8) && (offset >= 128)) ch1010832@2198: read_opcode |= EEPROM_A8_OPCODE_SPI; ch1010832@2198: ch1010832@2198: /* Send the READ command (opcode + addr) */ ch1010832@2198: e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); ch1010832@2198: e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits); ch1010832@2198: ch1010832@2198: /* Read the data. The address of the eeprom internally increments with ch1010832@2198: * each byte (spi) being read, saving on the overhead of eeprom setup ch1010832@2198: * and tear-down. The address counter will roll over if reading beyond ch1010832@2198: * the size of the eeprom, thus allowing the entire memory to be read ch1010832@2198: * starting from any offset. */ ch1010832@2198: for (i = 0; i < words; i++) { ch1010832@2198: word_in = e1000_shift_in_ee_bits(hw, 16); ch1010832@2198: data[i] = (word_in >> 8) | (word_in << 8); ch1010832@2198: } ch1010832@2198: } else if (eeprom->type == e1000_eeprom_microwire) { ch1010832@2198: for (i = 0; i < words; i++) { ch1010832@2198: /* Send the READ command (opcode + addr) */ ch1010832@2198: e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, ch1010832@2198: eeprom->opcode_bits); ch1010832@2198: e1000_shift_out_ee_bits(hw, (u16)(offset + i), ch1010832@2198: eeprom->address_bits); ch1010832@2198: ch1010832@2198: /* Read the data. For microwire, each word requires the overhead ch1010832@2198: * of eeprom setup and tear-down. */ ch1010832@2198: data[i] = e1000_shift_in_ee_bits(hw, 16); ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* End this read operation */ ch1010832@2198: e1000_release_eeprom(hw); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a 16 bit word from the EEPROM using the EERD register. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset of word in the EEPROM to read ch1010832@2198: * data - word read from the EEPROM ch1010832@2198: * words - number of words to read ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data) ch1010832@2198: { ch1010832@2198: u32 i, eerd = 0; ch1010832@2198: s32 error = 0; ch1010832@2198: ch1010832@2198: for (i = 0; i < words; i++) { ch1010832@2198: eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + ch1010832@2198: E1000_EEPROM_RW_REG_START; ch1010832@2198: ch1010832@2198: ew32(EERD, eerd); ch1010832@2198: error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); ch1010832@2198: ch1010832@2198: if (error) { ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA); ch1010832@2198: ch1010832@2198: } ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a 16 bit word from the EEPROM using the EEWR register. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset of word in the EEPROM to read ch1010832@2198: * data - word read from the EEPROM ch1010832@2198: * words - number of words to read ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data) ch1010832@2198: { ch1010832@2198: u32 register_value = 0; ch1010832@2198: u32 i = 0; ch1010832@2198: s32 error = 0; ch1010832@2198: ch1010832@2198: if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) ch1010832@2198: return -E1000_ERR_SWFW_SYNC; ch1010832@2198: ch1010832@2198: for (i = 0; i < words; i++) { ch1010832@2198: register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | ch1010832@2198: ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | ch1010832@2198: E1000_EEPROM_RW_REG_START; ch1010832@2198: ch1010832@2198: error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); ch1010832@2198: if (error) { ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ew32(EEWR, register_value); ch1010832@2198: ch1010832@2198: error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); ch1010832@2198: ch1010832@2198: if (error) { ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Polls the status bit (bit 1) of the EERD to determine when the read is done. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) ch1010832@2198: { ch1010832@2198: u32 attempts = 100000; ch1010832@2198: u32 i, reg = 0; ch1010832@2198: s32 done = E1000_ERR_EEPROM; ch1010832@2198: ch1010832@2198: for (i = 0; i < attempts; i++) { ch1010832@2198: if (eerd == E1000_EEPROM_POLL_READ) ch1010832@2198: reg = er32(EERD); ch1010832@2198: else ch1010832@2198: reg = er32(EEWR); ch1010832@2198: ch1010832@2198: if (reg & E1000_EEPROM_RW_REG_DONE) { ch1010832@2198: done = E1000_SUCCESS; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: udelay(5); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return done; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * Description: Determines if the onboard NVM is FLASH or EEPROM. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ****************************************************************************/ ch1010832@2198: static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 eecd = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: return false; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82573) { ch1010832@2198: eecd = er32(EECD); ch1010832@2198: ch1010832@2198: /* Isolate bits 15 & 16 */ ch1010832@2198: eecd = ((eecd >> 15) & 0x03); ch1010832@2198: ch1010832@2198: /* If both bits are set, device is Flash type */ ch1010832@2198: if (eecd == 0x03) { ch1010832@2198: return false; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return true; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Verifies that the EEPROM has a valid checksum ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Reads the first 64 16 bit words of the EEPROM and sums the values read. ch1010832@2198: * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is ch1010832@2198: * valid. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u16 checksum = 0; ch1010832@2198: u16 i, eeprom_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_validate_eeprom_checksum"); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) { ch1010832@2198: /* Check bit 4 of word 10h. If it is 0, firmware is done updating ch1010832@2198: * 10h-12h. Checksum may need to be fixed. */ ch1010832@2198: e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); ch1010832@2198: if ((eeprom_data & 0x10) == 0) { ch1010832@2198: /* Read 0x23 and check bit 15. This bit is a 1 when the checksum ch1010832@2198: * has already been fixed. If the checksum is still wrong and this ch1010832@2198: * bit is a 1, we need to return bad checksum. Otherwise, we need ch1010832@2198: * to set this bit to a 1 and update the checksum. */ ch1010832@2198: e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); ch1010832@2198: if ((eeprom_data & 0x8000) == 0) { ch1010832@2198: eeprom_data |= 0x8000; ch1010832@2198: e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); ch1010832@2198: e1000_update_eeprom_checksum(hw); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /* Drivers must allocate the shadow ram structure for the ch1010832@2198: * EEPROM checksum to be updated. Otherwise, this bit as well ch1010832@2198: * as the checksum must both be set correctly for this ch1010832@2198: * validation to pass. ch1010832@2198: */ ch1010832@2198: e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); ch1010832@2198: if ((eeprom_data & 0x40) == 0) { ch1010832@2198: eeprom_data |= 0x40; ch1010832@2198: e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); ch1010832@2198: e1000_update_eeprom_checksum(hw); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { ch1010832@2198: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { ch1010832@2198: DEBUGOUT("EEPROM Read Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: checksum += eeprom_data; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (checksum == (u16)EEPROM_SUM) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: else { ch1010832@2198: DEBUGOUT("EEPROM Checksum Invalid\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Calculates the EEPROM checksum and writes it to the EEPROM ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. ch1010832@2198: * Writes the difference to word offset 63 of the EEPROM. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl_ext; ch1010832@2198: u16 checksum = 0; ch1010832@2198: u16 i, eeprom_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_update_eeprom_checksum"); ch1010832@2198: ch1010832@2198: for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { ch1010832@2198: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { ch1010832@2198: DEBUGOUT("EEPROM Read Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: checksum += eeprom_data; ch1010832@2198: } ch1010832@2198: checksum = (u16)EEPROM_SUM - checksum; ch1010832@2198: if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { ch1010832@2198: DEBUGOUT("EEPROM Write Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } else if (hw->eeprom.type == e1000_eeprom_flash) { ch1010832@2198: e1000_commit_shadow_ram(hw); ch1010832@2198: } else if (hw->eeprom.type == e1000_eeprom_ich8) { ch1010832@2198: e1000_commit_shadow_ram(hw); ch1010832@2198: /* Reload the EEPROM, or else modifications will not appear ch1010832@2198: * until after next adapter reset. */ ch1010832@2198: ctrl_ext = er32(CTRL_EXT); ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_EE_RST; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: msleep(10); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Parent function for writing words to the different EEPROM types. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset within the EEPROM to be written to ch1010832@2198: * words - number of words to write ch1010832@2198: * data - 16 bit word to be written to the EEPROM ch1010832@2198: * ch1010832@2198: * If e1000_update_eeprom_checksum is not called after this function, the ch1010832@2198: * EEPROM will most likely contain an invalid checksum. ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ch1010832@2198: { ch1010832@2198: s32 ret; ch1010832@2198: spin_lock(&e1000_eeprom_lock); ch1010832@2198: ret = e1000_do_write_eeprom(hw, offset, words, data); ch1010832@2198: spin_unlock(&e1000_eeprom_lock); ch1010832@2198: return ret; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: s32 status = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_write_eeprom"); ch1010832@2198: ch1010832@2198: /* If eeprom is not yet detected, do so now */ ch1010832@2198: if (eeprom->word_size == 0) ch1010832@2198: e1000_init_eeprom_params(hw); ch1010832@2198: ch1010832@2198: /* A check for invalid values: offset too large, too many words, and not ch1010832@2198: * enough words. ch1010832@2198: */ ch1010832@2198: if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || ch1010832@2198: (words == 0)) { ch1010832@2198: DEBUGOUT("\"words\" parameter out of bounds\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* 82573 writes only through eewr */ ch1010832@2198: if (eeprom->use_eewr) ch1010832@2198: return e1000_write_eeprom_eewr(hw, offset, words, data); ch1010832@2198: ch1010832@2198: if (eeprom->type == e1000_eeprom_ich8) ch1010832@2198: return e1000_write_eeprom_ich8(hw, offset, words, data); ch1010832@2198: ch1010832@2198: /* Prepare the EEPROM for writing */ ch1010832@2198: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: ch1010832@2198: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@2198: status = e1000_write_eeprom_microwire(hw, offset, words, data); ch1010832@2198: } else { ch1010832@2198: status = e1000_write_eeprom_spi(hw, offset, words, data); ch1010832@2198: msleep(10); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Done with writing */ ch1010832@2198: e1000_release_eeprom(hw); ch1010832@2198: ch1010832@2198: return status; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a 16 bit word to a given offset in an SPI EEPROM. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset within the EEPROM to be written to ch1010832@2198: * words - number of words to write ch1010832@2198: * data - pointer to array of 8 bit words to be written to the EEPROM ch1010832@2198: * ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u16 widx = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_write_eeprom_spi"); ch1010832@2198: ch1010832@2198: while (widx < words) { ch1010832@2198: u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; ch1010832@2198: ch1010832@2198: if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; ch1010832@2198: ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: ch1010832@2198: /* Send the WRITE ENABLE command (8 bit opcode ) */ ch1010832@2198: e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, ch1010832@2198: eeprom->opcode_bits); ch1010832@2198: ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: ch1010832@2198: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ ch1010832@2198: if ((eeprom->address_bits == 8) && (offset >= 128)) ch1010832@2198: write_opcode |= EEPROM_A8_OPCODE_SPI; ch1010832@2198: ch1010832@2198: /* Send the Write command (8-bit opcode + addr) */ ch1010832@2198: e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); ch1010832@2198: ch1010832@2198: e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2), ch1010832@2198: eeprom->address_bits); ch1010832@2198: ch1010832@2198: /* Send the data */ ch1010832@2198: ch1010832@2198: /* Loop to allow for up to whole page write (32 bytes) of eeprom */ ch1010832@2198: while (widx < words) { ch1010832@2198: u16 word_out = data[widx]; ch1010832@2198: word_out = (word_out >> 8) | (word_out << 8); ch1010832@2198: e1000_shift_out_ee_bits(hw, word_out, 16); ch1010832@2198: widx++; ch1010832@2198: ch1010832@2198: /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE ch1010832@2198: * operation, while the smaller eeproms are capable of an 8-byte ch1010832@2198: * PAGE WRITE operation. Break the inner loop to pass new address ch1010832@2198: */ ch1010832@2198: if ((((offset + widx)*2) % eeprom->page_size) == 0) { ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a 16 bit word to a given offset in a Microwire EEPROM. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset within the EEPROM to be written to ch1010832@2198: * words - number of words to write ch1010832@2198: * data - pointer to array of 16 bit words to be written to the EEPROM ch1010832@2198: * ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, ch1010832@2198: u16 words, u16 *data) ch1010832@2198: { ch1010832@2198: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@2198: u32 eecd; ch1010832@2198: u16 words_written = 0; ch1010832@2198: u16 i = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_write_eeprom_microwire"); ch1010832@2198: ch1010832@2198: /* Send the write enable command to the EEPROM (3-bit opcode plus ch1010832@2198: * 6/8-bit dummy address beginning with 11). It's less work to include ch1010832@2198: * the 11 of the dummy address as part of the opcode than it is to shift ch1010832@2198: * it over the correct number of bits for the address. This puts the ch1010832@2198: * EEPROM into write/erase mode. ch1010832@2198: */ ch1010832@2198: e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, ch1010832@2198: (u16)(eeprom->opcode_bits + 2)); ch1010832@2198: ch1010832@2198: e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); ch1010832@2198: ch1010832@2198: /* Prepare the EEPROM */ ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: ch1010832@2198: while (words_written < words) { ch1010832@2198: /* Send the Write command (3-bit opcode + addr) */ ch1010832@2198: e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, ch1010832@2198: eeprom->opcode_bits); ch1010832@2198: ch1010832@2198: e1000_shift_out_ee_bits(hw, (u16)(offset + words_written), ch1010832@2198: eeprom->address_bits); ch1010832@2198: ch1010832@2198: /* Send the data */ ch1010832@2198: e1000_shift_out_ee_bits(hw, data[words_written], 16); ch1010832@2198: ch1010832@2198: /* Toggle the CS line. This in effect tells the EEPROM to execute ch1010832@2198: * the previous command. ch1010832@2198: */ ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: ch1010832@2198: /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will ch1010832@2198: * signal that the command has been completed by raising the DO signal. ch1010832@2198: * If DO does not go high in 10 milliseconds, then error out. ch1010832@2198: */ ch1010832@2198: for (i = 0; i < 200; i++) { ch1010832@2198: eecd = er32(EECD); ch1010832@2198: if (eecd & E1000_EECD_DO) break; ch1010832@2198: udelay(50); ch1010832@2198: } ch1010832@2198: if (i == 200) { ch1010832@2198: DEBUGOUT("EEPROM Write did not complete\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Recover from write */ ch1010832@2198: e1000_standby_eeprom(hw); ch1010832@2198: ch1010832@2198: words_written++; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Send the write disable command to the EEPROM (3-bit opcode plus ch1010832@2198: * 6/8-bit dummy address beginning with 10). It's less work to include ch1010832@2198: * the 10 of the dummy address as part of the opcode than it is to shift ch1010832@2198: * it over the correct number of bits for the address. This takes the ch1010832@2198: * EEPROM out of write/erase mode. ch1010832@2198: */ ch1010832@2198: e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, ch1010832@2198: (u16)(eeprom->opcode_bits + 2)); ch1010832@2198: ch1010832@2198: e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Flushes the cached eeprom to NVM. This is done by saving the modified values ch1010832@2198: * in the eeprom cache and the non modified values in the currently active bank ch1010832@2198: * to the new bank. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset of word in the EEPROM to read ch1010832@2198: * data - word read from the EEPROM ch1010832@2198: * words - number of words to read ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_commit_shadow_ram(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 attempts = 100000; ch1010832@2198: u32 eecd = 0; ch1010832@2198: u32 flop = 0; ch1010832@2198: u32 i = 0; ch1010832@2198: s32 error = E1000_SUCCESS; ch1010832@2198: u32 old_bank_offset = 0; ch1010832@2198: u32 new_bank_offset = 0; ch1010832@2198: u8 low_byte = 0; ch1010832@2198: u8 high_byte = 0; ch1010832@2198: bool sector_write_failed = false; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82573) { ch1010832@2198: /* The flop register will be used to determine if flash type is STM */ ch1010832@2198: flop = er32(FLOP); ch1010832@2198: for (i=0; i < attempts; i++) { ch1010832@2198: eecd = er32(EECD); ch1010832@2198: if ((eecd & E1000_EECD_FLUPD) == 0) { ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: udelay(5); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (i == attempts) { ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* If STM opcode located in bits 15:8 of flop, reset firmware */ ch1010832@2198: if ((flop & 0xFF00) == E1000_STM_OPCODE) { ch1010832@2198: ew32(HICR, E1000_HICR_FW_RESET); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Perform the flash update */ ch1010832@2198: ew32(EECD, eecd | E1000_EECD_FLUPD); ch1010832@2198: ch1010832@2198: for (i=0; i < attempts; i++) { ch1010832@2198: eecd = er32(EECD); ch1010832@2198: if ((eecd & E1000_EECD_FLUPD) == 0) { ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: udelay(5); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (i == attempts) { ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { ch1010832@2198: /* We're writing to the opposite bank so if we're on bank 1, ch1010832@2198: * write to bank 0 etc. We also need to erase the segment that ch1010832@2198: * is going to be written */ ch1010832@2198: if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { ch1010832@2198: new_bank_offset = hw->flash_bank_size * 2; ch1010832@2198: old_bank_offset = 0; ch1010832@2198: e1000_erase_ich8_4k_segment(hw, 1); ch1010832@2198: } else { ch1010832@2198: old_bank_offset = hw->flash_bank_size * 2; ch1010832@2198: new_bank_offset = 0; ch1010832@2198: e1000_erase_ich8_4k_segment(hw, 0); ch1010832@2198: } ch1010832@2198: ch1010832@2198: sector_write_failed = false; ch1010832@2198: /* Loop for every byte in the shadow RAM, ch1010832@2198: * which is in units of words. */ ch1010832@2198: for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { ch1010832@2198: /* Determine whether to write the value stored ch1010832@2198: * in the other NVM bank or a modified value stored ch1010832@2198: * in the shadow RAM */ ch1010832@2198: if (hw->eeprom_shadow_ram[i].modified) { ch1010832@2198: low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word; ch1010832@2198: udelay(100); ch1010832@2198: error = e1000_verify_write_ich8_byte(hw, ch1010832@2198: (i << 1) + new_bank_offset, low_byte); ch1010832@2198: ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: sector_write_failed = true; ch1010832@2198: else { ch1010832@2198: high_byte = ch1010832@2198: (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); ch1010832@2198: udelay(100); ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, ch1010832@2198: &low_byte); ch1010832@2198: udelay(100); ch1010832@2198: error = e1000_verify_write_ich8_byte(hw, ch1010832@2198: (i << 1) + new_bank_offset, low_byte); ch1010832@2198: ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: sector_write_failed = true; ch1010832@2198: else { ch1010832@2198: e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, ch1010832@2198: &high_byte); ch1010832@2198: udelay(100); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* If the write of the low byte was successful, go ahead and ch1010832@2198: * write the high byte while checking to make sure that if it ch1010832@2198: * is the signature byte, then it is handled properly */ ch1010832@2198: if (!sector_write_failed) { ch1010832@2198: /* If the word is 0x13, then make sure the signature bits ch1010832@2198: * (15:14) are 11b until the commit has completed. ch1010832@2198: * This will allow us to write 10b which indicates the ch1010832@2198: * signature is valid. We want to do this after the write ch1010832@2198: * has completed so that we don't mark the segment valid ch1010832@2198: * while the write is still in progress */ ch1010832@2198: if (i == E1000_ICH_NVM_SIG_WORD) ch1010832@2198: high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; ch1010832@2198: ch1010832@2198: error = e1000_verify_write_ich8_byte(hw, ch1010832@2198: (i << 1) + new_bank_offset + 1, high_byte); ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: sector_write_failed = true; ch1010832@2198: ch1010832@2198: } else { ch1010832@2198: /* If the write failed then break from the loop and ch1010832@2198: * return an error */ ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Don't bother writing the segment valid bits if sector ch1010832@2198: * programming failed. */ ch1010832@2198: if (!sector_write_failed) { ch1010832@2198: /* Finally validate the new segment by setting bit 15:14 ch1010832@2198: * to 10b in word 0x13 , this can be done without an ch1010832@2198: * erase as well since these bits are 11 to start with ch1010832@2198: * and we need to change bit 14 to 0b */ ch1010832@2198: e1000_read_ich8_byte(hw, ch1010832@2198: E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, ch1010832@2198: &high_byte); ch1010832@2198: high_byte &= 0xBF; ch1010832@2198: error = e1000_verify_write_ich8_byte(hw, ch1010832@2198: E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); ch1010832@2198: /* And invalidate the previously valid segment by setting ch1010832@2198: * its signature word (0x13) high_byte to 0b. This can be ch1010832@2198: * done without an erase because flash erase sets all bits ch1010832@2198: * to 1's. We can write 1's to 0's without an erase */ ch1010832@2198: if (error == E1000_SUCCESS) { ch1010832@2198: error = e1000_verify_write_ich8_byte(hw, ch1010832@2198: E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Clear the now not used entry in the cache */ ch1010832@2198: for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { ch1010832@2198: hw->eeprom_shadow_ram[i].modified = false; ch1010832@2198: hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the ch1010832@2198: * second function of dual function devices ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_read_mac_addr(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u16 offset; ch1010832@2198: u16 eeprom_data, i; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_read_mac_addr"); ch1010832@2198: ch1010832@2198: for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { ch1010832@2198: offset = i >> 1; ch1010832@2198: if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { ch1010832@2198: DEBUGOUT("EEPROM Read Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF); ch1010832@2198: hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8); ch1010832@2198: } ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: case e1000_82546: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: if (er32(STATUS) & E1000_STATUS_FUNC_1) ch1010832@2198: hw->perm_mac_addr[5] ^= 0x01; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: for (i = 0; i < NODE_ADDRESS_SIZE; i++) ch1010832@2198: hw->mac_addr[i] = hw->perm_mac_addr[i]; ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Initializes receive address filters. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Places the MAC address in receive address register 0 and clears the rest ch1010832@2198: * of the receive addresss registers. Clears the multicast table. Assumes ch1010832@2198: * the receiver is in reset when the routine is called. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_init_rx_addrs(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 i; ch1010832@2198: u32 rar_num; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_init_rx_addrs"); ch1010832@2198: ch1010832@2198: /* Setup the receive address. */ ch1010832@2198: DEBUGOUT("Programming MAC Address into RAR[0]\n"); ch1010832@2198: ch1010832@2198: e1000_rar_set(hw, hw->mac_addr, 0); ch1010832@2198: ch1010832@2198: rar_num = E1000_RAR_ENTRIES; ch1010832@2198: ch1010832@2198: /* Reserve a spot for the Locally Administered Address to work around ch1010832@2198: * an 82571 issue in which a reset on one port will reload the MAC on ch1010832@2198: * the other port. */ ch1010832@2198: if ((hw->mac_type == e1000_82571) && (hw->laa_is_present)) ch1010832@2198: rar_num -= 1; ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: rar_num = E1000_RAR_ENTRIES_ICH8LAN; ch1010832@2198: ch1010832@2198: /* Zero out the other 15 receive addresses. */ ch1010832@2198: DEBUGOUT("Clearing RAR[1-15]\n"); ch1010832@2198: for (i = 1; i < rar_num; i++) { ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Hashes an address to determine its location in the multicast table ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * mc_addr - the multicast address to hash ch1010832@2198: *****************************************************************************/ ch1010832@2198: u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) ch1010832@2198: { ch1010832@2198: u32 hash_value = 0; ch1010832@2198: ch1010832@2198: /* The portion of the address that is used for the hash table is ch1010832@2198: * determined by the mc_filter_type setting. ch1010832@2198: */ ch1010832@2198: switch (hw->mc_filter_type) { ch1010832@2198: /* [0] [1] [2] [3] [4] [5] ch1010832@2198: * 01 AA 00 12 34 56 ch1010832@2198: * LSB MSB ch1010832@2198: */ ch1010832@2198: case 0: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /* [47:38] i.e. 0x158 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2)); ch1010832@2198: } else { ch1010832@2198: /* [47:36] i.e. 0x563 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: case 1: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /* [46:37] i.e. 0x2B1 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3)); ch1010832@2198: } else { ch1010832@2198: /* [46:35] i.e. 0xAC6 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: case 2: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /*[45:36] i.e. 0x163 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); ch1010832@2198: } else { ch1010832@2198: /* [45:34] i.e. 0x5D8 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: case 3: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /* [43:34] i.e. 0x18D for above example address */ ch1010832@2198: hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); ch1010832@2198: } else { ch1010832@2198: /* [43:32] i.e. 0x634 for above example address */ ch1010832@2198: hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: hash_value &= 0xFFF; ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: hash_value &= 0x3FF; ch1010832@2198: ch1010832@2198: return hash_value; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Sets the bit in the multicast table corresponding to the hash value. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * hash_value - Multicast address hash value ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_mta_set(struct e1000_hw *hw, u32 hash_value) ch1010832@2198: { ch1010832@2198: u32 hash_bit, hash_reg; ch1010832@2198: u32 mta; ch1010832@2198: u32 temp; ch1010832@2198: ch1010832@2198: /* The MTA is a register array of 128 32-bit registers. ch1010832@2198: * It is treated like an array of 4096 bits. We want to set ch1010832@2198: * bit BitArray[hash_value]. So we figure out what register ch1010832@2198: * the bit is in, read it, OR in the new bit, then write ch1010832@2198: * back the new value. The register is determined by the ch1010832@2198: * upper 7 bits of the hash value and the bit within that ch1010832@2198: * register are determined by the lower 5 bits of the value. ch1010832@2198: */ ch1010832@2198: hash_reg = (hash_value >> 5) & 0x7F; ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: hash_reg &= 0x1F; ch1010832@2198: ch1010832@2198: hash_bit = hash_value & 0x1F; ch1010832@2198: ch1010832@2198: mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); ch1010832@2198: ch1010832@2198: mta |= (1 << hash_bit); ch1010832@2198: ch1010832@2198: /* If we are on an 82544 and we are trying to write an odd offset ch1010832@2198: * in the MTA, save off the previous entry before writing and ch1010832@2198: * restore the old value after writing. ch1010832@2198: */ ch1010832@2198: if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { ch1010832@2198: temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } else { ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Puts an ethernet address into a receive address register. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * addr - Address to put into receive address register ch1010832@2198: * index - Receive address register to write ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ch1010832@2198: { ch1010832@2198: u32 rar_low, rar_high; ch1010832@2198: ch1010832@2198: /* HW expects these in little endian so we reverse the byte order ch1010832@2198: * from network order (big endian) to little endian ch1010832@2198: */ ch1010832@2198: rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | ch1010832@2198: ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); ch1010832@2198: rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); ch1010832@2198: ch1010832@2198: /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx ch1010832@2198: * unit hang. ch1010832@2198: * ch1010832@2198: * Description: ch1010832@2198: * If there are any Rx frames queued up or otherwise present in the HW ch1010832@2198: * before RSS is enabled, and then we enable RSS, the HW Rx unit will ch1010832@2198: * hang. To work around this issue, we have to disable receives and ch1010832@2198: * flush out all Rx frames before we enable RSS. To do so, we modify we ch1010832@2198: * redirect all Rx traffic to manageability and then reset the HW. ch1010832@2198: * This flushes away Rx frames, and (since the redirections to ch1010832@2198: * manageability persists across resets) keeps new ones from coming in ch1010832@2198: * while we work. Then, we clear the Address Valid AV bit for all MAC ch1010832@2198: * addresses and undo the re-direction to manageability. ch1010832@2198: * Now, frames are coming in again, but the MAC won't accept them, so ch1010832@2198: * far so good. We now proceed to initialize RSS (if necessary) and ch1010832@2198: * configure the Rx unit. Last, we re-enable the AV bits and continue ch1010832@2198: * on our merry way. ch1010832@2198: */ ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: if (hw->leave_av_bit_off) ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: /* Indicate to hardware the Address is Valid. */ ch1010832@2198: rar_high |= E1000_RAH_AV; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a value to the specified offset in the VLAN filter table. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - Offset in VLAN filer table to write ch1010832@2198: * value - Value to write into VLAN filter table ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ch1010832@2198: { ch1010832@2198: u32 temp; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: return; ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { ch1010832@2198: temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } else { ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Clears the VLAN filer table ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_clear_vfta(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 offset; ch1010832@2198: u32 vfta_value = 0; ch1010832@2198: u32 vfta_offset = 0; ch1010832@2198: u32 vfta_bit_in_reg = 0; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: return; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82573) { ch1010832@2198: if (hw->mng_cookie.vlan_id != 0) { ch1010832@2198: /* The VFTA is a 4096b bit-field, each identifying a single VLAN ch1010832@2198: * ID. The following operations determine which 32b entry ch1010832@2198: * (i.e. offset) into the array we want to set the VLAN ID ch1010832@2198: * (i.e. bit) of the manageability unit. */ ch1010832@2198: vfta_offset = (hw->mng_cookie.vlan_id >> ch1010832@2198: E1000_VFTA_ENTRY_SHIFT) & ch1010832@2198: E1000_VFTA_ENTRY_MASK; ch1010832@2198: vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & ch1010832@2198: E1000_VFTA_ENTRY_BIT_SHIFT_MASK); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { ch1010832@2198: /* If the offset we want to clear is the same offset of the ch1010832@2198: * manageability VLAN ID, then clear all bits except that of the ch1010832@2198: * manageability unit */ ch1010832@2198: vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; ch1010832@2198: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_id_led_init(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ledctl; ch1010832@2198: const u32 ledctl_mask = 0x000000FF; ch1010832@2198: const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; ch1010832@2198: const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; ch1010832@2198: u16 eeprom_data, i, temp; ch1010832@2198: const u16 led_mask = 0x0F; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_id_led_init"); ch1010832@2198: ch1010832@2198: if (hw->mac_type < e1000_82540) { ch1010832@2198: /* Nothing to do */ ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ledctl = er32(LEDCTL); ch1010832@2198: hw->ledctl_default = ledctl; ch1010832@2198: hw->ledctl_mode1 = hw->ledctl_default; ch1010832@2198: hw->ledctl_mode2 = hw->ledctl_default; ch1010832@2198: ch1010832@2198: if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { ch1010832@2198: DEBUGOUT("EEPROM Read Error\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82573) && ch1010832@2198: (eeprom_data == ID_LED_RESERVED_82573)) ch1010832@2198: eeprom_data = ID_LED_DEFAULT_82573; ch1010832@2198: else if ((eeprom_data == ID_LED_RESERVED_0000) || ch1010832@2198: (eeprom_data == ID_LED_RESERVED_FFFF)) { ch1010832@2198: if (hw->mac_type == e1000_ich8lan) ch1010832@2198: eeprom_data = ID_LED_DEFAULT_ICH8LAN; ch1010832@2198: else ch1010832@2198: eeprom_data = ID_LED_DEFAULT; ch1010832@2198: } ch1010832@2198: ch1010832@2198: for (i = 0; i < 4; i++) { ch1010832@2198: temp = (eeprom_data >> (i << 2)) & led_mask; ch1010832@2198: switch (temp) { ch1010832@2198: case ID_LED_ON1_DEF2: ch1010832@2198: case ID_LED_ON1_ON2: ch1010832@2198: case ID_LED_ON1_OFF2: ch1010832@2198: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ch1010832@2198: hw->ledctl_mode1 |= ledctl_on << (i << 3); ch1010832@2198: break; ch1010832@2198: case ID_LED_OFF1_DEF2: ch1010832@2198: case ID_LED_OFF1_ON2: ch1010832@2198: case ID_LED_OFF1_OFF2: ch1010832@2198: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ch1010832@2198: hw->ledctl_mode1 |= ledctl_off << (i << 3); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: /* Do nothing */ ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: switch (temp) { ch1010832@2198: case ID_LED_DEF1_ON2: ch1010832@2198: case ID_LED_ON1_ON2: ch1010832@2198: case ID_LED_OFF1_ON2: ch1010832@2198: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ch1010832@2198: hw->ledctl_mode2 |= ledctl_on << (i << 3); ch1010832@2198: break; ch1010832@2198: case ID_LED_DEF1_OFF2: ch1010832@2198: case ID_LED_ON1_OFF2: ch1010832@2198: case ID_LED_OFF1_OFF2: ch1010832@2198: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ch1010832@2198: hw->ledctl_mode2 |= ledctl_off << (i << 3); ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: /* Do nothing */ ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Prepares SW controlable LED for use and saves the current state of the LED. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_setup_led(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ledctl; ch1010832@2198: s32 ret_val = E1000_SUCCESS; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_setup_led"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: case e1000_82543: ch1010832@2198: case e1000_82544: ch1010832@2198: /* No setup necessary */ ch1010832@2198: break; ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82547: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: /* Turn off PHY Smart Power Down (if enabled) */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@2198: &hw->phy_spd_default); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@2198: (u16)(hw->phy_spd_default & ch1010832@2198: ~IGP01E1000_GMII_SPD)); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: /* Fall Through */ ch1010832@2198: default: ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: ledctl = er32(LEDCTL); ch1010832@2198: /* Save current LEDCTL settings */ ch1010832@2198: hw->ledctl_default = ledctl; ch1010832@2198: /* Turn off LED0 */ ch1010832@2198: ledctl &= ~(E1000_LEDCTL_LED0_IVRT | ch1010832@2198: E1000_LEDCTL_LED0_BLINK | ch1010832@2198: E1000_LEDCTL_LED0_MODE_MASK); ch1010832@2198: ledctl |= (E1000_LEDCTL_MODE_LED_OFF << ch1010832@2198: E1000_LEDCTL_LED0_MODE_SHIFT); ch1010832@2198: ew32(LEDCTL, ledctl); ch1010832@2198: } else if (hw->media_type == e1000_media_type_copper) ch1010832@2198: ew32(LEDCTL, hw->ledctl_mode1); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Used on 82571 and later Si that has LED blink bits. ch1010832@2198: * Callers must use their own timer and should have already called ch1010832@2198: * e1000_id_led_init() ch1010832@2198: * Call e1000_cleanup led() to stop blinking ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_blink_led_start(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s16 i; ch1010832@2198: u32 ledctl_blink = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_id_led_blink_on"); ch1010832@2198: ch1010832@2198: if (hw->mac_type < e1000_82571) { ch1010832@2198: /* Nothing to do */ ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: /* always blink LED0 for PCI-E fiber */ ch1010832@2198: ledctl_blink = E1000_LEDCTL_LED0_BLINK | ch1010832@2198: (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); ch1010832@2198: } else { ch1010832@2198: /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ ch1010832@2198: ledctl_blink = hw->ledctl_mode2; ch1010832@2198: for (i=0; i < 4; i++) ch1010832@2198: if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == ch1010832@2198: E1000_LEDCTL_MODE_LED_ON) ch1010832@2198: ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); ch1010832@2198: } ch1010832@2198: ch1010832@2198: ew32(LEDCTL, ledctl_blink); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Restores the saved state of the SW controlable LED. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_cleanup_led(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val = E1000_SUCCESS; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_cleanup_led"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: case e1000_82543: ch1010832@2198: case e1000_82544: ch1010832@2198: /* No cleanup necessary */ ch1010832@2198: break; ch1010832@2198: case e1000_82541: ch1010832@2198: case e1000_82547: ch1010832@2198: case e1000_82541_rev_2: ch1010832@2198: case e1000_82547_rev_2: ch1010832@2198: /* Turn on PHY Smart Power Down (if previously enabled) */ ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@2198: hw->phy_spd_default); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: /* Fall Through */ ch1010832@2198: default: ch1010832@2198: if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: /* Restore LEDCTL settings */ ch1010832@2198: ew32(LEDCTL, hw->ledctl_default); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Turns on the software controllable LED ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_led_on(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_led_on"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: case e1000_82543: ch1010832@2198: /* Set SW Defineable Pin 0 to turn on the LED */ ch1010832@2198: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: break; ch1010832@2198: case e1000_82544: ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: /* Set SW Defineable Pin 0 to turn on the LED */ ch1010832@2198: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: } else { ch1010832@2198: /* Clear SW Defineable Pin 0 to turn on the LED */ ch1010832@2198: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: /* Clear SW Defineable Pin 0 to turn on the LED */ ch1010832@2198: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: } else if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, ch1010832@2198: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); ch1010832@2198: } else if (hw->media_type == e1000_media_type_copper) { ch1010832@2198: ew32(LEDCTL, hw->ledctl_mode2); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Turns off the software controllable LED ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_led_off(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl = er32(CTRL); ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_led_off"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: case e1000_82543: ch1010832@2198: /* Clear SW Defineable Pin 0 to turn off the LED */ ch1010832@2198: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: break; ch1010832@2198: case e1000_82544: ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: /* Clear SW Defineable Pin 0 to turn off the LED */ ch1010832@2198: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: } else { ch1010832@2198: /* Set SW Defineable Pin 0 to turn off the LED */ ch1010832@2198: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: if (hw->media_type == e1000_media_type_fiber) { ch1010832@2198: /* Set SW Defineable Pin 0 to turn off the LED */ ch1010832@2198: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@2198: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@2198: } else if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, ch1010832@2198: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); ch1010832@2198: } else if (hw->media_type == e1000_media_type_copper) { ch1010832@2198: ew32(LEDCTL, hw->ledctl_mode1); ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Clears all hardware statistics counters. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_clear_hw_cntrs(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: volatile u32 temp; ch1010832@2198: ch1010832@2198: temp = er32(CRCERRS); ch1010832@2198: temp = er32(SYMERRS); ch1010832@2198: temp = er32(MPC); ch1010832@2198: temp = er32(SCC); ch1010832@2198: temp = er32(ECOL); ch1010832@2198: temp = er32(MCC); ch1010832@2198: temp = er32(LATECOL); ch1010832@2198: temp = er32(COLC); ch1010832@2198: temp = er32(DC); ch1010832@2198: temp = er32(SEC); ch1010832@2198: temp = er32(RLEC); ch1010832@2198: temp = er32(XONRXC); ch1010832@2198: temp = er32(XONTXC); ch1010832@2198: temp = er32(XOFFRXC); ch1010832@2198: temp = er32(XOFFTXC); ch1010832@2198: temp = er32(FCRUC); ch1010832@2198: ch1010832@2198: if (hw->mac_type != e1000_ich8lan) { ch1010832@2198: temp = er32(PRC64); ch1010832@2198: temp = er32(PRC127); ch1010832@2198: temp = er32(PRC255); ch1010832@2198: temp = er32(PRC511); ch1010832@2198: temp = er32(PRC1023); ch1010832@2198: temp = er32(PRC1522); ch1010832@2198: } ch1010832@2198: ch1010832@2198: temp = er32(GPRC); ch1010832@2198: temp = er32(BPRC); ch1010832@2198: temp = er32(MPRC); ch1010832@2198: temp = er32(GPTC); ch1010832@2198: temp = er32(GORCL); ch1010832@2198: temp = er32(GORCH); ch1010832@2198: temp = er32(GOTCL); ch1010832@2198: temp = er32(GOTCH); ch1010832@2198: temp = er32(RNBC); ch1010832@2198: temp = er32(RUC); ch1010832@2198: temp = er32(RFC); ch1010832@2198: temp = er32(ROC); ch1010832@2198: temp = er32(RJC); ch1010832@2198: temp = er32(TORL); ch1010832@2198: temp = er32(TORH); ch1010832@2198: temp = er32(TOTL); ch1010832@2198: temp = er32(TOTH); ch1010832@2198: temp = er32(TPR); ch1010832@2198: temp = er32(TPT); ch1010832@2198: ch1010832@2198: if (hw->mac_type != e1000_ich8lan) { ch1010832@2198: temp = er32(PTC64); ch1010832@2198: temp = er32(PTC127); ch1010832@2198: temp = er32(PTC255); ch1010832@2198: temp = er32(PTC511); ch1010832@2198: temp = er32(PTC1023); ch1010832@2198: temp = er32(PTC1522); ch1010832@2198: } ch1010832@2198: ch1010832@2198: temp = er32(MPTC); ch1010832@2198: temp = er32(BPTC); ch1010832@2198: ch1010832@2198: if (hw->mac_type < e1000_82543) return; ch1010832@2198: ch1010832@2198: temp = er32(ALGNERRC); ch1010832@2198: temp = er32(RXERRC); ch1010832@2198: temp = er32(TNCRS); ch1010832@2198: temp = er32(CEXTERR); ch1010832@2198: temp = er32(TSCTC); ch1010832@2198: temp = er32(TSCTFC); ch1010832@2198: ch1010832@2198: if (hw->mac_type <= e1000_82544) return; ch1010832@2198: ch1010832@2198: temp = er32(MGTPRC); ch1010832@2198: temp = er32(MGTPDC); ch1010832@2198: temp = er32(MGTPTC); ch1010832@2198: ch1010832@2198: if (hw->mac_type <= e1000_82547_rev_2) return; ch1010832@2198: ch1010832@2198: temp = er32(IAC); ch1010832@2198: temp = er32(ICRXOC); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) return; ch1010832@2198: ch1010832@2198: temp = er32(ICRXPTC); ch1010832@2198: temp = er32(ICRXATC); ch1010832@2198: temp = er32(ICTXPTC); ch1010832@2198: temp = er32(ICTXATC); ch1010832@2198: temp = er32(ICTXQEC); ch1010832@2198: temp = er32(ICTXQMTC); ch1010832@2198: temp = er32(ICRXDMTC); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Resets Adaptive IFS to its default state. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * Call this after e1000_init_hw. You may override the IFS defaults by setting ch1010832@2198: * hw->ifs_params_forced to true. However, you must initialize hw-> ch1010832@2198: * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio ch1010832@2198: * before calling this function. ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_reset_adaptive(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: DEBUGFUNC("e1000_reset_adaptive"); ch1010832@2198: ch1010832@2198: if (hw->adaptive_ifs) { ch1010832@2198: if (!hw->ifs_params_forced) { ch1010832@2198: hw->current_ifs_val = 0; ch1010832@2198: hw->ifs_min_val = IFS_MIN; ch1010832@2198: hw->ifs_max_val = IFS_MAX; ch1010832@2198: hw->ifs_step_size = IFS_STEP; ch1010832@2198: hw->ifs_ratio = IFS_RATIO; ch1010832@2198: } ch1010832@2198: hw->in_ifs_mode = false; ch1010832@2198: ew32(AIT, 0); ch1010832@2198: } else { ch1010832@2198: DEBUGOUT("Not in Adaptive IFS mode!\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Called during the callback/watchdog routine to update IFS value based on ch1010832@2198: * the ratio of transmits to collisions. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * tx_packets - Number of transmits since last callback ch1010832@2198: * total_collisions - Number of collisions since last callback ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_update_adaptive(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: DEBUGFUNC("e1000_update_adaptive"); ch1010832@2198: ch1010832@2198: if (hw->adaptive_ifs) { ch1010832@2198: if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { ch1010832@2198: if (hw->tx_packet_delta > MIN_NUM_XMITS) { ch1010832@2198: hw->in_ifs_mode = true; ch1010832@2198: if (hw->current_ifs_val < hw->ifs_max_val) { ch1010832@2198: if (hw->current_ifs_val == 0) ch1010832@2198: hw->current_ifs_val = hw->ifs_min_val; ch1010832@2198: else ch1010832@2198: hw->current_ifs_val += hw->ifs_step_size; ch1010832@2198: ew32(AIT, hw->current_ifs_val); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { ch1010832@2198: hw->current_ifs_val = 0; ch1010832@2198: hw->in_ifs_mode = false; ch1010832@2198: ew32(AIT, 0); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: DEBUGOUT("Not in Adaptive IFS mode!\n"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * frame_len - The length of the frame in question ch1010832@2198: * mac_addr - The Ethernet destination address of the frame in question ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, ch1010832@2198: u32 frame_len, u8 *mac_addr) ch1010832@2198: { ch1010832@2198: u64 carry_bit; ch1010832@2198: ch1010832@2198: /* First adjust the frame length. */ ch1010832@2198: frame_len--; ch1010832@2198: /* We need to adjust the statistics counters, since the hardware ch1010832@2198: * counters overcount this packet as a CRC error and undercount ch1010832@2198: * the packet as a good packet ch1010832@2198: */ ch1010832@2198: /* This packet should not be counted as a CRC error. */ ch1010832@2198: stats->crcerrs--; ch1010832@2198: /* This packet does count as a Good Packet Received. */ ch1010832@2198: stats->gprc++; ch1010832@2198: ch1010832@2198: /* Adjust the Good Octets received counters */ ch1010832@2198: carry_bit = 0x80000000 & stats->gorcl; ch1010832@2198: stats->gorcl += frame_len; ch1010832@2198: /* If the high bit of Gorcl (the low 32 bits of the Good Octets ch1010832@2198: * Received Count) was one before the addition, ch1010832@2198: * AND it is zero after, then we lost the carry out, ch1010832@2198: * need to add one to Gorch (Good Octets Received Count High). ch1010832@2198: * This could be simplified if all environments supported ch1010832@2198: * 64-bit integers. ch1010832@2198: */ ch1010832@2198: if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) ch1010832@2198: stats->gorch++; ch1010832@2198: /* Is this a broadcast or multicast? Check broadcast first, ch1010832@2198: * since the test for a multicast frame will test positive on ch1010832@2198: * a broadcast frame. ch1010832@2198: */ ch1010832@2198: if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff)) ch1010832@2198: /* Broadcast packet */ ch1010832@2198: stats->bprc++; ch1010832@2198: else if (*mac_addr & 0x01) ch1010832@2198: /* Multicast packet */ ch1010832@2198: stats->mprc++; ch1010832@2198: ch1010832@2198: if (frame_len == hw->max_frame_size) { ch1010832@2198: /* In this case, the hardware has overcounted the number of ch1010832@2198: * oversize frames. ch1010832@2198: */ ch1010832@2198: if (stats->roc > 0) ch1010832@2198: stats->roc--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Adjust the bin counters when the extra byte put the frame in the ch1010832@2198: * wrong bin. Remember that the frame_len was adjusted above. ch1010832@2198: */ ch1010832@2198: if (frame_len == 64) { ch1010832@2198: stats->prc64++; ch1010832@2198: stats->prc127--; ch1010832@2198: } else if (frame_len == 127) { ch1010832@2198: stats->prc127++; ch1010832@2198: stats->prc255--; ch1010832@2198: } else if (frame_len == 255) { ch1010832@2198: stats->prc255++; ch1010832@2198: stats->prc511--; ch1010832@2198: } else if (frame_len == 511) { ch1010832@2198: stats->prc511++; ch1010832@2198: stats->prc1023--; ch1010832@2198: } else if (frame_len == 1023) { ch1010832@2198: stats->prc1023++; ch1010832@2198: stats->prc1522--; ch1010832@2198: } else if (frame_len == 1522) { ch1010832@2198: stats->prc1522++; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Gets the current PCI bus type, speed, and width of the hardware ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: void e1000_get_bus_info(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 pci_ex_link_status; ch1010832@2198: u32 status; ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82542_rev2_0: ch1010832@2198: case e1000_82542_rev2_1: ch1010832@2198: hw->bus_type = e1000_bus_type_pci; ch1010832@2198: hw->bus_speed = e1000_bus_speed_unknown; ch1010832@2198: hw->bus_width = e1000_bus_width_unknown; ch1010832@2198: break; ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: case e1000_82573: ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: hw->bus_type = e1000_bus_type_pci_express; ch1010832@2198: hw->bus_speed = e1000_bus_speed_2500; ch1010832@2198: ret_val = e1000_read_pcie_cap_reg(hw, ch1010832@2198: PCI_EX_LINK_STATUS, ch1010832@2198: &pci_ex_link_status); ch1010832@2198: if (ret_val) ch1010832@2198: hw->bus_width = e1000_bus_width_unknown; ch1010832@2198: else ch1010832@2198: hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> ch1010832@2198: PCI_EX_LINK_WIDTH_SHIFT; ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: hw->bus_type = e1000_bus_type_pci_express; ch1010832@2198: hw->bus_speed = e1000_bus_speed_2500; ch1010832@2198: hw->bus_width = e1000_bus_width_pciex_1; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: status = er32(STATUS); ch1010832@2198: hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? ch1010832@2198: e1000_bus_type_pcix : e1000_bus_type_pci; ch1010832@2198: ch1010832@2198: if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { ch1010832@2198: hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? ch1010832@2198: e1000_bus_speed_66 : e1000_bus_speed_120; ch1010832@2198: } else if (hw->bus_type == e1000_bus_type_pci) { ch1010832@2198: hw->bus_speed = (status & E1000_STATUS_PCI66) ? ch1010832@2198: e1000_bus_speed_66 : e1000_bus_speed_33; ch1010832@2198: } else { ch1010832@2198: switch (status & E1000_STATUS_PCIX_SPEED) { ch1010832@2198: case E1000_STATUS_PCIX_SPEED_66: ch1010832@2198: hw->bus_speed = e1000_bus_speed_66; ch1010832@2198: break; ch1010832@2198: case E1000_STATUS_PCIX_SPEED_100: ch1010832@2198: hw->bus_speed = e1000_bus_speed_100; ch1010832@2198: break; ch1010832@2198: case E1000_STATUS_PCIX_SPEED_133: ch1010832@2198: hw->bus_speed = e1000_bus_speed_133; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: hw->bus_speed = e1000_bus_speed_reserved; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: hw->bus_width = (status & E1000_STATUS_BUS64) ? ch1010832@2198: e1000_bus_width_64 : e1000_bus_width_32; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a value to one of the devices registers using port I/O (as opposed to ch1010832@2198: * memory mapped I/O). Only 82544 and newer devices support port I/O. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset to write to ch1010832@2198: * value - value to write ch1010832@2198: *****************************************************************************/ ch1010832@2198: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) ch1010832@2198: { ch1010832@2198: unsigned long io_addr = hw->io_base; ch1010832@2198: unsigned long io_data = hw->io_base + 4; ch1010832@2198: ch1010832@2198: e1000_io_write(hw, io_addr, offset); ch1010832@2198: e1000_io_write(hw, io_data, value); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Estimates the cable length. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * min_length - The estimated minimum length ch1010832@2198: * max_length - The estimated maximum length ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_XXX ch1010832@2198: * E1000_SUCCESS ch1010832@2198: * ch1010832@2198: * This function always returns a ranged length (minimum & maximum). ch1010832@2198: * So for M88 phy's, this function interprets the one value returned from the ch1010832@2198: * register to the minimum and maximum range. ch1010832@2198: * For IGP phy's, the function calculates the range by the AGC registers. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, ch1010832@2198: u16 *max_length) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 agc_value = 0; ch1010832@2198: u16 i, phy_data; ch1010832@2198: u16 cable_length; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_cable_length"); ch1010832@2198: ch1010832@2198: *min_length = *max_length = 0; ch1010832@2198: ch1010832@2198: /* Use old method for Phy older than IGP */ ch1010832@2198: if (hw->phy_type == e1000_phy_m88) { ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> ch1010832@2198: M88E1000_PSSR_CABLE_LENGTH_SHIFT; ch1010832@2198: ch1010832@2198: /* Convert the enum value to ranged values */ ch1010832@2198: switch (cable_length) { ch1010832@2198: case e1000_cable_length_50: ch1010832@2198: *min_length = 0; ch1010832@2198: *max_length = e1000_igp_cable_length_50; ch1010832@2198: break; ch1010832@2198: case e1000_cable_length_50_80: ch1010832@2198: *min_length = e1000_igp_cable_length_50; ch1010832@2198: *max_length = e1000_igp_cable_length_80; ch1010832@2198: break; ch1010832@2198: case e1000_cable_length_80_110: ch1010832@2198: *min_length = e1000_igp_cable_length_80; ch1010832@2198: *max_length = e1000_igp_cable_length_110; ch1010832@2198: break; ch1010832@2198: case e1000_cable_length_110_140: ch1010832@2198: *min_length = e1000_igp_cable_length_110; ch1010832@2198: *max_length = e1000_igp_cable_length_140; ch1010832@2198: break; ch1010832@2198: case e1000_cable_length_140: ch1010832@2198: *min_length = e1000_igp_cable_length_140; ch1010832@2198: *max_length = e1000_igp_cable_length_170; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } else if (hw->phy_type == e1000_phy_gg82563) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; ch1010832@2198: ch1010832@2198: switch (cable_length) { ch1010832@2198: case e1000_gg_cable_length_60: ch1010832@2198: *min_length = 0; ch1010832@2198: *max_length = e1000_igp_cable_length_60; ch1010832@2198: break; ch1010832@2198: case e1000_gg_cable_length_60_115: ch1010832@2198: *min_length = e1000_igp_cable_length_60; ch1010832@2198: *max_length = e1000_igp_cable_length_115; ch1010832@2198: break; ch1010832@2198: case e1000_gg_cable_length_115_150: ch1010832@2198: *min_length = e1000_igp_cable_length_115; ch1010832@2198: *max_length = e1000_igp_cable_length_150; ch1010832@2198: break; ch1010832@2198: case e1000_gg_cable_length_150: ch1010832@2198: *min_length = e1000_igp_cable_length_150; ch1010832@2198: *max_length = e1000_igp_cable_length_180; ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ ch1010832@2198: u16 cur_agc_value; ch1010832@2198: u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; ch1010832@2198: u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = ch1010832@2198: {IGP01E1000_PHY_AGC_A, ch1010832@2198: IGP01E1000_PHY_AGC_B, ch1010832@2198: IGP01E1000_PHY_AGC_C, ch1010832@2198: IGP01E1000_PHY_AGC_D}; ch1010832@2198: /* Read the AGC registers for all channels */ ch1010832@2198: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; ch1010832@2198: ch1010832@2198: /* Value bound check. */ ch1010832@2198: if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || ch1010832@2198: (cur_agc_value == 0)) ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: ch1010832@2198: agc_value += cur_agc_value; ch1010832@2198: ch1010832@2198: /* Update minimal AGC value. */ ch1010832@2198: if (min_agc_value > cur_agc_value) ch1010832@2198: min_agc_value = cur_agc_value; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Remove the minimal AGC result for length < 50m */ ch1010832@2198: if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { ch1010832@2198: agc_value -= min_agc_value; ch1010832@2198: ch1010832@2198: /* Get the average length of the remaining 3 channels */ ch1010832@2198: agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); ch1010832@2198: } else { ch1010832@2198: /* Get the average length of all the 4 channels. */ ch1010832@2198: agc_value /= IGP01E1000_PHY_CHANNEL_NUM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Set the range of the calculated length. */ ch1010832@2198: *min_length = ((e1000_igp_cable_length_table[agc_value] - ch1010832@2198: IGP01E1000_AGC_RANGE) > 0) ? ch1010832@2198: (e1000_igp_cable_length_table[agc_value] - ch1010832@2198: IGP01E1000_AGC_RANGE) : 0; ch1010832@2198: *max_length = e1000_igp_cable_length_table[agc_value] + ch1010832@2198: IGP01E1000_AGC_RANGE; ch1010832@2198: } else if (hw->phy_type == e1000_phy_igp_2 || ch1010832@2198: hw->phy_type == e1000_phy_igp_3) { ch1010832@2198: u16 cur_agc_index, max_agc_index = 0; ch1010832@2198: u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; ch1010832@2198: u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = ch1010832@2198: {IGP02E1000_PHY_AGC_A, ch1010832@2198: IGP02E1000_PHY_AGC_B, ch1010832@2198: IGP02E1000_PHY_AGC_C, ch1010832@2198: IGP02E1000_PHY_AGC_D}; ch1010832@2198: /* Read the AGC registers for all channels */ ch1010832@2198: for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Getting bits 15:9, which represent the combination of course and ch1010832@2198: * fine gain values. The result is a number that can be put into ch1010832@2198: * the lookup table to obtain the approximate cable length. */ ch1010832@2198: cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & ch1010832@2198: IGP02E1000_AGC_LENGTH_MASK; ch1010832@2198: ch1010832@2198: /* Array index bound check. */ ch1010832@2198: if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || ch1010832@2198: (cur_agc_index == 0)) ch1010832@2198: return -E1000_ERR_PHY; ch1010832@2198: ch1010832@2198: /* Remove min & max AGC values from calculation. */ ch1010832@2198: if (e1000_igp_2_cable_length_table[min_agc_index] > ch1010832@2198: e1000_igp_2_cable_length_table[cur_agc_index]) ch1010832@2198: min_agc_index = cur_agc_index; ch1010832@2198: if (e1000_igp_2_cable_length_table[max_agc_index] < ch1010832@2198: e1000_igp_2_cable_length_table[cur_agc_index]) ch1010832@2198: max_agc_index = cur_agc_index; ch1010832@2198: ch1010832@2198: agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; ch1010832@2198: } ch1010832@2198: ch1010832@2198: agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + ch1010832@2198: e1000_igp_2_cable_length_table[max_agc_index]); ch1010832@2198: agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); ch1010832@2198: ch1010832@2198: /* Calculate cable length with the error range of +/- 10 meters. */ ch1010832@2198: *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? ch1010832@2198: (agc_value - IGP02E1000_AGC_RANGE) : 0; ch1010832@2198: *max_length = agc_value + IGP02E1000_AGC_RANGE; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Check the cable polarity ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * polarity - output parameter : 0 - Polarity is not reversed ch1010832@2198: * 1 - Polarity is reversed. ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_XXX ch1010832@2198: * E1000_SUCCESS ch1010832@2198: * ch1010832@2198: * For phy's older than IGP, this function simply reads the polarity bit in the ch1010832@2198: * Phy Status register. For IGP phy's, this bit is valid only if link speed is ch1010832@2198: * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will ch1010832@2198: * return 0. If the link speed is 1000 Mbps the polarity status is in the ch1010832@2198: * IGP01E1000_PHY_PCS_INIT_REG. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_check_polarity(struct e1000_hw *hw, ch1010832@2198: e1000_rev_polarity *polarity) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_check_polarity"); ch1010832@2198: ch1010832@2198: if ((hw->phy_type == e1000_phy_m88) || ch1010832@2198: (hw->phy_type == e1000_phy_gg82563)) { ch1010832@2198: /* return the Polarity bit in the Status register. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> ch1010832@2198: M88E1000_PSSR_REV_POLARITY_SHIFT) ? ch1010832@2198: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; ch1010832@2198: ch1010832@2198: } else if (hw->phy_type == e1000_phy_igp || ch1010832@2198: hw->phy_type == e1000_phy_igp_3 || ch1010832@2198: hw->phy_type == e1000_phy_igp_2) { ch1010832@2198: /* Read the Status register to check the speed */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to ch1010832@2198: * find the polarity status */ ch1010832@2198: if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == ch1010832@2198: IGP01E1000_PSSR_SPEED_1000MBPS) { ch1010832@2198: ch1010832@2198: /* Read the GIG initialization PCS register (0x00B4) */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Check the polarity bits */ ch1010832@2198: *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? ch1010832@2198: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; ch1010832@2198: } else { ch1010832@2198: /* For 10 Mbps, read the polarity bit in the status register. (for ch1010832@2198: * 100 Mbps this bit is always 0) */ ch1010832@2198: *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? ch1010832@2198: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; ch1010832@2198: } ch1010832@2198: } else if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> ch1010832@2198: IFE_PESC_POLARITY_REVERSED_SHIFT) ? ch1010832@2198: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Check if Downshift occured ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * downshift - output parameter : 0 - No Downshift ocured. ch1010832@2198: * 1 - Downshift ocured. ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_XXX ch1010832@2198: * E1000_SUCCESS ch1010832@2198: * ch1010832@2198: * For phy's older than IGP, this function reads the Downshift bit in the Phy ch1010832@2198: * Specific Status register. For IGP phy's, it reads the Downgrade bit in the ch1010832@2198: * Link Health register. In IGP this bit is latched high, so the driver must ch1010832@2198: * read it immediately after link is established. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_check_downshift(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_check_downshift"); ch1010832@2198: ch1010832@2198: if (hw->phy_type == e1000_phy_igp || ch1010832@2198: hw->phy_type == e1000_phy_igp_3 || ch1010832@2198: hw->phy_type == e1000_phy_igp_2) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; ch1010832@2198: } else if ((hw->phy_type == e1000_phy_m88) || ch1010832@2198: (hw->phy_type == e1000_phy_gg82563)) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> ch1010832@2198: M88E1000_PSSR_DOWNSHIFT_SHIFT; ch1010832@2198: } else if (hw->phy_type == e1000_phy_ife) { ch1010832@2198: /* e1000_phy_ife supports 10/100 speed only */ ch1010832@2198: hw->speed_downgraded = false; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * ch1010832@2198: * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a ch1010832@2198: * gigabit link is achieved to improve link quality. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_PHY if fail to read/write the PHY ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ****************************************************************************/ ch1010832@2198: ch1010832@2198: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data, phy_saved_data, speed, duplex, i; ch1010832@2198: u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = ch1010832@2198: {IGP01E1000_PHY_AGC_PARAM_A, ch1010832@2198: IGP01E1000_PHY_AGC_PARAM_B, ch1010832@2198: IGP01E1000_PHY_AGC_PARAM_C, ch1010832@2198: IGP01E1000_PHY_AGC_PARAM_D}; ch1010832@2198: u16 min_length, max_length; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_config_dsp_after_link_change"); ch1010832@2198: ch1010832@2198: if (hw->phy_type != e1000_phy_igp) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: if (link_up) { ch1010832@2198: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); ch1010832@2198: if (ret_val) { ch1010832@2198: DEBUGOUT("Error getting link speed and duplex\n"); ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (speed == SPEED_1000) { ch1010832@2198: ch1010832@2198: ret_val = e1000_get_cable_length(hw, &min_length, &max_length); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if ((hw->dsp_config_state == e1000_dsp_config_enabled) && ch1010832@2198: min_length >= e1000_igp_cable_length_50) { ch1010832@2198: ch1010832@2198: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: hw->dsp_config_state = e1000_dsp_config_activated; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if ((hw->ffe_config_state == e1000_ffe_config_enabled) && ch1010832@2198: (min_length < e1000_igp_cable_length_50)) { ch1010832@2198: ch1010832@2198: u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; ch1010832@2198: u32 idle_errs = 0; ch1010832@2198: ch1010832@2198: /* clear previous idle error counts */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: for (i = 0; i < ffe_idle_err_timeout; i++) { ch1010832@2198: udelay(1000); ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); ch1010832@2198: if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { ch1010832@2198: hw->ffe_config_state = e1000_ffe_config_active; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, ch1010832@2198: IGP01E1000_PHY_DSP_FFE, ch1010832@2198: IGP01E1000_PHY_DSP_FFE_CM_CP); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (idle_errs) ch1010832@2198: ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: if (hw->dsp_config_state == e1000_dsp_config_activated) { ch1010832@2198: /* Save off the current value of register 0x2F5B to be restored at ch1010832@2198: * the end of the routines. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Disable the PHY transmitter */ ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: mdelay(20); ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@2198: IGP01E1000_IEEE_FORCE_GIGA); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; ch1010832@2198: phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@2198: IGP01E1000_IEEE_RESTART_AUTONEG); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: mdelay(20); ch1010832@2198: ch1010832@2198: /* Now enable the transmitter */ ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->dsp_config_state = e1000_dsp_config_enabled; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->ffe_config_state == e1000_ffe_config_active) { ch1010832@2198: /* Save off the current value of register 0x2F5B to be restored at ch1010832@2198: * the end of the routines. */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Disable the PHY transmitter */ ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: mdelay(20); ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@2198: IGP01E1000_IEEE_FORCE_GIGA); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, ch1010832@2198: IGP01E1000_PHY_DSP_FFE_DEFAULT); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@2198: IGP01E1000_IEEE_RESTART_AUTONEG); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: mdelay(20); ch1010832@2198: ch1010832@2198: /* Now enable the transmitter */ ch1010832@2198: ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); ch1010832@2198: ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->ffe_config_state = e1000_ffe_config_enabled; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * Set PHY to class A mode ch1010832@2198: * Assumes the following operations will follow to enable the new class mode. ch1010832@2198: * 1. Do a PHY soft reset ch1010832@2198: * 2. Restart auto-negotiation or force link. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_set_phy_mode(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 eeprom_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_set_phy_mode"); ch1010832@2198: ch1010832@2198: if ((hw->mac_type == e1000_82545_rev_3) && ch1010832@2198: (hw->media_type == e1000_media_type_copper)) { ch1010832@2198: ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); ch1010832@2198: if (ret_val) { ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if ((eeprom_data != EEPROM_RESERVED_WORD) && ch1010832@2198: (eeprom_data & EEPROM_PHY_CLASS_A)) { ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: hw->phy_reset_disable = false; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * ch1010832@2198: * This function sets the lplu state according to the active flag. When ch1010832@2198: * activating lplu this function also disables smart speed and vise versa. ch1010832@2198: * lplu will not be activated unless the device autonegotiation advertisment ch1010832@2198: * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * active - true to enable lplu false to disable lplu. ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_PHY if fail to read/write the PHY ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ****************************************************************************/ ch1010832@2198: ch1010832@2198: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) ch1010832@2198: { ch1010832@2198: u32 phy_ctrl = 0; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: DEBUGFUNC("e1000_set_d3_lplu_state"); ch1010832@2198: ch1010832@2198: if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 ch1010832@2198: && hw->phy_type != e1000_phy_igp_3) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* During driver activity LPLU should not be used or it will attain link ch1010832@2198: * from the lowest speeds starting from 10Mbps. The capability is used for ch1010832@2198: * Dx transitions and states */ ch1010832@2198: if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: /* MAC writes into PHY register based on the state transition ch1010832@2198: * and start auto-negotiation. SW driver can overwrite the settings ch1010832@2198: * in CSR PHY power control E1000_PHY_CTRL register. */ ch1010832@2198: phy_ctrl = er32(PHY_CTRL); ch1010832@2198: } else { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!active) { ch1010832@2198: if (hw->mac_type == e1000_82541_rev_2 || ch1010832@2198: hw->mac_type == e1000_82547_rev_2) { ch1010832@2198: phy_data &= ~IGP01E1000_GMII_FLEX_SPD; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else { ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; ch1010832@2198: ew32(PHY_CTRL, phy_ctrl); ch1010832@2198: } else { ch1010832@2198: phy_data &= ~IGP02E1000_PM_D3_LPLU; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during ch1010832@2198: * Dx states where the power conservation is most important. During ch1010832@2198: * driver activity we should enable SmartSpeed, so performance is ch1010832@2198: * maintained. */ ch1010832@2198: if (hw->smart_speed == e1000_smart_speed_on) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else if (hw->smart_speed == e1000_smart_speed_off) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || ch1010832@2198: (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || ch1010832@2198: (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_82541_rev_2 || ch1010832@2198: hw->mac_type == e1000_82547_rev_2) { ch1010832@2198: phy_data |= IGP01E1000_GMII_FLEX_SPD; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else { ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; ch1010832@2198: ew32(PHY_CTRL, phy_ctrl); ch1010832@2198: } else { ch1010832@2198: phy_data |= IGP02E1000_PM_D3_LPLU; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* When LPLU is enabled we should disable SmartSpeed */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * ch1010832@2198: * This function sets the lplu d0 state according to the active flag. When ch1010832@2198: * activating lplu this function also disables smart speed and vise versa. ch1010832@2198: * lplu will not be activated unless the device autonegotiation advertisment ch1010832@2198: * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * active - true to enable lplu false to disable lplu. ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_PHY if fail to read/write the PHY ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ****************************************************************************/ ch1010832@2198: ch1010832@2198: static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) ch1010832@2198: { ch1010832@2198: u32 phy_ctrl = 0; ch1010832@2198: s32 ret_val; ch1010832@2198: u16 phy_data; ch1010832@2198: DEBUGFUNC("e1000_set_d0_lplu_state"); ch1010832@2198: ch1010832@2198: if (hw->mac_type <= e1000_82547_rev_2) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: phy_ctrl = er32(PHY_CTRL); ch1010832@2198: } else { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!active) { ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; ch1010832@2198: ew32(PHY_CTRL, phy_ctrl); ch1010832@2198: } else { ch1010832@2198: phy_data &= ~IGP02E1000_PM_D0_LPLU; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during ch1010832@2198: * Dx states where the power conservation is most important. During ch1010832@2198: * driver activity we should enable SmartSpeed, so performance is ch1010832@2198: * maintained. */ ch1010832@2198: if (hw->smart_speed == e1000_smart_speed_on) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } else if (hw->smart_speed == e1000_smart_speed_off) { ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@2198: phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: } else { ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; ch1010832@2198: ew32(PHY_CTRL, phy_ctrl); ch1010832@2198: } else { ch1010832@2198: phy_data |= IGP02E1000_PM_D0_LPLU; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* When LPLU is enabled we should disable SmartSpeed */ ch1010832@2198: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Change VCO speed register to improve Bit Error Rate performance of SERDES. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_set_vco_speed(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 default_page = 0; ch1010832@2198: u16 phy_data; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_set_vco_speed"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82545_rev_3: ch1010832@2198: case e1000_82546_rev_3: ch1010832@2198: break; ch1010832@2198: default: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Set PHY register 30, page 5, bit 8 to 0 */ ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* Set PHY register 30, page 4, bit 11 to 1 */ ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: phy_data |= M88E1000_PHY_VCO_REG_BIT11; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function reads the cookie from ARC ram. ch1010832@2198: * ch1010832@2198: * returns: - E1000_SUCCESS . ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer) ch1010832@2198: { ch1010832@2198: u8 i; ch1010832@2198: u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET; ch1010832@2198: u8 length = E1000_MNG_DHCP_COOKIE_LENGTH; ch1010832@2198: ch1010832@2198: length = (length >> 2); ch1010832@2198: offset = (offset >> 2); ch1010832@2198: ch1010832@2198: for (i = 0; i < length; i++) { ch1010832@2198: *((u32 *)buffer + i) = ch1010832@2198: E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function checks whether the HOST IF is enabled for command operaton ch1010832@2198: * and also checks whether the previous command is completed. ch1010832@2198: * It busy waits in case of previous command is not completed. ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or ch1010832@2198: * timeout ch1010832@2198: * - E1000_SUCCESS for success. ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 hicr; ch1010832@2198: u8 i; ch1010832@2198: ch1010832@2198: /* Check that the host interface is enabled. */ ch1010832@2198: hicr = er32(HICR); ch1010832@2198: if ((hicr & E1000_HICR_EN) == 0) { ch1010832@2198: DEBUGOUT("E1000_HOST_EN bit disabled.\n"); ch1010832@2198: return -E1000_ERR_HOST_INTERFACE_COMMAND; ch1010832@2198: } ch1010832@2198: /* check the previous command is completed */ ch1010832@2198: for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { ch1010832@2198: hicr = er32(HICR); ch1010832@2198: if (!(hicr & E1000_HICR_C)) ch1010832@2198: break; ch1010832@2198: mdelay(1); ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { ch1010832@2198: DEBUGOUT("Previous command timeout failed .\n"); ch1010832@2198: return -E1000_ERR_HOST_INTERFACE_COMMAND; ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function writes the buffer content at the offset given on the host if. ch1010832@2198: * It also does alignment considerations to do the writes in most efficient way. ch1010832@2198: * Also fills up the sum of the buffer in *buffer parameter. ch1010832@2198: * ch1010832@2198: * returns - E1000_SUCCESS for success. ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, ch1010832@2198: u16 offset, u8 *sum) ch1010832@2198: { ch1010832@2198: u8 *tmp; ch1010832@2198: u8 *bufptr = buffer; ch1010832@2198: u32 data = 0; ch1010832@2198: u16 remaining, i, j, prev_bytes; ch1010832@2198: ch1010832@2198: /* sum = only sum of the data and it is not checksum */ ch1010832@2198: ch1010832@2198: if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { ch1010832@2198: return -E1000_ERR_PARAM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: tmp = (u8 *)&data; ch1010832@2198: prev_bytes = offset & 0x3; ch1010832@2198: offset &= 0xFFFC; ch1010832@2198: offset >>= 2; ch1010832@2198: ch1010832@2198: if (prev_bytes) { ch1010832@2198: data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); ch1010832@2198: for (j = prev_bytes; j < sizeof(u32); j++) { ch1010832@2198: *(tmp + j) = *bufptr++; ch1010832@2198: *sum += *(tmp + j); ch1010832@2198: } ch1010832@2198: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); ch1010832@2198: length -= j - prev_bytes; ch1010832@2198: offset++; ch1010832@2198: } ch1010832@2198: ch1010832@2198: remaining = length & 0x3; ch1010832@2198: length -= remaining; ch1010832@2198: ch1010832@2198: /* Calculate length in DWORDs */ ch1010832@2198: length >>= 2; ch1010832@2198: ch1010832@2198: /* The device driver writes the relevant command block into the ch1010832@2198: * ram area. */ ch1010832@2198: for (i = 0; i < length; i++) { ch1010832@2198: for (j = 0; j < sizeof(u32); j++) { ch1010832@2198: *(tmp + j) = *bufptr++; ch1010832@2198: *sum += *(tmp + j); ch1010832@2198: } ch1010832@2198: ch1010832@2198: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); ch1010832@2198: } ch1010832@2198: if (remaining) { ch1010832@2198: for (j = 0; j < sizeof(u32); j++) { ch1010832@2198: if (j < remaining) ch1010832@2198: *(tmp + j) = *bufptr++; ch1010832@2198: else ch1010832@2198: *(tmp + j) = 0; ch1010832@2198: ch1010832@2198: *sum += *(tmp + j); ch1010832@2198: } ch1010832@2198: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function writes the command header after does the checksum calculation. ch1010832@2198: * ch1010832@2198: * returns - E1000_SUCCESS for success. ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, ch1010832@2198: struct e1000_host_mng_command_header *hdr) ch1010832@2198: { ch1010832@2198: u16 i; ch1010832@2198: u8 sum; ch1010832@2198: u8 *buffer; ch1010832@2198: ch1010832@2198: /* Write the whole command header structure which includes sum of ch1010832@2198: * the buffer */ ch1010832@2198: ch1010832@2198: u16 length = sizeof(struct e1000_host_mng_command_header); ch1010832@2198: ch1010832@2198: sum = hdr->checksum; ch1010832@2198: hdr->checksum = 0; ch1010832@2198: ch1010832@2198: buffer = (u8 *)hdr; ch1010832@2198: i = length; ch1010832@2198: while (i--) ch1010832@2198: sum += buffer[i]; ch1010832@2198: ch1010832@2198: hdr->checksum = 0 - sum; ch1010832@2198: ch1010832@2198: length >>= 2; ch1010832@2198: /* The device driver writes the relevant command block into the ram area. */ ch1010832@2198: for (i = 0; i < length; i++) { ch1010832@2198: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i)); ch1010832@2198: E1000_WRITE_FLUSH(); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function indicates to ARC that a new command is pending which completes ch1010832@2198: * one write operation by the driver. ch1010832@2198: * ch1010832@2198: * returns - E1000_SUCCESS for success. ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_mng_write_commit(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 hicr; ch1010832@2198: ch1010832@2198: hicr = er32(HICR); ch1010832@2198: /* Setting this bit tells the ARC that a new command is pending. */ ch1010832@2198: ew32(HICR, hicr | E1000_HICR_C); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function checks the mode of the firmware. ch1010832@2198: * ch1010832@2198: * returns - true when the mode is IAMT or false. ch1010832@2198: ****************************************************************************/ ch1010832@2198: bool e1000_check_mng_mode(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 fwsm; ch1010832@2198: ch1010832@2198: fwsm = er32(FWSM); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: if ((fwsm & E1000_FWSM_MODE_MASK) == ch1010832@2198: (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) ch1010832@2198: return true; ch1010832@2198: } else if ((fwsm & E1000_FWSM_MODE_MASK) == ch1010832@2198: (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) ch1010832@2198: return true; ch1010832@2198: ch1010832@2198: return false; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function writes the dhcp info . ch1010832@2198: ****************************************************************************/ ch1010832@2198: s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: struct e1000_host_mng_command_header hdr; ch1010832@2198: ch1010832@2198: hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; ch1010832@2198: hdr.command_length = length; ch1010832@2198: hdr.reserved1 = 0; ch1010832@2198: hdr.reserved2 = 0; ch1010832@2198: hdr.checksum = 0; ch1010832@2198: ch1010832@2198: ret_val = e1000_mng_enable_host_if(hw); ch1010832@2198: if (ret_val == E1000_SUCCESS) { ch1010832@2198: ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), ch1010832@2198: &(hdr.checksum)); ch1010832@2198: if (ret_val == E1000_SUCCESS) { ch1010832@2198: ret_val = e1000_mng_write_cmd_header(hw, &hdr); ch1010832@2198: if (ret_val == E1000_SUCCESS) ch1010832@2198: ret_val = e1000_mng_write_commit(hw); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function calculates the checksum. ch1010832@2198: * ch1010832@2198: * returns - checksum of buffer contents. ch1010832@2198: ****************************************************************************/ ch1010832@2198: static u8 e1000_calculate_mng_checksum(char *buffer, u32 length) ch1010832@2198: { ch1010832@2198: u8 sum = 0; ch1010832@2198: u32 i; ch1010832@2198: ch1010832@2198: if (!buffer) ch1010832@2198: return 0; ch1010832@2198: ch1010832@2198: for (i=0; i < length; i++) ch1010832@2198: sum += buffer[i]; ch1010832@2198: ch1010832@2198: return (u8)(0 - sum); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /***************************************************************************** ch1010832@2198: * This function checks whether tx pkt filtering needs to be enabled or not. ch1010832@2198: * ch1010832@2198: * returns - true for packet filtering or false. ch1010832@2198: ****************************************************************************/ ch1010832@2198: bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: /* called in init as well as watchdog timer functions */ ch1010832@2198: ch1010832@2198: s32 ret_val, checksum; ch1010832@2198: bool tx_filter = false; ch1010832@2198: struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); ch1010832@2198: u8 *buffer = (u8 *) &(hw->mng_cookie); ch1010832@2198: ch1010832@2198: if (e1000_check_mng_mode(hw)) { ch1010832@2198: ret_val = e1000_mng_enable_host_if(hw); ch1010832@2198: if (ret_val == E1000_SUCCESS) { ch1010832@2198: ret_val = e1000_host_if_read_cookie(hw, buffer); ch1010832@2198: if (ret_val == E1000_SUCCESS) { ch1010832@2198: checksum = hdr->checksum; ch1010832@2198: hdr->checksum = 0; ch1010832@2198: if ((hdr->signature == E1000_IAMT_SIGNATURE) && ch1010832@2198: checksum == e1000_calculate_mng_checksum((char *)buffer, ch1010832@2198: E1000_MNG_DHCP_COOKIE_LENGTH)) { ch1010832@2198: if (hdr->status & ch1010832@2198: E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) ch1010832@2198: tx_filter = true; ch1010832@2198: } else ch1010832@2198: tx_filter = true; ch1010832@2198: } else ch1010832@2198: tx_filter = true; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: hw->tx_pkt_filtering = tx_filter; ch1010832@2198: return tx_filter; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Verifies the hardware needs to allow ARPs to be processed by the host ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - true/false ch1010832@2198: * ch1010832@2198: *****************************************************************************/ ch1010832@2198: u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 manc; ch1010832@2198: u32 fwsm, factps; ch1010832@2198: ch1010832@2198: if (hw->asf_firmware_present) { ch1010832@2198: manc = er32(MANC); ch1010832@2198: ch1010832@2198: if (!(manc & E1000_MANC_RCV_TCO_EN) || ch1010832@2198: !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) ch1010832@2198: return false; ch1010832@2198: if (e1000_arc_subsystem_valid(hw)) { ch1010832@2198: fwsm = er32(FWSM); ch1010832@2198: factps = er32(FACTPS); ch1010832@2198: ch1010832@2198: if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == ch1010832@2198: e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) ch1010832@2198: return true; ch1010832@2198: } else ch1010832@2198: if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) ch1010832@2198: return true; ch1010832@2198: } ch1010832@2198: return false; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 ret_val; ch1010832@2198: u16 mii_status_reg; ch1010832@2198: u16 i; ch1010832@2198: ch1010832@2198: /* Polarity reversal workaround for forced 10F/10H links. */ ch1010832@2198: ch1010832@2198: /* Disable the transmitter on the PHY */ ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* This loop will early-out if the NO link condition has been met. */ ch1010832@2198: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@2198: /* Read the MII Status Register and wait for Link Status bit ch1010832@2198: * to be clear. ch1010832@2198: */ ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; ch1010832@2198: mdelay(100); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Recommended delay time after link has been lost */ ch1010832@2198: mdelay(1000); ch1010832@2198: ch1010832@2198: /* Now we will re-enable th transmitter on the PHY */ ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: mdelay(50); ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: mdelay(50); ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: mdelay(50); ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: /* This loop will early-out if the link condition has been met. */ ch1010832@2198: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@2198: /* Read the MII Status Register and wait for Link Status bit ch1010832@2198: * to be set. ch1010832@2198: */ ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: if (mii_status_reg & MII_SR_LINK_STATUS) break; ch1010832@2198: mdelay(100); ch1010832@2198: } ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * ch1010832@2198: * Disables PCI-Express master access. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - none. ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static void e1000_set_pci_express_master_disable(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 ctrl; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_set_pci_express_master_disable"); ch1010832@2198: ch1010832@2198: if (hw->bus_type != e1000_bus_type_pci_express) ch1010832@2198: return; ch1010832@2198: ch1010832@2198: ctrl = er32(CTRL); ch1010832@2198: ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; ch1010832@2198: ew32(CTRL, ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /******************************************************************************* ch1010832@2198: * ch1010832@2198: * Disables PCI-Express master access and verifies there are no pending requests ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't ch1010832@2198: * caused the master requests to be disabled. ch1010832@2198: * E1000_SUCCESS master requests disabled. ch1010832@2198: * ch1010832@2198: ******************************************************************************/ ch1010832@2198: s32 e1000_disable_pciex_master(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_disable_pciex_master"); ch1010832@2198: ch1010832@2198: if (hw->bus_type != e1000_bus_type_pci_express) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: e1000_set_pci_express_master_disable(hw); ch1010832@2198: ch1010832@2198: while (timeout) { ch1010832@2198: if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) ch1010832@2198: break; ch1010832@2198: else ch1010832@2198: udelay(100); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!timeout) { ch1010832@2198: DEBUGOUT("Master requests are pending.\n"); ch1010832@2198: return -E1000_ERR_MASTER_REQUESTS_PENDING; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /******************************************************************************* ch1010832@2198: * ch1010832@2198: * Check for EEPROM Auto Read bit done. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_RESET if fail to reset MAC ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ******************************************************************************/ ch1010832@2198: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 timeout = AUTO_READ_DONE_TIMEOUT; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_auto_rd_done"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: default: ch1010832@2198: msleep(5); ch1010832@2198: break; ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: case e1000_82573: ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: case e1000_ich8lan: ch1010832@2198: while (timeout) { ch1010832@2198: if (er32(EECD) & E1000_EECD_AUTO_RD) ch1010832@2198: break; ch1010832@2198: else msleep(1); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!timeout) { ch1010832@2198: DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); ch1010832@2198: return -E1000_ERR_RESET; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. ch1010832@2198: * Need to wait for PHY configuration completion before accessing NVM ch1010832@2198: * and PHY. */ ch1010832@2198: if (hw->mac_type == e1000_82573) ch1010832@2198: msleep(25); ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * Checks if the PHY configuration is done ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_RESET if fail to reset MAC ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 timeout = PHY_CFG_TIMEOUT; ch1010832@2198: u32 cfg_mask = E1000_EEPROM_CFG_DONE; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_phy_cfg_done"); ch1010832@2198: ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: default: ch1010832@2198: mdelay(10); ch1010832@2198: break; ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: /* Separate *_CFG_DONE_* bit for each port */ ch1010832@2198: if (er32(STATUS) & E1000_STATUS_FUNC_1) ch1010832@2198: cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; ch1010832@2198: /* Fall Through */ ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: while (timeout) { ch1010832@2198: if (er32(EEMNGCTL) & cfg_mask) ch1010832@2198: break; ch1010832@2198: else ch1010832@2198: msleep(1); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: if (!timeout) { ch1010832@2198: DEBUGOUT("MNG configuration cycle has not completed.\n"); ch1010832@2198: return -E1000_ERR_RESET; ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * ch1010832@2198: * Using the combination of SMBI and SWESMBI semaphore bits when resetting ch1010832@2198: * adapter or Eeprom access. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_EEPROM if fail to access EEPROM. ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 timeout; ch1010832@2198: u32 swsm; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); ch1010832@2198: ch1010832@2198: if (!hw->eeprom_semaphore_present) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_80003es2lan) { ch1010832@2198: /* Get the SW semaphore. */ ch1010832@2198: if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Get the FW semaphore. */ ch1010832@2198: timeout = hw->eeprom.word_size + 1; ch1010832@2198: while (timeout) { ch1010832@2198: swsm = er32(SWSM); ch1010832@2198: swsm |= E1000_SWSM_SWESMBI; ch1010832@2198: ew32(SWSM, swsm); ch1010832@2198: /* if we managed to set the bit we got the semaphore. */ ch1010832@2198: swsm = er32(SWSM); ch1010832@2198: if (swsm & E1000_SWSM_SWESMBI) ch1010832@2198: break; ch1010832@2198: ch1010832@2198: udelay(50); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!timeout) { ch1010832@2198: /* Release semaphores */ ch1010832@2198: e1000_put_hw_eeprom_semaphore(hw); ch1010832@2198: DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); ch1010832@2198: return -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * This function clears HW semaphore bits. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - None. ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 swsm; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); ch1010832@2198: ch1010832@2198: if (!hw->eeprom_semaphore_present) ch1010832@2198: return; ch1010832@2198: ch1010832@2198: swsm = er32(SWSM); ch1010832@2198: if (hw->mac_type == e1000_80003es2lan) { ch1010832@2198: /* Release both semaphores. */ ch1010832@2198: swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); ch1010832@2198: } else ch1010832@2198: swsm &= ~(E1000_SWSM_SWESMBI); ch1010832@2198: ew32(SWSM, swsm); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * ch1010832@2198: * Obtaining software semaphore bit (SMBI) before resetting PHY. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_ERR_RESET if fail to obtain semaphore. ch1010832@2198: * E1000_SUCCESS at any other case. ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static s32 e1000_get_software_semaphore(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 timeout = hw->eeprom.word_size + 1; ch1010832@2198: u32 swsm; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_software_semaphore"); ch1010832@2198: ch1010832@2198: if (hw->mac_type != e1000_80003es2lan) { ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: while (timeout) { ch1010832@2198: swsm = er32(SWSM); ch1010832@2198: /* If SMBI bit cleared, it is now set and we hold the semaphore */ ch1010832@2198: if (!(swsm & E1000_SWSM_SMBI)) ch1010832@2198: break; ch1010832@2198: mdelay(1); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!timeout) { ch1010832@2198: DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); ch1010832@2198: return -E1000_ERR_RESET; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * ch1010832@2198: * Release semaphore bit (SMBI). ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static void e1000_release_software_semaphore(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 swsm; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_release_software_semaphore"); ch1010832@2198: ch1010832@2198: if (hw->mac_type != e1000_80003es2lan) { ch1010832@2198: return; ch1010832@2198: } ch1010832@2198: ch1010832@2198: swsm = er32(SWSM); ch1010832@2198: /* Release the SW semaphores.*/ ch1010832@2198: swsm &= ~E1000_SWSM_SMBI; ch1010832@2198: ew32(SWSM, swsm); ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Checks if PHY reset is blocked due to SOL/IDER session, for example. ch1010832@2198: * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to ch1010832@2198: * the caller to figure out how to deal with it. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: * returns: - E1000_BLK_PHY_RESET ch1010832@2198: * E1000_SUCCESS ch1010832@2198: * ch1010832@2198: *****************************************************************************/ ch1010832@2198: s32 e1000_check_phy_reset_block(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 manc = 0; ch1010832@2198: u32 fwsm = 0; ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: fwsm = er32(FWSM); ch1010832@2198: return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS ch1010832@2198: : E1000_BLK_PHY_RESET; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (hw->mac_type > e1000_82547_rev_2) ch1010832@2198: manc = er32(MANC); ch1010832@2198: return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? ch1010832@2198: E1000_BLK_PHY_RESET : E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 fwsm; ch1010832@2198: ch1010832@2198: /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC ch1010832@2198: * may not be provided a DMA clock when no manageability features are ch1010832@2198: * enabled. We do not want to perform any reads/writes to these registers ch1010832@2198: * if this is the case. We read FWSM to determine the manageability mode. ch1010832@2198: */ ch1010832@2198: switch (hw->mac_type) { ch1010832@2198: case e1000_82571: ch1010832@2198: case e1000_82572: ch1010832@2198: case e1000_82573: ch1010832@2198: case e1000_80003es2lan: ch1010832@2198: fwsm = er32(FWSM); ch1010832@2198: if ((fwsm & E1000_FWSM_MODE_MASK) != 0) ch1010832@2198: return true; ch1010832@2198: break; ch1010832@2198: case e1000_ich8lan: ch1010832@2198: return true; ch1010832@2198: default: ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: return false; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Configure PCI-Ex no-snoop ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code. ch1010832@2198: * no_snoop - Bitmap of no-snoop events. ch1010832@2198: * ch1010832@2198: * returns: E1000_SUCCESS ch1010832@2198: * ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop) ch1010832@2198: { ch1010832@2198: u32 gcr_reg = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_set_pci_ex_no_snoop"); ch1010832@2198: ch1010832@2198: if (hw->bus_type == e1000_bus_type_unknown) ch1010832@2198: e1000_get_bus_info(hw); ch1010832@2198: ch1010832@2198: if (hw->bus_type != e1000_bus_type_pci_express) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: if (no_snoop) { ch1010832@2198: gcr_reg = er32(GCR); ch1010832@2198: gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); ch1010832@2198: gcr_reg |= no_snoop; ch1010832@2198: ew32(GCR, gcr_reg); ch1010832@2198: } ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: u32 ctrl_ext; ch1010832@2198: ch1010832@2198: ew32(GCR, PCI_EX_82566_SNOOP_ALL); ch1010832@2198: ch1010832@2198: ctrl_ext = er32(CTRL_EXT); ch1010832@2198: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; ch1010832@2198: ew32(CTRL_EXT, ctrl_ext); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * ch1010832@2198: * Get software semaphore FLAG bit (SWFLAG). ch1010832@2198: * SWFLAG is used to synchronize the access to all shared resource between ch1010832@2198: * SW, FW and HW. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static s32 e1000_get_software_flag(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: s32 timeout = PHY_CFG_TIMEOUT; ch1010832@2198: u32 extcnf_ctrl; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_get_software_flag"); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: while (timeout) { ch1010832@2198: extcnf_ctrl = er32(EXTCNF_CTRL); ch1010832@2198: extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; ch1010832@2198: ew32(EXTCNF_CTRL, extcnf_ctrl); ch1010832@2198: ch1010832@2198: extcnf_ctrl = er32(EXTCNF_CTRL); ch1010832@2198: if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) ch1010832@2198: break; ch1010832@2198: mdelay(1); ch1010832@2198: timeout--; ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (!timeout) { ch1010832@2198: DEBUGOUT("FW or HW locks the resource too long.\n"); ch1010832@2198: return -E1000_ERR_CONFIG; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /*************************************************************************** ch1010832@2198: * ch1010832@2198: * Release software semaphore FLAG bit (SWFLAG). ch1010832@2198: * SWFLAG is used to synchronize the access to all shared resource between ch1010832@2198: * SW, FW and HW. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: * ch1010832@2198: ***************************************************************************/ ch1010832@2198: static void e1000_release_software_flag(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 extcnf_ctrl; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_release_software_flag"); ch1010832@2198: ch1010832@2198: if (hw->mac_type == e1000_ich8lan) { ch1010832@2198: extcnf_ctrl= er32(EXTCNF_CTRL); ch1010832@2198: extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; ch1010832@2198: ew32(EXTCNF_CTRL, extcnf_ctrl); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access ch1010832@2198: * register. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset of word in the EEPROM to read ch1010832@2198: * data - word read from the EEPROM ch1010832@2198: * words - number of words to read ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data) ch1010832@2198: { ch1010832@2198: s32 error = E1000_SUCCESS; ch1010832@2198: u32 flash_bank = 0; ch1010832@2198: u32 act_offset = 0; ch1010832@2198: u32 bank_offset = 0; ch1010832@2198: u16 word = 0; ch1010832@2198: u16 i = 0; ch1010832@2198: ch1010832@2198: /* We need to know which is the valid flash bank. In the event ch1010832@2198: * that we didn't allocate eeprom_shadow_ram, we may not be ch1010832@2198: * managing flash_bank. So it cannot be trusted and needs ch1010832@2198: * to be updated with each read. ch1010832@2198: */ ch1010832@2198: /* Value of bit 22 corresponds to the flash bank we're on. */ ch1010832@2198: flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; ch1010832@2198: ch1010832@2198: /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ ch1010832@2198: bank_offset = flash_bank * (hw->flash_bank_size * 2); ch1010832@2198: ch1010832@2198: error = e1000_get_software_flag(hw); ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: return error; ch1010832@2198: ch1010832@2198: for (i = 0; i < words; i++) { ch1010832@2198: if (hw->eeprom_shadow_ram != NULL && ch1010832@2198: hw->eeprom_shadow_ram[offset+i].modified) { ch1010832@2198: data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; ch1010832@2198: } else { ch1010832@2198: /* The NVM part needs a byte offset, hence * 2 */ ch1010832@2198: act_offset = bank_offset + ((offset + i) * 2); ch1010832@2198: error = e1000_read_ich8_word(hw, act_offset, &word); ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: break; ch1010832@2198: data[i] = word; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_release_software_flag(hw); ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access ch1010832@2198: * register. Actually, writes are written to the shadow ram cache in the hw ch1010832@2198: * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to ch1010832@2198: * the NVM, which occurs when the NVM checksum is updated. ch1010832@2198: * ch1010832@2198: * hw - Struct containing variables accessed by shared code ch1010832@2198: * offset - offset of word in the EEPROM to write ch1010832@2198: * words - number of words to write ch1010832@2198: * data - words to write to the EEPROM ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@2198: u16 *data) ch1010832@2198: { ch1010832@2198: u32 i = 0; ch1010832@2198: s32 error = E1000_SUCCESS; ch1010832@2198: ch1010832@2198: error = e1000_get_software_flag(hw); ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: return error; ch1010832@2198: ch1010832@2198: /* A driver can write to the NVM only if it has eeprom_shadow_ram ch1010832@2198: * allocated. Subsequent reads to the modified words are read from ch1010832@2198: * this cached structure as well. Writes will only go into this ch1010832@2198: * cached structure unless it's followed by a call to ch1010832@2198: * e1000_update_eeprom_checksum() where it will commit the changes ch1010832@2198: * and clear the "modified" field. ch1010832@2198: */ ch1010832@2198: if (hw->eeprom_shadow_ram != NULL) { ch1010832@2198: for (i = 0; i < words; i++) { ch1010832@2198: if ((offset + i) < E1000_SHADOW_RAM_WORDS) { ch1010832@2198: hw->eeprom_shadow_ram[offset+i].modified = true; ch1010832@2198: hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; ch1010832@2198: } else { ch1010832@2198: error = -E1000_ERR_EEPROM; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } else { ch1010832@2198: /* Drivers have the option to not allocate eeprom_shadow_ram as long ch1010832@2198: * as they don't perform any NVM writes. An attempt in doing so ch1010832@2198: * will result in this error. ch1010832@2198: */ ch1010832@2198: error = -E1000_ERR_EEPROM; ch1010832@2198: } ch1010832@2198: ch1010832@2198: e1000_release_software_flag(hw); ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * This function does initial flash setup so that a new read/write/erase cycle ch1010832@2198: * can be started. ch1010832@2198: * ch1010832@2198: * hw - The pointer to the hw structure ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_ich8_cycle_init(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: union ich8_hws_flash_status hsfsts; ch1010832@2198: s32 error = E1000_ERR_EEPROM; ch1010832@2198: s32 i = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_ich8_cycle_init"); ch1010832@2198: ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: ch1010832@2198: /* May be check the Flash Des Valid bit in Hw status */ ch1010832@2198: if (hsfsts.hsf_status.fldesvalid == 0) { ch1010832@2198: DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Clear FCERR in Hw status by writing 1 */ ch1010832@2198: /* Clear DAEL in Hw status by writing a 1 */ ch1010832@2198: hsfsts.hsf_status.flcerr = 1; ch1010832@2198: hsfsts.hsf_status.dael = 1; ch1010832@2198: ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); ch1010832@2198: ch1010832@2198: /* Either we should have a hardware SPI cycle in progress bit to check ch1010832@2198: * against, in order to start a new cycle or FDONE bit should be changed ch1010832@2198: * in the hardware so that it is 1 after harware reset, which can then be ch1010832@2198: * used as an indication whether a cycle is in progress or has been ch1010832@2198: * completed .. we should also have some software semaphore mechanism to ch1010832@2198: * guard FDONE or the cycle in progress bit so that two threads access to ch1010832@2198: * those bits can be sequentiallized or a way so that 2 threads dont ch1010832@2198: * start the cycle at the same time */ ch1010832@2198: ch1010832@2198: if (hsfsts.hsf_status.flcinprog == 0) { ch1010832@2198: /* There is no cycle running at present, so we can start a cycle */ ch1010832@2198: /* Begin by setting Flash Cycle Done. */ ch1010832@2198: hsfsts.hsf_status.flcdone = 1; ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); ch1010832@2198: error = E1000_SUCCESS; ch1010832@2198: } else { ch1010832@2198: /* otherwise poll for sometime so the current cycle has a chance ch1010832@2198: * to end before giving up. */ ch1010832@2198: for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: if (hsfsts.hsf_status.flcinprog == 0) { ch1010832@2198: error = E1000_SUCCESS; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: udelay(1); ch1010832@2198: } ch1010832@2198: if (error == E1000_SUCCESS) { ch1010832@2198: /* Successful in waiting for previous cycle to timeout, ch1010832@2198: * now set the Flash Cycle Done. */ ch1010832@2198: hsfsts.hsf_status.flcdone = 1; ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); ch1010832@2198: } else { ch1010832@2198: DEBUGOUT("Flash controller busy, cannot get access"); ch1010832@2198: } ch1010832@2198: } ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * This function starts a flash cycle and waits for its completion ch1010832@2198: * ch1010832@2198: * hw - The pointer to the hw structure ch1010832@2198: ****************************************************************************/ ch1010832@2198: static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout) ch1010832@2198: { ch1010832@2198: union ich8_hws_flash_ctrl hsflctl; ch1010832@2198: union ich8_hws_flash_status hsfsts; ch1010832@2198: s32 error = E1000_ERR_EEPROM; ch1010832@2198: u32 i = 0; ch1010832@2198: ch1010832@2198: /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ ch1010832@2198: hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); ch1010832@2198: hsflctl.hsf_ctrl.flcgo = 1; ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); ch1010832@2198: ch1010832@2198: /* wait till FDONE bit is set to 1 */ ch1010832@2198: do { ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: if (hsfsts.hsf_status.flcdone == 1) ch1010832@2198: break; ch1010832@2198: udelay(1); ch1010832@2198: i++; ch1010832@2198: } while (i < timeout); ch1010832@2198: if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { ch1010832@2198: error = E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a byte or word from the NVM using the ICH8 flash access registers. ch1010832@2198: * ch1010832@2198: * hw - The pointer to the hw structure ch1010832@2198: * index - The index of the byte or word to read. ch1010832@2198: * size - Size of data to read, 1=byte 2=word ch1010832@2198: * data - Pointer to the word to store the value read. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, ch1010832@2198: u16 *data) ch1010832@2198: { ch1010832@2198: union ich8_hws_flash_status hsfsts; ch1010832@2198: union ich8_hws_flash_ctrl hsflctl; ch1010832@2198: u32 flash_linear_address; ch1010832@2198: u32 flash_data = 0; ch1010832@2198: s32 error = -E1000_ERR_EEPROM; ch1010832@2198: s32 count = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_read_ich8_data"); ch1010832@2198: ch1010832@2198: if (size < 1 || size > 2 || data == NULL || ch1010832@2198: index > ICH_FLASH_LINEAR_ADDR_MASK) ch1010832@2198: return error; ch1010832@2198: ch1010832@2198: flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + ch1010832@2198: hw->flash_base_addr; ch1010832@2198: ch1010832@2198: do { ch1010832@2198: udelay(1); ch1010832@2198: /* Steps */ ch1010832@2198: error = e1000_ich8_cycle_init(hw); ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: break; ch1010832@2198: ch1010832@2198: hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); ch1010832@2198: /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ ch1010832@2198: hsflctl.hsf_ctrl.fldbcount = size - 1; ch1010832@2198: hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); ch1010832@2198: ch1010832@2198: /* Write the last 24 bits of index into Flash Linear address field in ch1010832@2198: * Flash Address */ ch1010832@2198: /* TODO: TBD maybe check the index against the size of flash */ ch1010832@2198: ch1010832@2198: E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); ch1010832@2198: ch1010832@2198: error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); ch1010832@2198: ch1010832@2198: /* Check if FCERR is set to 1, if set to 1, clear it and try the whole ch1010832@2198: * sequence a few more times, else read in (shift in) the Flash Data0, ch1010832@2198: * the order is least significant byte first msb to lsb */ ch1010832@2198: if (error == E1000_SUCCESS) { ch1010832@2198: flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); ch1010832@2198: if (size == 1) { ch1010832@2198: *data = (u8)(flash_data & 0x000000FF); ch1010832@2198: } else if (size == 2) { ch1010832@2198: *data = (u16)(flash_data & 0x0000FFFF); ch1010832@2198: } ch1010832@2198: break; ch1010832@2198: } else { ch1010832@2198: /* If we've gotten here, then things are probably completely hosed, ch1010832@2198: * but if the error condition is detected, it won't hurt to give ch1010832@2198: * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. ch1010832@2198: */ ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: if (hsfsts.hsf_status.flcerr == 1) { ch1010832@2198: /* Repeat for some time before giving up. */ ch1010832@2198: continue; ch1010832@2198: } else if (hsfsts.hsf_status.flcdone == 0) { ch1010832@2198: DEBUGOUT("Timeout error - flash cycle did not complete."); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes One /two bytes to the NVM using the ICH8 flash access registers. ch1010832@2198: * ch1010832@2198: * hw - The pointer to the hw structure ch1010832@2198: * index - The index of the byte/word to read. ch1010832@2198: * size - Size of data to read, 1=byte 2=word ch1010832@2198: * data - The byte(s) to write to the NVM. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, ch1010832@2198: u16 data) ch1010832@2198: { ch1010832@2198: union ich8_hws_flash_status hsfsts; ch1010832@2198: union ich8_hws_flash_ctrl hsflctl; ch1010832@2198: u32 flash_linear_address; ch1010832@2198: u32 flash_data = 0; ch1010832@2198: s32 error = -E1000_ERR_EEPROM; ch1010832@2198: s32 count = 0; ch1010832@2198: ch1010832@2198: DEBUGFUNC("e1000_write_ich8_data"); ch1010832@2198: ch1010832@2198: if (size < 1 || size > 2 || data > size * 0xff || ch1010832@2198: index > ICH_FLASH_LINEAR_ADDR_MASK) ch1010832@2198: return error; ch1010832@2198: ch1010832@2198: flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + ch1010832@2198: hw->flash_base_addr; ch1010832@2198: ch1010832@2198: do { ch1010832@2198: udelay(1); ch1010832@2198: /* Steps */ ch1010832@2198: error = e1000_ich8_cycle_init(hw); ch1010832@2198: if (error != E1000_SUCCESS) ch1010832@2198: break; ch1010832@2198: ch1010832@2198: hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); ch1010832@2198: /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ ch1010832@2198: hsflctl.hsf_ctrl.fldbcount = size -1; ch1010832@2198: hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); ch1010832@2198: ch1010832@2198: /* Write the last 24 bits of index into Flash Linear address field in ch1010832@2198: * Flash Address */ ch1010832@2198: E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); ch1010832@2198: ch1010832@2198: if (size == 1) ch1010832@2198: flash_data = (u32)data & 0x00FF; ch1010832@2198: else ch1010832@2198: flash_data = (u32)data; ch1010832@2198: ch1010832@2198: E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); ch1010832@2198: ch1010832@2198: /* check if FCERR is set to 1 , if set to 1, clear it and try the whole ch1010832@2198: * sequence a few more times else done */ ch1010832@2198: error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); ch1010832@2198: if (error == E1000_SUCCESS) { ch1010832@2198: break; ch1010832@2198: } else { ch1010832@2198: /* If we're here, then things are most likely completely hosed, ch1010832@2198: * but if the error condition is detected, it won't hurt to give ch1010832@2198: * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. ch1010832@2198: */ ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: if (hsfsts.hsf_status.flcerr == 1) { ch1010832@2198: /* Repeat for some time before giving up. */ ch1010832@2198: continue; ch1010832@2198: } else if (hsfsts.hsf_status.flcdone == 0) { ch1010832@2198: DEBUGOUT("Timeout error - flash cycle did not complete."); ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a single byte from the NVM using the ICH8 flash access registers. ch1010832@2198: * ch1010832@2198: * hw - pointer to e1000_hw structure ch1010832@2198: * index - The index of the byte to read. ch1010832@2198: * data - Pointer to a byte to store the value read. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data) ch1010832@2198: { ch1010832@2198: s32 status = E1000_SUCCESS; ch1010832@2198: u16 word = 0; ch1010832@2198: ch1010832@2198: status = e1000_read_ich8_data(hw, index, 1, &word); ch1010832@2198: if (status == E1000_SUCCESS) { ch1010832@2198: *data = (u8)word; ch1010832@2198: } ch1010832@2198: ch1010832@2198: return status; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a single byte to the NVM using the ICH8 flash access registers. ch1010832@2198: * Performs verification by reading back the value and then going through ch1010832@2198: * a retry algorithm before giving up. ch1010832@2198: * ch1010832@2198: * hw - pointer to e1000_hw structure ch1010832@2198: * index - The index of the byte to write. ch1010832@2198: * byte - The byte to write to the NVM. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte) ch1010832@2198: { ch1010832@2198: s32 error = E1000_SUCCESS; ch1010832@2198: s32 program_retries = 0; ch1010832@2198: ch1010832@2198: DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); ch1010832@2198: ch1010832@2198: error = e1000_write_ich8_byte(hw, index, byte); ch1010832@2198: ch1010832@2198: if (error != E1000_SUCCESS) { ch1010832@2198: for (program_retries = 0; program_retries < 100; program_retries++) { ch1010832@2198: DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); ch1010832@2198: error = e1000_write_ich8_byte(hw, index, byte); ch1010832@2198: udelay(100); ch1010832@2198: if (error == E1000_SUCCESS) ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: if (program_retries == 100) ch1010832@2198: error = E1000_ERR_EEPROM; ch1010832@2198: ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Writes a single byte to the NVM using the ICH8 flash access registers. ch1010832@2198: * ch1010832@2198: * hw - pointer to e1000_hw structure ch1010832@2198: * index - The index of the byte to read. ch1010832@2198: * data - The byte to write to the NVM. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data) ch1010832@2198: { ch1010832@2198: s32 status = E1000_SUCCESS; ch1010832@2198: u16 word = (u16)data; ch1010832@2198: ch1010832@2198: status = e1000_write_ich8_data(hw, index, 1, word); ch1010832@2198: ch1010832@2198: return status; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Reads a word from the NVM using the ICH8 flash access registers. ch1010832@2198: * ch1010832@2198: * hw - pointer to e1000_hw structure ch1010832@2198: * index - The starting byte index of the word to read. ch1010832@2198: * data - Pointer to a word to store the value read. ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data) ch1010832@2198: { ch1010832@2198: s32 status = E1000_SUCCESS; ch1010832@2198: status = e1000_read_ich8_data(hw, index, 2, data); ch1010832@2198: return status; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 ch1010832@2198: * based. ch1010832@2198: * ch1010832@2198: * hw - pointer to e1000_hw structure ch1010832@2198: * bank - 0 for first bank, 1 for second bank ch1010832@2198: * ch1010832@2198: * Note that this function may actually erase as much as 8 or 64 KBytes. The ch1010832@2198: * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the ch1010832@2198: * bank size may be 4, 8 or 64 KBytes ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank) ch1010832@2198: { ch1010832@2198: union ich8_hws_flash_status hsfsts; ch1010832@2198: union ich8_hws_flash_ctrl hsflctl; ch1010832@2198: u32 flash_linear_address; ch1010832@2198: s32 count = 0; ch1010832@2198: s32 error = E1000_ERR_EEPROM; ch1010832@2198: s32 iteration; ch1010832@2198: s32 sub_sector_size = 0; ch1010832@2198: s32 bank_size; ch1010832@2198: s32 j = 0; ch1010832@2198: s32 error_flag = 0; ch1010832@2198: ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: ch1010832@2198: /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ ch1010832@2198: /* 00: The Hw sector is 256 bytes, hence we need to erase 16 ch1010832@2198: * consecutive sectors. The start index for the nth Hw sector can be ch1010832@2198: * calculated as bank * 4096 + n * 256 ch1010832@2198: * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. ch1010832@2198: * The start index for the nth Hw sector can be calculated ch1010832@2198: * as bank * 4096 ch1010832@2198: * 10: The HW sector is 8K bytes ch1010832@2198: * 11: The Hw sector size is 64K bytes */ ch1010832@2198: if (hsfsts.hsf_status.berasesz == 0x0) { ch1010832@2198: /* Hw sector size 256 */ ch1010832@2198: sub_sector_size = ICH_FLASH_SEG_SIZE_256; ch1010832@2198: bank_size = ICH_FLASH_SECTOR_SIZE; ch1010832@2198: iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; ch1010832@2198: } else if (hsfsts.hsf_status.berasesz == 0x1) { ch1010832@2198: bank_size = ICH_FLASH_SEG_SIZE_4K; ch1010832@2198: iteration = 1; ch1010832@2198: } else if (hsfsts.hsf_status.berasesz == 0x3) { ch1010832@2198: bank_size = ICH_FLASH_SEG_SIZE_64K; ch1010832@2198: iteration = 1; ch1010832@2198: } else { ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: for (j = 0; j < iteration ; j++) { ch1010832@2198: do { ch1010832@2198: count++; ch1010832@2198: /* Steps */ ch1010832@2198: error = e1000_ich8_cycle_init(hw); ch1010832@2198: if (error != E1000_SUCCESS) { ch1010832@2198: error_flag = 1; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: ch1010832@2198: /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash ch1010832@2198: * Control */ ch1010832@2198: hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); ch1010832@2198: hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; ch1010832@2198: E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); ch1010832@2198: ch1010832@2198: /* Write the last 24 bits of an index within the block into Flash ch1010832@2198: * Linear address field in Flash Address. This probably needs to ch1010832@2198: * be calculated here based off the on-chip erase sector size and ch1010832@2198: * the software bank size (4, 8 or 64 KBytes) */ ch1010832@2198: flash_linear_address = bank * bank_size + j * sub_sector_size; ch1010832@2198: flash_linear_address += hw->flash_base_addr; ch1010832@2198: flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; ch1010832@2198: ch1010832@2198: E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); ch1010832@2198: ch1010832@2198: error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); ch1010832@2198: /* Check if FCERR is set to 1. If 1, clear it and try the whole ch1010832@2198: * sequence a few more times else Done */ ch1010832@2198: if (error == E1000_SUCCESS) { ch1010832@2198: break; ch1010832@2198: } else { ch1010832@2198: hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); ch1010832@2198: if (hsfsts.hsf_status.flcerr == 1) { ch1010832@2198: /* repeat for some time before giving up */ ch1010832@2198: continue; ch1010832@2198: } else if (hsfsts.hsf_status.flcdone == 0) { ch1010832@2198: error_flag = 1; ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); ch1010832@2198: if (error_flag == 1) ch1010832@2198: break; ch1010832@2198: } ch1010832@2198: if (error_flag != 1) ch1010832@2198: error = E1000_SUCCESS; ch1010832@2198: return error; ch1010832@2198: } ch1010832@2198: ch1010832@2198: static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, ch1010832@2198: u32 cnf_base_addr, ch1010832@2198: u32 cnf_size) ch1010832@2198: { ch1010832@2198: u32 ret_val = E1000_SUCCESS; ch1010832@2198: u16 word_addr, reg_data, reg_addr; ch1010832@2198: u16 i; ch1010832@2198: ch1010832@2198: /* cnf_base_addr is in DWORD */ ch1010832@2198: word_addr = (u16)(cnf_base_addr << 1); ch1010832@2198: ch1010832@2198: /* cnf_size is returned in size of dwords */ ch1010832@2198: for (i = 0; i < cnf_size; i++) { ch1010832@2198: ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_get_software_flag(hw); ch1010832@2198: if (ret_val != E1000_SUCCESS) ch1010832@2198: return ret_val; ch1010832@2198: ch1010832@2198: ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data); ch1010832@2198: ch1010832@2198: e1000_release_software_flag(hw); ch1010832@2198: } ch1010832@2198: ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: ch1010832@2198: ch1010832@2198: /****************************************************************************** ch1010832@2198: * This function initializes the PHY from the NVM on ICH8 platforms. This ch1010832@2198: * is needed due to an issue where the NVM configuration is not properly ch1010832@2198: * autoloaded after power transitions. Therefore, after each PHY reset, we ch1010832@2198: * will load the configuration data out of the NVM manually. ch1010832@2198: * ch1010832@2198: * hw: Struct containing variables accessed by shared code ch1010832@2198: *****************************************************************************/ ch1010832@2198: static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw) ch1010832@2198: { ch1010832@2198: u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop; ch1010832@2198: ch1010832@2198: if (hw->phy_type != e1000_phy_igp_3) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Check if SW needs configure the PHY */ ch1010832@2198: reg_data = er32(FEXTNVM); ch1010832@2198: if (!(reg_data & FEXTNVM_SW_CONFIG)) ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: ch1010832@2198: /* Wait for basic configuration completes before proceeding*/ ch1010832@2198: loop = 0; ch1010832@2198: do { ch1010832@2198: reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE; ch1010832@2198: udelay(100); ch1010832@2198: loop++; ch1010832@2198: } while ((!reg_data) && (loop < 50)); ch1010832@2198: ch1010832@2198: /* Clear the Init Done bit for the next init event */ ch1010832@2198: reg_data = er32(STATUS); ch1010832@2198: reg_data &= ~E1000_STATUS_LAN_INIT_DONE; ch1010832@2198: ew32(STATUS, reg_data); ch1010832@2198: ch1010832@2198: /* Make sure HW does not configure LCD from PHY extended configuration ch1010832@2198: before SW configuration */ ch1010832@2198: reg_data = er32(EXTCNF_CTRL); ch1010832@2198: if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { ch1010832@2198: reg_data = er32(EXTCNF_SIZE); ch1010832@2198: cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; ch1010832@2198: cnf_size >>= 16; ch1010832@2198: if (cnf_size) { ch1010832@2198: reg_data = er32(EXTCNF_CTRL); ch1010832@2198: cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; ch1010832@2198: /* cnf_base_addr is in DWORD */ ch1010832@2198: cnf_base_addr >>= 16; ch1010832@2198: ch1010832@2198: /* Configure LCD from extended configuration region. */ ch1010832@2198: ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, ch1010832@2198: cnf_size); ch1010832@2198: if (ret_val) ch1010832@2198: return ret_val; ch1010832@2198: } ch1010832@2198: } ch1010832@2198: ch1010832@2198: return E1000_SUCCESS; ch1010832@2198: } ch1010832@2198: