fp@2587: /*******************************************************************************
fp@2587: 
fp@2587:   Intel PRO/1000 Linux driver
fp@2587:   Copyright(c) 1999 - 2013 Intel Corporation.
fp@2587: 
fp@2587:   This program is free software; you can redistribute it and/or modify it
fp@2587:   under the terms and conditions of the GNU General Public License,
fp@2587:   version 2, as published by the Free Software Foundation.
fp@2587: 
fp@2587:   This program is distributed in the hope it will be useful, but WITHOUT
fp@2587:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2587:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2587:   more details.
fp@2587: 
fp@2587:   You should have received a copy of the GNU General Public License along with
fp@2587:   this program; if not, write to the Free Software Foundation, Inc.,
fp@2587:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
fp@2587: 
fp@2587:   The full GNU General Public License is included in this distribution in
fp@2587:   the file called "COPYING".
fp@2587: 
fp@2587:   Contact Information:
fp@2587:   Linux NICS <linux.nics@intel.com>
fp@2587:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2587:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2587: 
fp@2587: *******************************************************************************/
fp@2587: 
fp@2587: /* Linux PRO/1000 Ethernet Driver main header file */
fp@2587: 
fp@2587: #ifndef _E1000_H_
fp@2587: #define _E1000_H_
fp@2587: 
fp@2587: #include <linux/bitops.h>
fp@2587: #include <linux/types.h>
fp@2587: #include <linux/timer.h>
fp@2587: #include <linux/workqueue.h>
fp@2587: #include <linux/io.h>
fp@2587: #include <linux/netdevice.h>
fp@2587: #include <linux/pci.h>
fp@2587: #include <linux/pci-aspm.h>
fp@2587: #include <linux/crc32.h>
fp@2587: #include <linux/if_vlan.h>
fp@2587: #include <linux/clocksource.h>
fp@2587: #include <linux/net_tstamp.h>
fp@2587: #include <linux/ptp_clock_kernel.h>
fp@2587: #include <linux/ptp_classify.h>
fp@2587: #include <linux/mii.h>
fp@2587: #include <linux/mdio.h>
fp@2587: #include "hw.h"
fp@2587: 
fp@2587: struct e1000_info;
fp@2587: 
fp@2587: #define e_dbg(format, arg...) \
fp@2587: 	netdev_dbg(hw->adapter->netdev, format, ## arg)
fp@2587: #define e_err(format, arg...) \
fp@2587: 	netdev_err(adapter->netdev, format, ## arg)
fp@2587: #define e_info(format, arg...) \
fp@2587: 	netdev_info(adapter->netdev, format, ## arg)
fp@2587: #define e_warn(format, arg...) \
fp@2587: 	netdev_warn(adapter->netdev, format, ## arg)
fp@2587: #define e_notice(format, arg...) \
fp@2587: 	netdev_notice(adapter->netdev, format, ## arg)
fp@2587: 
fp@2587: /* Interrupt modes, as used by the IntMode parameter */
fp@2587: #define E1000E_INT_MODE_LEGACY		0
fp@2587: #define E1000E_INT_MODE_MSI		1
fp@2587: #define E1000E_INT_MODE_MSIX		2
fp@2587: 
fp@2587: /* Tx/Rx descriptor defines */
fp@2587: #define E1000_DEFAULT_TXD		256
fp@2587: #define E1000_MAX_TXD			4096
fp@2587: #define E1000_MIN_TXD			64
fp@2587: 
fp@2587: #define E1000_DEFAULT_RXD		256
fp@2587: #define E1000_MAX_RXD			4096
fp@2587: #define E1000_MIN_RXD			64
fp@2587: 
fp@2587: #define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
fp@2587: #define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
fp@2587: 
fp@2587: #define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
fp@2587: 
fp@2587: /* How many Tx Descriptors do we need to call netif_wake_queue ? */
fp@2587: /* How many Rx Buffers do we bundle into one write to the hardware ? */
fp@2587: #define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
fp@2587: 
fp@2587: #define AUTO_ALL_MODES			0
fp@2587: #define E1000_EEPROM_APME		0x0400
fp@2587: 
fp@2587: #define E1000_MNG_VLAN_NONE		(-1)
fp@2587: 
fp@2587: #define DEFAULT_JUMBO			9234
fp@2587: 
fp@2587: /* Time to wait before putting the device into D3 if there's no link (in ms). */
fp@2587: #define LINK_TIMEOUT		100
fp@2587: 
fp@2587: /* Count for polling __E1000_RESET condition every 10-20msec.
fp@2587:  * Experimentation has shown the reset can take approximately 210msec.
fp@2587:  */
fp@2587: #define E1000_CHECK_RESET_COUNT		25
fp@2587: 
fp@2587: #define DEFAULT_RDTR			0
fp@2587: #define DEFAULT_RADV			8
fp@2587: #define BURST_RDTR			0x20
fp@2587: #define BURST_RADV			0x20
fp@2587: 
fp@2587: /* in the case of WTHRESH, it appears at least the 82571/2 hardware
fp@2587:  * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
fp@2587:  * WTHRESH=4, so a setting of 5 gives the most efficient bus
fp@2587:  * utilization but to avoid possible Tx stalls, set it to 1
fp@2587:  */
fp@2587: #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
fp@2587: 	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
fp@2587: 	 E1000_TXDCTL_COUNT_DESC |                             \
fp@2587: 	 (1 << 16) | /* wthresh must be +1 more than desired */\
fp@2587: 	 (1 << 8)  | /* hthresh */                             \
fp@2587: 	 0x1f)       /* pthresh */
fp@2587: 
fp@2587: #define E1000_RXDCTL_DMA_BURST_ENABLE                          \
fp@2587: 	(0x01000000 | /* set descriptor granularity */         \
fp@2587: 	 (4 << 16)  | /* set writeback threshold    */         \
fp@2587: 	 (4 << 8)   | /* set prefetch threshold     */         \
fp@2587: 	 0x20)        /* set hthresh                */
fp@2587: 
fp@2587: #define E1000_TIDV_FPD (1 << 31)
fp@2587: #define E1000_RDTR_FPD (1 << 31)
fp@2587: 
fp@2587: enum e1000_boards {
fp@2587: 	board_82571,
fp@2587: 	board_82572,
fp@2587: 	board_82573,
fp@2587: 	board_82574,
fp@2587: 	board_82583,
fp@2587: 	board_80003es2lan,
fp@2587: 	board_ich8lan,
fp@2587: 	board_ich9lan,
fp@2587: 	board_ich10lan,
fp@2587: 	board_pchlan,
fp@2587: 	board_pch2lan,
fp@2587: 	board_pch_lpt,
fp@2587: };
fp@2587: 
fp@2587: struct e1000_ps_page {
fp@2587: 	struct page *page;
fp@2587: 	u64 dma; /* must be u64 - written to hw */
fp@2587: };
fp@2587: 
fp@2587: /* wrappers around a pointer to a socket buffer,
fp@2587:  * so a DMA handle can be stored along with the buffer
fp@2587:  */
fp@2587: struct e1000_buffer {
fp@2587: 	dma_addr_t dma;
fp@2587: 	struct sk_buff *skb;
fp@2587: 	union {
fp@2587: 		/* Tx */
fp@2587: 		struct {
fp@2587: 			unsigned long time_stamp;
fp@2587: 			u16 length;
fp@2587: 			u16 next_to_watch;
fp@2587: 			unsigned int segs;
fp@2587: 			unsigned int bytecount;
fp@2587: 			u16 mapped_as_page;
fp@2587: 		};
fp@2587: 		/* Rx */
fp@2587: 		struct {
fp@2587: 			/* arrays of page information for packet split */
fp@2587: 			struct e1000_ps_page *ps_pages;
fp@2587: 			struct page *page;
fp@2587: 		};
fp@2587: 	};
fp@2587: };
fp@2587: 
fp@2587: struct e1000_ring {
fp@2587: 	struct e1000_adapter *adapter;	/* back pointer to adapter */
fp@2587: 	void *desc;			/* pointer to ring memory  */
fp@2587: 	dma_addr_t dma;			/* phys address of ring    */
fp@2587: 	unsigned int size;		/* length of ring in bytes */
fp@2587: 	unsigned int count;		/* number of desc. in ring */
fp@2587: 
fp@2587: 	u16 next_to_use;
fp@2587: 	u16 next_to_clean;
fp@2587: 
fp@2587: 	void __iomem *head;
fp@2587: 	void __iomem *tail;
fp@2587: 
fp@2587: 	/* array of buffer information structs */
fp@2587: 	struct e1000_buffer *buffer_info;
fp@2587: 
fp@2587: 	char name[IFNAMSIZ + 5];
fp@2587: 	u32 ims_val;
fp@2587: 	u32 itr_val;
fp@2587: 	void __iomem *itr_register;
fp@2587: 	int set_itr;
fp@2587: 
fp@2587: 	struct sk_buff *rx_skb_top;
fp@2587: };
fp@2587: 
fp@2587: /* PHY register snapshot values */
fp@2587: struct e1000_phy_regs {
fp@2587: 	u16 bmcr;		/* basic mode control register    */
fp@2587: 	u16 bmsr;		/* basic mode status register     */
fp@2587: 	u16 advertise;		/* auto-negotiation advertisement */
fp@2587: 	u16 lpa;		/* link partner ability register  */
fp@2587: 	u16 expansion;		/* auto-negotiation expansion reg */
fp@2587: 	u16 ctrl1000;		/* 1000BASE-T control register    */
fp@2587: 	u16 stat1000;		/* 1000BASE-T status register     */
fp@2587: 	u16 estatus;		/* extended status register       */
fp@2587: };
fp@2587: 
fp@2587: /* board specific private data structure */
fp@2587: struct e1000_adapter {
fp@2587: 	struct timer_list watchdog_timer;
fp@2587: 	struct timer_list phy_info_timer;
fp@2587: 	struct timer_list blink_timer;
fp@2587: 
fp@2587: 	struct work_struct reset_task;
fp@2587: 	struct work_struct watchdog_task;
fp@2587: 
fp@2587: 	const struct e1000_info *ei;
fp@2587: 
fp@2587: 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
fp@2587: 	u32 bd_number;
fp@2587: 	u32 rx_buffer_len;
fp@2587: 	u16 mng_vlan_id;
fp@2587: 	u16 link_speed;
fp@2587: 	u16 link_duplex;
fp@2587: 	u16 eeprom_vers;
fp@2587: 
fp@2587: 	/* track device up/down/testing state */
fp@2587: 	unsigned long state;
fp@2587: 
fp@2587: 	/* Interrupt Throttle Rate */
fp@2587: 	u32 itr;
fp@2587: 	u32 itr_setting;
fp@2587: 	u16 tx_itr;
fp@2587: 	u16 rx_itr;
fp@2587: 
fp@2587: 	/* Tx - one ring per active queue */
fp@2587: 	struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
fp@2587: 	u32 tx_fifo_limit;
fp@2587: 
fp@2587: 	struct napi_struct napi;
fp@2587: 
fp@2587: 	unsigned int uncorr_errors;	/* uncorrectable ECC errors */
fp@2587: 	unsigned int corr_errors;	/* correctable ECC errors */
fp@2587: 	unsigned int restart_queue;
fp@2587: 	u32 txd_cmd;
fp@2587: 
fp@2587: 	bool detect_tx_hung;
fp@2587: 	bool tx_hang_recheck;
fp@2587: 	u8 tx_timeout_factor;
fp@2587: 
fp@2587: 	u32 tx_int_delay;
fp@2587: 	u32 tx_abs_int_delay;
fp@2587: 
fp@2587: 	unsigned int total_tx_bytes;
fp@2587: 	unsigned int total_tx_packets;
fp@2587: 	unsigned int total_rx_bytes;
fp@2587: 	unsigned int total_rx_packets;
fp@2587: 
fp@2587: 	/* Tx stats */
fp@2587: 	u64 tpt_old;
fp@2587: 	u64 colc_old;
fp@2587: 	u32 gotc;
fp@2587: 	u64 gotc_old;
fp@2587: 	u32 tx_timeout_count;
fp@2587: 	u32 tx_fifo_head;
fp@2587: 	u32 tx_head_addr;
fp@2587: 	u32 tx_fifo_size;
fp@2587: 	u32 tx_dma_failed;
fp@2587: 
fp@2587: 	/* Rx */
fp@2587: 	bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
fp@2587: 			  int work_to_do) ____cacheline_aligned_in_smp;
fp@2587: 	void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
fp@2587: 			      gfp_t gfp);
fp@2587: 	struct e1000_ring *rx_ring;
fp@2587: 
fp@2587: 	u32 rx_int_delay;
fp@2587: 	u32 rx_abs_int_delay;
fp@2587: 
fp@2587: 	/* Rx stats */
fp@2587: 	u64 hw_csum_err;
fp@2587: 	u64 hw_csum_good;
fp@2587: 	u64 rx_hdr_split;
fp@2587: 	u32 gorc;
fp@2587: 	u64 gorc_old;
fp@2587: 	u32 alloc_rx_buff_failed;
fp@2587: 	u32 rx_dma_failed;
fp@2587: 	u32 rx_hwtstamp_cleared;
fp@2587: 
fp@2587: 	unsigned int rx_ps_pages;
fp@2587: 	u16 rx_ps_bsize0;
fp@2587: 	u32 max_frame_size;
fp@2587: 	u32 min_frame_size;
fp@2587: 
fp@2587: 	/* OS defined structs */
fp@2587: 	struct net_device *netdev;
fp@2587: 	struct pci_dev *pdev;
fp@2587: 
fp@2587: 	/* structs defined in e1000_hw.h */
fp@2587: 	struct e1000_hw hw;
fp@2587: 
fp@2587: 	spinlock_t stats64_lock;	/* protects statistics counters */
fp@2587: 	struct e1000_hw_stats stats;
fp@2587: 	struct e1000_phy_info phy_info;
fp@2587: 	struct e1000_phy_stats phy_stats;
fp@2587: 
fp@2587: 	/* Snapshot of PHY registers */
fp@2587: 	struct e1000_phy_regs phy_regs;
fp@2587: 
fp@2587: 	struct e1000_ring test_tx_ring;
fp@2587: 	struct e1000_ring test_rx_ring;
fp@2587: 	u32 test_icr;
fp@2587: 
fp@2587: 	u32 msg_enable;
fp@2587: 	unsigned int num_vectors;
fp@2587: 	struct msix_entry *msix_entries;
fp@2587: 	int int_mode;
fp@2587: 	u32 eiac_mask;
fp@2587: 
fp@2587: 	u32 eeprom_wol;
fp@2587: 	u32 wol;
fp@2587: 	u32 pba;
fp@2587: 	u32 max_hw_frame_size;
fp@2587: 
fp@2587: 	bool fc_autoneg;
fp@2587: 
fp@2587: 	unsigned int flags;
fp@2587: 	unsigned int flags2;
fp@2587: 	struct work_struct downshift_task;
fp@2587: 	struct work_struct update_phy_task;
fp@2587: 	struct work_struct print_hang_task;
fp@2587: 
fp@2587: 	bool idle_check;
fp@2587: 	int phy_hang_count;
fp@2587: 
fp@2587: 	u16 tx_ring_count;
fp@2587: 	u16 rx_ring_count;
fp@2587: 
fp@2587: 	struct hwtstamp_config hwtstamp_config;
fp@2587: 	struct delayed_work systim_overflow_work;
fp@2587: 	struct sk_buff *tx_hwtstamp_skb;
fp@2587: 	struct work_struct tx_hwtstamp_work;
fp@2587: 	spinlock_t systim_lock;	/* protects SYSTIML/H regsters */
fp@2587: 	struct cyclecounter cc;
fp@2587: 	struct timecounter tc;
fp@2587: 	struct ptp_clock *ptp_clock;
fp@2587: 	struct ptp_clock_info ptp_clock_info;
fp@2587: 
fp@2587: 	u16 eee_advert;
fp@2587: };
fp@2587: 
fp@2587: struct e1000_info {
fp@2587: 	enum e1000_mac_type	mac;
fp@2587: 	unsigned int		flags;
fp@2587: 	unsigned int		flags2;
fp@2587: 	u32			pba;
fp@2587: 	u32			max_hw_frame_size;
fp@2587: 	s32			(*get_variants)(struct e1000_adapter *);
fp@2587: 	const struct e1000_mac_operations *mac_ops;
fp@2587: 	const struct e1000_phy_operations *phy_ops;
fp@2587: 	const struct e1000_nvm_operations *nvm_ops;
fp@2587: };
fp@2587: 
fp@2587: s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
fp@2587: 
fp@2587: /* The system time is maintained by a 64-bit counter comprised of the 32-bit
fp@2587:  * SYSTIMH and SYSTIML registers.  How the counter increments (and therefore
fp@2587:  * its resolution) is based on the contents of the TIMINCA register - it
fp@2587:  * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
fp@2587:  * For the best accuracy, the incperiod should be as small as possible.  The
fp@2587:  * incvalue is scaled by a factor as large as possible (while still fitting
fp@2587:  * in bits 23:0) so that relatively small clock corrections can be made.
fp@2587:  *
fp@2587:  * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
fp@2587:  * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
fp@2587:  * bits to count nanoseconds leaving the rest for fractional nonseconds.
fp@2587:  */
fp@2587: #define INCVALUE_96MHz		125
fp@2587: #define INCVALUE_SHIFT_96MHz	17
fp@2587: #define INCPERIOD_SHIFT_96MHz	2
fp@2587: #define INCPERIOD_96MHz		(12 >> INCPERIOD_SHIFT_96MHz)
fp@2587: 
fp@2587: #define INCVALUE_25MHz		40
fp@2587: #define INCVALUE_SHIFT_25MHz	18
fp@2587: #define INCPERIOD_25MHz		1
fp@2587: 
fp@2587: /* Another drawback of scaling the incvalue by a large factor is the
fp@2587:  * 64-bit SYSTIM register overflows more quickly.  This is dealt with
fp@2587:  * by simply reading the clock before it overflows.
fp@2587:  *
fp@2587:  * Clock	ns bits	Overflows after
fp@2587:  * ~~~~~~	~~~~~~~	~~~~~~~~~~~~~~~
fp@2587:  * 96MHz	47-bit	2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
fp@2587:  * 25MHz	46-bit	2^46 / 10^9 / 3600 = 19.55 hours
fp@2587:  */
fp@2587: #define E1000_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 60 * 4)
fp@2587: 
fp@2587: /* hardware capability, feature, and workaround flags */
fp@2587: #define FLAG_HAS_AMT                      (1 << 0)
fp@2587: #define FLAG_HAS_FLASH                    (1 << 1)
fp@2587: #define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
fp@2587: #define FLAG_HAS_WOL                      (1 << 3)
fp@2587: /* reserved bit4 */
fp@2587: #define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
fp@2587: #define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
fp@2587: #define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
fp@2587: #define FLAG_READ_ONLY_NVM                (1 << 8)
fp@2587: #define FLAG_IS_ICH                       (1 << 9)
fp@2587: #define FLAG_HAS_MSIX                     (1 << 10)
fp@2587: #define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
fp@2587: #define FLAG_IS_QUAD_PORT_A               (1 << 12)
fp@2587: #define FLAG_IS_QUAD_PORT                 (1 << 13)
fp@2587: #define FLAG_HAS_HW_TIMESTAMP             (1 << 14)
fp@2587: #define FLAG_APME_IN_WUC                  (1 << 15)
fp@2587: #define FLAG_APME_IN_CTRL3                (1 << 16)
fp@2587: #define FLAG_APME_CHECK_PORT_B            (1 << 17)
fp@2587: #define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
fp@2587: #define FLAG_NO_WAKE_UCAST                (1 << 19)
fp@2587: #define FLAG_MNG_PT_ENABLED               (1 << 20)
fp@2587: #define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
fp@2587: #define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
fp@2587: #define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
fp@2587: #define FLAG_RX_NEEDS_RESTART             (1 << 24)
fp@2587: #define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
fp@2587: #define FLAG_SMART_POWER_DOWN             (1 << 26)
fp@2587: #define FLAG_MSI_ENABLED                  (1 << 27)
fp@2587: /* reserved (1 << 28) */
fp@2587: #define FLAG_TSO_FORCE                    (1 << 29)
fp@2587: #define FLAG_RESTART_NOW                  (1 << 30)
fp@2587: #define FLAG_MSI_TEST_FAILED              (1 << 31)
fp@2587: 
fp@2587: #define FLAG2_CRC_STRIPPING               (1 << 0)
fp@2587: #define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
fp@2587: #define FLAG2_IS_DISCARDING               (1 << 2)
fp@2587: #define FLAG2_DISABLE_ASPM_L1             (1 << 3)
fp@2587: #define FLAG2_HAS_PHY_STATS               (1 << 4)
fp@2587: #define FLAG2_HAS_EEE                     (1 << 5)
fp@2587: #define FLAG2_DMA_BURST                   (1 << 6)
fp@2587: #define FLAG2_DISABLE_ASPM_L0S            (1 << 7)
fp@2587: #define FLAG2_DISABLE_AIM                 (1 << 8)
fp@2587: #define FLAG2_CHECK_PHY_HANG              (1 << 9)
fp@2587: #define FLAG2_NO_DISABLE_RX               (1 << 10)
fp@2587: #define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)
fp@2587: #define FLAG2_DFLT_CRC_STRIPPING          (1 << 12)
fp@2587: #define FLAG2_CHECK_RX_HWTSTAMP           (1 << 13)
fp@2587: 
fp@2587: #define E1000_RX_DESC_PS(R, i)	    \
fp@2587: 	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
fp@2587: #define E1000_RX_DESC_EXT(R, i)	    \
fp@2587: 	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
fp@2587: #define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
fp@2587: #define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
fp@2587: #define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
fp@2587: 
fp@2587: enum e1000_state_t {
fp@2587: 	__E1000_TESTING,
fp@2587: 	__E1000_RESETTING,
fp@2587: 	__E1000_ACCESS_SHARED_RESOURCE,
fp@2587: 	__E1000_DOWN
fp@2587: };
fp@2587: 
fp@2587: enum latency_range {
fp@2587: 	lowest_latency = 0,
fp@2587: 	low_latency = 1,
fp@2587: 	bulk_latency = 2,
fp@2587: 	latency_invalid = 255
fp@2587: };
fp@2587: 
fp@2587: extern char e1000e_driver_name[];
fp@2587: extern const char e1000e_driver_version[];
fp@2587: 
fp@2587: void e1000e_check_options(struct e1000_adapter *adapter);
fp@2587: void e1000e_set_ethtool_ops(struct net_device *netdev);
fp@2587: 
fp@2587: int e1000e_up(struct e1000_adapter *adapter);
fp@2587: void e1000e_down(struct e1000_adapter *adapter);
fp@2587: void e1000e_reinit_locked(struct e1000_adapter *adapter);
fp@2587: void e1000e_reset(struct e1000_adapter *adapter);
fp@2587: void e1000e_power_up_phy(struct e1000_adapter *adapter);
fp@2587: int e1000e_setup_rx_resources(struct e1000_ring *ring);
fp@2587: int e1000e_setup_tx_resources(struct e1000_ring *ring);
fp@2587: void e1000e_free_rx_resources(struct e1000_ring *ring);
fp@2587: void e1000e_free_tx_resources(struct e1000_ring *ring);
fp@2587: struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
fp@2587: 					     struct rtnl_link_stats64 *stats);
fp@2587: void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
fp@2587: void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
fp@2587: void e1000e_get_hw_control(struct e1000_adapter *adapter);
fp@2587: void e1000e_release_hw_control(struct e1000_adapter *adapter);
fp@2587: void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
fp@2587: 
fp@2587: extern unsigned int copybreak;
fp@2587: 
fp@2587: extern const struct e1000_info e1000_82571_info;
fp@2587: extern const struct e1000_info e1000_82572_info;
fp@2587: extern const struct e1000_info e1000_82573_info;
fp@2587: extern const struct e1000_info e1000_82574_info;
fp@2587: extern const struct e1000_info e1000_82583_info;
fp@2587: extern const struct e1000_info e1000_ich8_info;
fp@2587: extern const struct e1000_info e1000_ich9_info;
fp@2587: extern const struct e1000_info e1000_ich10_info;
fp@2587: extern const struct e1000_info e1000_pch_info;
fp@2587: extern const struct e1000_info e1000_pch2_info;
fp@2587: extern const struct e1000_info e1000_pch_lpt_info;
fp@2587: extern const struct e1000_info e1000_es2_info;
fp@2587: 
fp@2587: void e1000e_ptp_init(struct e1000_adapter *adapter);
fp@2587: void e1000e_ptp_remove(struct e1000_adapter *adapter);
fp@2587: 
fp@2587: static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	return hw->phy.ops.reset(hw);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2587: {
fp@2587: 	return hw->phy.ops.read_reg(hw, offset, data);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2587: {
fp@2587: 	return hw->phy.ops.read_reg_locked(hw, offset, data);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
fp@2587: {
fp@2587: 	return hw->phy.ops.write_reg(hw, offset, data);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
fp@2587: {
fp@2587: 	return hw->phy.ops.write_reg_locked(hw, offset, data);
fp@2587: }
fp@2587: 
fp@2587: void e1000e_reload_nvm_generic(struct e1000_hw *hw);
fp@2587: 
fp@2587: static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	if (hw->mac.ops.read_mac_addr)
fp@2587: 		return hw->mac.ops.read_mac_addr(hw);
fp@2587: 
fp@2587: 	return e1000_read_mac_addr_generic(hw);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	return hw->nvm.ops.validate(hw);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	return hw->nvm.ops.update(hw);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
fp@2587: 				 u16 *data)
fp@2587: {
fp@2587: 	return hw->nvm.ops.read(hw, offset, words, data);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
fp@2587: 				  u16 *data)
fp@2587: {
fp@2587: 	return hw->nvm.ops.write(hw, offset, words, data);
fp@2587: }
fp@2587: 
fp@2587: static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	return hw->phy.ops.get_info(hw);
fp@2587: }
fp@2587: 
fp@2587: static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
fp@2587: {
fp@2587: 	return readl(hw->hw_addr + reg);
fp@2587: }
fp@2587: 
fp@2587: #define er32(reg)	__er32(hw, E1000_##reg)
fp@2587: 
fp@2587: /**
fp@2587:  * __ew32_prepare - prepare to write to MAC CSR register on certain parts
fp@2587:  * @hw: pointer to the HW structure
fp@2587:  *
fp@2587:  * When updating the MAC CSR registers, the Manageability Engine (ME) could
fp@2587:  * be accessing the registers at the same time.  Normally, this is handled in
fp@2587:  * h/w by an arbiter but on some parts there is a bug that acknowledges Host
fp@2587:  * accesses later than it should which could result in the register to have
fp@2587:  * an incorrect value.  Workaround this by checking the FWSM register which
fp@2587:  * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
fp@2587:  * and try again a number of times.
fp@2587:  **/
fp@2587: static inline s32 __ew32_prepare(struct e1000_hw *hw)
fp@2587: {
fp@2587: 	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
fp@2587: 
fp@2587: 	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
fp@2587: 		udelay(50);
fp@2587: 
fp@2587: 	return i;
fp@2587: }
fp@2587: 
fp@2587: static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
fp@2587: {
fp@2587: 	if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
fp@2587: 		__ew32_prepare(hw);
fp@2587: 
fp@2587: 	writel(val, hw->hw_addr + reg);
fp@2587: }
fp@2587: 
fp@2587: #define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))
fp@2587: 
fp@2587: #define e1e_flush()	er32(STATUS)
fp@2587: 
fp@2587: #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
fp@2587: 	(__ew32((a), (reg + ((offset) << 2)), (value)))
fp@2587: 
fp@2587: #define E1000_READ_REG_ARRAY(a, reg, offset) \
fp@2587: 	(readl((a)->hw_addr + reg + ((offset) << 2)))
fp@2587: 
fp@2587: #endif /* _E1000_H_ */