ch1010832@1992: /******************************************************************************* ch1010832@1992: ch1010832@1992: Intel PRO/1000 Linux driver ch1010832@1992: Copyright(c) 1999 - 2006 Intel Corporation. ch1010832@1992: ch1010832@1992: This program is free software; you can redistribute it and/or modify it ch1010832@1992: under the terms and conditions of the GNU General Public License, ch1010832@1992: version 2, as published by the Free Software Foundation. ch1010832@1992: ch1010832@1992: This program is distributed in the hope it will be useful, but WITHOUT ch1010832@1992: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ch1010832@1992: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ch1010832@1992: more details. ch1010832@1992: ch1010832@1992: You should have received a copy of the GNU General Public License along with ch1010832@1992: this program; if not, write to the Free Software Foundation, Inc., ch1010832@1992: 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ch1010832@1992: ch1010832@1992: The full GNU General Public License is included in this distribution in ch1010832@1992: the file called "COPYING". ch1010832@1992: ch1010832@1992: Contact Information: ch1010832@1992: Linux NICS ch1010832@1992: e1000-devel Mailing List ch1010832@1992: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ch1010832@1992: ch1010832@1992: */ ch1010832@1992: ch1010832@1992: /* e1000_hw.c ch1010832@1992: * Shared functions for accessing and configuring the MAC ch1010832@1992: */ ch1010832@1992: ch1010832@1992: #include "e1000_hw.h" ch1010832@1992: ch1010832@1992: static s32 e1000_check_downshift(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_check_polarity(struct e1000_hw *hw, ch1010832@1992: e1000_rev_polarity *polarity); ch1010832@1992: static void e1000_clear_hw_cntrs(struct e1000_hw *hw); ch1010832@1992: static void e1000_clear_vfta(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, ch1010832@1992: bool link_up); ch1010832@1992: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_detect_gig_phy(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, ch1010832@1992: u16 *max_length); ch1010832@1992: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_id_led_init(struct e1000_hw *hw); ch1010832@1992: static void e1000_init_rx_addrs(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, ch1010832@1992: struct e1000_phy_info *phy_info); ch1010832@1992: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, ch1010832@1992: struct e1000_phy_info *phy_info); ch1010832@1992: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); ch1010832@1992: static s32 e1000_wait_autoneg(struct e1000_hw *hw); ch1010832@1992: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); ch1010832@1992: static s32 e1000_set_phy_type(struct e1000_hw *hw); ch1010832@1992: static void e1000_phy_init_script(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_setup_copper_link(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); ch1010832@1992: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); ch1010832@1992: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); ch1010832@1992: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); ch1010832@1992: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, ch1010832@1992: u16 words, u16 *data); ch1010832@1992: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, ch1010832@1992: u16 words, u16 *data); ch1010832@1992: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); ch1010832@1992: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); ch1010832@1992: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); ch1010832@1992: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); ch1010832@1992: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@1992: u16 phy_data); ch1010832@1992: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@1992: u16 *phy_data); ch1010832@1992: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); ch1010832@1992: static s32 e1000_acquire_eeprom(struct e1000_hw *hw); ch1010832@1992: static void e1000_release_eeprom(struct e1000_hw *hw); ch1010832@1992: static void e1000_standby_eeprom(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_set_vco_speed(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_set_phy_mode(struct e1000_hw *hw); ch1010832@1992: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@1992: u16 *data); ch1010832@1992: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@1992: u16 *data); ch1010832@1992: ch1010832@1992: /* IGP cable length table */ ch1010832@1992: static const ch1010832@1992: u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { ch1010832@1992: 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ch1010832@1992: 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, ch1010832@1992: 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, ch1010832@1992: 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, ch1010832@1992: 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, ch1010832@1992: 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, ch1010832@1992: 100, ch1010832@1992: 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, ch1010832@1992: 110, 110, ch1010832@1992: 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, ch1010832@1992: 120, 120 ch1010832@1992: }; ch1010832@1992: ch1010832@1992: static DEFINE_SPINLOCK(e1000_eeprom_lock); ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_set_phy_type - Set the phy type member in the hw struct. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static s32 e1000_set_phy_type(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_set_phy_type"); ch1010832@1992: ch1010832@1992: if (hw->mac_type == e1000_undefined) ch1010832@1992: return -E1000_ERR_PHY_TYPE; ch1010832@1992: ch1010832@1992: switch (hw->phy_id) { ch1010832@1992: case M88E1000_E_PHY_ID: ch1010832@1992: case M88E1000_I_PHY_ID: ch1010832@1992: case M88E1011_I_PHY_ID: ch1010832@1992: case M88E1111_I_PHY_ID: ch1010832@1992: hw->phy_type = e1000_phy_m88; ch1010832@1992: break; ch1010832@1992: case IGP01E1000_I_PHY_ID: ch1010832@1992: if (hw->mac_type == e1000_82541 || ch1010832@1992: hw->mac_type == e1000_82541_rev_2 || ch1010832@1992: hw->mac_type == e1000_82547 || ch1010832@1992: hw->mac_type == e1000_82547_rev_2) { ch1010832@1992: hw->phy_type = e1000_phy_igp; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: default: ch1010832@1992: /* Should never have loaded on this device */ ch1010832@1992: hw->phy_type = e1000_phy_undefined; ch1010832@1992: return -E1000_ERR_PHY_TYPE; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static void e1000_phy_init_script(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ret_val; ch1010832@1992: u16 phy_saved_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_init_script"); ch1010832@1992: ch1010832@1992: if (hw->phy_init_script) { ch1010832@1992: msleep(20); ch1010832@1992: ch1010832@1992: /* Save off the current value of register 0x2F5B to be restored at ch1010832@1992: * the end of this routine. */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); ch1010832@1992: ch1010832@1992: /* Disabled the PHY transmitter */ ch1010832@1992: e1000_write_phy_reg(hw, 0x2F5B, 0x0003); ch1010832@1992: msleep(20); ch1010832@1992: ch1010832@1992: e1000_write_phy_reg(hw, 0x0000, 0x0140); ch1010832@1992: msleep(5); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82547: ch1010832@1992: e1000_write_phy_reg(hw, 0x1F95, 0x0001); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F71, 0xBD21); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F79, 0x0018); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F30, 0x1600); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F31, 0x0014); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F32, 0x161C); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F94, 0x0003); ch1010832@1992: e1000_write_phy_reg(hw, 0x1F96, 0x003F); ch1010832@1992: e1000_write_phy_reg(hw, 0x2010, 0x0008); ch1010832@1992: break; ch1010832@1992: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: e1000_write_phy_reg(hw, 0x1F73, 0x0099); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: e1000_write_phy_reg(hw, 0x0000, 0x3300); ch1010832@1992: msleep(20); ch1010832@1992: ch1010832@1992: /* Now enable the transmitter */ ch1010832@1992: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); ch1010832@1992: ch1010832@1992: if (hw->mac_type == e1000_82547) { ch1010832@1992: u16 fused, fine, coarse; ch1010832@1992: ch1010832@1992: /* Move to analog registers page */ ch1010832@1992: e1000_read_phy_reg(hw, ch1010832@1992: IGP01E1000_ANALOG_SPARE_FUSE_STATUS, ch1010832@1992: &fused); ch1010832@1992: ch1010832@1992: if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { ch1010832@1992: e1000_read_phy_reg(hw, ch1010832@1992: IGP01E1000_ANALOG_FUSE_STATUS, ch1010832@1992: &fused); ch1010832@1992: ch1010832@1992: fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; ch1010832@1992: coarse = ch1010832@1992: fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; ch1010832@1992: ch1010832@1992: if (coarse > ch1010832@1992: IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { ch1010832@1992: coarse -= ch1010832@1992: IGP01E1000_ANALOG_FUSE_COARSE_10; ch1010832@1992: fine -= IGP01E1000_ANALOG_FUSE_FINE_1; ch1010832@1992: } else if (coarse == ch1010832@1992: IGP01E1000_ANALOG_FUSE_COARSE_THRESH) ch1010832@1992: fine -= IGP01E1000_ANALOG_FUSE_FINE_10; ch1010832@1992: ch1010832@1992: fused = ch1010832@1992: (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | ch1010832@1992: (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | ch1010832@1992: (coarse & ch1010832@1992: IGP01E1000_ANALOG_FUSE_COARSE_MASK); ch1010832@1992: ch1010832@1992: e1000_write_phy_reg(hw, ch1010832@1992: IGP01E1000_ANALOG_FUSE_CONTROL, ch1010832@1992: fused); ch1010832@1992: e1000_write_phy_reg(hw, ch1010832@1992: IGP01E1000_ANALOG_FUSE_BYPASS, ch1010832@1992: IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_set_mac_type - Set the mac type member in the hw struct. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: s32 e1000_set_mac_type(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_set_mac_type"); ch1010832@1992: ch1010832@1992: switch (hw->device_id) { ch1010832@1992: case E1000_DEV_ID_82542: ch1010832@1992: switch (hw->revision_id) { ch1010832@1992: case E1000_82542_2_0_REV_ID: ch1010832@1992: hw->mac_type = e1000_82542_rev2_0; ch1010832@1992: break; ch1010832@1992: case E1000_82542_2_1_REV_ID: ch1010832@1992: hw->mac_type = e1000_82542_rev2_1; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: /* Invalid 82542 revision ID */ ch1010832@1992: return -E1000_ERR_MAC_TYPE; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82543GC_FIBER: ch1010832@1992: case E1000_DEV_ID_82543GC_COPPER: ch1010832@1992: hw->mac_type = e1000_82543; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82544EI_COPPER: ch1010832@1992: case E1000_DEV_ID_82544EI_FIBER: ch1010832@1992: case E1000_DEV_ID_82544GC_COPPER: ch1010832@1992: case E1000_DEV_ID_82544GC_LOM: ch1010832@1992: hw->mac_type = e1000_82544; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82540EM: ch1010832@1992: case E1000_DEV_ID_82540EM_LOM: ch1010832@1992: case E1000_DEV_ID_82540EP: ch1010832@1992: case E1000_DEV_ID_82540EP_LOM: ch1010832@1992: case E1000_DEV_ID_82540EP_LP: ch1010832@1992: hw->mac_type = e1000_82540; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82545EM_COPPER: ch1010832@1992: case E1000_DEV_ID_82545EM_FIBER: ch1010832@1992: hw->mac_type = e1000_82545; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82545GM_COPPER: ch1010832@1992: case E1000_DEV_ID_82545GM_FIBER: ch1010832@1992: case E1000_DEV_ID_82545GM_SERDES: ch1010832@1992: hw->mac_type = e1000_82545_rev_3; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82546EB_COPPER: ch1010832@1992: case E1000_DEV_ID_82546EB_FIBER: ch1010832@1992: case E1000_DEV_ID_82546EB_QUAD_COPPER: ch1010832@1992: hw->mac_type = e1000_82546; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82546GB_COPPER: ch1010832@1992: case E1000_DEV_ID_82546GB_FIBER: ch1010832@1992: case E1000_DEV_ID_82546GB_SERDES: ch1010832@1992: case E1000_DEV_ID_82546GB_PCIE: ch1010832@1992: case E1000_DEV_ID_82546GB_QUAD_COPPER: ch1010832@1992: case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: ch1010832@1992: hw->mac_type = e1000_82546_rev_3; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82541EI: ch1010832@1992: case E1000_DEV_ID_82541EI_MOBILE: ch1010832@1992: case E1000_DEV_ID_82541ER_LOM: ch1010832@1992: hw->mac_type = e1000_82541; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82541ER: ch1010832@1992: case E1000_DEV_ID_82541GI: ch1010832@1992: case E1000_DEV_ID_82541GI_LF: ch1010832@1992: case E1000_DEV_ID_82541GI_MOBILE: ch1010832@1992: hw->mac_type = e1000_82541_rev_2; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82547EI: ch1010832@1992: case E1000_DEV_ID_82547EI_MOBILE: ch1010832@1992: hw->mac_type = e1000_82547; ch1010832@1992: break; ch1010832@1992: case E1000_DEV_ID_82547GI: ch1010832@1992: hw->mac_type = e1000_82547_rev_2; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: /* Should never have loaded on this device */ ch1010832@1992: return -E1000_ERR_MAC_TYPE; ch1010832@1992: } ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82547: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: hw->asf_firmware_present = true; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* The 82543 chip does not count tx_carrier_errors properly in ch1010832@1992: * FD mode ch1010832@1992: */ ch1010832@1992: if (hw->mac_type == e1000_82543) ch1010832@1992: hw->bad_tx_carr_stats_fd = true; ch1010832@1992: ch1010832@1992: if (hw->mac_type > e1000_82544) ch1010832@1992: hw->has_smbus = true; ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_set_media_type - Set media type and TBI compatibility. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: void e1000_set_media_type(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 status; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_set_media_type"); ch1010832@1992: ch1010832@1992: if (hw->mac_type != e1000_82543) { ch1010832@1992: /* tbi_compatibility is only valid on 82543 */ ch1010832@1992: hw->tbi_compatibility_en = false; ch1010832@1992: } ch1010832@1992: ch1010832@1992: switch (hw->device_id) { ch1010832@1992: case E1000_DEV_ID_82545GM_SERDES: ch1010832@1992: case E1000_DEV_ID_82546GB_SERDES: ch1010832@1992: hw->media_type = e1000_media_type_internal_serdes; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: hw->media_type = e1000_media_type_fiber; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: status = er32(STATUS); ch1010832@1992: if (status & E1000_STATUS_TBIMODE) { ch1010832@1992: hw->media_type = e1000_media_type_fiber; ch1010832@1992: /* tbi_compatibility not valid on fiber */ ch1010832@1992: hw->tbi_compatibility_en = false; ch1010832@1992: } else { ch1010832@1992: hw->media_type = e1000_media_type_copper; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_reset_hw: reset the hardware completely ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Reset the transmit and receive units; mask and clear all interrupts. ch1010832@1992: */ ch1010832@1992: s32 e1000_reset_hw(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: u32 ctrl_ext; ch1010832@1992: u32 icr; ch1010832@1992: u32 manc; ch1010832@1992: u32 led_ctrl; ch1010832@1992: s32 ret_val; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_reset_hw"); ch1010832@1992: ch1010832@1992: /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ ch1010832@1992: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@1992: DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); ch1010832@1992: e1000_pci_clear_mwi(hw); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Clear interrupt mask to stop board from generating interrupts */ ch1010832@1992: DEBUGOUT("Masking off all interrupts\n"); ch1010832@1992: ew32(IMC, 0xffffffff); ch1010832@1992: ch1010832@1992: /* Disable the Transmit and Receive units. Then delay to allow ch1010832@1992: * any pending transactions to complete before we hit the MAC with ch1010832@1992: * the global reset. ch1010832@1992: */ ch1010832@1992: ew32(RCTL, 0); ch1010832@1992: ew32(TCTL, E1000_TCTL_PSP); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ ch1010832@1992: hw->tbi_compatibility_on = false; ch1010832@1992: ch1010832@1992: /* Delay to allow any outstanding PCI transactions to complete before ch1010832@1992: * resetting the device ch1010832@1992: */ ch1010832@1992: msleep(10); ch1010832@1992: ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: /* Must reset the PHY before resetting the MAC */ ch1010832@1992: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@1992: ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); ch1010832@1992: msleep(5); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Issue a global reset to the MAC. This will reset the chip's ch1010832@1992: * transmit, receive, DMA, and link units. It will not effect ch1010832@1992: * the current PCI configuration. The global reset bit is self- ch1010832@1992: * clearing, and should clear within a microsecond. ch1010832@1992: */ ch1010832@1992: DEBUGOUT("Issuing a global reset to MAC\n"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82544: ch1010832@1992: case e1000_82540: ch1010832@1992: case e1000_82545: ch1010832@1992: case e1000_82546: ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: /* These controllers can't ack the 64-bit write when issuing the ch1010832@1992: * reset, so use IO-mapping as a workaround to issue the reset */ ch1010832@1992: E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); ch1010832@1992: break; ch1010832@1992: case e1000_82545_rev_3: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: /* Reset is performed on a shadow of the control register */ ch1010832@1992: ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: ew32(CTRL, (ctrl | E1000_CTRL_RST)); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* After MAC reset, force reload of EEPROM to restore power-on settings to ch1010832@1992: * device. Later controllers reload the EEPROM automatically, so just wait ch1010832@1992: * for reload to complete. ch1010832@1992: */ ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: case e1000_82543: ch1010832@1992: case e1000_82544: ch1010832@1992: /* Wait for reset to complete */ ch1010832@1992: udelay(10); ch1010832@1992: ctrl_ext = er32(CTRL_EXT); ch1010832@1992: ctrl_ext |= E1000_CTRL_EXT_EE_RST; ch1010832@1992: ew32(CTRL_EXT, ctrl_ext); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: /* Wait for EEPROM reload */ ch1010832@1992: msleep(2); ch1010832@1992: break; ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: /* Wait for EEPROM reload */ ch1010832@1992: msleep(20); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: /* Auto read done will delay 5ms or poll based on mac type */ ch1010832@1992: ret_val = e1000_get_auto_rd_done(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Disable HW ARPs on ASF enabled adapters */ ch1010832@1992: if (hw->mac_type >= e1000_82540) { ch1010832@1992: manc = er32(MANC); ch1010832@1992: manc &= ~(E1000_MANC_ARP_EN); ch1010832@1992: ew32(MANC, manc); ch1010832@1992: } ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@1992: e1000_phy_init_script(hw); ch1010832@1992: ch1010832@1992: /* Configure activity LED after PHY reset */ ch1010832@1992: led_ctrl = er32(LEDCTL); ch1010832@1992: led_ctrl &= IGP_ACTIVITY_LED_MASK; ch1010832@1992: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ch1010832@1992: ew32(LEDCTL, led_ctrl); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Clear interrupt mask to stop board from generating interrupts */ ch1010832@1992: DEBUGOUT("Masking off all interrupts\n"); ch1010832@1992: ew32(IMC, 0xffffffff); ch1010832@1992: ch1010832@1992: /* Clear any pending interrupt events. */ ch1010832@1992: icr = er32(ICR); ch1010832@1992: ch1010832@1992: /* If MWI was previously enabled, reenable it. */ ch1010832@1992: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@1992: if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) ch1010832@1992: e1000_pci_set_mwi(hw); ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_init_hw: Performs basic configuration of the adapter. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Assumes that the controller has previously been reset and is in a ch1010832@1992: * post-reset uninitialized state. Initializes the receive address registers, ch1010832@1992: * multicast table, and VLAN filter table. Calls routines to setup link ch1010832@1992: * configuration and flow control settings. Clears all on-chip counters. Leaves ch1010832@1992: * the transmit and receive units disabled and uninitialized. ch1010832@1992: */ ch1010832@1992: s32 e1000_init_hw(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: u32 i; ch1010832@1992: s32 ret_val; ch1010832@1992: u32 mta_size; ch1010832@1992: u32 ctrl_ext; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_init_hw"); ch1010832@1992: ch1010832@1992: /* Initialize Identification LED */ ch1010832@1992: ret_val = e1000_id_led_init(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Initializing Identification LED\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Set the media type and TBI compatibility */ ch1010832@1992: e1000_set_media_type(hw); ch1010832@1992: ch1010832@1992: /* Disabling VLAN filtering. */ ch1010832@1992: DEBUGOUT("Initializing the IEEE VLAN\n"); ch1010832@1992: if (hw->mac_type < e1000_82545_rev_3) ch1010832@1992: ew32(VET, 0); ch1010832@1992: e1000_clear_vfta(hw); ch1010832@1992: ch1010832@1992: /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ ch1010832@1992: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@1992: DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); ch1010832@1992: e1000_pci_clear_mwi(hw); ch1010832@1992: ew32(RCTL, E1000_RCTL_RST); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: msleep(5); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Setup the receive address. This involves initializing all of the Receive ch1010832@1992: * Address Registers (RARs 0 - 15). ch1010832@1992: */ ch1010832@1992: e1000_init_rx_addrs(hw); ch1010832@1992: ch1010832@1992: /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ ch1010832@1992: if (hw->mac_type == e1000_82542_rev2_0) { ch1010832@1992: ew32(RCTL, 0); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: msleep(1); ch1010832@1992: if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) ch1010832@1992: e1000_pci_set_mwi(hw); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Zero out the Multicast HASH table */ ch1010832@1992: DEBUGOUT("Zeroing the MTA\n"); ch1010832@1992: mta_size = E1000_MC_TBL_SIZE; ch1010832@1992: for (i = 0; i < mta_size; i++) { ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); ch1010832@1992: /* use write flush to prevent Memory Write Block (MWB) from ch1010832@1992: * occurring when accessing our register space */ ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Set the PCI priority bit correctly in the CTRL register. This ch1010832@1992: * determines if the adapter gives priority to receives, or if it ch1010832@1992: * gives equal priority to transmits and receives. Valid only on ch1010832@1992: * 82542 and 82543 silicon. ch1010832@1992: */ ch1010832@1992: if (hw->dma_fairness && hw->mac_type <= e1000_82543) { ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ew32(CTRL, ctrl | E1000_CTRL_PRIOR); ch1010832@1992: } ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82545_rev_3: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ ch1010832@1992: if (hw->bus_type == e1000_bus_type_pcix ch1010832@1992: && e1000_pcix_get_mmrbc(hw) > 2048) ch1010832@1992: e1000_pcix_set_mmrbc(hw, 2048); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Call a subroutine to configure the link and setup flow control. */ ch1010832@1992: ret_val = e1000_setup_link(hw); ch1010832@1992: ch1010832@1992: /* Set the transmit descriptor write-back policy */ ch1010832@1992: if (hw->mac_type > e1000_82544) { ch1010832@1992: ctrl = er32(TXDCTL); ch1010832@1992: ctrl = ch1010832@1992: (ctrl & ~E1000_TXDCTL_WTHRESH) | ch1010832@1992: E1000_TXDCTL_FULL_TX_DESC_WB; ch1010832@1992: ew32(TXDCTL, ctrl); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Clear all of the statistics registers (clear on read). It is ch1010832@1992: * important that we do this after we have tried to establish link ch1010832@1992: * because the symbol error count will increment wildly if there ch1010832@1992: * is no link. ch1010832@1992: */ ch1010832@1992: e1000_clear_hw_cntrs(hw); ch1010832@1992: ch1010832@1992: if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || ch1010832@1992: hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { ch1010832@1992: ctrl_ext = er32(CTRL_EXT); ch1010832@1992: /* Relaxed ordering must be disabled to avoid a parity ch1010832@1992: * error crash in a PCI slot. */ ch1010832@1992: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; ch1010832@1992: ew32(CTRL_EXT, ctrl_ext); ch1010832@1992: } ch1010832@1992: ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. ch1010832@1992: * @hw: Struct containing variables accessed by shared code. ch1010832@1992: */ ch1010832@1992: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u16 eeprom_data; ch1010832@1992: s32 ret_val; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_adjust_serdes_amplitude"); ch1010832@1992: ch1010832@1992: if (hw->media_type != e1000_media_type_internal_serdes) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82545_rev_3: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, ch1010832@1992: &eeprom_data); ch1010832@1992: if (ret_val) { ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (eeprom_data != EEPROM_RESERVED_WORD) { ch1010832@1992: /* Adjust SERDES output amplitude only. */ ch1010832@1992: eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_setup_link - Configures flow control and link settings. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Determines which flow control settings to use. Calls the appropriate media- ch1010832@1992: * specific link configuration function. Configures the flow control settings. ch1010832@1992: * Assuming the adapter has a valid link partner, a valid link should be ch1010832@1992: * established. Assumes the hardware has previously been reset and the ch1010832@1992: * transmitter and receiver are not enabled. ch1010832@1992: */ ch1010832@1992: s32 e1000_setup_link(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl_ext; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 eeprom_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_setup_link"); ch1010832@1992: ch1010832@1992: /* Read and store word 0x0F of the EEPROM. This word contains bits ch1010832@1992: * that determine the hardware's default PAUSE (flow control) mode, ch1010832@1992: * a bit that determines whether the HW defaults to enabling or ch1010832@1992: * disabling auto-negotiation, and the direction of the ch1010832@1992: * SW defined pins. If there is no SW over-ride of the flow ch1010832@1992: * control setting, then the variable hw->fc will ch1010832@1992: * be initialized based on a value in the EEPROM. ch1010832@1992: */ ch1010832@1992: if (hw->fc == E1000_FC_DEFAULT) { ch1010832@1992: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, ch1010832@1992: 1, &eeprom_data); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("EEPROM Read Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) ch1010832@1992: hw->fc = E1000_FC_NONE; ch1010832@1992: else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == ch1010832@1992: EEPROM_WORD0F_ASM_DIR) ch1010832@1992: hw->fc = E1000_FC_TX_PAUSE; ch1010832@1992: else ch1010832@1992: hw->fc = E1000_FC_FULL; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* We want to save off the original Flow Control configuration just ch1010832@1992: * in case we get disconnected and then reconnected into a different ch1010832@1992: * hub or switch with different Flow Control capabilities. ch1010832@1992: */ ch1010832@1992: if (hw->mac_type == e1000_82542_rev2_0) ch1010832@1992: hw->fc &= (~E1000_FC_TX_PAUSE); ch1010832@1992: ch1010832@1992: if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) ch1010832@1992: hw->fc &= (~E1000_FC_RX_PAUSE); ch1010832@1992: ch1010832@1992: hw->original_fc = hw->fc; ch1010832@1992: ch1010832@1992: DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); ch1010832@1992: ch1010832@1992: /* Take the 4 bits from EEPROM word 0x0F that determine the initial ch1010832@1992: * polarity value for the SW controlled pins, and setup the ch1010832@1992: * Extended Device Control reg with that info. ch1010832@1992: * This is needed because one of the SW controlled pins is used for ch1010832@1992: * signal detection. So this should be done before e1000_setup_pcs_link() ch1010832@1992: * or e1000_phy_setup() is called. ch1010832@1992: */ ch1010832@1992: if (hw->mac_type == e1000_82543) { ch1010832@1992: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, ch1010832@1992: 1, &eeprom_data); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("EEPROM Read Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << ch1010832@1992: SWDPIO__EXT_SHIFT); ch1010832@1992: ew32(CTRL_EXT, ctrl_ext); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Call the necessary subroutine to configure the link. */ ch1010832@1992: ret_val = (hw->media_type == e1000_media_type_copper) ? ch1010832@1992: e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); ch1010832@1992: ch1010832@1992: /* Initialize the flow control address, type, and PAUSE timer ch1010832@1992: * registers to their default values. This is done even if flow ch1010832@1992: * control is disabled, because it does not hurt anything to ch1010832@1992: * initialize these registers. ch1010832@1992: */ ch1010832@1992: DEBUGOUT ch1010832@1992: ("Initializing the Flow Control address, type and timer regs\n"); ch1010832@1992: ch1010832@1992: ew32(FCT, FLOW_CONTROL_TYPE); ch1010832@1992: ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); ch1010832@1992: ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); ch1010832@1992: ch1010832@1992: ew32(FCTTV, hw->fc_pause_time); ch1010832@1992: ch1010832@1992: /* Set the flow control receive threshold registers. Normally, ch1010832@1992: * these registers will be set to a default threshold that may be ch1010832@1992: * adjusted later by the driver's runtime code. However, if the ch1010832@1992: * ability to transmit pause frames in not enabled, then these ch1010832@1992: * registers will be set to 0. ch1010832@1992: */ ch1010832@1992: if (!(hw->fc & E1000_FC_TX_PAUSE)) { ch1010832@1992: ew32(FCRTL, 0); ch1010832@1992: ew32(FCRTH, 0); ch1010832@1992: } else { ch1010832@1992: /* We need to set up the Receive Threshold high and low water marks ch1010832@1992: * as well as (optionally) enabling the transmission of XON frames. ch1010832@1992: */ ch1010832@1992: if (hw->fc_send_xon) { ch1010832@1992: ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); ch1010832@1992: ew32(FCRTH, hw->fc_high_water); ch1010832@1992: } else { ch1010832@1992: ew32(FCRTL, hw->fc_low_water); ch1010832@1992: ew32(FCRTH, hw->fc_high_water); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_setup_fiber_serdes_link - prepare fiber or serdes link ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Manipulates Physical Coding Sublayer functions in order to configure ch1010832@1992: * link. Assumes the hardware has been previously reset and the transmitter ch1010832@1992: * and receiver are not enabled. ch1010832@1992: */ ch1010832@1992: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: u32 status; ch1010832@1992: u32 txcw = 0; ch1010832@1992: u32 i; ch1010832@1992: u32 signal = 0; ch1010832@1992: s32 ret_val; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_setup_fiber_serdes_link"); ch1010832@1992: ch1010832@1992: /* On adapters with a MAC newer than 82544, SWDP 1 will be ch1010832@1992: * set when the optics detect a signal. On older adapters, it will be ch1010832@1992: * cleared when there is a signal. This applies to fiber media only. ch1010832@1992: * If we're on serdes media, adjust the output amplitude to value ch1010832@1992: * set in the EEPROM. ch1010832@1992: */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) ch1010832@1992: signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; ch1010832@1992: ch1010832@1992: ret_val = e1000_adjust_serdes_amplitude(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Take the link out of reset */ ch1010832@1992: ctrl &= ~(E1000_CTRL_LRST); ch1010832@1992: ch1010832@1992: /* Adjust VCO speed to improve BER performance */ ch1010832@1992: ret_val = e1000_set_vco_speed(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: e1000_config_collision_dist(hw); ch1010832@1992: ch1010832@1992: /* Check for a software override of the flow control settings, and setup ch1010832@1992: * the device accordingly. If auto-negotiation is enabled, then software ch1010832@1992: * will have to set the "PAUSE" bits to the correct value in the Tranmsit ch1010832@1992: * Config Word Register (TXCW) and re-start auto-negotiation. However, if ch1010832@1992: * auto-negotiation is disabled, then software will have to manually ch1010832@1992: * configure the two flow control enable bits in the CTRL register. ch1010832@1992: * ch1010832@1992: * The possible values of the "fc" parameter are: ch1010832@1992: * 0: Flow control is completely disabled ch1010832@1992: * 1: Rx flow control is enabled (we can receive pause frames, but ch1010832@1992: * not send pause frames). ch1010832@1992: * 2: Tx flow control is enabled (we can send pause frames but we do ch1010832@1992: * not support receiving pause frames). ch1010832@1992: * 3: Both Rx and TX flow control (symmetric) are enabled. ch1010832@1992: */ ch1010832@1992: switch (hw->fc) { ch1010832@1992: case E1000_FC_NONE: ch1010832@1992: /* Flow control is completely disabled by a software over-ride. */ ch1010832@1992: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); ch1010832@1992: break; ch1010832@1992: case E1000_FC_RX_PAUSE: ch1010832@1992: /* RX Flow control is enabled and TX Flow control is disabled by a ch1010832@1992: * software over-ride. Since there really isn't a way to advertise ch1010832@1992: * that we are capable of RX Pause ONLY, we will advertise that we ch1010832@1992: * support both symmetric and asymmetric RX PAUSE. Later, we will ch1010832@1992: * disable the adapter's ability to send PAUSE frames. ch1010832@1992: */ ch1010832@1992: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ch1010832@1992: break; ch1010832@1992: case E1000_FC_TX_PAUSE: ch1010832@1992: /* TX Flow control is enabled, and RX Flow control is disabled, by a ch1010832@1992: * software over-ride. ch1010832@1992: */ ch1010832@1992: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); ch1010832@1992: break; ch1010832@1992: case E1000_FC_FULL: ch1010832@1992: /* Flow control (both RX and TX) is enabled by a software over-ride. */ ch1010832@1992: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: DEBUGOUT("Flow control param set incorrectly\n"); ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Since auto-negotiation is enabled, take the link out of reset (the link ch1010832@1992: * will be in reset, because we previously reset the chip). This will ch1010832@1992: * restart auto-negotiation. If auto-negotiation is successful then the ch1010832@1992: * link-up status bit will be set and the flow control enable bits (RFCE ch1010832@1992: * and TFCE) will be set according to their negotiated value. ch1010832@1992: */ ch1010832@1992: DEBUGOUT("Auto-negotiation enabled\n"); ch1010832@1992: ch1010832@1992: ew32(TXCW, txcw); ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: hw->txcw = txcw; ch1010832@1992: msleep(1); ch1010832@1992: ch1010832@1992: /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" ch1010832@1992: * indication in the Device Status Register. Time-out if a link isn't ch1010832@1992: * seen in 500 milliseconds seconds (Auto-negotiation should complete in ch1010832@1992: * less than 500 milliseconds even if the other end is doing it in SW). ch1010832@1992: * For internal serdes, we just assume a signal is present, then poll. ch1010832@1992: */ ch1010832@1992: if (hw->media_type == e1000_media_type_internal_serdes || ch1010832@1992: (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { ch1010832@1992: DEBUGOUT("Looking for Link\n"); ch1010832@1992: for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { ch1010832@1992: msleep(10); ch1010832@1992: status = er32(STATUS); ch1010832@1992: if (status & E1000_STATUS_LU) ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: if (i == (LINK_UP_TIMEOUT / 10)) { ch1010832@1992: DEBUGOUT("Never got a valid link from auto-neg!!!\n"); ch1010832@1992: hw->autoneg_failed = 1; ch1010832@1992: /* AutoNeg failed to achieve a link, so we'll call ch1010832@1992: * e1000_check_for_link. This routine will force the link up if ch1010832@1992: * we detect a signal. This will allow us to communicate with ch1010832@1992: * non-autonegotiating link partners. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_check_for_link(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error while checking for link\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: hw->autoneg_failed = 0; ch1010832@1992: } else { ch1010832@1992: hw->autoneg_failed = 0; ch1010832@1992: DEBUGOUT("Valid Link Found\n"); ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: DEBUGOUT("No Signal Detected\n"); ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_copper_link_preconfig - early configuration for copper ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Make sure we have a valid PHY and change PHY mode before link setup. ch1010832@1992: */ ch1010832@1992: static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_copper_link_preconfig"); ch1010832@1992: ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: /* With 82543, we need to force speed and duplex on the MAC equal to what ch1010832@1992: * the PHY speed and duplex configuration is. In addition, we need to ch1010832@1992: * perform a hardware reset on the PHY to take it out of reset. ch1010832@1992: */ ch1010832@1992: if (hw->mac_type > e1000_82543) { ch1010832@1992: ctrl |= E1000_CTRL_SLU; ch1010832@1992: ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: } else { ch1010832@1992: ctrl |= ch1010832@1992: (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: ret_val = e1000_phy_hw_reset(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Make sure we have a valid PHY */ ch1010832@1992: ret_val = e1000_detect_gig_phy(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error, did not detect valid phy.\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: DEBUGOUT1("Phy ID = %x \n", hw->phy_id); ch1010832@1992: ch1010832@1992: /* Set PHY to class A mode (if necessary) */ ch1010832@1992: ret_val = e1000_set_phy_mode(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82545_rev_3) || ch1010832@1992: (hw->mac_type == e1000_82546_rev_3)) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@1992: phy_data |= 0x00000008; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->mac_type <= e1000_82543 || ch1010832@1992: hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || ch1010832@1992: hw->mac_type == e1000_82541_rev_2 ch1010832@1992: || hw->mac_type == e1000_82547_rev_2) ch1010832@1992: hw->phy_reset_disable = false; ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 led_ctrl; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_copper_link_igp_setup"); ch1010832@1992: ch1010832@1992: if (hw->phy_reset_disable) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: ret_val = e1000_phy_reset(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Resetting the PHY\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Wait 15ms for MAC to configure PHY from eeprom settings */ ch1010832@1992: msleep(15); ch1010832@1992: /* Configure activity LED after PHY reset */ ch1010832@1992: led_ctrl = er32(LEDCTL); ch1010832@1992: led_ctrl &= IGP_ACTIVITY_LED_MASK; ch1010832@1992: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ch1010832@1992: ew32(LEDCTL, led_ctrl); ch1010832@1992: ch1010832@1992: /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ ch1010832@1992: if (hw->phy_type == e1000_phy_igp) { ch1010832@1992: /* disable lplu d3 during driver init */ ch1010832@1992: ret_val = e1000_set_d3_lplu_state(hw, false); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Disabling LPLU D3\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Configure mdi-mdix settings */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@1992: hw->dsp_config_state = e1000_dsp_config_disabled; ch1010832@1992: /* Force MDI for earlier revs of the IGP PHY */ ch1010832@1992: phy_data &= ch1010832@1992: ~(IGP01E1000_PSCR_AUTO_MDIX | ch1010832@1992: IGP01E1000_PSCR_FORCE_MDI_MDIX); ch1010832@1992: hw->mdix = 1; ch1010832@1992: ch1010832@1992: } else { ch1010832@1992: hw->dsp_config_state = e1000_dsp_config_enabled; ch1010832@1992: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ch1010832@1992: ch1010832@1992: switch (hw->mdix) { ch1010832@1992: case 1: ch1010832@1992: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ch1010832@1992: break; ch1010832@1992: case 2: ch1010832@1992: phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; ch1010832@1992: break; ch1010832@1992: case 0: ch1010832@1992: default: ch1010832@1992: phy_data |= IGP01E1000_PSCR_AUTO_MDIX; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* set auto-master slave resolution settings */ ch1010832@1992: if (hw->autoneg) { ch1010832@1992: e1000_ms_type phy_ms_setting = hw->master_slave; ch1010832@1992: ch1010832@1992: if (hw->ffe_config_state == e1000_ffe_config_active) ch1010832@1992: hw->ffe_config_state = e1000_ffe_config_enabled; ch1010832@1992: ch1010832@1992: if (hw->dsp_config_state == e1000_dsp_config_activated) ch1010832@1992: hw->dsp_config_state = e1000_dsp_config_enabled; ch1010832@1992: ch1010832@1992: /* when autonegotiation advertisement is only 1000Mbps then we ch1010832@1992: * should disable SmartSpeed and enable Auto MasterSlave ch1010832@1992: * resolution as hardware default. */ ch1010832@1992: if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { ch1010832@1992: /* Disable SmartSpeed */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: /* Set auto Master/Slave resolution process */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: phy_data &= ~CR_1000T_MS_ENABLE; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* load defaults for future use */ ch1010832@1992: hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? ch1010832@1992: ((phy_data & CR_1000T_MS_VALUE) ? ch1010832@1992: e1000_ms_force_master : ch1010832@1992: e1000_ms_force_slave) : e1000_ms_auto; ch1010832@1992: ch1010832@1992: switch (phy_ms_setting) { ch1010832@1992: case e1000_ms_force_master: ch1010832@1992: phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); ch1010832@1992: break; ch1010832@1992: case e1000_ms_force_slave: ch1010832@1992: phy_data |= CR_1000T_MS_ENABLE; ch1010832@1992: phy_data &= ~(CR_1000T_MS_VALUE); ch1010832@1992: break; ch1010832@1992: case e1000_ms_auto: ch1010832@1992: phy_data &= ~CR_1000T_MS_ENABLE; ch1010832@1992: default: ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_copper_link_mgp_setup"); ch1010832@1992: ch1010832@1992: if (hw->phy_reset_disable) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: /* Enable CRS on TX. This must be set for half-duplex operation. */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ch1010832@1992: ch1010832@1992: /* Options: ch1010832@1992: * MDI/MDI-X = 0 (default) ch1010832@1992: * 0 - Auto for all speeds ch1010832@1992: * 1 - MDI mode ch1010832@1992: * 2 - MDI-X mode ch1010832@1992: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) ch1010832@1992: */ ch1010832@1992: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ch1010832@1992: ch1010832@1992: switch (hw->mdix) { ch1010832@1992: case 1: ch1010832@1992: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; ch1010832@1992: break; ch1010832@1992: case 2: ch1010832@1992: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; ch1010832@1992: break; ch1010832@1992: case 3: ch1010832@1992: phy_data |= M88E1000_PSCR_AUTO_X_1000T; ch1010832@1992: break; ch1010832@1992: case 0: ch1010832@1992: default: ch1010832@1992: phy_data |= M88E1000_PSCR_AUTO_X_MODE; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Options: ch1010832@1992: * disable_polarity_correction = 0 (default) ch1010832@1992: * Automatic Correction for Reversed Cable Polarity ch1010832@1992: * 0 - Disabled ch1010832@1992: * 1 - Enabled ch1010832@1992: */ ch1010832@1992: phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; ch1010832@1992: if (hw->disable_polarity_correction == 1) ch1010832@1992: phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (hw->phy_revision < M88E1011_I_REV_4) { ch1010832@1992: /* Force TX_CLK in the Extended PHY Specific Control Register ch1010832@1992: * to 25MHz clock. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= M88E1000_EPSCR_TX_CLK_25; ch1010832@1992: ch1010832@1992: if ((hw->phy_revision == E1000_REVISION_2) && ch1010832@1992: (hw->phy_id == M88E1111_I_PHY_ID)) { ch1010832@1992: /* Vidalia Phy, set the downshift counter to 5x */ ch1010832@1992: phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); ch1010832@1992: phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, ch1010832@1992: M88E1000_EXT_PHY_SPEC_CTRL, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } else { ch1010832@1992: /* Configure Master and Slave downshift values */ ch1010832@1992: phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | ch1010832@1992: M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); ch1010832@1992: phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | ch1010832@1992: M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); ch1010832@1992: ret_val = e1000_write_phy_reg(hw, ch1010832@1992: M88E1000_EXT_PHY_SPEC_CTRL, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* SW Reset the PHY so all changes take effect */ ch1010832@1992: ret_val = e1000_phy_reset(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Resetting the PHY\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_copper_link_autoneg - setup auto-neg ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Setup auto-negotiation and flow control advertisements, ch1010832@1992: * and then perform auto-negotiation. ch1010832@1992: */ ch1010832@1992: static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_copper_link_autoneg"); ch1010832@1992: ch1010832@1992: /* Perform some bounds checking on the hw->autoneg_advertised ch1010832@1992: * parameter. If this variable is zero, then set it to the default. ch1010832@1992: */ ch1010832@1992: hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; ch1010832@1992: ch1010832@1992: /* If autoneg_advertised is zero, we assume it was not defaulted ch1010832@1992: * by the calling code so we set to advertise full capability. ch1010832@1992: */ ch1010832@1992: if (hw->autoneg_advertised == 0) ch1010832@1992: hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; ch1010832@1992: ch1010832@1992: DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); ch1010832@1992: ret_val = e1000_phy_setup_autoneg(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Setting up Auto-Negotiation\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: DEBUGOUT("Restarting Auto-Neg\n"); ch1010832@1992: ch1010832@1992: /* Restart auto-negotiation by setting the Auto Neg Enable bit and ch1010832@1992: * the Auto Neg Restart bit in the PHY control register. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); ch1010832@1992: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Does the user want to wait for Auto-Neg to complete here, or ch1010832@1992: * check at a later time (for example, callback routine). ch1010832@1992: */ ch1010832@1992: if (hw->wait_autoneg_complete) { ch1010832@1992: ret_val = e1000_wait_autoneg(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Error while waiting for autoneg to complete\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: hw->get_link_status = true; ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_copper_link_postconfig - post link setup ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Config the MAC and the PHY after link is up. ch1010832@1992: * 1) Set up the MAC to the current PHY speed/duplex ch1010832@1992: * if we are on 82543. If we ch1010832@1992: * are on newer silicon, we only need to configure ch1010832@1992: * collision distance in the Transmit Control Register. ch1010832@1992: * 2) Set up flow control on the MAC to that established with ch1010832@1992: * the link partner. ch1010832@1992: * 3) Config DSP to improve Gigabit link quality for some PHY revisions. ch1010832@1992: */ ch1010832@1992: static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: DEBUGFUNC("e1000_copper_link_postconfig"); ch1010832@1992: ch1010832@1992: if (hw->mac_type >= e1000_82544) { ch1010832@1992: e1000_config_collision_dist(hw); ch1010832@1992: } else { ch1010832@1992: ret_val = e1000_config_mac_to_phy(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error configuring MAC to PHY settings\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ret_val = e1000_config_fc_after_link_up(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Configuring Flow Control\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Config DSP to improve Giga link quality */ ch1010832@1992: if (hw->phy_type == e1000_phy_igp) { ch1010832@1992: ret_val = e1000_config_dsp_after_link_change(hw, true); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Configuring DSP after link up\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_setup_copper_link - phy/speed/duplex setting ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Detects which PHY is present and sets up the speed and duplex ch1010832@1992: */ ch1010832@1992: static s32 e1000_setup_copper_link(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 i; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_setup_copper_link"); ch1010832@1992: ch1010832@1992: /* Check if it is a valid PHY and set PHY mode if necessary. */ ch1010832@1992: ret_val = e1000_copper_link_preconfig(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_igp) { ch1010832@1992: ret_val = e1000_copper_link_igp_setup(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } else if (hw->phy_type == e1000_phy_m88) { ch1010832@1992: ret_val = e1000_copper_link_mgp_setup(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->autoneg) { ch1010832@1992: /* Setup autoneg and flow control advertisement ch1010832@1992: * and perform autonegotiation */ ch1010832@1992: ret_val = e1000_copper_link_autoneg(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } else { ch1010832@1992: /* PHY will be set to 10H, 10F, 100H,or 100F ch1010832@1992: * depending on value from forced_speed_duplex. */ ch1010832@1992: DEBUGOUT("Forcing speed and duplex\n"); ch1010832@1992: ret_val = e1000_phy_force_speed_duplex(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Forcing Speed and Duplex\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Check link status. Wait up to 100 microseconds for link to become ch1010832@1992: * valid. ch1010832@1992: */ ch1010832@1992: for (i = 0; i < 10; i++) { ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (phy_data & MII_SR_LINK_STATUS) { ch1010832@1992: /* Config the MAC and PHY after link is up */ ch1010832@1992: ret_val = e1000_copper_link_postconfig(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: DEBUGOUT("Valid link established!!!\n"); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: udelay(10); ch1010832@1992: } ch1010832@1992: ch1010832@1992: DEBUGOUT("Unable to establish link!!!\n"); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_setup_autoneg - phy settings ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Configures PHY autoneg and flow control advertisement settings ch1010832@1992: */ ch1010832@1992: s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 mii_autoneg_adv_reg; ch1010832@1992: u16 mii_1000t_ctrl_reg; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_setup_autoneg"); ch1010832@1992: ch1010832@1992: /* Read the MII Auto-Neg Advertisement Register (Address 4). */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Read the MII 1000Base-T Control Register (Address 9). */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Need to parse both autoneg_advertised and fc and set up ch1010832@1992: * the appropriate PHY registers. First we will parse for ch1010832@1992: * autoneg_advertised software override. Since we can advertise ch1010832@1992: * a plethora of combinations, we need to check each bit ch1010832@1992: * individually. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: /* First we clear all the 10/100 mb speed bits in the Auto-Neg ch1010832@1992: * Advertisement Register (Address 4) and the 1000 mb speed bits in ch1010832@1992: * the 1000Base-T Control Register (Address 9). ch1010832@1992: */ ch1010832@1992: mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; ch1010832@1992: mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; ch1010832@1992: ch1010832@1992: DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); ch1010832@1992: ch1010832@1992: /* Do we want to advertise 10 Mb Half Duplex? */ ch1010832@1992: if (hw->autoneg_advertised & ADVERTISE_10_HALF) { ch1010832@1992: DEBUGOUT("Advertise 10mb Half duplex\n"); ch1010832@1992: mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Do we want to advertise 10 Mb Full Duplex? */ ch1010832@1992: if (hw->autoneg_advertised & ADVERTISE_10_FULL) { ch1010832@1992: DEBUGOUT("Advertise 10mb Full duplex\n"); ch1010832@1992: mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Do we want to advertise 100 Mb Half Duplex? */ ch1010832@1992: if (hw->autoneg_advertised & ADVERTISE_100_HALF) { ch1010832@1992: DEBUGOUT("Advertise 100mb Half duplex\n"); ch1010832@1992: mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Do we want to advertise 100 Mb Full Duplex? */ ch1010832@1992: if (hw->autoneg_advertised & ADVERTISE_100_FULL) { ch1010832@1992: DEBUGOUT("Advertise 100mb Full duplex\n"); ch1010832@1992: mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ ch1010832@1992: if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Advertise 1000mb Half duplex requested, request denied!\n"); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Do we want to advertise 1000 Mb Full Duplex? */ ch1010832@1992: if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { ch1010832@1992: DEBUGOUT("Advertise 1000mb Full duplex\n"); ch1010832@1992: mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Check for a software override of the flow control settings, and ch1010832@1992: * setup the PHY advertisement registers accordingly. If ch1010832@1992: * auto-negotiation is enabled, then software will have to set the ch1010832@1992: * "PAUSE" bits to the correct value in the Auto-Negotiation ch1010832@1992: * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. ch1010832@1992: * ch1010832@1992: * The possible values of the "fc" parameter are: ch1010832@1992: * 0: Flow control is completely disabled ch1010832@1992: * 1: Rx flow control is enabled (we can receive pause frames ch1010832@1992: * but not send pause frames). ch1010832@1992: * 2: Tx flow control is enabled (we can send pause frames ch1010832@1992: * but we do not support receiving pause frames). ch1010832@1992: * 3: Both Rx and TX flow control (symmetric) are enabled. ch1010832@1992: * other: No software override. The flow control configuration ch1010832@1992: * in the EEPROM is used. ch1010832@1992: */ ch1010832@1992: switch (hw->fc) { ch1010832@1992: case E1000_FC_NONE: /* 0 */ ch1010832@1992: /* Flow control (RX & TX) is completely disabled by a ch1010832@1992: * software over-ride. ch1010832@1992: */ ch1010832@1992: mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ch1010832@1992: break; ch1010832@1992: case E1000_FC_RX_PAUSE: /* 1 */ ch1010832@1992: /* RX Flow control is enabled, and TX Flow control is ch1010832@1992: * disabled, by a software over-ride. ch1010832@1992: */ ch1010832@1992: /* Since there really isn't a way to advertise that we are ch1010832@1992: * capable of RX Pause ONLY, we will advertise that we ch1010832@1992: * support both symmetric and asymmetric RX PAUSE. Later ch1010832@1992: * (in e1000_config_fc_after_link_up) we will disable the ch1010832@1992: *hw's ability to send PAUSE frames. ch1010832@1992: */ ch1010832@1992: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ch1010832@1992: break; ch1010832@1992: case E1000_FC_TX_PAUSE: /* 2 */ ch1010832@1992: /* TX Flow control is enabled, and RX Flow control is ch1010832@1992: * disabled, by a software over-ride. ch1010832@1992: */ ch1010832@1992: mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; ch1010832@1992: mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; ch1010832@1992: break; ch1010832@1992: case E1000_FC_FULL: /* 3 */ ch1010832@1992: /* Flow control (both RX and TX) is enabled by a software ch1010832@1992: * over-ride. ch1010832@1992: */ ch1010832@1992: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: DEBUGOUT("Flow control param set incorrectly\n"); ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_force_speed_duplex - force link settings ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Force PHY speed and duplex settings to hw->forced_speed_duplex ch1010832@1992: */ ch1010832@1992: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 mii_ctrl_reg; ch1010832@1992: u16 mii_status_reg; ch1010832@1992: u16 phy_data; ch1010832@1992: u16 i; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_force_speed_duplex"); ch1010832@1992: ch1010832@1992: /* Turn off Flow control if we are forcing speed and duplex. */ ch1010832@1992: hw->fc = E1000_FC_NONE; ch1010832@1992: ch1010832@1992: DEBUGOUT1("hw->fc = %d\n", hw->fc); ch1010832@1992: ch1010832@1992: /* Read the Device Control Register. */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ ch1010832@1992: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ch1010832@1992: ctrl &= ~(DEVICE_SPEED_MASK); ch1010832@1992: ch1010832@1992: /* Clear the Auto Speed Detect Enable bit. */ ch1010832@1992: ctrl &= ~E1000_CTRL_ASDE; ch1010832@1992: ch1010832@1992: /* Read the MII Control Register. */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* We need to disable autoneg in order to force link and duplex. */ ch1010832@1992: ch1010832@1992: mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; ch1010832@1992: ch1010832@1992: /* Are we forcing Full or Half Duplex? */ ch1010832@1992: if (hw->forced_speed_duplex == e1000_100_full || ch1010832@1992: hw->forced_speed_duplex == e1000_10_full) { ch1010832@1992: /* We want to force full duplex so we SET the full duplex bits in the ch1010832@1992: * Device and MII Control Registers. ch1010832@1992: */ ch1010832@1992: ctrl |= E1000_CTRL_FD; ch1010832@1992: mii_ctrl_reg |= MII_CR_FULL_DUPLEX; ch1010832@1992: DEBUGOUT("Full Duplex\n"); ch1010832@1992: } else { ch1010832@1992: /* We want to force half duplex so we CLEAR the full duplex bits in ch1010832@1992: * the Device and MII Control Registers. ch1010832@1992: */ ch1010832@1992: ctrl &= ~E1000_CTRL_FD; ch1010832@1992: mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; ch1010832@1992: DEBUGOUT("Half Duplex\n"); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Are we forcing 100Mbps??? */ ch1010832@1992: if (hw->forced_speed_duplex == e1000_100_full || ch1010832@1992: hw->forced_speed_duplex == e1000_100_half) { ch1010832@1992: /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ ch1010832@1992: ctrl |= E1000_CTRL_SPD_100; ch1010832@1992: mii_ctrl_reg |= MII_CR_SPEED_100; ch1010832@1992: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); ch1010832@1992: DEBUGOUT("Forcing 100mb "); ch1010832@1992: } else { ch1010832@1992: /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ ch1010832@1992: ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); ch1010832@1992: mii_ctrl_reg |= MII_CR_SPEED_10; ch1010832@1992: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); ch1010832@1992: DEBUGOUT("Forcing 10mb "); ch1010832@1992: } ch1010832@1992: ch1010832@1992: e1000_config_collision_dist(hw); ch1010832@1992: ch1010832@1992: /* Write the configured values back to the Device Control Reg. */ ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_m88) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI ch1010832@1992: * forced whenever speed are duplex are forced. ch1010832@1992: */ ch1010832@1992: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); ch1010832@1992: ch1010832@1992: /* Need to reset the PHY or these changes will be ignored */ ch1010832@1992: mii_ctrl_reg |= MII_CR_RESET; ch1010832@1992: ch1010832@1992: /* Disable MDI-X support for 10/100 */ ch1010832@1992: } else { ch1010832@1992: /* Clear Auto-Crossover to force MDI manually. IGP requires MDI ch1010832@1992: * forced whenever speed or duplex are forced. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; ch1010832@1992: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Write back the modified PHY MII control register. */ ch1010832@1992: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: udelay(1); ch1010832@1992: ch1010832@1992: /* The wait_autoneg_complete flag may be a little misleading here. ch1010832@1992: * Since we are forcing speed and duplex, Auto-Neg is not enabled. ch1010832@1992: * But we do want to delay for a period while forcing only so we ch1010832@1992: * don't generate false No Link messages. So we will wait here ch1010832@1992: * only if the user has set wait_autoneg_complete to 1, which is ch1010832@1992: * the default. ch1010832@1992: */ ch1010832@1992: if (hw->wait_autoneg_complete) { ch1010832@1992: /* We will wait for autoneg to complete. */ ch1010832@1992: DEBUGOUT("Waiting for forced speed/duplex link.\n"); ch1010832@1992: mii_status_reg = 0; ch1010832@1992: ch1010832@1992: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ ch1010832@1992: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@1992: /* Read the MII Status Register and wait for Auto-Neg Complete bit ch1010832@1992: * to be set. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (mii_status_reg & MII_SR_LINK_STATUS) ch1010832@1992: break; ch1010832@1992: msleep(100); ch1010832@1992: } ch1010832@1992: if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { ch1010832@1992: /* We didn't get link. Reset the DSP and wait again for link. */ ch1010832@1992: ret_val = e1000_phy_reset_dsp(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error Resetting PHY DSP\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: /* This loop will early-out if the link condition has been met. */ ch1010832@1992: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@1992: if (mii_status_reg & MII_SR_LINK_STATUS) ch1010832@1992: break; ch1010832@1992: msleep(100); ch1010832@1992: /* Read the MII Status Register and wait for Auto-Neg Complete bit ch1010832@1992: * to be set. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_m88) { ch1010832@1992: /* Because we reset the PHY above, we need to re-force TX_CLK in the ch1010832@1992: * Extended PHY Specific Control Register to 25MHz clock. This value ch1010832@1992: * defaults back to a 2.5MHz clock when the PHY is reset. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= M88E1000_EPSCR_TX_CLK_25; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* In addition, because of the s/w reset above, we need to enable CRS on ch1010832@1992: * TX. This must be set for both full and half duplex operation. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) ch1010832@1992: && (!hw->autoneg) ch1010832@1992: && (hw->forced_speed_duplex == e1000_10_full ch1010832@1992: || hw->forced_speed_duplex == e1000_10_half)) { ch1010832@1992: ret_val = e1000_polarity_reversal_workaround(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_config_collision_dist - set collision distance register ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Sets the collision distance in the Transmit Control register. ch1010832@1992: * Link should have been established previously. Reads the speed and duplex ch1010832@1992: * information from the Device Status register. ch1010832@1992: */ ch1010832@1992: void e1000_config_collision_dist(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 tctl, coll_dist; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_config_collision_dist"); ch1010832@1992: ch1010832@1992: if (hw->mac_type < e1000_82543) ch1010832@1992: coll_dist = E1000_COLLISION_DISTANCE_82542; ch1010832@1992: else ch1010832@1992: coll_dist = E1000_COLLISION_DISTANCE; ch1010832@1992: ch1010832@1992: tctl = er32(TCTL); ch1010832@1992: ch1010832@1992: tctl &= ~E1000_TCTL_COLD; ch1010832@1992: tctl |= coll_dist << E1000_COLD_SHIFT; ch1010832@1992: ch1010832@1992: ew32(TCTL, tctl); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_config_mac_to_phy - sync phy and mac settings ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @mii_reg: data to write to the MII control register ch1010832@1992: * ch1010832@1992: * Sets MAC speed and duplex settings to reflect the those in the PHY ch1010832@1992: * The contents of the PHY register containing the needed information need to ch1010832@1992: * be passed in. ch1010832@1992: */ ch1010832@1992: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_config_mac_to_phy"); ch1010832@1992: ch1010832@1992: /* 82544 or newer MAC, Auto Speed Detection takes care of ch1010832@1992: * MAC speed/duplex configuration.*/ ch1010832@1992: if (hw->mac_type >= e1000_82544) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: /* Read the Device Control Register and set the bits to Force Speed ch1010832@1992: * and Duplex. ch1010832@1992: */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); ch1010832@1992: ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); ch1010832@1992: ch1010832@1992: /* Set up duplex in the Device Control and Transmit Control ch1010832@1992: * registers depending on negotiated values. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (phy_data & M88E1000_PSSR_DPLX) ch1010832@1992: ctrl |= E1000_CTRL_FD; ch1010832@1992: else ch1010832@1992: ctrl &= ~E1000_CTRL_FD; ch1010832@1992: ch1010832@1992: e1000_config_collision_dist(hw); ch1010832@1992: ch1010832@1992: /* Set up speed in the Device Control register depending on ch1010832@1992: * negotiated values. ch1010832@1992: */ ch1010832@1992: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) ch1010832@1992: ctrl |= E1000_CTRL_SPD_1000; ch1010832@1992: else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) ch1010832@1992: ctrl |= E1000_CTRL_SPD_100; ch1010832@1992: ch1010832@1992: /* Write the configured values back to the Device Control Reg. */ ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_force_mac_fc - force flow control settings ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Forces the MAC's flow control settings. ch1010832@1992: * Sets the TFCE and RFCE bits in the device control register to reflect ch1010832@1992: * the adapter settings. TFCE and RFCE need to be explicitly set by ch1010832@1992: * software when a Copper PHY is used because autonegotiation is managed ch1010832@1992: * by the PHY rather than the MAC. Software must also configure these ch1010832@1992: * bits when link is forced on a fiber connection. ch1010832@1992: */ ch1010832@1992: s32 e1000_force_mac_fc(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_force_mac_fc"); ch1010832@1992: ch1010832@1992: /* Get the current configuration of the Device Control Register */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: /* Because we didn't get link via the internal auto-negotiation ch1010832@1992: * mechanism (we either forced link or we got link via PHY ch1010832@1992: * auto-neg), we have to manually enable/disable transmit an ch1010832@1992: * receive flow control. ch1010832@1992: * ch1010832@1992: * The "Case" statement below enables/disable flow control ch1010832@1992: * according to the "hw->fc" parameter. ch1010832@1992: * ch1010832@1992: * The possible values of the "fc" parameter are: ch1010832@1992: * 0: Flow control is completely disabled ch1010832@1992: * 1: Rx flow control is enabled (we can receive pause ch1010832@1992: * frames but not send pause frames). ch1010832@1992: * 2: Tx flow control is enabled (we can send pause frames ch1010832@1992: * frames but we do not receive pause frames). ch1010832@1992: * 3: Both Rx and TX flow control (symmetric) is enabled. ch1010832@1992: * other: No other values should be possible at this point. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: switch (hw->fc) { ch1010832@1992: case E1000_FC_NONE: ch1010832@1992: ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); ch1010832@1992: break; ch1010832@1992: case E1000_FC_RX_PAUSE: ch1010832@1992: ctrl &= (~E1000_CTRL_TFCE); ch1010832@1992: ctrl |= E1000_CTRL_RFCE; ch1010832@1992: break; ch1010832@1992: case E1000_FC_TX_PAUSE: ch1010832@1992: ctrl &= (~E1000_CTRL_RFCE); ch1010832@1992: ctrl |= E1000_CTRL_TFCE; ch1010832@1992: break; ch1010832@1992: case E1000_FC_FULL: ch1010832@1992: ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: DEBUGOUT("Flow control param set incorrectly\n"); ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Disable TX Flow Control for 82542 (rev 2.0) */ ch1010832@1992: if (hw->mac_type == e1000_82542_rev2_0) ch1010832@1992: ctrl &= (~E1000_CTRL_TFCE); ch1010832@1992: ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_config_fc_after_link_up - configure flow control after autoneg ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Configures flow control settings after link is established ch1010832@1992: * Should be called immediately after a valid link has been established. ch1010832@1992: * Forces MAC flow control settings if link was forced. When in MII/GMII mode ch1010832@1992: * and autonegotiation is enabled, the MAC flow control settings will be set ch1010832@1992: * based on the flow control negotiated by the PHY. In TBI mode, the TFCE ch1010832@1992: * and RFCE bits will be automatically set to the negotiated flow control mode. ch1010832@1992: */ ch1010832@1992: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 mii_status_reg; ch1010832@1992: u16 mii_nway_adv_reg; ch1010832@1992: u16 mii_nway_lp_ability_reg; ch1010832@1992: u16 speed; ch1010832@1992: u16 duplex; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_config_fc_after_link_up"); ch1010832@1992: ch1010832@1992: /* Check for the case where we have fiber media and auto-neg failed ch1010832@1992: * so we had to force link. In this case, we need to force the ch1010832@1992: * configuration of the MAC to match the "fc" parameter. ch1010832@1992: */ ch1010832@1992: if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ch1010832@1992: || ((hw->media_type == e1000_media_type_internal_serdes) ch1010832@1992: && (hw->autoneg_failed)) ch1010832@1992: || ((hw->media_type == e1000_media_type_copper) ch1010832@1992: && (!hw->autoneg))) { ch1010832@1992: ret_val = e1000_force_mac_fc(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error forcing flow control settings\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Check for the case where we have copper media and auto-neg is ch1010832@1992: * enabled. In this case, we need to check and see if Auto-Neg ch1010832@1992: * has completed, and if so, how the PHY and link partner has ch1010832@1992: * flow control configured. ch1010832@1992: */ ch1010832@1992: if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { ch1010832@1992: /* Read the MII Status Register and check to see if AutoNeg ch1010832@1992: * has completed. We read this twice because this reg has ch1010832@1992: * some "sticky" (latched) bits. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { ch1010832@1992: /* The AutoNeg process has completed, so we now need to ch1010832@1992: * read both the Auto Negotiation Advertisement Register ch1010832@1992: * (Address 4) and the Auto_Negotiation Base Page Ability ch1010832@1992: * Register (Address 5) to determine how flow control was ch1010832@1992: * negotiated. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, ch1010832@1992: &mii_nway_adv_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, ch1010832@1992: &mii_nway_lp_ability_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Two bits in the Auto Negotiation Advertisement Register ch1010832@1992: * (Address 4) and two bits in the Auto Negotiation Base ch1010832@1992: * Page Ability Register (Address 5) determine flow control ch1010832@1992: * for both the PHY and the link partner. The following ch1010832@1992: * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, ch1010832@1992: * 1999, describes these PAUSE resolution bits and how flow ch1010832@1992: * control is determined based upon these settings. ch1010832@1992: * NOTE: DC = Don't Care ch1010832@1992: * ch1010832@1992: * LOCAL DEVICE | LINK PARTNER ch1010832@1992: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution ch1010832@1992: *-------|---------|-------|---------|-------------------- ch1010832@1992: * 0 | 0 | DC | DC | E1000_FC_NONE ch1010832@1992: * 0 | 1 | 0 | DC | E1000_FC_NONE ch1010832@1992: * 0 | 1 | 1 | 0 | E1000_FC_NONE ch1010832@1992: * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE ch1010832@1992: * 1 | 0 | 0 | DC | E1000_FC_NONE ch1010832@1992: * 1 | DC | 1 | DC | E1000_FC_FULL ch1010832@1992: * 1 | 1 | 0 | 0 | E1000_FC_NONE ch1010832@1992: * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE ch1010832@1992: * ch1010832@1992: */ ch1010832@1992: /* Are both PAUSE bits set to 1? If so, this implies ch1010832@1992: * Symmetric Flow Control is enabled at both ends. The ch1010832@1992: * ASM_DIR bits are irrelevant per the spec. ch1010832@1992: * ch1010832@1992: * For Symmetric Flow Control: ch1010832@1992: * ch1010832@1992: * LOCAL DEVICE | LINK PARTNER ch1010832@1992: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ch1010832@1992: *-------|---------|-------|---------|-------------------- ch1010832@1992: * 1 | DC | 1 | DC | E1000_FC_FULL ch1010832@1992: * ch1010832@1992: */ ch1010832@1992: if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ch1010832@1992: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { ch1010832@1992: /* Now we need to check if the user selected RX ONLY ch1010832@1992: * of pause frames. In this case, we had to advertise ch1010832@1992: * FULL flow control because we could not advertise RX ch1010832@1992: * ONLY. Hence, we must now check to see if we need to ch1010832@1992: * turn OFF the TRANSMISSION of PAUSE frames. ch1010832@1992: */ ch1010832@1992: if (hw->original_fc == E1000_FC_FULL) { ch1010832@1992: hw->fc = E1000_FC_FULL; ch1010832@1992: DEBUGOUT("Flow Control = FULL.\n"); ch1010832@1992: } else { ch1010832@1992: hw->fc = E1000_FC_RX_PAUSE; ch1010832@1992: DEBUGOUT ch1010832@1992: ("Flow Control = RX PAUSE frames only.\n"); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: /* For receiving PAUSE frames ONLY. ch1010832@1992: * ch1010832@1992: * LOCAL DEVICE | LINK PARTNER ch1010832@1992: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ch1010832@1992: *-------|---------|-------|---------|-------------------- ch1010832@1992: * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE ch1010832@1992: * ch1010832@1992: */ ch1010832@1992: else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && ch1010832@1992: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ch1010832@1992: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ch1010832@1992: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) ch1010832@1992: { ch1010832@1992: hw->fc = E1000_FC_TX_PAUSE; ch1010832@1992: DEBUGOUT ch1010832@1992: ("Flow Control = TX PAUSE frames only.\n"); ch1010832@1992: } ch1010832@1992: /* For transmitting PAUSE frames ONLY. ch1010832@1992: * ch1010832@1992: * LOCAL DEVICE | LINK PARTNER ch1010832@1992: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result ch1010832@1992: *-------|---------|-------|---------|-------------------- ch1010832@1992: * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE ch1010832@1992: * ch1010832@1992: */ ch1010832@1992: else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && ch1010832@1992: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && ch1010832@1992: !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && ch1010832@1992: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) ch1010832@1992: { ch1010832@1992: hw->fc = E1000_FC_RX_PAUSE; ch1010832@1992: DEBUGOUT ch1010832@1992: ("Flow Control = RX PAUSE frames only.\n"); ch1010832@1992: } ch1010832@1992: /* Per the IEEE spec, at this point flow control should be ch1010832@1992: * disabled. However, we want to consider that we could ch1010832@1992: * be connected to a legacy switch that doesn't advertise ch1010832@1992: * desired flow control, but can be forced on the link ch1010832@1992: * partner. So if we advertised no flow control, that is ch1010832@1992: * what we will resolve to. If we advertised some kind of ch1010832@1992: * receive capability (Rx Pause Only or Full Flow Control) ch1010832@1992: * and the link partner advertised none, we will configure ch1010832@1992: * ourselves to enable Rx Flow Control only. We can do ch1010832@1992: * this safely for two reasons: If the link partner really ch1010832@1992: * didn't want flow control enabled, and we enable Rx, no ch1010832@1992: * harm done since we won't be receiving any PAUSE frames ch1010832@1992: * anyway. If the intent on the link partner was to have ch1010832@1992: * flow control enabled, then by us enabling RX only, we ch1010832@1992: * can at least receive pause frames and process them. ch1010832@1992: * This is a good idea because in most cases, since we are ch1010832@1992: * predominantly a server NIC, more times than not we will ch1010832@1992: * be asked to delay transmission of packets than asking ch1010832@1992: * our link partner to pause transmission of frames. ch1010832@1992: */ ch1010832@1992: else if ((hw->original_fc == E1000_FC_NONE || ch1010832@1992: hw->original_fc == E1000_FC_TX_PAUSE) || ch1010832@1992: hw->fc_strict_ieee) { ch1010832@1992: hw->fc = E1000_FC_NONE; ch1010832@1992: DEBUGOUT("Flow Control = NONE.\n"); ch1010832@1992: } else { ch1010832@1992: hw->fc = E1000_FC_RX_PAUSE; ch1010832@1992: DEBUGOUT ch1010832@1992: ("Flow Control = RX PAUSE frames only.\n"); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Now we need to do one last check... If we auto- ch1010832@1992: * negotiated to HALF DUPLEX, flow control should not be ch1010832@1992: * enabled per IEEE 802.3 spec. ch1010832@1992: */ ch1010832@1992: ret_val = ch1010832@1992: e1000_get_speed_and_duplex(hw, &speed, &duplex); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Error getting link speed and duplex\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (duplex == HALF_DUPLEX) ch1010832@1992: hw->fc = E1000_FC_NONE; ch1010832@1992: ch1010832@1992: /* Now we call a subroutine to actually force the MAC ch1010832@1992: * controller to use the correct flow control settings. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_force_mac_fc(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Error forcing flow control settings\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Copper PHY and Auto Neg has not completed.\n"); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_check_for_serdes_link_generic - Check for link (Serdes) ch1010832@1992: * @hw: pointer to the HW structure ch1010832@1992: * ch1010832@1992: * Checks for link up on the hardware. If link is not up and we have ch1010832@1992: * a signal, then we need to force link up. ch1010832@1992: */ ch1010832@1992: static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 rxcw; ch1010832@1992: u32 ctrl; ch1010832@1992: u32 status; ch1010832@1992: s32 ret_val = E1000_SUCCESS; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_check_for_serdes_link_generic"); ch1010832@1992: ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: status = er32(STATUS); ch1010832@1992: rxcw = er32(RXCW); ch1010832@1992: ch1010832@1992: /* ch1010832@1992: * If we don't have link (auto-negotiation failed or link partner ch1010832@1992: * cannot auto-negotiate), and our link partner is not trying to ch1010832@1992: * auto-negotiate with us (we are receiving idles or data), ch1010832@1992: * we need to force link up. We also need to give auto-negotiation ch1010832@1992: * time to complete. ch1010832@1992: */ ch1010832@1992: /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ ch1010832@1992: if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { ch1010832@1992: if (hw->autoneg_failed == 0) { ch1010832@1992: hw->autoneg_failed = 1; ch1010832@1992: goto out; ch1010832@1992: } ch1010832@1992: DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); ch1010832@1992: ch1010832@1992: /* Disable auto-negotiation in the TXCW register */ ch1010832@1992: ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); ch1010832@1992: ch1010832@1992: /* Force link-up and also force full-duplex. */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: ch1010832@1992: /* Configure Flow Control after forcing link up. */ ch1010832@1992: ret_val = e1000_config_fc_after_link_up(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error configuring flow control\n"); ch1010832@1992: goto out; ch1010832@1992: } ch1010832@1992: } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { ch1010832@1992: /* ch1010832@1992: * If we are forcing link and we are receiving /C/ ordered ch1010832@1992: * sets, re-enable auto-negotiation in the TXCW register ch1010832@1992: * and disable forced link in the Device Control register ch1010832@1992: * in an attempt to auto-negotiate with our link partner. ch1010832@1992: */ ch1010832@1992: DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); ch1010832@1992: ew32(TXCW, hw->txcw); ch1010832@1992: ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); ch1010832@1992: ch1010832@1992: hw->serdes_has_link = true; ch1010832@1992: } else if (!(E1000_TXCW_ANE & er32(TXCW))) { ch1010832@1992: /* ch1010832@1992: * If we force link for non-auto-negotiation switch, check ch1010832@1992: * link status based on MAC synchronization for internal ch1010832@1992: * serdes media type. ch1010832@1992: */ ch1010832@1992: /* SYNCH bit and IV bit are sticky. */ ch1010832@1992: udelay(10); ch1010832@1992: rxcw = er32(RXCW); ch1010832@1992: if (rxcw & E1000_RXCW_SYNCH) { ch1010832@1992: if (!(rxcw & E1000_RXCW_IV)) { ch1010832@1992: hw->serdes_has_link = true; ch1010832@1992: DEBUGOUT("SERDES: Link up - forced.\n"); ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: hw->serdes_has_link = false; ch1010832@1992: DEBUGOUT("SERDES: Link down - force failed.\n"); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (E1000_TXCW_ANE & er32(TXCW)) { ch1010832@1992: status = er32(STATUS); ch1010832@1992: if (status & E1000_STATUS_LU) { ch1010832@1992: /* SYNCH bit and IV bit are sticky, so reread rxcw. */ ch1010832@1992: udelay(10); ch1010832@1992: rxcw = er32(RXCW); ch1010832@1992: if (rxcw & E1000_RXCW_SYNCH) { ch1010832@1992: if (!(rxcw & E1000_RXCW_IV)) { ch1010832@1992: hw->serdes_has_link = true; ch1010832@1992: DEBUGOUT("SERDES: Link up - autoneg " ch1010832@1992: "completed successfully.\n"); ch1010832@1992: } else { ch1010832@1992: hw->serdes_has_link = false; ch1010832@1992: DEBUGOUT("SERDES: Link down - invalid" ch1010832@1992: "codewords detected in autoneg.\n"); ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: hw->serdes_has_link = false; ch1010832@1992: DEBUGOUT("SERDES: Link down - no sync.\n"); ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: hw->serdes_has_link = false; ch1010832@1992: DEBUGOUT("SERDES: Link down - autoneg failed\n"); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: out: ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_check_for_link ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Checks to see if the link status of the hardware has changed. ch1010832@1992: * Called by any function that needs to check the link status of the adapter. ch1010832@1992: */ ch1010832@1992: s32 e1000_check_for_link(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 rxcw = 0; ch1010832@1992: u32 ctrl; ch1010832@1992: u32 status; ch1010832@1992: u32 rctl; ch1010832@1992: u32 icr; ch1010832@1992: u32 signal = 0; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_check_for_link"); ch1010832@1992: ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: status = er32(STATUS); ch1010832@1992: ch1010832@1992: /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be ch1010832@1992: * set when the optics detect a signal. On older adapters, it will be ch1010832@1992: * cleared when there is a signal. This applies to fiber media only. ch1010832@1992: */ ch1010832@1992: if ((hw->media_type == e1000_media_type_fiber) || ch1010832@1992: (hw->media_type == e1000_media_type_internal_serdes)) { ch1010832@1992: rxcw = er32(RXCW); ch1010832@1992: ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) { ch1010832@1992: signal = ch1010832@1992: (hw->mac_type > ch1010832@1992: e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; ch1010832@1992: if (status & E1000_STATUS_LU) ch1010832@1992: hw->get_link_status = false; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* If we have a copper PHY then we only want to go out to the PHY ch1010832@1992: * registers to see if Auto-Neg has completed and/or if our link ch1010832@1992: * status has changed. The get_link_status flag will be set if we ch1010832@1992: * receive a Link Status Change interrupt or we have Rx Sequence ch1010832@1992: * Errors. ch1010832@1992: */ ch1010832@1992: if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { ch1010832@1992: /* First we want to see if the MII Status Register reports ch1010832@1992: * link. If so, then we want to get the current speed/duplex ch1010832@1992: * of the PHY. ch1010832@1992: * Read the register twice since the link bit is sticky. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (phy_data & MII_SR_LINK_STATUS) { ch1010832@1992: hw->get_link_status = false; ch1010832@1992: /* Check if there was DownShift, must be checked immediately after ch1010832@1992: * link-up */ ch1010832@1992: e1000_check_downshift(hw); ch1010832@1992: ch1010832@1992: /* If we are on 82544 or 82543 silicon and speed/duplex ch1010832@1992: * are forced to 10H or 10F, then we will implement the polarity ch1010832@1992: * reversal workaround. We disable interrupts first, and upon ch1010832@1992: * returning, place the devices interrupt state to its previous ch1010832@1992: * value except for the link status change interrupt which will ch1010832@1992: * happen due to the execution of this workaround. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82544 ch1010832@1992: || hw->mac_type == e1000_82543) && (!hw->autoneg) ch1010832@1992: && (hw->forced_speed_duplex == e1000_10_full ch1010832@1992: || hw->forced_speed_duplex == e1000_10_half)) { ch1010832@1992: ew32(IMC, 0xffffffff); ch1010832@1992: ret_val = ch1010832@1992: e1000_polarity_reversal_workaround(hw); ch1010832@1992: icr = er32(ICR); ch1010832@1992: ew32(ICS, (icr & ~E1000_ICS_LSC)); ch1010832@1992: ew32(IMS, IMS_ENABLE_MASK); ch1010832@1992: } ch1010832@1992: ch1010832@1992: } else { ch1010832@1992: /* No link detected */ ch1010832@1992: e1000_config_dsp_after_link_change(hw, false); ch1010832@1992: return 0; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* If we are forcing speed/duplex, then we simply return since ch1010832@1992: * we have already determined whether we have link or not. ch1010832@1992: */ ch1010832@1992: if (!hw->autoneg) ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: ch1010832@1992: /* optimize the dsp settings for the igp phy */ ch1010832@1992: e1000_config_dsp_after_link_change(hw, true); ch1010832@1992: ch1010832@1992: /* We have a M88E1000 PHY and Auto-Neg is enabled. If we ch1010832@1992: * have Si on board that is 82544 or newer, Auto ch1010832@1992: * Speed Detection takes care of MAC speed/duplex ch1010832@1992: * configuration. So we only need to configure Collision ch1010832@1992: * Distance in the MAC. Otherwise, we need to force ch1010832@1992: * speed/duplex on the MAC to the current PHY speed/duplex ch1010832@1992: * settings. ch1010832@1992: */ ch1010832@1992: if (hw->mac_type >= e1000_82544) ch1010832@1992: e1000_config_collision_dist(hw); ch1010832@1992: else { ch1010832@1992: ret_val = e1000_config_mac_to_phy(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Error configuring MAC to PHY settings\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Configure Flow Control now that Auto-Neg has completed. First, we ch1010832@1992: * need to restore the desired flow control settings because we may ch1010832@1992: * have had to re-autoneg with a different link partner. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_config_fc_after_link_up(hw); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error configuring flow control\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* At this point we know that we are on copper and we have ch1010832@1992: * auto-negotiated link. These are conditions for checking the link ch1010832@1992: * partner capability register. We use the link speed to determine if ch1010832@1992: * TBI compatibility needs to be turned on or off. If the link is not ch1010832@1992: * at gigabit speed, then TBI compatibility is not needed. If we are ch1010832@1992: * at gigabit speed, we turn on TBI compatibility. ch1010832@1992: */ ch1010832@1992: if (hw->tbi_compatibility_en) { ch1010832@1992: u16 speed, duplex; ch1010832@1992: ret_val = ch1010832@1992: e1000_get_speed_and_duplex(hw, &speed, &duplex); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT ch1010832@1992: ("Error getting link speed and duplex\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: if (speed != SPEED_1000) { ch1010832@1992: /* If link speed is not set to gigabit speed, we do not need ch1010832@1992: * to enable TBI compatibility. ch1010832@1992: */ ch1010832@1992: if (hw->tbi_compatibility_on) { ch1010832@1992: /* If we previously were in the mode, turn it off. */ ch1010832@1992: rctl = er32(RCTL); ch1010832@1992: rctl &= ~E1000_RCTL_SBP; ch1010832@1992: ew32(RCTL, rctl); ch1010832@1992: hw->tbi_compatibility_on = false; ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: /* If TBI compatibility is was previously off, turn it on. For ch1010832@1992: * compatibility with a TBI link partner, we will store bad ch1010832@1992: * packets. Some frames have an additional byte on the end and ch1010832@1992: * will look like CRC errors to to the hardware. ch1010832@1992: */ ch1010832@1992: if (!hw->tbi_compatibility_on) { ch1010832@1992: hw->tbi_compatibility_on = true; ch1010832@1992: rctl = er32(RCTL); ch1010832@1992: rctl |= E1000_RCTL_SBP; ch1010832@1992: ew32(RCTL, rctl); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: if ((hw->media_type == e1000_media_type_fiber) || ch1010832@1992: (hw->media_type == e1000_media_type_internal_serdes)) ch1010832@1992: e1000_check_for_serdes_link_generic(hw); ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_get_speed_and_duplex ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @speed: Speed of the connection ch1010832@1992: * @duplex: Duplex setting of the connection ch1010832@1992: ch1010832@1992: * Detects the current speed and duplex settings of the hardware. ch1010832@1992: */ ch1010832@1992: s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) ch1010832@1992: { ch1010832@1992: u32 status; ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_get_speed_and_duplex"); ch1010832@1992: ch1010832@1992: if (hw->mac_type >= e1000_82543) { ch1010832@1992: status = er32(STATUS); ch1010832@1992: if (status & E1000_STATUS_SPEED_1000) { ch1010832@1992: *speed = SPEED_1000; ch1010832@1992: DEBUGOUT("1000 Mbs, "); ch1010832@1992: } else if (status & E1000_STATUS_SPEED_100) { ch1010832@1992: *speed = SPEED_100; ch1010832@1992: DEBUGOUT("100 Mbs, "); ch1010832@1992: } else { ch1010832@1992: *speed = SPEED_10; ch1010832@1992: DEBUGOUT("10 Mbs, "); ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (status & E1000_STATUS_FD) { ch1010832@1992: *duplex = FULL_DUPLEX; ch1010832@1992: DEBUGOUT("Full Duplex\n"); ch1010832@1992: } else { ch1010832@1992: *duplex = HALF_DUPLEX; ch1010832@1992: DEBUGOUT(" Half Duplex\n"); ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: DEBUGOUT("1000 Mbs, Full Duplex\n"); ch1010832@1992: *speed = SPEED_1000; ch1010832@1992: *duplex = FULL_DUPLEX; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* IGP01 PHY may advertise full duplex operation after speed downgrade even ch1010832@1992: * if it is operating at half duplex. Here we set the duplex settings to ch1010832@1992: * match the duplex in the link partner's capabilities. ch1010832@1992: */ ch1010832@1992: if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) ch1010832@1992: *duplex = HALF_DUPLEX; ch1010832@1992: else { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: if ((*speed == SPEED_100 ch1010832@1992: && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ch1010832@1992: || (*speed == SPEED_10 ch1010832@1992: && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) ch1010832@1992: *duplex = HALF_DUPLEX; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_wait_autoneg ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Blocks until autoneg completes or times out (~4.5 seconds) ch1010832@1992: */ ch1010832@1992: static s32 e1000_wait_autoneg(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 i; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_wait_autoneg"); ch1010832@1992: DEBUGOUT("Waiting for Auto-Neg to complete.\n"); ch1010832@1992: ch1010832@1992: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ ch1010832@1992: for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { ch1010832@1992: /* Read the MII Status Register and wait for Auto-Neg ch1010832@1992: * Complete bit to be set. ch1010832@1992: */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: if (phy_data & MII_SR_AUTONEG_COMPLETE) { ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: msleep(100); ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_raise_mdi_clk - Raises the Management Data Clock ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @ctrl: Device control register's current value ch1010832@1992: */ ch1010832@1992: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) ch1010832@1992: { ch1010832@1992: /* Raise the clock input to the Management Data Clock (by setting the MDC ch1010832@1992: * bit), and then delay 10 microseconds. ch1010832@1992: */ ch1010832@1992: ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(10); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_lower_mdi_clk - Lowers the Management Data Clock ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @ctrl: Device control register's current value ch1010832@1992: */ ch1010832@1992: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) ch1010832@1992: { ch1010832@1992: /* Lower the clock input to the Management Data Clock (by clearing the MDC ch1010832@1992: * bit), and then delay 10 microseconds. ch1010832@1992: */ ch1010832@1992: ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(10); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @data: Data to send out to the PHY ch1010832@1992: * @count: Number of bits to shift out ch1010832@1992: * ch1010832@1992: * Bits are shifted out in MSB to LSB order. ch1010832@1992: */ ch1010832@1992: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: u32 mask; ch1010832@1992: ch1010832@1992: /* We need to shift "count" number of bits out to the PHY. So, the value ch1010832@1992: * in the "data" parameter will be shifted out to the PHY one bit at a ch1010832@1992: * time. In order to do this, "data" must be broken down into bits. ch1010832@1992: */ ch1010832@1992: mask = 0x01; ch1010832@1992: mask <<= (count - 1); ch1010832@1992: ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ ch1010832@1992: ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); ch1010832@1992: ch1010832@1992: while (mask) { ch1010832@1992: /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and ch1010832@1992: * then raising and lowering the Management Data Clock. A "0" is ch1010832@1992: * shifted out to the PHY by setting the MDIO bit to "0" and then ch1010832@1992: * raising and lowering the clock. ch1010832@1992: */ ch1010832@1992: if (data & mask) ch1010832@1992: ctrl |= E1000_CTRL_MDIO; ch1010832@1992: else ch1010832@1992: ctrl &= ~E1000_CTRL_MDIO; ch1010832@1992: ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: udelay(10); ch1010832@1992: ch1010832@1992: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@1992: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@1992: ch1010832@1992: mask = mask >> 1; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Bits are shifted in in MSB to LSB order. ch1010832@1992: */ ch1010832@1992: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl; ch1010832@1992: u16 data = 0; ch1010832@1992: u8 i; ch1010832@1992: ch1010832@1992: /* In order to read a register from the PHY, we need to shift in a total ch1010832@1992: * of 18 bits from the PHY. The first two bit (turnaround) times are used ch1010832@1992: * to avoid contention on the MDIO pin when a read operation is performed. ch1010832@1992: * These two bits are ignored by us and thrown away. Bits are "shifted in" ch1010832@1992: * by raising the input to the Management Data Clock (setting the MDC bit), ch1010832@1992: * and then reading the value of the MDIO bit. ch1010832@1992: */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ ch1010832@1992: ctrl &= ~E1000_CTRL_MDIO_DIR; ch1010832@1992: ctrl &= ~E1000_CTRL_MDIO; ch1010832@1992: ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: /* Raise and Lower the clock before reading in the data. This accounts for ch1010832@1992: * the turnaround bits. The first clock occurred when we clocked out the ch1010832@1992: * last bit of the Register Address. ch1010832@1992: */ ch1010832@1992: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@1992: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@1992: ch1010832@1992: for (data = 0, i = 0; i < 16; i++) { ch1010832@1992: data = data << 1; ch1010832@1992: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: /* Check to see if we shifted in a "1". */ ch1010832@1992: if (ctrl & E1000_CTRL_MDIO) ch1010832@1992: data |= 1; ch1010832@1992: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@1992: } ch1010832@1992: ch1010832@1992: e1000_raise_mdi_clk(hw, &ctrl); ch1010832@1992: e1000_lower_mdi_clk(hw, &ctrl); ch1010832@1992: ch1010832@1992: return data; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_read_phy_reg - read a phy register ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @reg_addr: address of the PHY register to read ch1010832@1992: * ch1010832@1992: * Reads the value from a PHY register, if the value is on a specific non zero ch1010832@1992: * page, sets the page first. ch1010832@1992: */ ch1010832@1992: s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) ch1010832@1992: { ch1010832@1992: u32 ret_val; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_read_phy_reg"); ch1010832@1992: ch1010832@1992: if ((hw->phy_type == e1000_phy_igp) && ch1010832@1992: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ch1010832@1992: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, ch1010832@1992: (u16) reg_addr); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, ch1010832@1992: phy_data); ch1010832@1992: ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@1992: u16 *phy_data) ch1010832@1992: { ch1010832@1992: u32 i; ch1010832@1992: u32 mdic = 0; ch1010832@1992: const u32 phy_addr = 1; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_read_phy_reg_ex"); ch1010832@1992: ch1010832@1992: if (reg_addr > MAX_PHY_REG_ADDRESS) { ch1010832@1992: DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); ch1010832@1992: return -E1000_ERR_PARAM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->mac_type > e1000_82543) { ch1010832@1992: /* Set up Op-code, Phy Address, and register address in the MDI ch1010832@1992: * Control register. The MAC will take care of interfacing with the ch1010832@1992: * PHY to retrieve the desired data. ch1010832@1992: */ ch1010832@1992: mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | ch1010832@1992: (phy_addr << E1000_MDIC_PHY_SHIFT) | ch1010832@1992: (E1000_MDIC_OP_READ)); ch1010832@1992: ch1010832@1992: ew32(MDIC, mdic); ch1010832@1992: ch1010832@1992: /* Poll the ready bit to see if the MDI read completed */ ch1010832@1992: for (i = 0; i < 64; i++) { ch1010832@1992: udelay(50); ch1010832@1992: mdic = er32(MDIC); ch1010832@1992: if (mdic & E1000_MDIC_READY) ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: if (!(mdic & E1000_MDIC_READY)) { ch1010832@1992: DEBUGOUT("MDI Read did not complete\n"); ch1010832@1992: return -E1000_ERR_PHY; ch1010832@1992: } ch1010832@1992: if (mdic & E1000_MDIC_ERROR) { ch1010832@1992: DEBUGOUT("MDI Error\n"); ch1010832@1992: return -E1000_ERR_PHY; ch1010832@1992: } ch1010832@1992: *phy_data = (u16) mdic; ch1010832@1992: } else { ch1010832@1992: /* We must first send a preamble through the MDIO pin to signal the ch1010832@1992: * beginning of an MII instruction. This is done by sending 32 ch1010832@1992: * consecutive "1" bits. ch1010832@1992: */ ch1010832@1992: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); ch1010832@1992: ch1010832@1992: /* Now combine the next few fields that are required for a read ch1010832@1992: * operation. We use this method instead of calling the ch1010832@1992: * e1000_shift_out_mdi_bits routine five different times. The format of ch1010832@1992: * a MII read instruction consists of a shift out of 14 bits and is ch1010832@1992: * defined as follows: ch1010832@1992: * ch1010832@1992: * followed by a shift in of 18 bits. This first two bits shifted in ch1010832@1992: * are TurnAround bits used to avoid contention on the MDIO pin when a ch1010832@1992: * READ operation is performed. These two bits are thrown away ch1010832@1992: * followed by a shift in of 16 bits which contains the desired data. ch1010832@1992: */ ch1010832@1992: mdic = ((reg_addr) | (phy_addr << 5) | ch1010832@1992: (PHY_OP_READ << 10) | (PHY_SOF << 12)); ch1010832@1992: ch1010832@1992: e1000_shift_out_mdi_bits(hw, mdic, 14); ch1010832@1992: ch1010832@1992: /* Now that we've shifted out the read command to the MII, we need to ch1010832@1992: * "shift in" the 16-bit value (18 total bits) of the requested PHY ch1010832@1992: * register address. ch1010832@1992: */ ch1010832@1992: *phy_data = e1000_shift_in_mdi_bits(hw); ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_write_phy_reg - write a phy register ch1010832@1992: * ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @reg_addr: address of the PHY register to write ch1010832@1992: * @data: data to write to the PHY ch1010832@1992: ch1010832@1992: * Writes a value to a PHY register ch1010832@1992: */ ch1010832@1992: s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) ch1010832@1992: { ch1010832@1992: u32 ret_val; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_write_phy_reg"); ch1010832@1992: ch1010832@1992: if ((hw->phy_type == e1000_phy_igp) && ch1010832@1992: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ch1010832@1992: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, ch1010832@1992: (u16) reg_addr); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, ch1010832@1992: phy_data); ch1010832@1992: ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, ch1010832@1992: u16 phy_data) ch1010832@1992: { ch1010832@1992: u32 i; ch1010832@1992: u32 mdic = 0; ch1010832@1992: const u32 phy_addr = 1; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_write_phy_reg_ex"); ch1010832@1992: ch1010832@1992: if (reg_addr > MAX_PHY_REG_ADDRESS) { ch1010832@1992: DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); ch1010832@1992: return -E1000_ERR_PARAM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->mac_type > e1000_82543) { ch1010832@1992: /* Set up Op-code, Phy Address, register address, and data intended ch1010832@1992: * for the PHY register in the MDI Control register. The MAC will take ch1010832@1992: * care of interfacing with the PHY to send the desired data. ch1010832@1992: */ ch1010832@1992: mdic = (((u32) phy_data) | ch1010832@1992: (reg_addr << E1000_MDIC_REG_SHIFT) | ch1010832@1992: (phy_addr << E1000_MDIC_PHY_SHIFT) | ch1010832@1992: (E1000_MDIC_OP_WRITE)); ch1010832@1992: ch1010832@1992: ew32(MDIC, mdic); ch1010832@1992: ch1010832@1992: /* Poll the ready bit to see if the MDI read completed */ ch1010832@1992: for (i = 0; i < 641; i++) { ch1010832@1992: udelay(5); ch1010832@1992: mdic = er32(MDIC); ch1010832@1992: if (mdic & E1000_MDIC_READY) ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: if (!(mdic & E1000_MDIC_READY)) { ch1010832@1992: DEBUGOUT("MDI Write did not complete\n"); ch1010832@1992: return -E1000_ERR_PHY; ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: /* We'll need to use the SW defined pins to shift the write command ch1010832@1992: * out to the PHY. We first send a preamble to the PHY to signal the ch1010832@1992: * beginning of the MII instruction. This is done by sending 32 ch1010832@1992: * consecutive "1" bits. ch1010832@1992: */ ch1010832@1992: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); ch1010832@1992: ch1010832@1992: /* Now combine the remaining required fields that will indicate a ch1010832@1992: * write operation. We use this method instead of calling the ch1010832@1992: * e1000_shift_out_mdi_bits routine for each field in the command. The ch1010832@1992: * format of a MII write instruction is as follows: ch1010832@1992: * . ch1010832@1992: */ ch1010832@1992: mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | ch1010832@1992: (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); ch1010832@1992: mdic <<= 16; ch1010832@1992: mdic |= (u32) phy_data; ch1010832@1992: ch1010832@1992: e1000_shift_out_mdi_bits(hw, mdic, 32); ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_hw_reset - reset the phy, hardware style ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Returns the PHY to the power-on reset state ch1010832@1992: */ ch1010832@1992: s32 e1000_phy_hw_reset(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl, ctrl_ext; ch1010832@1992: u32 led_ctrl; ch1010832@1992: s32 ret_val; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_hw_reset"); ch1010832@1992: ch1010832@1992: DEBUGOUT("Resetting Phy...\n"); ch1010832@1992: ch1010832@1992: if (hw->mac_type > e1000_82543) { ch1010832@1992: /* Read the device control register and assert the E1000_CTRL_PHY_RST ch1010832@1992: * bit. Then, take it out of reset. ch1010832@1992: * For e1000 hardware, we delay for 10ms between the assert ch1010832@1992: * and deassert. ch1010832@1992: */ ch1010832@1992: ctrl = er32(CTRL); ch1010832@1992: ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: msleep(10); ch1010832@1992: ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: } else { ch1010832@1992: /* Read the Extended Device Control Register, assert the PHY_RESET_DIR ch1010832@1992: * bit to put the PHY into reset. Then, take it out of reset. ch1010832@1992: */ ch1010832@1992: ctrl_ext = er32(CTRL_EXT); ch1010832@1992: ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; ch1010832@1992: ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; ch1010832@1992: ew32(CTRL_EXT, ctrl_ext); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: msleep(10); ch1010832@1992: ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; ch1010832@1992: ew32(CTRL_EXT, ctrl_ext); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: udelay(150); ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { ch1010832@1992: /* Configure activity LED after PHY reset */ ch1010832@1992: led_ctrl = er32(LEDCTL); ch1010832@1992: led_ctrl &= IGP_ACTIVITY_LED_MASK; ch1010832@1992: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); ch1010832@1992: ew32(LEDCTL, led_ctrl); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Wait for FW to finish PHY configuration. */ ch1010832@1992: ret_val = e1000_get_phy_cfg_done(hw); ch1010832@1992: if (ret_val != E1000_SUCCESS) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_reset - reset the phy to commit settings ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Resets the PHY ch1010832@1992: * Sets bit 15 of the MII Control register ch1010832@1992: */ ch1010832@1992: s32 e1000_phy_reset(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_reset"); ch1010832@1992: ch1010832@1992: switch (hw->phy_type) { ch1010832@1992: case e1000_phy_igp: ch1010832@1992: ret_val = e1000_phy_hw_reset(hw); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= MII_CR_RESET; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: udelay(1); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_igp) ch1010832@1992: e1000_phy_init_script(hw); ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_detect_gig_phy - check the phy type ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Probes the expected PHY address for known PHY IDs ch1010832@1992: */ ch1010832@1992: static s32 e1000_detect_gig_phy(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 phy_init_status, ret_val; ch1010832@1992: u16 phy_id_high, phy_id_low; ch1010832@1992: bool match = false; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_detect_gig_phy"); ch1010832@1992: ch1010832@1992: if (hw->phy_id != 0) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: /* Read the PHY ID Registers to identify which PHY is onboard. */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->phy_id = (u32) (phy_id_high << 16); ch1010832@1992: udelay(20); ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); ch1010832@1992: hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82543: ch1010832@1992: if (hw->phy_id == M88E1000_E_PHY_ID) ch1010832@1992: match = true; ch1010832@1992: break; ch1010832@1992: case e1000_82544: ch1010832@1992: if (hw->phy_id == M88E1000_I_PHY_ID) ch1010832@1992: match = true; ch1010832@1992: break; ch1010832@1992: case e1000_82540: ch1010832@1992: case e1000_82545: ch1010832@1992: case e1000_82545_rev_3: ch1010832@1992: case e1000_82546: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: if (hw->phy_id == M88E1011_I_PHY_ID) ch1010832@1992: match = true; ch1010832@1992: break; ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: if (hw->phy_id == IGP01E1000_I_PHY_ID) ch1010832@1992: match = true; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: } ch1010832@1992: phy_init_status = e1000_set_phy_type(hw); ch1010832@1992: ch1010832@1992: if ((match) && (phy_init_status == E1000_SUCCESS)) { ch1010832@1992: DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); ch1010832@1992: return -E1000_ERR_PHY; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_reset_dsp - reset DSP ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Resets the PHY's DSP ch1010832@1992: */ ch1010832@1992: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: DEBUGFUNC("e1000_phy_reset_dsp"); ch1010832@1992: ch1010832@1992: do { ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 29, 0x001d); ch1010832@1992: if (ret_val) ch1010832@1992: break; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); ch1010832@1992: if (ret_val) ch1010832@1992: break; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 30, 0x0000); ch1010832@1992: if (ret_val) ch1010832@1992: break; ch1010832@1992: ret_val = E1000_SUCCESS; ch1010832@1992: } while (0); ch1010832@1992: ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_igp_get_info - get igp specific registers ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @phy_info: PHY information structure ch1010832@1992: * ch1010832@1992: * Get PHY information from various PHY registers for igp PHY only. ch1010832@1992: */ ch1010832@1992: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, ch1010832@1992: struct e1000_phy_info *phy_info) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data, min_length, max_length, average; ch1010832@1992: e1000_rev_polarity polarity; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_igp_get_info"); ch1010832@1992: ch1010832@1992: /* The downshift status is checked only once, after link is established, ch1010832@1992: * and it stored in the hw->speed_downgraded parameter. */ ch1010832@1992: phy_info->downshift = (e1000_downshift) hw->speed_downgraded; ch1010832@1992: ch1010832@1992: /* IGP01E1000 does not need to support it. */ ch1010832@1992: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; ch1010832@1992: ch1010832@1992: /* IGP01E1000 always correct polarity reversal */ ch1010832@1992: phy_info->polarity_correction = e1000_polarity_reversal_enabled; ch1010832@1992: ch1010832@1992: /* Check polarity status */ ch1010832@1992: ret_val = e1000_check_polarity(hw, &polarity); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_info->cable_polarity = polarity; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_info->mdix_mode = ch1010832@1992: (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> ch1010832@1992: IGP01E1000_PSSR_MDIX_SHIFT); ch1010832@1992: ch1010832@1992: if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == ch1010832@1992: IGP01E1000_PSSR_SPEED_1000MBPS) { ch1010832@1992: /* Local/Remote Receiver Information are only valid at 1000 Mbps */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> ch1010832@1992: SR_1000T_LOCAL_RX_STATUS_SHIFT) ? ch1010832@1992: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@1992: phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> ch1010832@1992: SR_1000T_REMOTE_RX_STATUS_SHIFT) ? ch1010832@1992: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@1992: ch1010832@1992: /* Get cable length */ ch1010832@1992: ret_val = e1000_get_cable_length(hw, &min_length, &max_length); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Translate to old method */ ch1010832@1992: average = (max_length + min_length) / 2; ch1010832@1992: ch1010832@1992: if (average <= e1000_igp_cable_length_50) ch1010832@1992: phy_info->cable_length = e1000_cable_length_50; ch1010832@1992: else if (average <= e1000_igp_cable_length_80) ch1010832@1992: phy_info->cable_length = e1000_cable_length_50_80; ch1010832@1992: else if (average <= e1000_igp_cable_length_110) ch1010832@1992: phy_info->cable_length = e1000_cable_length_80_110; ch1010832@1992: else if (average <= e1000_igp_cable_length_140) ch1010832@1992: phy_info->cable_length = e1000_cable_length_110_140; ch1010832@1992: else ch1010832@1992: phy_info->cable_length = e1000_cable_length_140; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_m88_get_info - get m88 specific registers ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @phy_info: PHY information structure ch1010832@1992: * ch1010832@1992: * Get PHY information from various PHY registers for m88 PHY only. ch1010832@1992: */ ch1010832@1992: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, ch1010832@1992: struct e1000_phy_info *phy_info) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: e1000_rev_polarity polarity; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_m88_get_info"); ch1010832@1992: ch1010832@1992: /* The downshift status is checked only once, after link is established, ch1010832@1992: * and it stored in the hw->speed_downgraded parameter. */ ch1010832@1992: phy_info->downshift = (e1000_downshift) hw->speed_downgraded; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_info->extended_10bt_distance = ch1010832@1992: ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> ch1010832@1992: M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? ch1010832@1992: e1000_10bt_ext_dist_enable_lower : ch1010832@1992: e1000_10bt_ext_dist_enable_normal; ch1010832@1992: ch1010832@1992: phy_info->polarity_correction = ch1010832@1992: ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> ch1010832@1992: M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? ch1010832@1992: e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; ch1010832@1992: ch1010832@1992: /* Check polarity status */ ch1010832@1992: ret_val = e1000_check_polarity(hw, &polarity); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: phy_info->cable_polarity = polarity; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_info->mdix_mode = ch1010832@1992: (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> ch1010832@1992: M88E1000_PSSR_MDIX_SHIFT); ch1010832@1992: ch1010832@1992: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { ch1010832@1992: /* Cable Length Estimation and Local/Remote Receiver Information ch1010832@1992: * are only valid at 1000 Mbps. ch1010832@1992: */ ch1010832@1992: phy_info->cable_length = ch1010832@1992: (e1000_cable_length) ((phy_data & ch1010832@1992: M88E1000_PSSR_CABLE_LENGTH) >> ch1010832@1992: M88E1000_PSSR_CABLE_LENGTH_SHIFT); ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> ch1010832@1992: SR_1000T_LOCAL_RX_STATUS_SHIFT) ? ch1010832@1992: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@1992: phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> ch1010832@1992: SR_1000T_REMOTE_RX_STATUS_SHIFT) ? ch1010832@1992: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; ch1010832@1992: ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_phy_get_info - request phy info ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @phy_info: PHY information structure ch1010832@1992: * ch1010832@1992: * Get PHY information from various PHY registers ch1010832@1992: */ ch1010832@1992: s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_phy_get_info"); ch1010832@1992: ch1010832@1992: phy_info->cable_length = e1000_cable_length_undefined; ch1010832@1992: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; ch1010832@1992: phy_info->cable_polarity = e1000_rev_polarity_undefined; ch1010832@1992: phy_info->downshift = e1000_downshift_undefined; ch1010832@1992: phy_info->polarity_correction = e1000_polarity_reversal_undefined; ch1010832@1992: phy_info->mdix_mode = e1000_auto_x_mode_undefined; ch1010832@1992: phy_info->local_rx = e1000_1000t_rx_status_undefined; ch1010832@1992: phy_info->remote_rx = e1000_1000t_rx_status_undefined; ch1010832@1992: ch1010832@1992: if (hw->media_type != e1000_media_type_copper) { ch1010832@1992: DEBUGOUT("PHY info is only valid for copper media\n"); ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { ch1010832@1992: DEBUGOUT("PHY info is only valid if link is up\n"); ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_igp) ch1010832@1992: return e1000_phy_igp_get_info(hw, phy_info); ch1010832@1992: else ch1010832@1992: return e1000_phy_m88_get_info(hw, phy_info); ch1010832@1992: } ch1010832@1992: ch1010832@1992: s32 e1000_validate_mdi_setting(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_validate_mdi_settings"); ch1010832@1992: ch1010832@1992: if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { ch1010832@1992: DEBUGOUT("Invalid MDI setting detected\n"); ch1010832@1992: hw->mdix = 1; ch1010832@1992: return -E1000_ERR_CONFIG; ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_init_eeprom_params - initialize sw eeprom vars ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Sets up eeprom variables in the hw struct. Must be called after mac_type ch1010832@1992: * is configured. ch1010832@1992: */ ch1010832@1992: s32 e1000_init_eeprom_params(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u32 eecd = er32(EECD); ch1010832@1992: s32 ret_val = E1000_SUCCESS; ch1010832@1992: u16 eeprom_size; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_init_eeprom_params"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: case e1000_82543: ch1010832@1992: case e1000_82544: ch1010832@1992: eeprom->type = e1000_eeprom_microwire; ch1010832@1992: eeprom->word_size = 64; ch1010832@1992: eeprom->opcode_bits = 3; ch1010832@1992: eeprom->address_bits = 6; ch1010832@1992: eeprom->delay_usec = 50; ch1010832@1992: break; ch1010832@1992: case e1000_82540: ch1010832@1992: case e1000_82545: ch1010832@1992: case e1000_82545_rev_3: ch1010832@1992: case e1000_82546: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: eeprom->type = e1000_eeprom_microwire; ch1010832@1992: eeprom->opcode_bits = 3; ch1010832@1992: eeprom->delay_usec = 50; ch1010832@1992: if (eecd & E1000_EECD_SIZE) { ch1010832@1992: eeprom->word_size = 256; ch1010832@1992: eeprom->address_bits = 8; ch1010832@1992: } else { ch1010832@1992: eeprom->word_size = 64; ch1010832@1992: eeprom->address_bits = 6; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: if (eecd & E1000_EECD_TYPE) { ch1010832@1992: eeprom->type = e1000_eeprom_spi; ch1010832@1992: eeprom->opcode_bits = 8; ch1010832@1992: eeprom->delay_usec = 1; ch1010832@1992: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@1992: eeprom->page_size = 32; ch1010832@1992: eeprom->address_bits = 16; ch1010832@1992: } else { ch1010832@1992: eeprom->page_size = 8; ch1010832@1992: eeprom->address_bits = 8; ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: eeprom->type = e1000_eeprom_microwire; ch1010832@1992: eeprom->opcode_bits = 3; ch1010832@1992: eeprom->delay_usec = 50; ch1010832@1992: if (eecd & E1000_EECD_ADDR_BITS) { ch1010832@1992: eeprom->word_size = 256; ch1010832@1992: eeprom->address_bits = 8; ch1010832@1992: } else { ch1010832@1992: eeprom->word_size = 64; ch1010832@1992: eeprom->address_bits = 6; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (eeprom->type == e1000_eeprom_spi) { ch1010832@1992: /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to ch1010832@1992: * 32KB (incremented by powers of 2). ch1010832@1992: */ ch1010832@1992: /* Set to default value for initial eeprom read. */ ch1010832@1992: eeprom->word_size = 64; ch1010832@1992: ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: eeprom_size = ch1010832@1992: (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; ch1010832@1992: /* 256B eeprom size was not supported in earlier hardware, so we ch1010832@1992: * bump eeprom_size up one to ensure that "1" (which maps to 256B) ch1010832@1992: * is never the result used in the shifting logic below. */ ch1010832@1992: if (eeprom_size) ch1010832@1992: eeprom_size++; ch1010832@1992: ch1010832@1992: eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); ch1010832@1992: } ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_raise_ee_clk - Raises the EEPROM's clock input. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @eecd: EECD's current value ch1010832@1992: */ ch1010832@1992: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) ch1010832@1992: { ch1010832@1992: /* Raise the clock input to the EEPROM (by setting the SK bit), and then ch1010832@1992: * wait microseconds. ch1010832@1992: */ ch1010832@1992: *eecd = *eecd | E1000_EECD_SK; ch1010832@1992: ew32(EECD, *eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(hw->eeprom.delay_usec); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_lower_ee_clk - Lowers the EEPROM's clock input. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @eecd: EECD's current value ch1010832@1992: */ ch1010832@1992: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) ch1010832@1992: { ch1010832@1992: /* Lower the clock input to the EEPROM (by clearing the SK bit), and then ch1010832@1992: * wait 50 microseconds. ch1010832@1992: */ ch1010832@1992: *eecd = *eecd & ~E1000_EECD_SK; ch1010832@1992: ew32(EECD, *eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(hw->eeprom.delay_usec); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @data: data to send to the EEPROM ch1010832@1992: * @count: number of bits to shift out ch1010832@1992: */ ch1010832@1992: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u32 eecd; ch1010832@1992: u32 mask; ch1010832@1992: ch1010832@1992: /* We need to shift "count" bits out to the EEPROM. So, value in the ch1010832@1992: * "data" parameter will be shifted out to the EEPROM one bit at a time. ch1010832@1992: * In order to do this, "data" must be broken down into bits. ch1010832@1992: */ ch1010832@1992: mask = 0x01 << (count - 1); ch1010832@1992: eecd = er32(EECD); ch1010832@1992: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@1992: eecd &= ~E1000_EECD_DO; ch1010832@1992: } else if (eeprom->type == e1000_eeprom_spi) { ch1010832@1992: eecd |= E1000_EECD_DO; ch1010832@1992: } ch1010832@1992: do { ch1010832@1992: /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", ch1010832@1992: * and then raising and then lowering the clock (the SK bit controls ch1010832@1992: * the clock input to the EEPROM). A "0" is shifted out to the EEPROM ch1010832@1992: * by setting "DI" to "0" and then raising and then lowering the clock. ch1010832@1992: */ ch1010832@1992: eecd &= ~E1000_EECD_DI; ch1010832@1992: ch1010832@1992: if (data & mask) ch1010832@1992: eecd |= E1000_EECD_DI; ch1010832@1992: ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: ch1010832@1992: e1000_raise_ee_clk(hw, &eecd); ch1010832@1992: e1000_lower_ee_clk(hw, &eecd); ch1010832@1992: ch1010832@1992: mask = mask >> 1; ch1010832@1992: ch1010832@1992: } while (mask); ch1010832@1992: ch1010832@1992: /* We leave the "DI" bit set to "0" when we leave this routine. */ ch1010832@1992: eecd &= ~E1000_EECD_DI; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @count: number of bits to shift in ch1010832@1992: */ ch1010832@1992: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) ch1010832@1992: { ch1010832@1992: u32 eecd; ch1010832@1992: u32 i; ch1010832@1992: u16 data; ch1010832@1992: ch1010832@1992: /* In order to read a register from the EEPROM, we need to shift 'count' ch1010832@1992: * bits in from the EEPROM. Bits are "shifted in" by raising the clock ch1010832@1992: * input to the EEPROM (setting the SK bit), and then reading the value of ch1010832@1992: * the "DO" bit. During this "shifting in" process the "DI" bit should ch1010832@1992: * always be clear. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: eecd = er32(EECD); ch1010832@1992: ch1010832@1992: eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); ch1010832@1992: data = 0; ch1010832@1992: ch1010832@1992: for (i = 0; i < count; i++) { ch1010832@1992: data = data << 1; ch1010832@1992: e1000_raise_ee_clk(hw, &eecd); ch1010832@1992: ch1010832@1992: eecd = er32(EECD); ch1010832@1992: ch1010832@1992: eecd &= ~(E1000_EECD_DI); ch1010832@1992: if (eecd & E1000_EECD_DO) ch1010832@1992: data |= 1; ch1010832@1992: ch1010832@1992: e1000_lower_ee_clk(hw, &eecd); ch1010832@1992: } ch1010832@1992: ch1010832@1992: return data; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_acquire_eeprom - Prepares EEPROM for access ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This ch1010832@1992: * function should be called before issuing a command to the EEPROM. ch1010832@1992: */ ch1010832@1992: static s32 e1000_acquire_eeprom(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u32 eecd, i = 0; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_acquire_eeprom"); ch1010832@1992: ch1010832@1992: eecd = er32(EECD); ch1010832@1992: ch1010832@1992: /* Request EEPROM Access */ ch1010832@1992: if (hw->mac_type > e1000_82544) { ch1010832@1992: eecd |= E1000_EECD_REQ; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: eecd = er32(EECD); ch1010832@1992: while ((!(eecd & E1000_EECD_GNT)) && ch1010832@1992: (i < E1000_EEPROM_GRANT_ATTEMPTS)) { ch1010832@1992: i++; ch1010832@1992: udelay(5); ch1010832@1992: eecd = er32(EECD); ch1010832@1992: } ch1010832@1992: if (!(eecd & E1000_EECD_GNT)) { ch1010832@1992: eecd &= ~E1000_EECD_REQ; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: DEBUGOUT("Could not acquire EEPROM grant\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Setup EEPROM for Read/Write */ ch1010832@1992: ch1010832@1992: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@1992: /* Clear SK and DI */ ch1010832@1992: eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: ch1010832@1992: /* Set CS */ ch1010832@1992: eecd |= E1000_EECD_CS; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: } else if (eeprom->type == e1000_eeprom_spi) { ch1010832@1992: /* Clear SK and CS */ ch1010832@1992: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: udelay(1); ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_standby_eeprom - Returns EEPROM to a "standby" state ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static void e1000_standby_eeprom(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u32 eecd; ch1010832@1992: ch1010832@1992: eecd = er32(EECD); ch1010832@1992: ch1010832@1992: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@1992: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: ch1010832@1992: /* Clock high */ ch1010832@1992: eecd |= E1000_EECD_SK; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: ch1010832@1992: /* Select EEPROM */ ch1010832@1992: eecd |= E1000_EECD_CS; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: ch1010832@1992: /* Clock low */ ch1010832@1992: eecd &= ~E1000_EECD_SK; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: } else if (eeprom->type == e1000_eeprom_spi) { ch1010832@1992: /* Toggle CS to flush commands */ ch1010832@1992: eecd |= E1000_EECD_CS; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: eecd &= ~E1000_EECD_CS; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(eeprom->delay_usec); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_release_eeprom - drop chip select ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Terminates a command by inverting the EEPROM's chip select pin ch1010832@1992: */ ch1010832@1992: static void e1000_release_eeprom(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 eecd; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_release_eeprom"); ch1010832@1992: ch1010832@1992: eecd = er32(EECD); ch1010832@1992: ch1010832@1992: if (hw->eeprom.type == e1000_eeprom_spi) { ch1010832@1992: eecd |= E1000_EECD_CS; /* Pull CS high */ ch1010832@1992: eecd &= ~E1000_EECD_SK; /* Lower SCK */ ch1010832@1992: ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: ch1010832@1992: udelay(hw->eeprom.delay_usec); ch1010832@1992: } else if (hw->eeprom.type == e1000_eeprom_microwire) { ch1010832@1992: /* cleanup eeprom */ ch1010832@1992: ch1010832@1992: /* CS on Microwire is active-high */ ch1010832@1992: eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); ch1010832@1992: ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: ch1010832@1992: /* Rising edge of clock */ ch1010832@1992: eecd |= E1000_EECD_SK; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(hw->eeprom.delay_usec); ch1010832@1992: ch1010832@1992: /* Falling edge of clock */ ch1010832@1992: eecd &= ~E1000_EECD_SK; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: udelay(hw->eeprom.delay_usec); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Stop requesting EEPROM access */ ch1010832@1992: if (hw->mac_type > e1000_82544) { ch1010832@1992: eecd &= ~E1000_EECD_REQ; ch1010832@1992: ew32(EECD, eecd); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u16 retry_count = 0; ch1010832@1992: u8 spi_stat_reg; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_spi_eeprom_ready"); ch1010832@1992: ch1010832@1992: /* Read "Status Register" repeatedly until the LSB is cleared. The ch1010832@1992: * EEPROM will signal that the command has been completed by clearing ch1010832@1992: * bit 0 of the internal status register. If it's not cleared within ch1010832@1992: * 5 milliseconds, then error out. ch1010832@1992: */ ch1010832@1992: retry_count = 0; ch1010832@1992: do { ch1010832@1992: e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, ch1010832@1992: hw->eeprom.opcode_bits); ch1010832@1992: spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); ch1010832@1992: if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) ch1010832@1992: break; ch1010832@1992: ch1010832@1992: udelay(5); ch1010832@1992: retry_count += 5; ch1010832@1992: ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: } while (retry_count < EEPROM_MAX_RETRY_SPI); ch1010832@1992: ch1010832@1992: /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and ch1010832@1992: * only 0-5mSec on 5V devices) ch1010832@1992: */ ch1010832@1992: if (retry_count >= EEPROM_MAX_RETRY_SPI) { ch1010832@1992: DEBUGOUT("SPI EEPROM Status error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @offset: offset of word in the EEPROM to read ch1010832@1992: * @data: word read from the EEPROM ch1010832@1992: * @words: number of words to read ch1010832@1992: */ ch1010832@1992: s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ch1010832@1992: { ch1010832@1992: s32 ret; ch1010832@1992: spin_lock(&e1000_eeprom_lock); ch1010832@1992: ret = e1000_do_read_eeprom(hw, offset, words, data); ch1010832@1992: spin_unlock(&e1000_eeprom_lock); ch1010832@1992: return ret; ch1010832@1992: } ch1010832@1992: ch1010832@1992: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@1992: u16 *data) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u32 i = 0; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_read_eeprom"); ch1010832@1992: ch1010832@1992: /* If eeprom is not yet detected, do so now */ ch1010832@1992: if (eeprom->word_size == 0) ch1010832@1992: e1000_init_eeprom_params(hw); ch1010832@1992: ch1010832@1992: /* A check for invalid values: offset too large, too many words, and not ch1010832@1992: * enough words. ch1010832@1992: */ ch1010832@1992: if ((offset >= eeprom->word_size) ch1010832@1992: || (words > eeprom->word_size - offset) || (words == 0)) { ch1010832@1992: DEBUGOUT2 ch1010832@1992: ("\"words\" parameter out of bounds. Words = %d, size = %d\n", ch1010832@1992: offset, eeprom->word_size); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* EEPROM's that don't use EERD to read require us to bit-bang the SPI ch1010832@1992: * directly. In this case, we need to acquire the EEPROM so that ch1010832@1992: * FW or other port software does not interrupt. ch1010832@1992: */ ch1010832@1992: /* Prepare the EEPROM for bit-bang reading */ ch1010832@1992: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: ch1010832@1992: /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have ch1010832@1992: * acquired the EEPROM at this point, so any returns should release it */ ch1010832@1992: if (eeprom->type == e1000_eeprom_spi) { ch1010832@1992: u16 word_in; ch1010832@1992: u8 read_opcode = EEPROM_READ_OPCODE_SPI; ch1010832@1992: ch1010832@1992: if (e1000_spi_eeprom_ready(hw)) { ch1010832@1992: e1000_release_eeprom(hw); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: ch1010832@1992: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ ch1010832@1992: if ((eeprom->address_bits == 8) && (offset >= 128)) ch1010832@1992: read_opcode |= EEPROM_A8_OPCODE_SPI; ch1010832@1992: ch1010832@1992: /* Send the READ command (opcode + addr) */ ch1010832@1992: e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); ch1010832@1992: e1000_shift_out_ee_bits(hw, (u16) (offset * 2), ch1010832@1992: eeprom->address_bits); ch1010832@1992: ch1010832@1992: /* Read the data. The address of the eeprom internally increments with ch1010832@1992: * each byte (spi) being read, saving on the overhead of eeprom setup ch1010832@1992: * and tear-down. The address counter will roll over if reading beyond ch1010832@1992: * the size of the eeprom, thus allowing the entire memory to be read ch1010832@1992: * starting from any offset. */ ch1010832@1992: for (i = 0; i < words; i++) { ch1010832@1992: word_in = e1000_shift_in_ee_bits(hw, 16); ch1010832@1992: data[i] = (word_in >> 8) | (word_in << 8); ch1010832@1992: } ch1010832@1992: } else if (eeprom->type == e1000_eeprom_microwire) { ch1010832@1992: for (i = 0; i < words; i++) { ch1010832@1992: /* Send the READ command (opcode + addr) */ ch1010832@1992: e1000_shift_out_ee_bits(hw, ch1010832@1992: EEPROM_READ_OPCODE_MICROWIRE, ch1010832@1992: eeprom->opcode_bits); ch1010832@1992: e1000_shift_out_ee_bits(hw, (u16) (offset + i), ch1010832@1992: eeprom->address_bits); ch1010832@1992: ch1010832@1992: /* Read the data. For microwire, each word requires the overhead ch1010832@1992: * of eeprom setup and tear-down. */ ch1010832@1992: data[i] = e1000_shift_in_ee_bits(hw, 16); ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* End this read operation */ ch1010832@1992: e1000_release_eeprom(hw); ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Reads the first 64 16 bit words of the EEPROM and sums the values read. ch1010832@1992: * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is ch1010832@1992: * valid. ch1010832@1992: */ ch1010832@1992: s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u16 checksum = 0; ch1010832@1992: u16 i, eeprom_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_validate_eeprom_checksum"); ch1010832@1992: ch1010832@1992: for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { ch1010832@1992: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { ch1010832@1992: DEBUGOUT("EEPROM Read Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: checksum += eeprom_data; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (checksum == (u16) EEPROM_SUM) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: else { ch1010832@1992: DEBUGOUT("EEPROM Checksum Invalid\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. ch1010832@1992: * Writes the difference to word offset 63 of the EEPROM. ch1010832@1992: */ ch1010832@1992: s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u16 checksum = 0; ch1010832@1992: u16 i, eeprom_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_update_eeprom_checksum"); ch1010832@1992: ch1010832@1992: for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { ch1010832@1992: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { ch1010832@1992: DEBUGOUT("EEPROM Read Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: checksum += eeprom_data; ch1010832@1992: } ch1010832@1992: checksum = (u16) EEPROM_SUM - checksum; ch1010832@1992: if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { ch1010832@1992: DEBUGOUT("EEPROM Write Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_write_eeprom - write words to the different EEPROM types. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @offset: offset within the EEPROM to be written to ch1010832@1992: * @words: number of words to write ch1010832@1992: * @data: 16 bit word to be written to the EEPROM ch1010832@1992: * ch1010832@1992: * If e1000_update_eeprom_checksum is not called after this function, the ch1010832@1992: * EEPROM will most likely contain an invalid checksum. ch1010832@1992: */ ch1010832@1992: s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) ch1010832@1992: { ch1010832@1992: s32 ret; ch1010832@1992: spin_lock(&e1000_eeprom_lock); ch1010832@1992: ret = e1000_do_write_eeprom(hw, offset, words, data); ch1010832@1992: spin_unlock(&e1000_eeprom_lock); ch1010832@1992: return ret; ch1010832@1992: } ch1010832@1992: ch1010832@1992: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@1992: u16 *data) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: s32 status = 0; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_write_eeprom"); ch1010832@1992: ch1010832@1992: /* If eeprom is not yet detected, do so now */ ch1010832@1992: if (eeprom->word_size == 0) ch1010832@1992: e1000_init_eeprom_params(hw); ch1010832@1992: ch1010832@1992: /* A check for invalid values: offset too large, too many words, and not ch1010832@1992: * enough words. ch1010832@1992: */ ch1010832@1992: if ((offset >= eeprom->word_size) ch1010832@1992: || (words > eeprom->word_size - offset) || (words == 0)) { ch1010832@1992: DEBUGOUT("\"words\" parameter out of bounds\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Prepare the EEPROM for writing */ ch1010832@1992: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: ch1010832@1992: if (eeprom->type == e1000_eeprom_microwire) { ch1010832@1992: status = e1000_write_eeprom_microwire(hw, offset, words, data); ch1010832@1992: } else { ch1010832@1992: status = e1000_write_eeprom_spi(hw, offset, words, data); ch1010832@1992: msleep(10); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Done with writing */ ch1010832@1992: e1000_release_eeprom(hw); ch1010832@1992: ch1010832@1992: return status; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @offset: offset within the EEPROM to be written to ch1010832@1992: * @words: number of words to write ch1010832@1992: * @data: pointer to array of 8 bit words to be written to the EEPROM ch1010832@1992: */ ch1010832@1992: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, ch1010832@1992: u16 *data) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u16 widx = 0; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_write_eeprom_spi"); ch1010832@1992: ch1010832@1992: while (widx < words) { ch1010832@1992: u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; ch1010832@1992: ch1010832@1992: if (e1000_spi_eeprom_ready(hw)) ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: ch1010832@1992: /* Send the WRITE ENABLE command (8 bit opcode ) */ ch1010832@1992: e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, ch1010832@1992: eeprom->opcode_bits); ch1010832@1992: ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: ch1010832@1992: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ ch1010832@1992: if ((eeprom->address_bits == 8) && (offset >= 128)) ch1010832@1992: write_opcode |= EEPROM_A8_OPCODE_SPI; ch1010832@1992: ch1010832@1992: /* Send the Write command (8-bit opcode + addr) */ ch1010832@1992: e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); ch1010832@1992: ch1010832@1992: e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), ch1010832@1992: eeprom->address_bits); ch1010832@1992: ch1010832@1992: /* Send the data */ ch1010832@1992: ch1010832@1992: /* Loop to allow for up to whole page write (32 bytes) of eeprom */ ch1010832@1992: while (widx < words) { ch1010832@1992: u16 word_out = data[widx]; ch1010832@1992: word_out = (word_out >> 8) | (word_out << 8); ch1010832@1992: e1000_shift_out_ee_bits(hw, word_out, 16); ch1010832@1992: widx++; ch1010832@1992: ch1010832@1992: /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE ch1010832@1992: * operation, while the smaller eeproms are capable of an 8-byte ch1010832@1992: * PAGE WRITE operation. Break the inner loop to pass new address ch1010832@1992: */ ch1010832@1992: if ((((offset + widx) * 2) % eeprom->page_size) == 0) { ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @offset: offset within the EEPROM to be written to ch1010832@1992: * @words: number of words to write ch1010832@1992: * @data: pointer to array of 8 bit words to be written to the EEPROM ch1010832@1992: */ ch1010832@1992: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, ch1010832@1992: u16 words, u16 *data) ch1010832@1992: { ch1010832@1992: struct e1000_eeprom_info *eeprom = &hw->eeprom; ch1010832@1992: u32 eecd; ch1010832@1992: u16 words_written = 0; ch1010832@1992: u16 i = 0; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_write_eeprom_microwire"); ch1010832@1992: ch1010832@1992: /* Send the write enable command to the EEPROM (3-bit opcode plus ch1010832@1992: * 6/8-bit dummy address beginning with 11). It's less work to include ch1010832@1992: * the 11 of the dummy address as part of the opcode than it is to shift ch1010832@1992: * it over the correct number of bits for the address. This puts the ch1010832@1992: * EEPROM into write/erase mode. ch1010832@1992: */ ch1010832@1992: e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, ch1010832@1992: (u16) (eeprom->opcode_bits + 2)); ch1010832@1992: ch1010832@1992: e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); ch1010832@1992: ch1010832@1992: /* Prepare the EEPROM */ ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: ch1010832@1992: while (words_written < words) { ch1010832@1992: /* Send the Write command (3-bit opcode + addr) */ ch1010832@1992: e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, ch1010832@1992: eeprom->opcode_bits); ch1010832@1992: ch1010832@1992: e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), ch1010832@1992: eeprom->address_bits); ch1010832@1992: ch1010832@1992: /* Send the data */ ch1010832@1992: e1000_shift_out_ee_bits(hw, data[words_written], 16); ch1010832@1992: ch1010832@1992: /* Toggle the CS line. This in effect tells the EEPROM to execute ch1010832@1992: * the previous command. ch1010832@1992: */ ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: ch1010832@1992: /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will ch1010832@1992: * signal that the command has been completed by raising the DO signal. ch1010832@1992: * If DO does not go high in 10 milliseconds, then error out. ch1010832@1992: */ ch1010832@1992: for (i = 0; i < 200; i++) { ch1010832@1992: eecd = er32(EECD); ch1010832@1992: if (eecd & E1000_EECD_DO) ch1010832@1992: break; ch1010832@1992: udelay(50); ch1010832@1992: } ch1010832@1992: if (i == 200) { ch1010832@1992: DEBUGOUT("EEPROM Write did not complete\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Recover from write */ ch1010832@1992: e1000_standby_eeprom(hw); ch1010832@1992: ch1010832@1992: words_written++; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Send the write disable command to the EEPROM (3-bit opcode plus ch1010832@1992: * 6/8-bit dummy address beginning with 10). It's less work to include ch1010832@1992: * the 10 of the dummy address as part of the opcode than it is to shift ch1010832@1992: * it over the correct number of bits for the address. This takes the ch1010832@1992: * EEPROM out of write/erase mode. ch1010832@1992: */ ch1010832@1992: e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, ch1010832@1992: (u16) (eeprom->opcode_bits + 2)); ch1010832@1992: ch1010832@1992: e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_read_mac_addr - read the adapters MAC from eeprom ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the ch1010832@1992: * second function of dual function devices ch1010832@1992: */ ch1010832@1992: s32 e1000_read_mac_addr(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u16 offset; ch1010832@1992: u16 eeprom_data, i; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_read_mac_addr"); ch1010832@1992: ch1010832@1992: for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { ch1010832@1992: offset = i >> 1; ch1010832@1992: if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { ch1010832@1992: DEBUGOUT("EEPROM Read Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); ch1010832@1992: hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); ch1010832@1992: } ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: default: ch1010832@1992: break; ch1010832@1992: case e1000_82546: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: if (er32(STATUS) & E1000_STATUS_FUNC_1) ch1010832@1992: hw->perm_mac_addr[5] ^= 0x01; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: for (i = 0; i < NODE_ADDRESS_SIZE; i++) ch1010832@1992: hw->mac_addr[i] = hw->perm_mac_addr[i]; ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_init_rx_addrs - Initializes receive address filters. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Places the MAC address in receive address register 0 and clears the rest ch1010832@1992: * of the receive address registers. Clears the multicast table. Assumes ch1010832@1992: * the receiver is in reset when the routine is called. ch1010832@1992: */ ch1010832@1992: static void e1000_init_rx_addrs(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 i; ch1010832@1992: u32 rar_num; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_init_rx_addrs"); ch1010832@1992: ch1010832@1992: /* Setup the receive address. */ ch1010832@1992: DEBUGOUT("Programming MAC Address into RAR[0]\n"); ch1010832@1992: ch1010832@1992: e1000_rar_set(hw, hw->mac_addr, 0); ch1010832@1992: ch1010832@1992: rar_num = E1000_RAR_ENTRIES; ch1010832@1992: ch1010832@1992: /* Zero out the other 15 receive addresses. */ ch1010832@1992: DEBUGOUT("Clearing RAR[1-15]\n"); ch1010832@1992: for (i = 1; i < rar_num; i++) { ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @mc_addr: the multicast address to hash ch1010832@1992: */ ch1010832@1992: u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) ch1010832@1992: { ch1010832@1992: u32 hash_value = 0; ch1010832@1992: ch1010832@1992: /* The portion of the address that is used for the hash table is ch1010832@1992: * determined by the mc_filter_type setting. ch1010832@1992: */ ch1010832@1992: switch (hw->mc_filter_type) { ch1010832@1992: /* [0] [1] [2] [3] [4] [5] ch1010832@1992: * 01 AA 00 12 34 56 ch1010832@1992: * LSB MSB ch1010832@1992: */ ch1010832@1992: case 0: ch1010832@1992: /* [47:36] i.e. 0x563 for above example address */ ch1010832@1992: hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); ch1010832@1992: break; ch1010832@1992: case 1: ch1010832@1992: /* [46:35] i.e. 0xAC6 for above example address */ ch1010832@1992: hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); ch1010832@1992: break; ch1010832@1992: case 2: ch1010832@1992: /* [45:34] i.e. 0x5D8 for above example address */ ch1010832@1992: hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); ch1010832@1992: break; ch1010832@1992: case 3: ch1010832@1992: /* [43:32] i.e. 0x634 for above example address */ ch1010832@1992: hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: hash_value &= 0xFFF; ch1010832@1992: return hash_value; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_rar_set - Puts an ethernet address into a receive address register. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @addr: Address to put into receive address register ch1010832@1992: * @index: Receive address register to write ch1010832@1992: */ ch1010832@1992: void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) ch1010832@1992: { ch1010832@1992: u32 rar_low, rar_high; ch1010832@1992: ch1010832@1992: /* HW expects these in little endian so we reverse the byte order ch1010832@1992: * from network order (big endian) to little endian ch1010832@1992: */ ch1010832@1992: rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | ch1010832@1992: ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); ch1010832@1992: rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); ch1010832@1992: ch1010832@1992: /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx ch1010832@1992: * unit hang. ch1010832@1992: * ch1010832@1992: * Description: ch1010832@1992: * If there are any Rx frames queued up or otherwise present in the HW ch1010832@1992: * before RSS is enabled, and then we enable RSS, the HW Rx unit will ch1010832@1992: * hang. To work around this issue, we have to disable receives and ch1010832@1992: * flush out all Rx frames before we enable RSS. To do so, we modify we ch1010832@1992: * redirect all Rx traffic to manageability and then reset the HW. ch1010832@1992: * This flushes away Rx frames, and (since the redirections to ch1010832@1992: * manageability persists across resets) keeps new ones from coming in ch1010832@1992: * while we work. Then, we clear the Address Valid AV bit for all MAC ch1010832@1992: * addresses and undo the re-direction to manageability. ch1010832@1992: * Now, frames are coming in again, but the MAC won't accept them, so ch1010832@1992: * far so good. We now proceed to initialize RSS (if necessary) and ch1010832@1992: * configure the Rx unit. Last, we re-enable the AV bits and continue ch1010832@1992: * on our merry way. ch1010832@1992: */ ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: default: ch1010832@1992: /* Indicate to hardware the Address is Valid. */ ch1010832@1992: rar_high |= E1000_RAH_AV; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @offset: Offset in VLAN filer table to write ch1010832@1992: * @value: Value to write into VLAN filter table ch1010832@1992: */ ch1010832@1992: void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) ch1010832@1992: { ch1010832@1992: u32 temp; ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { ch1010832@1992: temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } else { ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_clear_vfta - Clears the VLAN filer table ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static void e1000_clear_vfta(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 offset; ch1010832@1992: u32 vfta_value = 0; ch1010832@1992: u32 vfta_offset = 0; ch1010832@1992: u32 vfta_bit_in_reg = 0; ch1010832@1992: ch1010832@1992: for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { ch1010832@1992: /* If the offset we want to clear is the same offset of the ch1010832@1992: * manageability VLAN ID, then clear all bits except that of the ch1010832@1992: * manageability unit */ ch1010832@1992: vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; ch1010832@1992: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); ch1010832@1992: E1000_WRITE_FLUSH(); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: static s32 e1000_id_led_init(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ledctl; ch1010832@1992: const u32 ledctl_mask = 0x000000FF; ch1010832@1992: const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; ch1010832@1992: const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; ch1010832@1992: u16 eeprom_data, i, temp; ch1010832@1992: const u16 led_mask = 0x0F; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_id_led_init"); ch1010832@1992: ch1010832@1992: if (hw->mac_type < e1000_82540) { ch1010832@1992: /* Nothing to do */ ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ledctl = er32(LEDCTL); ch1010832@1992: hw->ledctl_default = ledctl; ch1010832@1992: hw->ledctl_mode1 = hw->ledctl_default; ch1010832@1992: hw->ledctl_mode2 = hw->ledctl_default; ch1010832@1992: ch1010832@1992: if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { ch1010832@1992: DEBUGOUT("EEPROM Read Error\n"); ch1010832@1992: return -E1000_ERR_EEPROM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if ((eeprom_data == ID_LED_RESERVED_0000) || ch1010832@1992: (eeprom_data == ID_LED_RESERVED_FFFF)) { ch1010832@1992: eeprom_data = ID_LED_DEFAULT; ch1010832@1992: } ch1010832@1992: ch1010832@1992: for (i = 0; i < 4; i++) { ch1010832@1992: temp = (eeprom_data >> (i << 2)) & led_mask; ch1010832@1992: switch (temp) { ch1010832@1992: case ID_LED_ON1_DEF2: ch1010832@1992: case ID_LED_ON1_ON2: ch1010832@1992: case ID_LED_ON1_OFF2: ch1010832@1992: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ch1010832@1992: hw->ledctl_mode1 |= ledctl_on << (i << 3); ch1010832@1992: break; ch1010832@1992: case ID_LED_OFF1_DEF2: ch1010832@1992: case ID_LED_OFF1_ON2: ch1010832@1992: case ID_LED_OFF1_OFF2: ch1010832@1992: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); ch1010832@1992: hw->ledctl_mode1 |= ledctl_off << (i << 3); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: /* Do nothing */ ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: switch (temp) { ch1010832@1992: case ID_LED_DEF1_ON2: ch1010832@1992: case ID_LED_ON1_ON2: ch1010832@1992: case ID_LED_OFF1_ON2: ch1010832@1992: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ch1010832@1992: hw->ledctl_mode2 |= ledctl_on << (i << 3); ch1010832@1992: break; ch1010832@1992: case ID_LED_DEF1_OFF2: ch1010832@1992: case ID_LED_ON1_OFF2: ch1010832@1992: case ID_LED_OFF1_OFF2: ch1010832@1992: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); ch1010832@1992: hw->ledctl_mode2 |= ledctl_off << (i << 3); ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: /* Do nothing */ ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_setup_led ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Prepares SW controlable LED for use and saves the current state of the LED. ch1010832@1992: */ ch1010832@1992: s32 e1000_setup_led(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ledctl; ch1010832@1992: s32 ret_val = E1000_SUCCESS; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_setup_led"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: case e1000_82543: ch1010832@1992: case e1000_82544: ch1010832@1992: /* No setup necessary */ ch1010832@1992: break; ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82547: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: /* Turn off PHY Smart Power Down (if enabled) */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@1992: &hw->phy_spd_default); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@1992: (u16) (hw->phy_spd_default & ch1010832@1992: ~IGP01E1000_GMII_SPD)); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: /* Fall Through */ ch1010832@1992: default: ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) { ch1010832@1992: ledctl = er32(LEDCTL); ch1010832@1992: /* Save current LEDCTL settings */ ch1010832@1992: hw->ledctl_default = ledctl; ch1010832@1992: /* Turn off LED0 */ ch1010832@1992: ledctl &= ~(E1000_LEDCTL_LED0_IVRT | ch1010832@1992: E1000_LEDCTL_LED0_BLINK | ch1010832@1992: E1000_LEDCTL_LED0_MODE_MASK); ch1010832@1992: ledctl |= (E1000_LEDCTL_MODE_LED_OFF << ch1010832@1992: E1000_LEDCTL_LED0_MODE_SHIFT); ch1010832@1992: ew32(LEDCTL, ledctl); ch1010832@1992: } else if (hw->media_type == e1000_media_type_copper) ch1010832@1992: ew32(LEDCTL, hw->ledctl_mode1); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_cleanup_led - Restores the saved state of the SW controlable LED. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: s32 e1000_cleanup_led(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val = E1000_SUCCESS; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_cleanup_led"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: case e1000_82543: ch1010832@1992: case e1000_82544: ch1010832@1992: /* No cleanup necessary */ ch1010832@1992: break; ch1010832@1992: case e1000_82541: ch1010832@1992: case e1000_82547: ch1010832@1992: case e1000_82541_rev_2: ch1010832@1992: case e1000_82547_rev_2: ch1010832@1992: /* Turn on PHY Smart Power Down (if previously enabled) */ ch1010832@1992: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@1992: hw->phy_spd_default); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: /* Fall Through */ ch1010832@1992: default: ch1010832@1992: /* Restore LEDCTL settings */ ch1010832@1992: ew32(LEDCTL, hw->ledctl_default); ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_led_on - Turns on the software controllable LED ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: s32 e1000_led_on(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_led_on"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: case e1000_82543: ch1010832@1992: /* Set SW Defineable Pin 0 to turn on the LED */ ch1010832@1992: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: break; ch1010832@1992: case e1000_82544: ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) { ch1010832@1992: /* Set SW Defineable Pin 0 to turn on the LED */ ch1010832@1992: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: } else { ch1010832@1992: /* Clear SW Defineable Pin 0 to turn on the LED */ ch1010832@1992: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) { ch1010832@1992: /* Clear SW Defineable Pin 0 to turn on the LED */ ch1010832@1992: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: } else if (hw->media_type == e1000_media_type_copper) { ch1010832@1992: ew32(LEDCTL, hw->ledctl_mode2); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_led_off - Turns off the software controllable LED ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: s32 e1000_led_off(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 ctrl = er32(CTRL); ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_led_off"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: case e1000_82543: ch1010832@1992: /* Clear SW Defineable Pin 0 to turn off the LED */ ch1010832@1992: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: break; ch1010832@1992: case e1000_82544: ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) { ch1010832@1992: /* Clear SW Defineable Pin 0 to turn off the LED */ ch1010832@1992: ctrl &= ~E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: } else { ch1010832@1992: /* Set SW Defineable Pin 0 to turn off the LED */ ch1010832@1992: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: if (hw->media_type == e1000_media_type_fiber) { ch1010832@1992: /* Set SW Defineable Pin 0 to turn off the LED */ ch1010832@1992: ctrl |= E1000_CTRL_SWDPIN0; ch1010832@1992: ctrl |= E1000_CTRL_SWDPIO0; ch1010832@1992: } else if (hw->media_type == e1000_media_type_copper) { ch1010832@1992: ew32(LEDCTL, hw->ledctl_mode1); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ew32(CTRL, ctrl); ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_clear_hw_cntrs - Clears all hardware statistics counters. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: */ ch1010832@1992: static void e1000_clear_hw_cntrs(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: volatile u32 temp; ch1010832@1992: ch1010832@1992: temp = er32(CRCERRS); ch1010832@1992: temp = er32(SYMERRS); ch1010832@1992: temp = er32(MPC); ch1010832@1992: temp = er32(SCC); ch1010832@1992: temp = er32(ECOL); ch1010832@1992: temp = er32(MCC); ch1010832@1992: temp = er32(LATECOL); ch1010832@1992: temp = er32(COLC); ch1010832@1992: temp = er32(DC); ch1010832@1992: temp = er32(SEC); ch1010832@1992: temp = er32(RLEC); ch1010832@1992: temp = er32(XONRXC); ch1010832@1992: temp = er32(XONTXC); ch1010832@1992: temp = er32(XOFFRXC); ch1010832@1992: temp = er32(XOFFTXC); ch1010832@1992: temp = er32(FCRUC); ch1010832@1992: ch1010832@1992: temp = er32(PRC64); ch1010832@1992: temp = er32(PRC127); ch1010832@1992: temp = er32(PRC255); ch1010832@1992: temp = er32(PRC511); ch1010832@1992: temp = er32(PRC1023); ch1010832@1992: temp = er32(PRC1522); ch1010832@1992: ch1010832@1992: temp = er32(GPRC); ch1010832@1992: temp = er32(BPRC); ch1010832@1992: temp = er32(MPRC); ch1010832@1992: temp = er32(GPTC); ch1010832@1992: temp = er32(GORCL); ch1010832@1992: temp = er32(GORCH); ch1010832@1992: temp = er32(GOTCL); ch1010832@1992: temp = er32(GOTCH); ch1010832@1992: temp = er32(RNBC); ch1010832@1992: temp = er32(RUC); ch1010832@1992: temp = er32(RFC); ch1010832@1992: temp = er32(ROC); ch1010832@1992: temp = er32(RJC); ch1010832@1992: temp = er32(TORL); ch1010832@1992: temp = er32(TORH); ch1010832@1992: temp = er32(TOTL); ch1010832@1992: temp = er32(TOTH); ch1010832@1992: temp = er32(TPR); ch1010832@1992: temp = er32(TPT); ch1010832@1992: ch1010832@1992: temp = er32(PTC64); ch1010832@1992: temp = er32(PTC127); ch1010832@1992: temp = er32(PTC255); ch1010832@1992: temp = er32(PTC511); ch1010832@1992: temp = er32(PTC1023); ch1010832@1992: temp = er32(PTC1522); ch1010832@1992: ch1010832@1992: temp = er32(MPTC); ch1010832@1992: temp = er32(BPTC); ch1010832@1992: ch1010832@1992: if (hw->mac_type < e1000_82543) ch1010832@1992: return; ch1010832@1992: ch1010832@1992: temp = er32(ALGNERRC); ch1010832@1992: temp = er32(RXERRC); ch1010832@1992: temp = er32(TNCRS); ch1010832@1992: temp = er32(CEXTERR); ch1010832@1992: temp = er32(TSCTC); ch1010832@1992: temp = er32(TSCTFC); ch1010832@1992: ch1010832@1992: if (hw->mac_type <= e1000_82544) ch1010832@1992: return; ch1010832@1992: ch1010832@1992: temp = er32(MGTPRC); ch1010832@1992: temp = er32(MGTPDC); ch1010832@1992: temp = er32(MGTPTC); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_reset_adaptive - Resets Adaptive IFS to its default state. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Call this after e1000_init_hw. You may override the IFS defaults by setting ch1010832@1992: * hw->ifs_params_forced to true. However, you must initialize hw-> ch1010832@1992: * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio ch1010832@1992: * before calling this function. ch1010832@1992: */ ch1010832@1992: void e1000_reset_adaptive(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_reset_adaptive"); ch1010832@1992: ch1010832@1992: if (hw->adaptive_ifs) { ch1010832@1992: if (!hw->ifs_params_forced) { ch1010832@1992: hw->current_ifs_val = 0; ch1010832@1992: hw->ifs_min_val = IFS_MIN; ch1010832@1992: hw->ifs_max_val = IFS_MAX; ch1010832@1992: hw->ifs_step_size = IFS_STEP; ch1010832@1992: hw->ifs_ratio = IFS_RATIO; ch1010832@1992: } ch1010832@1992: hw->in_ifs_mode = false; ch1010832@1992: ew32(AIT, 0); ch1010832@1992: } else { ch1010832@1992: DEBUGOUT("Not in Adaptive IFS mode!\n"); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_update_adaptive - update adaptive IFS ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @tx_packets: Number of transmits since last callback ch1010832@1992: * @total_collisions: Number of collisions since last callback ch1010832@1992: * ch1010832@1992: * Called during the callback/watchdog routine to update IFS value based on ch1010832@1992: * the ratio of transmits to collisions. ch1010832@1992: */ ch1010832@1992: void e1000_update_adaptive(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_update_adaptive"); ch1010832@1992: ch1010832@1992: if (hw->adaptive_ifs) { ch1010832@1992: if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { ch1010832@1992: if (hw->tx_packet_delta > MIN_NUM_XMITS) { ch1010832@1992: hw->in_ifs_mode = true; ch1010832@1992: if (hw->current_ifs_val < hw->ifs_max_val) { ch1010832@1992: if (hw->current_ifs_val == 0) ch1010832@1992: hw->current_ifs_val = ch1010832@1992: hw->ifs_min_val; ch1010832@1992: else ch1010832@1992: hw->current_ifs_val += ch1010832@1992: hw->ifs_step_size; ch1010832@1992: ew32(AIT, hw->current_ifs_val); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: if (hw->in_ifs_mode ch1010832@1992: && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { ch1010832@1992: hw->current_ifs_val = 0; ch1010832@1992: hw->in_ifs_mode = false; ch1010832@1992: ew32(AIT, 0); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: DEBUGOUT("Not in Adaptive IFS mode!\n"); ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_tbi_adjust_stats ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @frame_len: The length of the frame in question ch1010832@1992: * @mac_addr: The Ethernet destination address of the frame in question ch1010832@1992: * ch1010832@1992: * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT ch1010832@1992: */ ch1010832@1992: void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, ch1010832@1992: u32 frame_len, u8 *mac_addr) ch1010832@1992: { ch1010832@1992: u64 carry_bit; ch1010832@1992: ch1010832@1992: /* First adjust the frame length. */ ch1010832@1992: frame_len--; ch1010832@1992: /* We need to adjust the statistics counters, since the hardware ch1010832@1992: * counters overcount this packet as a CRC error and undercount ch1010832@1992: * the packet as a good packet ch1010832@1992: */ ch1010832@1992: /* This packet should not be counted as a CRC error. */ ch1010832@1992: stats->crcerrs--; ch1010832@1992: /* This packet does count as a Good Packet Received. */ ch1010832@1992: stats->gprc++; ch1010832@1992: ch1010832@1992: /* Adjust the Good Octets received counters */ ch1010832@1992: carry_bit = 0x80000000 & stats->gorcl; ch1010832@1992: stats->gorcl += frame_len; ch1010832@1992: /* If the high bit of Gorcl (the low 32 bits of the Good Octets ch1010832@1992: * Received Count) was one before the addition, ch1010832@1992: * AND it is zero after, then we lost the carry out, ch1010832@1992: * need to add one to Gorch (Good Octets Received Count High). ch1010832@1992: * This could be simplified if all environments supported ch1010832@1992: * 64-bit integers. ch1010832@1992: */ ch1010832@1992: if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) ch1010832@1992: stats->gorch++; ch1010832@1992: /* Is this a broadcast or multicast? Check broadcast first, ch1010832@1992: * since the test for a multicast frame will test positive on ch1010832@1992: * a broadcast frame. ch1010832@1992: */ ch1010832@1992: if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) ch1010832@1992: /* Broadcast packet */ ch1010832@1992: stats->bprc++; ch1010832@1992: else if (*mac_addr & 0x01) ch1010832@1992: /* Multicast packet */ ch1010832@1992: stats->mprc++; ch1010832@1992: ch1010832@1992: if (frame_len == hw->max_frame_size) { ch1010832@1992: /* In this case, the hardware has overcounted the number of ch1010832@1992: * oversize frames. ch1010832@1992: */ ch1010832@1992: if (stats->roc > 0) ch1010832@1992: stats->roc--; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Adjust the bin counters when the extra byte put the frame in the ch1010832@1992: * wrong bin. Remember that the frame_len was adjusted above. ch1010832@1992: */ ch1010832@1992: if (frame_len == 64) { ch1010832@1992: stats->prc64++; ch1010832@1992: stats->prc127--; ch1010832@1992: } else if (frame_len == 127) { ch1010832@1992: stats->prc127++; ch1010832@1992: stats->prc255--; ch1010832@1992: } else if (frame_len == 255) { ch1010832@1992: stats->prc255++; ch1010832@1992: stats->prc511--; ch1010832@1992: } else if (frame_len == 511) { ch1010832@1992: stats->prc511++; ch1010832@1992: stats->prc1023--; ch1010832@1992: } else if (frame_len == 1023) { ch1010832@1992: stats->prc1023++; ch1010832@1992: stats->prc1522--; ch1010832@1992: } else if (frame_len == 1522) { ch1010832@1992: stats->prc1522++; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_get_bus_info ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Gets the current PCI bus type, speed, and width of the hardware ch1010832@1992: */ ch1010832@1992: void e1000_get_bus_info(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 status; ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82542_rev2_0: ch1010832@1992: case e1000_82542_rev2_1: ch1010832@1992: hw->bus_type = e1000_bus_type_pci; ch1010832@1992: hw->bus_speed = e1000_bus_speed_unknown; ch1010832@1992: hw->bus_width = e1000_bus_width_unknown; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: status = er32(STATUS); ch1010832@1992: hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? ch1010832@1992: e1000_bus_type_pcix : e1000_bus_type_pci; ch1010832@1992: ch1010832@1992: if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { ch1010832@1992: hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? ch1010832@1992: e1000_bus_speed_66 : e1000_bus_speed_120; ch1010832@1992: } else if (hw->bus_type == e1000_bus_type_pci) { ch1010832@1992: hw->bus_speed = (status & E1000_STATUS_PCI66) ? ch1010832@1992: e1000_bus_speed_66 : e1000_bus_speed_33; ch1010832@1992: } else { ch1010832@1992: switch (status & E1000_STATUS_PCIX_SPEED) { ch1010832@1992: case E1000_STATUS_PCIX_SPEED_66: ch1010832@1992: hw->bus_speed = e1000_bus_speed_66; ch1010832@1992: break; ch1010832@1992: case E1000_STATUS_PCIX_SPEED_100: ch1010832@1992: hw->bus_speed = e1000_bus_speed_100; ch1010832@1992: break; ch1010832@1992: case E1000_STATUS_PCIX_SPEED_133: ch1010832@1992: hw->bus_speed = e1000_bus_speed_133; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: hw->bus_speed = e1000_bus_speed_reserved; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: hw->bus_width = (status & E1000_STATUS_BUS64) ? ch1010832@1992: e1000_bus_width_64 : e1000_bus_width_32; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_write_reg_io ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @offset: offset to write to ch1010832@1992: * @value: value to write ch1010832@1992: * ch1010832@1992: * Writes a value to one of the devices registers using port I/O (as opposed to ch1010832@1992: * memory mapped I/O). Only 82544 and newer devices support port I/O. ch1010832@1992: */ ch1010832@1992: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) ch1010832@1992: { ch1010832@1992: unsigned long io_addr = hw->io_base; ch1010832@1992: unsigned long io_data = hw->io_base + 4; ch1010832@1992: ch1010832@1992: e1000_io_write(hw, io_addr, offset); ch1010832@1992: e1000_io_write(hw, io_data, value); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_get_cable_length - Estimates the cable length. ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @min_length: The estimated minimum length ch1010832@1992: * @max_length: The estimated maximum length ch1010832@1992: * ch1010832@1992: * returns: - E1000_ERR_XXX ch1010832@1992: * E1000_SUCCESS ch1010832@1992: * ch1010832@1992: * This function always returns a ranged length (minimum & maximum). ch1010832@1992: * So for M88 phy's, this function interprets the one value returned from the ch1010832@1992: * register to the minimum and maximum range. ch1010832@1992: * For IGP phy's, the function calculates the range by the AGC registers. ch1010832@1992: */ ch1010832@1992: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, ch1010832@1992: u16 *max_length) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 agc_value = 0; ch1010832@1992: u16 i, phy_data; ch1010832@1992: u16 cable_length; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_get_cable_length"); ch1010832@1992: ch1010832@1992: *min_length = *max_length = 0; ch1010832@1992: ch1010832@1992: /* Use old method for Phy older than IGP */ ch1010832@1992: if (hw->phy_type == e1000_phy_m88) { ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> ch1010832@1992: M88E1000_PSSR_CABLE_LENGTH_SHIFT; ch1010832@1992: ch1010832@1992: /* Convert the enum value to ranged values */ ch1010832@1992: switch (cable_length) { ch1010832@1992: case e1000_cable_length_50: ch1010832@1992: *min_length = 0; ch1010832@1992: *max_length = e1000_igp_cable_length_50; ch1010832@1992: break; ch1010832@1992: case e1000_cable_length_50_80: ch1010832@1992: *min_length = e1000_igp_cable_length_50; ch1010832@1992: *max_length = e1000_igp_cable_length_80; ch1010832@1992: break; ch1010832@1992: case e1000_cable_length_80_110: ch1010832@1992: *min_length = e1000_igp_cable_length_80; ch1010832@1992: *max_length = e1000_igp_cable_length_110; ch1010832@1992: break; ch1010832@1992: case e1000_cable_length_110_140: ch1010832@1992: *min_length = e1000_igp_cable_length_110; ch1010832@1992: *max_length = e1000_igp_cable_length_140; ch1010832@1992: break; ch1010832@1992: case e1000_cable_length_140: ch1010832@1992: *min_length = e1000_igp_cable_length_140; ch1010832@1992: *max_length = e1000_igp_cable_length_170; ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: return -E1000_ERR_PHY; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ ch1010832@1992: u16 cur_agc_value; ch1010832@1992: u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; ch1010832@1992: u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = ch1010832@1992: { IGP01E1000_PHY_AGC_A, ch1010832@1992: IGP01E1000_PHY_AGC_B, ch1010832@1992: IGP01E1000_PHY_AGC_C, ch1010832@1992: IGP01E1000_PHY_AGC_D ch1010832@1992: }; ch1010832@1992: /* Read the AGC registers for all channels */ ch1010832@1992: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; ch1010832@1992: ch1010832@1992: /* Value bound check. */ ch1010832@1992: if ((cur_agc_value >= ch1010832@1992: IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ch1010832@1992: || (cur_agc_value == 0)) ch1010832@1992: return -E1000_ERR_PHY; ch1010832@1992: ch1010832@1992: agc_value += cur_agc_value; ch1010832@1992: ch1010832@1992: /* Update minimal AGC value. */ ch1010832@1992: if (min_agc_value > cur_agc_value) ch1010832@1992: min_agc_value = cur_agc_value; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Remove the minimal AGC result for length < 50m */ ch1010832@1992: if (agc_value < ch1010832@1992: IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { ch1010832@1992: agc_value -= min_agc_value; ch1010832@1992: ch1010832@1992: /* Get the average length of the remaining 3 channels */ ch1010832@1992: agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); ch1010832@1992: } else { ch1010832@1992: /* Get the average length of all the 4 channels. */ ch1010832@1992: agc_value /= IGP01E1000_PHY_CHANNEL_NUM; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Set the range of the calculated length. */ ch1010832@1992: *min_length = ((e1000_igp_cable_length_table[agc_value] - ch1010832@1992: IGP01E1000_AGC_RANGE) > 0) ? ch1010832@1992: (e1000_igp_cable_length_table[agc_value] - ch1010832@1992: IGP01E1000_AGC_RANGE) : 0; ch1010832@1992: *max_length = e1000_igp_cable_length_table[agc_value] + ch1010832@1992: IGP01E1000_AGC_RANGE; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_check_polarity - Check the cable polarity ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @polarity: output parameter : 0 - Polarity is not reversed ch1010832@1992: * 1 - Polarity is reversed. ch1010832@1992: * ch1010832@1992: * returns: - E1000_ERR_XXX ch1010832@1992: * E1000_SUCCESS ch1010832@1992: * ch1010832@1992: * For phy's older than IGP, this function simply reads the polarity bit in the ch1010832@1992: * Phy Status register. For IGP phy's, this bit is valid only if link speed is ch1010832@1992: * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will ch1010832@1992: * return 0. If the link speed is 1000 Mbps the polarity status is in the ch1010832@1992: * IGP01E1000_PHY_PCS_INIT_REG. ch1010832@1992: */ ch1010832@1992: static s32 e1000_check_polarity(struct e1000_hw *hw, ch1010832@1992: e1000_rev_polarity *polarity) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_check_polarity"); ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_m88) { ch1010832@1992: /* return the Polarity bit in the Status register. */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> ch1010832@1992: M88E1000_PSSR_REV_POLARITY_SHIFT) ? ch1010832@1992: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; ch1010832@1992: ch1010832@1992: } else if (hw->phy_type == e1000_phy_igp) { ch1010832@1992: /* Read the Status register to check the speed */ ch1010832@1992: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to ch1010832@1992: * find the polarity status */ ch1010832@1992: if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == ch1010832@1992: IGP01E1000_PSSR_SPEED_1000MBPS) { ch1010832@1992: ch1010832@1992: /* Read the GIG initialization PCS register (0x00B4) */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Check the polarity bits */ ch1010832@1992: *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? ch1010832@1992: e1000_rev_polarity_reversed : ch1010832@1992: e1000_rev_polarity_normal; ch1010832@1992: } else { ch1010832@1992: /* For 10 Mbps, read the polarity bit in the status register. (for ch1010832@1992: * 100 Mbps this bit is always 0) */ ch1010832@1992: *polarity = ch1010832@1992: (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? ch1010832@1992: e1000_rev_polarity_reversed : ch1010832@1992: e1000_rev_polarity_normal; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_check_downshift - Check if Downshift occurred ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @downshift: output parameter : 0 - No Downshift occurred. ch1010832@1992: * 1 - Downshift occurred. ch1010832@1992: * ch1010832@1992: * returns: - E1000_ERR_XXX ch1010832@1992: * E1000_SUCCESS ch1010832@1992: * ch1010832@1992: * For phy's older than IGP, this function reads the Downshift bit in the Phy ch1010832@1992: * Specific Status register. For IGP phy's, it reads the Downgrade bit in the ch1010832@1992: * Link Health register. In IGP this bit is latched high, so the driver must ch1010832@1992: * read it immediately after link is established. ch1010832@1992: */ ch1010832@1992: static s32 e1000_check_downshift(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_check_downshift"); ch1010832@1992: ch1010832@1992: if (hw->phy_type == e1000_phy_igp) { ch1010832@1992: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->speed_downgraded = ch1010832@1992: (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; ch1010832@1992: } else if (hw->phy_type == e1000_phy_m88) { ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> ch1010832@1992: M88E1000_PSSR_DOWNSHIFT_SHIFT; ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_config_dsp_after_link_change ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @link_up: was link up at the time this was called ch1010832@1992: * ch1010832@1992: * returns: - E1000_ERR_PHY if fail to read/write the PHY ch1010832@1992: * E1000_SUCCESS at any other case. ch1010832@1992: * ch1010832@1992: * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a ch1010832@1992: * gigabit link is achieved to improve link quality. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data, phy_saved_data, speed, duplex, i; ch1010832@1992: u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = ch1010832@1992: { IGP01E1000_PHY_AGC_PARAM_A, ch1010832@1992: IGP01E1000_PHY_AGC_PARAM_B, ch1010832@1992: IGP01E1000_PHY_AGC_PARAM_C, ch1010832@1992: IGP01E1000_PHY_AGC_PARAM_D ch1010832@1992: }; ch1010832@1992: u16 min_length, max_length; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_config_dsp_after_link_change"); ch1010832@1992: ch1010832@1992: if (hw->phy_type != e1000_phy_igp) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: if (link_up) { ch1010832@1992: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); ch1010832@1992: if (ret_val) { ch1010832@1992: DEBUGOUT("Error getting link speed and duplex\n"); ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (speed == SPEED_1000) { ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_get_cable_length(hw, &min_length, ch1010832@1992: &max_length); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if ((hw->dsp_config_state == e1000_dsp_config_enabled) ch1010832@1992: && min_length >= e1000_igp_cable_length_50) { ch1010832@1992: ch1010832@1992: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, ch1010832@1992: dsp_reg_array[i], ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data &= ch1010832@1992: ~IGP01E1000_PHY_EDAC_MU_INDEX; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, ch1010832@1992: dsp_reg_array ch1010832@1992: [i], phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: hw->dsp_config_state = ch1010832@1992: e1000_dsp_config_activated; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if ((hw->ffe_config_state == e1000_ffe_config_enabled) ch1010832@1992: && (min_length < e1000_igp_cable_length_50)) { ch1010832@1992: ch1010832@1992: u16 ffe_idle_err_timeout = ch1010832@1992: FFE_IDLE_ERR_COUNT_TIMEOUT_20; ch1010832@1992: u32 idle_errs = 0; ch1010832@1992: ch1010832@1992: /* clear previous idle error counts */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, PHY_1000T_STATUS, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: for (i = 0; i < ffe_idle_err_timeout; i++) { ch1010832@1992: udelay(1000); ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, ch1010832@1992: PHY_1000T_STATUS, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: idle_errs += ch1010832@1992: (phy_data & ch1010832@1992: SR_1000T_IDLE_ERROR_CNT); ch1010832@1992: if (idle_errs > ch1010832@1992: SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) ch1010832@1992: { ch1010832@1992: hw->ffe_config_state = ch1010832@1992: e1000_ffe_config_active; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, ch1010832@1992: IGP01E1000_PHY_DSP_FFE, ch1010832@1992: IGP01E1000_PHY_DSP_FFE_CM_CP); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: break; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (idle_errs) ch1010832@1992: ffe_idle_err_timeout = ch1010832@1992: FFE_IDLE_ERR_COUNT_TIMEOUT_100; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } ch1010832@1992: } else { ch1010832@1992: if (hw->dsp_config_state == e1000_dsp_config_activated) { ch1010832@1992: /* Save off the current value of register 0x2F5B to be restored at ch1010832@1992: * the end of the routines. */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); ch1010832@1992: ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Disable the PHY transmitter */ ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); ch1010832@1992: ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: mdelay(20); ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@1992: IGP01E1000_IEEE_FORCE_GIGA); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, dsp_reg_array[i], ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; ch1010832@1992: phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, dsp_reg_array[i], ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@1992: IGP01E1000_IEEE_RESTART_AUTONEG); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: mdelay(20); ch1010832@1992: ch1010832@1992: /* Now enable the transmitter */ ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); ch1010832@1992: ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->dsp_config_state = e1000_dsp_config_enabled; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (hw->ffe_config_state == e1000_ffe_config_active) { ch1010832@1992: /* Save off the current value of register 0x2F5B to be restored at ch1010832@1992: * the end of the routines. */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); ch1010832@1992: ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Disable the PHY transmitter */ ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); ch1010832@1992: ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: mdelay(20); ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@1992: IGP01E1000_IEEE_FORCE_GIGA); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, ch1010832@1992: IGP01E1000_PHY_DSP_FFE_DEFAULT); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, 0x0000, ch1010832@1992: IGP01E1000_IEEE_RESTART_AUTONEG); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: mdelay(20); ch1010832@1992: ch1010832@1992: /* Now enable the transmitter */ ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); ch1010832@1992: ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->ffe_config_state = e1000_ffe_config_enabled; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_set_phy_mode - Set PHY to class A mode ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Assumes the following operations will follow to enable the new class mode. ch1010832@1992: * 1. Do a PHY soft reset ch1010832@1992: * 2. Restart auto-negotiation or force link. ch1010832@1992: */ ch1010832@1992: static s32 e1000_set_phy_mode(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 eeprom_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_set_phy_mode"); ch1010832@1992: ch1010832@1992: if ((hw->mac_type == e1000_82545_rev_3) && ch1010832@1992: (hw->media_type == e1000_media_type_copper)) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, ch1010832@1992: &eeprom_data); ch1010832@1992: if (ret_val) { ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if ((eeprom_data != EEPROM_RESERVED_WORD) && ch1010832@1992: (eeprom_data & EEPROM_PHY_CLASS_A)) { ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, ch1010832@1992: 0x000B); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, ch1010832@1992: 0x8104); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: hw->phy_reset_disable = false; ch1010832@1992: } ch1010832@1992: } ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_set_d3_lplu_state - set d3 link power state ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * @active: true to enable lplu false to disable lplu. ch1010832@1992: * ch1010832@1992: * This function sets the lplu state according to the active flag. When ch1010832@1992: * activating lplu this function also disables smart speed and vise versa. ch1010832@1992: * lplu will not be activated unless the device autonegotiation advertisement ch1010832@1992: * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. ch1010832@1992: * ch1010832@1992: * returns: - E1000_ERR_PHY if fail to read/write the PHY ch1010832@1992: * E1000_SUCCESS at any other case. ch1010832@1992: */ ch1010832@1992: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 phy_data; ch1010832@1992: DEBUGFUNC("e1000_set_d3_lplu_state"); ch1010832@1992: ch1010832@1992: if (hw->phy_type != e1000_phy_igp) ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: ch1010832@1992: /* During driver activity LPLU should not be used or it will attain link ch1010832@1992: * from the lowest speeds starting from 10Mbps. The capability is used for ch1010832@1992: * Dx transitions and states */ ch1010832@1992: if (hw->mac_type == e1000_82541_rev_2 ch1010832@1992: || hw->mac_type == e1000_82547_rev_2) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: if (!active) { ch1010832@1992: if (hw->mac_type == e1000_82541_rev_2 || ch1010832@1992: hw->mac_type == e1000_82547_rev_2) { ch1010832@1992: phy_data &= ~IGP01E1000_GMII_FLEX_SPD; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during ch1010832@1992: * Dx states where the power conservation is most important. During ch1010832@1992: * driver activity we should enable SmartSpeed, so performance is ch1010832@1992: * maintained. */ ch1010832@1992: if (hw->smart_speed == e1000_smart_speed_on) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= IGP01E1000_PSCFR_SMART_SPEED; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } else if (hw->smart_speed == e1000_smart_speed_off) { ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ch1010832@1992: || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ch1010832@1992: || (hw->autoneg_advertised == ch1010832@1992: AUTONEG_ADVERTISE_10_100_ALL)) { ch1010832@1992: ch1010832@1992: if (hw->mac_type == e1000_82541_rev_2 || ch1010832@1992: hw->mac_type == e1000_82547_rev_2) { ch1010832@1992: phy_data |= IGP01E1000_GMII_FLEX_SPD; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* When LPLU is enabled we should disable SmartSpeed */ ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, ch1010832@1992: phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_set_vco_speed ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Change VCO speed register to improve Bit Error Rate performance of SERDES. ch1010832@1992: */ ch1010832@1992: static s32 e1000_set_vco_speed(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 default_page = 0; ch1010832@1992: u16 phy_data; ch1010832@1992: ch1010832@1992: DEBUGFUNC("e1000_set_vco_speed"); ch1010832@1992: ch1010832@1992: switch (hw->mac_type) { ch1010832@1992: case e1000_82545_rev_3: ch1010832@1992: case e1000_82546_rev_3: ch1010832@1992: break; ch1010832@1992: default: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Set PHY register 30, page 5, bit 8 to 0 */ ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* Set PHY register 30, page 4, bit 11 to 1 */ ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: phy_data |= M88E1000_PHY_VCO_REG_BIT11; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = ch1010832@1992: e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_enable_mng_pass_thru - check for bmc pass through ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Verifies the hardware needs to allow ARPs to be processed by the host ch1010832@1992: * returns: - true/false ch1010832@1992: */ ch1010832@1992: u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: u32 manc; ch1010832@1992: ch1010832@1992: if (hw->asf_firmware_present) { ch1010832@1992: manc = er32(MANC); ch1010832@1992: ch1010832@1992: if (!(manc & E1000_MANC_RCV_TCO_EN) || ch1010832@1992: !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) ch1010832@1992: return false; ch1010832@1992: if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) ch1010832@1992: return true; ch1010832@1992: } ch1010832@1992: return false; ch1010832@1992: } ch1010832@1992: ch1010832@1992: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: s32 ret_val; ch1010832@1992: u16 mii_status_reg; ch1010832@1992: u16 i; ch1010832@1992: ch1010832@1992: /* Polarity reversal workaround for forced 10F/10H links. */ ch1010832@1992: ch1010832@1992: /* Disable the transmitter on the PHY */ ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* This loop will early-out if the NO link condition has been met. */ ch1010832@1992: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@1992: /* Read the MII Status Register and wait for Link Status bit ch1010832@1992: * to be clear. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) ch1010832@1992: break; ch1010832@1992: mdelay(100); ch1010832@1992: } ch1010832@1992: ch1010832@1992: /* Recommended delay time after link has been lost */ ch1010832@1992: mdelay(1000); ch1010832@1992: ch1010832@1992: /* Now we will re-enable th transmitter on the PHY */ ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: mdelay(50); ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: mdelay(50); ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: mdelay(50); ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: /* This loop will early-out if the link condition has been met. */ ch1010832@1992: for (i = PHY_FORCE_TIME; i > 0; i--) { ch1010832@1992: /* Read the MII Status Register and wait for Link Status bit ch1010832@1992: * to be set. ch1010832@1992: */ ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); ch1010832@1992: if (ret_val) ch1010832@1992: return ret_val; ch1010832@1992: ch1010832@1992: if (mii_status_reg & MII_SR_LINK_STATUS) ch1010832@1992: break; ch1010832@1992: mdelay(100); ch1010832@1992: } ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_get_auto_rd_done ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Check for EEPROM Auto Read bit done. ch1010832@1992: * returns: - E1000_ERR_RESET if fail to reset MAC ch1010832@1992: * E1000_SUCCESS at any other case. ch1010832@1992: */ ch1010832@1992: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_get_auto_rd_done"); ch1010832@1992: msleep(5); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: } ch1010832@1992: ch1010832@1992: /** ch1010832@1992: * e1000_get_phy_cfg_done ch1010832@1992: * @hw: Struct containing variables accessed by shared code ch1010832@1992: * ch1010832@1992: * Checks if the PHY configuration is done ch1010832@1992: * returns: - E1000_ERR_RESET if fail to reset MAC ch1010832@1992: * E1000_SUCCESS at any other case. ch1010832@1992: */ ch1010832@1992: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) ch1010832@1992: { ch1010832@1992: DEBUGFUNC("e1000_get_phy_cfg_done"); ch1010832@1992: mdelay(10); ch1010832@1992: return E1000_SUCCESS; ch1010832@1992: }