p@2550: /**
p@2550:     Network Driver for Beckhoff CCAT communication controller
p@2550:     Copyright (C) 2014  Beckhoff Automation GmbH
p@2550:     Author: Patrick Bruenn <p.bruenn@beckhoff.com>
p@2550: 
p@2550:     This program is free software; you can redistribute it and/or modify
p@2550:     it under the terms of the GNU General Public License as published by
p@2550:     the Free Software Foundation; either version 2 of the License, or
p@2550:     (at your option) any later version.
p@2550: 
p@2550:     This program is distributed in the hope that it will be useful,
p@2550:     but WITHOUT ANY WARRANTY; without even the implied warranty of
p@2550:     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
p@2550:     GNU General Public License for more details.
p@2550: 
p@2550:     You should have received a copy of the GNU General Public License along
p@2550:     with this program; if not, write to the Free Software Foundation, Inc.,
p@2550:     51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
p@2550: */
p@2550: 
p@2550: #include <linux/fs.h>
p@2550: #include <linux/kernel.h>
p@2550: #include <linux/module.h>
p@2550: #include <linux/sched.h>
p@2550: #include <linux/uaccess.h>
p@2552: #include "compat.h"
p@2550: #include "module.h"
p@2550: #include "print.h"
p@2550: #include "update.h"
p@2550: 
p@2550: #define CCAT_DATA_IN_4 0x038
p@2550: #define CCAT_DATA_IN_N 0x7F0
p@2550: #define CCAT_DATA_OUT_4 0x030
p@2550: #define CCAT_DATA_BLOCK_SIZE (size_t)((CCAT_DATA_IN_N - CCAT_DATA_IN_4)/8)
p@2550: #define CCAT_WRITE_BLOCK_SIZE 128
p@2550: #define CCAT_FLASH_SIZE (size_t)0xE0000
p@2550: 
p@2550: /**     FUNCTION_NAME            CMD,  CLOCKS          */
p@2550: #define CCAT_BULK_ERASE          0xE3, 8
p@2550: #define CCAT_GET_PROM_ID         0xD5, 40
p@2550: #define CCAT_READ_FLASH          0xC0, 32
p@2550: #define CCAT_READ_STATUS         0xA0, 16
p@2550: #define CCAT_WRITE_ENABLE        0x60, 8
p@2550: #define CCAT_WRITE_FLASH         0x40, 32
p@2550: 
p@2550: /* from http://graphics.stanford.edu/~seander/bithacks.html#ReverseByteWith32Bits */
p@2550: #define SWAP_BITS(B) \
p@2550: 	((((B) * 0x0802LU & 0x22110LU) | ((B) * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16)
p@2550: 
p@2550: /**
p@2550:  * struct update_buffer - keep track of a CCAT FPGA update
p@2550:  * @update: pointer to a valid ccat_update object
p@2550:  * @data: buffer used for write operations
p@2550:  * @size: number of bytes written to the data buffer, if 0 on ccat_update_release() no data will be written to FPGA
p@2550:  */
p@2550: struct update_buffer {
p@2550: 	struct ccat_update *update;
p@2550: 	char data[CCAT_FLASH_SIZE];
p@2550: 	size_t size;
p@2550: };
p@2550: 
p@2550: static void ccat_wait_status_cleared(void __iomem * const ioaddr);
p@2550: static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
p@2550: 			   uint32_t len, loff_t * off);
p@2550: static void ccat_write_flash(const struct update_buffer *const buf);
p@2550: static void ccat_update_cmd(void __iomem * const ioaddr, uint8_t cmd,
p@2550: 			    uint16_t clocks);
p@2550: static void ccat_update_destroy(struct kref *ref);
p@2550: 
p@2550: /**
p@2550:  * wait_until_busy_reset() - wait until the busy flag was reset
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  */
p@2550: static inline void wait_until_busy_reset(void __iomem * const ioaddr)
p@2550: {
p@2550: 	wmb();
p@2550: 	while (ioread8(ioaddr + 1)) {
p@2550: 		schedule();
p@2550: 	}
p@2550: }
p@2550: 
p@2550: static int ccat_update_open(struct inode *const i, struct file *const f)
p@2550: {
p@2550: 	struct ccat_update *update =
p@2550: 	    container_of(i->i_cdev, struct ccat_update, cdev);
p@2550: 	struct update_buffer *buf;
p@2550: 	kref_get(&update->refcount);
p@2550: 	if (atomic_read(&update->refcount.refcount) > 2) {
p@2550: 		kref_put(&update->refcount, ccat_update_destroy);
p@2550: 		return -EBUSY;
p@2550: 	}
p@2550: 
p@2550: 	buf = kzalloc(sizeof(*buf), GFP_KERNEL);
p@2550: 	if (!buf) {
p@2550: 		kref_put(&update->refcount, ccat_update_destroy);
p@2550: 		return -ENOMEM;
p@2550: 	}
p@2550: 
p@2550: 	buf->update = update;
p@2550: 	f->private_data = buf;
p@2550: 	return 0;
p@2550: }
p@2550: 
p@2550: static int ccat_update_release(struct inode *const i, struct file *const f)
p@2550: {
p@2550: 	const struct update_buffer *const buf = f->private_data;
p@2550: 	struct ccat_update *const update = buf->update;
p@2550: 	if (buf->size > 0) {
p@2550: 		ccat_update_cmd(update->ioaddr, CCAT_WRITE_ENABLE);
p@2550: 		ccat_update_cmd(update->ioaddr, CCAT_BULK_ERASE);
p@2550: 		ccat_wait_status_cleared(update->ioaddr);
p@2550: 		ccat_write_flash(buf);
p@2550: 	}
p@2550: 	kfree(f->private_data);
p@2550: 	kref_put(&update->refcount, ccat_update_destroy);
p@2550: 	return 0;
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_read() - Read CCAT configuration data from flash
p@2550:  * @f: file handle previously initialized with ccat_update_open()
p@2550:  * @buf: buffer in user space provided for our data
p@2550:  * @len: length of the user space buffer
p@2550:  * @off: current offset of our file operation
p@2550:  *
p@2550:  * Copies data from the CCAT FPGA's configuration flash to user space.
p@2550:  * Note that the size of the FPGA's firmware is not known exactly so it
p@2550:  * is very possible that the overall buffer ends with a lot of 0xff.
p@2550:  *
p@2550:  * Return: the number of bytes written, or 0 if EOF reached
p@2550:  */
p@2550: static ssize_t ccat_update_read(struct file *const f, char __user * buf,
p@2550: 				size_t len, loff_t * off)
p@2550: {
p@2550: 	struct update_buffer *update = f->private_data;
p@2550: 	if (!buf || !off) {
p@2550: 		return -EINVAL;
p@2550: 	}
p@2550: 	if (*off >= CCAT_FLASH_SIZE) {
p@2550: 		return 0;
p@2550: 	}
p@2550: 	if (*off + len >= CCAT_FLASH_SIZE) {
p@2550: 		len = CCAT_FLASH_SIZE - *off;
p@2550: 	}
p@2550: 	return ccat_read_flash(update->update->ioaddr, buf, len, off);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_write() - Write data to the CCAT FPGA's configuration flash
p@2550:  * @f: file handle previously initialized with ccat_update_open()
p@2550:  * @buf: buffer in user space providing the new configuration data (from *.rbf)
p@2550:  * @len: length of the user space buffer
p@2550:  * @off: current offset in the configuration data
p@2550:  *
p@2550:  * Copies data from user space (possibly a *.rbf) to the CCAT FPGA's
p@2550:  * configuration flash to user space.
p@2550:  *
p@2550:  * Return: the number of bytes written, or 0 if flash end is reached
p@2550:  */
p@2550: 
p@2550: static ssize_t ccat_update_write(struct file *const f, const char __user * buf,
p@2550: 				 size_t len, loff_t * off)
p@2550: {
p@2550: 	struct update_buffer *const update = f->private_data;
p@2550: 	if (*off + len > sizeof(update->data))
p@2550: 		return 0;
p@2550: 
p@2550: 	copy_from_user(update->data + *off, buf, len);
p@2550: 	*off += len;
p@2550: 	update->size = *off;
p@2550: 	return len;
p@2550: }
p@2550: 
p@2550: static struct file_operations update_ops = {
p@2550: 	.owner = THIS_MODULE,
p@2550: 	.open = ccat_update_open,
p@2550: 	.release = ccat_update_release,
p@2550: 	.read = ccat_update_read,
p@2550: 	.write = ccat_update_write,
p@2550: };
p@2550: 
p@2550: /**
p@2550:  * __ccat_update_cmd() - Helper to issue a FPGA flash command
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  * @cmd: the command identifier
p@2550:  * @clocks: the number of clocks associated with the specified command
p@2550:  *
p@2550:  * no write memory barrier is called and the busy flag is not evaluated
p@2550:  */
p@2550: static inline void __ccat_update_cmd(void __iomem * const ioaddr, uint8_t cmd,
p@2550: 				     uint16_t clocks)
p@2550: {
p@2550: 	iowrite8((0xff00 & clocks) >> 8, ioaddr);
p@2550: 	iowrite8(0x00ff & clocks, ioaddr + 0x8);
p@2550: 	iowrite8(cmd, ioaddr + 0x10);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_cmd() - Helper to issue a FPGA flash command
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  * @cmd: the command identifier
p@2550:  * @clocks: the number of clocks associated with the specified command
p@2550:  *
p@2550:  * Triggers a full flash command cycle with write memory barrier and
p@2550:  * command activate. This call blocks until the busy flag is reset.
p@2550:  */
p@2550: static inline void ccat_update_cmd(void __iomem * const ioaddr, uint8_t cmd,
p@2550: 				   uint16_t clocks)
p@2550: {
p@2550: 	__ccat_update_cmd(ioaddr, cmd, clocks);
p@2550: 	wmb();
p@2550: 	iowrite8(0xff, ioaddr + 0x7f8);
p@2550: 	wait_until_busy_reset(ioaddr);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_cmd_addr() - Helper to issue a FPGA flash command with address parameter
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  * @cmd: the command identifier
p@2550:  * @clocks: the number of clocks associated with the specified command
p@2550:  * @addr: 24 bit address associated with the specified command
p@2550:  *
p@2550:  * Triggers a full flash command cycle with write memory barrier and
p@2550:  * command activate. This call blocks until the busy flag is reset.
p@2550:  */
p@2550: static inline void ccat_update_cmd_addr(void __iomem * const ioaddr,
p@2550: 					uint8_t cmd, uint16_t clocks,
p@2550: 					uint32_t addr)
p@2550: {
p@2550: 	const uint8_t addr_0 = SWAP_BITS(addr & 0xff);
p@2550: 	const uint8_t addr_1 = SWAP_BITS((addr & 0xff00) >> 8);
p@2550: 	const uint8_t addr_2 = SWAP_BITS((addr & 0xff0000) >> 16);
p@2550: 	__ccat_update_cmd(ioaddr, cmd, clocks);
p@2550: 	iowrite8(addr_2, ioaddr + 0x18);
p@2550: 	iowrite8(addr_1, ioaddr + 0x20);
p@2550: 	iowrite8(addr_0, ioaddr + 0x28);
p@2550: 	wmb();
p@2550: 	iowrite8(0xff, ioaddr + 0x7f8);
p@2550: 	wait_until_busy_reset(ioaddr);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_get_prom_id() - Read CCAT PROM ID
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  *
p@2550:  * Return: the CCAT FPGA's PROM identifier
p@2550:  */
p@2550: uint8_t ccat_get_prom_id(void __iomem * const ioaddr)
p@2550: {
p@2550: 	ccat_update_cmd(ioaddr, CCAT_GET_PROM_ID);
p@2550: 	return ioread8(ioaddr + 0x38);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_get_status() - Read CCAT Update status
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  *
p@2550:  * Return: the current status of the CCAT Update function
p@2550:  */
p@2550: static uint8_t ccat_get_status(void __iomem * const ioaddr)
p@2550: {
p@2550: 	ccat_update_cmd(ioaddr, CCAT_READ_STATUS);
p@2550: 	return ioread8(ioaddr + 0x20);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_wait_status_cleared() - wait until CCAT status is cleared
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  *
p@2550:  * Blocks until bit 7 of the CCAT Update status is reset
p@2550:  */
p@2550: 
p@2550: static void ccat_wait_status_cleared(void __iomem * const ioaddr)
p@2550: {
p@2550: 	uint8_t status;
p@2550: 	do {
p@2550: 		status = ccat_get_status(ioaddr);
p@2550: 	} while (status & (1 << 7));
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_read_flash_block() - Read a block of CCAT configuration data from flash
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  * @addr: 24 bit address of the block to read
p@2550:  * @len: number of bytes to read from this block, len <= CCAT_DATA_BLOCK_SIZE
p@2550:  * @buf: output buffer in user space
p@2550:  *
p@2550:  * Copies one block of configuration data from the CCAT FPGA's flash to
p@2550:  * the user space buffer.
p@2550:  * Note that the size of the FPGA's firmware is not known exactly so it
p@2550:  * is very possible that the overall buffer ends with a lot of 0xff.
p@2550:  *
p@2550:  * Return: the number of bytes copied
p@2550:  */
p@2550: static int ccat_read_flash_block(void __iomem * const ioaddr,
p@2550: 				 const uint32_t addr, const uint16_t len,
p@2550: 				 char __user * const buf)
p@2550: {
p@2550: 	uint16_t i;
p@2550: 	const uint16_t clocks = 8 * len;
p@2550: 	ccat_update_cmd_addr(ioaddr, CCAT_READ_FLASH + clocks, addr);
p@2550: 	for (i = 0; i < len; i++) {
p@2550: 		put_user(ioread8(ioaddr + CCAT_DATA_IN_4 + 8 * i), buf + i);
p@2550: 	}
p@2550: 	return len;
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_read_flash() - Read a chunk of CCAT configuration data from flash
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  * @buf: output buffer in user space
p@2550:  * @len: number of bytes to read
p@2550:  * @off: offset in the configuration data
p@2550:  *
p@2550:  * Copies multiple blocks of configuration data from the CCAT FPGA's
p@2550:  * flash to the user space buffer.
p@2550:  *
p@2550:  * Return: the number of bytes copied
p@2550:  */
p@2550: static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
p@2550: 			   uint32_t len, loff_t * off)
p@2550: {
p@2550: 	const loff_t start = *off;
p@2550: 	while (len > CCAT_DATA_BLOCK_SIZE) {
p@2550: 		*off +=
p@2550: 		    ccat_read_flash_block(ioaddr, *off, CCAT_DATA_BLOCK_SIZE,
p@2550: 					  buf);
p@2550: 		buf += CCAT_DATA_BLOCK_SIZE;
p@2550: 		len -= CCAT_DATA_BLOCK_SIZE;
p@2550: 	}
p@2550: 	*off += ccat_read_flash_block(ioaddr, *off, len, buf);
p@2550: 	return *off - start;
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_write_flash_block() - Write a block of CCAT configuration data to flash
p@2550:  * @ioaddr: address of the CCAT Update function in PCI config space
p@2550:  * @addr: 24 bit start address in the CCAT FPGA's flash
p@2550:  * @len: number of bytes to write in this block, len <= CCAT_WRITE_BLOCK_SIZE
p@2550:  * @buf: input buffer
p@2550:  *
p@2550:  * Copies one block of configuration data to the CCAT FPGA's flash
p@2550:  *
p@2550:  * Return: the number of bytes copied
p@2550:  */
p@2550: static int ccat_write_flash_block(void __iomem * const ioaddr,
p@2550: 				  const uint32_t addr, const uint16_t len,
p@2550: 				  const char *const buf)
p@2550: {
p@2550: 	const uint16_t clocks = 8 * len;
p@2550: 	uint16_t i;
p@2550: 	ccat_update_cmd(ioaddr, CCAT_WRITE_ENABLE);
p@2550: 	for (i = 0; i < len; i++) {
p@2550: 		iowrite8(buf[i], ioaddr + CCAT_DATA_OUT_4 + 8 * i);
p@2550: 	}
p@2550: 	ccat_update_cmd_addr(ioaddr, CCAT_WRITE_FLASH + clocks, addr);
p@2550: 	ccat_wait_status_cleared(ioaddr);
p@2550: 	return len;
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_write_flash() - Write a new CCAT configuration to FPGA's flash
p@2550:  * @update: a CCAT Update buffer containing the new FPGA configuration
p@2550:  */
p@2550: static void ccat_write_flash(const struct update_buffer *const update)
p@2550: {
p@2550: 	const char *buf = update->data;
p@2550: 	uint32_t off = 0;
p@2550: 	size_t len = update->size;
p@2550: 	while (len > CCAT_WRITE_BLOCK_SIZE) {
p@2550: 		ccat_write_flash_block(update->update->ioaddr, off,
p@2550: 				       (uint16_t) CCAT_WRITE_BLOCK_SIZE, buf);
p@2550: 		off += CCAT_WRITE_BLOCK_SIZE;
p@2550: 		buf += CCAT_WRITE_BLOCK_SIZE;
p@2550: 		len -= CCAT_WRITE_BLOCK_SIZE;
p@2550: 	}
p@2550: 	ccat_write_flash_block(update->update->ioaddr, off, (uint16_t) len,
p@2550: 			       buf);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_init() - Initialize the CCAT Update function
p@2550:  */
p@2550: struct ccat_update *ccat_update_init(const struct ccat_device *const ccatdev,
p@2550: 				     void __iomem * const addr)
p@2550: {
p@2550: 	struct ccat_update *const update = kzalloc(sizeof(*update), GFP_KERNEL);
p@2550: 	if (!update) {
p@2550: 		return NULL;
p@2550: 	}
p@2550: 	kref_init(&update->refcount);
p@2550: 	update->ioaddr = ccatdev->bar[0].ioaddr + ioread32(addr + 0x8);
p@2550: 	memcpy_fromio(&update->info, addr, sizeof(update->info));
p@2550: 	print_update_info(&update->info, update->ioaddr);
p@2550: 
p@2550: 	if (0x00 != update->info.nRevision) {
p@2550: 		pr_warn("CCAT Update rev. %d not supported\n",
p@2550: 			update->info.nRevision);
p@2550: 		goto cleanup;
p@2550: 	}
p@2550: 
p@2550: 	if (alloc_chrdev_region(&update->dev, 0, 1, DRV_NAME)) {
p@2550: 		pr_warn("alloc_chrdev_region() failed\n");
p@2550: 		goto cleanup;
p@2550: 	}
p@2550: 
p@2550: 	update->class = class_create(THIS_MODULE, "ccat_update");
p@2550: 	if (NULL == update->class) {
p@2550: 		pr_warn("Create device class failed\n");
p@2550: 		goto cleanup;
p@2550: 	}
p@2550: 
p@2550: 	if (NULL ==
p@2550: 	    device_create(update->class, NULL, update->dev, NULL,
p@2550: 			  "ccat_update")) {
p@2550: 		pr_warn("device_create() failed\n");
p@2550: 		goto cleanup;
p@2550: 	}
p@2550: 
p@2550: 	cdev_init(&update->cdev, &update_ops);
p@2550: 	update->cdev.owner = THIS_MODULE;
p@2550: 	update->cdev.ops = &update_ops;
p@2550: 	if (cdev_add(&update->cdev, update->dev, 1)) {
p@2550: 		pr_warn("add update device failed\n");
p@2550: 		goto cleanup;
p@2550: 	}
p@2550: 	return update;
p@2550: cleanup:
p@2550: 	kref_put(&update->refcount, ccat_update_destroy);
p@2550: 	return NULL;
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_destroy() - Cleanup the CCAT Update function
p@2550:  * @ref: pointer to a struct kref embedded into a struct ccat_update, which we intend to destroy
p@2550:  *
p@2550:  * Retrieves the parent struct ccat_update and destroys it.
p@2550:  */
p@2550: static void ccat_update_destroy(struct kref *ref)
p@2550: {
p@2550: 	struct ccat_update *update =
p@2550: 	    container_of(ref, struct ccat_update, refcount);
p@2550: 	cdev_del(&update->cdev);
p@2550: 	device_destroy(update->class, update->dev);
p@2550: 	class_destroy(update->class);
p@2550: 	unregister_chrdev_region(update->dev, 1);
p@2550: 	kfree(update);
p@2550: 	pr_debug("%s(): done\n", __FUNCTION__);
p@2550: }
p@2550: 
p@2550: /**
p@2550:  * ccat_update_remove() - Prepare the CCAT Update function for removal
p@2550:  */
p@2550: void ccat_update_remove(struct ccat_update *update)
p@2550: {
p@2550: 	kref_put(&update->refcount, ccat_update_destroy);
p@2550: 	pr_debug("%s(): done\n", __FUNCTION__);
p@2550: }